2 * This file is part of the Chelsio T4 PCI-E SR-IOV Virtual Function Ethernet
5 * Copyright (c) 2009-2010 Chelsio Communications, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #ifndef __T4VF_COMMON_H__
37 #define __T4VF_COMMON_H__
39 #include "../cxgb4/t4fw_api.h"
41 #define CHELSIO_CHIP_CODE(version, revision) (((version) << 4) | (revision))
42 #define CHELSIO_CHIP_VERSION(code) (((code) >> 4) & 0xf)
43 #define CHELSIO_CHIP_RELEASE(code) ((code) & 0xf)
45 /* All T4 and later chips have their PCI-E Device IDs encoded as 0xVFPP where:
47 * V = "4" for T4; "5" for T5, etc. or
48 * = "a" for T4 FPGA; "b" for T4 FPGA, etc.
49 * F = "0" for PF 0..3; "4".."7" for PF4..7; and "8" for VFs
50 * PP = adapter product designation
52 #define CHELSIO_T4 0x4
53 #define CHELSIO_T5 0x5
56 T4_A1
= CHELSIO_CHIP_CODE(CHELSIO_T4
, 1),
57 T4_A2
= CHELSIO_CHIP_CODE(CHELSIO_T4
, 2),
61 T5_A0
= CHELSIO_CHIP_CODE(CHELSIO_T5
, 0),
62 T5_A1
= CHELSIO_CHIP_CODE(CHELSIO_T5
, 1),
68 * The "len16" field of a Firmware Command Structure ...
70 #define FW_LEN16(fw_struct) FW_CMD_LEN16(sizeof(fw_struct) / 16)
75 struct t4vf_port_stats
{
79 u64 tx_bcast_bytes
; /* broadcast */
81 u64 tx_mcast_bytes
; /* multicast */
83 u64 tx_ucast_bytes
; /* unicast */
85 u64 tx_drop_frames
; /* TX dropped frames */
86 u64 tx_offload_bytes
; /* offload */
87 u64 tx_offload_frames
;
92 u64 rx_bcast_bytes
; /* broadcast */
94 u64 rx_mcast_bytes
; /* multicast */
97 u64 rx_ucast_frames
; /* unicast */
99 u64 rx_err_frames
; /* RX error frames */
103 * Per-"port" (Virtual Interface) link configuration ...
106 unsigned int supported
; /* link capabilities */
107 unsigned int advertising
; /* advertised capabilities */
108 unsigned short requested_speed
; /* speed user has requested */
109 unsigned short speed
; /* actual link speed */
110 unsigned char requested_fc
; /* flow control user has requested */
111 unsigned char fc
; /* actual link flow control */
112 unsigned char autoneg
; /* autonegotiating? */
113 unsigned char link_ok
; /* link up? */
119 PAUSE_AUTONEG
= 1 << 2
123 * General device parameters ...
126 u32 fwrev
; /* firmware version */
127 u32 tprev
; /* TP Microcode Version */
131 * Scatter Gather Engine parameters. These are almost all determined by the
132 * Physical Function Driver. We just need to grab them to see within which
133 * environment we're playing ...
136 u32 sge_control
; /* padding, boundaries, lengths, etc. */
137 u32 sge_host_page_size
; /* RDMA page sizes */
138 u32 sge_queues_per_page
; /* RDMA queues/page */
139 u32 sge_user_mode_limits
; /* limits for BAR2 user mode accesses */
140 u32 sge_fl_buffer_size
[16]; /* free list buffer sizes */
141 u32 sge_ingress_rx_threshold
; /* RX counter interrupt threshold[4] */
142 u32 sge_timer_value_0_and_1
; /* interrupt coalescing timer values */
143 u32 sge_timer_value_2_and_3
;
144 u32 sge_timer_value_4_and_5
;
148 * Vital Product Data parameters.
151 u32 cclk
; /* Core Clock (KHz) */
155 * Global Receive Side Scaling (RSS) parameters in host-native format.
158 unsigned int mode
; /* RSS mode */
161 unsigned int synmapen
:1; /* SYN Map Enable */
162 unsigned int syn4tupenipv6
:1; /* enable hashing 4-tuple IPv6 SYNs */
163 unsigned int syn2tupenipv6
:1; /* enable hashing 2-tuple IPv6 SYNs */
164 unsigned int syn4tupenipv4
:1; /* enable hashing 4-tuple IPv4 SYNs */
165 unsigned int syn2tupenipv4
:1; /* enable hashing 2-tuple IPv4 SYNs */
166 unsigned int ofdmapen
:1; /* Offload Map Enable */
167 unsigned int tnlmapen
:1; /* Tunnel Map Enable */
168 unsigned int tnlalllookup
:1; /* Tunnel All Lookup */
169 unsigned int hashtoeplitz
:1; /* use Toeplitz hash */
175 * Virtual Interface RSS Configuration in host-native format.
177 union rss_vi_config
{
179 u16 defaultq
; /* Ingress Queue ID for !tnlalllookup */
180 unsigned int ip6fourtupen
:1; /* hash 4-tuple IPv6 ingress packets */
181 unsigned int ip6twotupen
:1; /* hash 2-tuple IPv6 ingress packets */
182 unsigned int ip4fourtupen
:1; /* hash 4-tuple IPv4 ingress packets */
183 unsigned int ip4twotupen
:1; /* hash 2-tuple IPv4 ingress packets */
184 int udpen
; /* hash 4-tuple UDP ingress packets */
189 * Maximum resources provisioned for a PCI VF.
191 struct vf_resources
{
192 unsigned int nvi
; /* N virtual interfaces */
193 unsigned int neq
; /* N egress Qs */
194 unsigned int nethctrl
; /* N egress ETH or CTRL Qs */
195 unsigned int niqflint
; /* N ingress Qs/w free list(s) & intr */
196 unsigned int niq
; /* N ingress Qs */
197 unsigned int tc
; /* PCI-E traffic class */
198 unsigned int pmask
; /* port access rights mask */
199 unsigned int nexactf
; /* N exact MPS filters */
200 unsigned int r_caps
; /* read capabilities */
201 unsigned int wx_caps
; /* write/execute capabilities */
205 * Per-"adapter" (Virtual Function) parameters.
207 struct adapter_params
{
208 struct dev_params dev
; /* general device parameters */
209 struct sge_params sge
; /* Scatter Gather Engine */
210 struct vpd_params vpd
; /* Vital Product Data */
211 struct rss_params rss
; /* Receive Side Scaling */
212 struct vf_resources vfres
; /* Virtual Function Resource limits */
213 enum chip_type chip
; /* chip code */
214 u8 nports
; /* # of Ethernet "ports" */
219 #ifndef PCI_VENDOR_ID_CHELSIO
220 # define PCI_VENDOR_ID_CHELSIO 0x1425
223 #define for_each_port(adapter, iter) \
224 for (iter = 0; iter < (adapter)->params.nports; iter++)
226 static inline bool is_10g_port(const struct link_config
*lc
)
228 return (lc
->supported
& SUPPORTED_10000baseT_Full
) != 0;
231 static inline unsigned int core_ticks_per_usec(const struct adapter
*adapter
)
233 return adapter
->params
.vpd
.cclk
/ 1000;
236 static inline unsigned int us_to_core_ticks(const struct adapter
*adapter
,
239 return (us
* adapter
->params
.vpd
.cclk
) / 1000;
242 static inline unsigned int core_ticks_to_us(const struct adapter
*adapter
,
245 return (ticks
* 1000) / adapter
->params
.vpd
.cclk
;
248 int t4vf_wr_mbox_core(struct adapter
*, const void *, int, void *, bool);
250 static inline int t4vf_wr_mbox(struct adapter
*adapter
, const void *cmd
,
253 return t4vf_wr_mbox_core(adapter
, cmd
, size
, rpl
, true);
256 static inline int t4vf_wr_mbox_ns(struct adapter
*adapter
, const void *cmd
,
259 return t4vf_wr_mbox_core(adapter
, cmd
, size
, rpl
, false);
262 static inline int is_t4(enum chip_type chip
)
264 return CHELSIO_CHIP_VERSION(chip
) == CHELSIO_T4
;
267 int t4vf_wait_dev_ready(struct adapter
*);
268 int t4vf_port_init(struct adapter
*, int);
270 int t4vf_fw_reset(struct adapter
*);
271 int t4vf_set_params(struct adapter
*, unsigned int, const u32
*, const u32
*);
273 int t4vf_get_sge_params(struct adapter
*);
274 int t4vf_get_vpd_params(struct adapter
*);
275 int t4vf_get_dev_params(struct adapter
*);
276 int t4vf_get_rss_glb_config(struct adapter
*);
277 int t4vf_get_vfres(struct adapter
*);
279 int t4vf_read_rss_vi_config(struct adapter
*, unsigned int,
280 union rss_vi_config
*);
281 int t4vf_write_rss_vi_config(struct adapter
*, unsigned int,
282 union rss_vi_config
*);
283 int t4vf_config_rss_range(struct adapter
*, unsigned int, int, int,
286 int t4vf_alloc_vi(struct adapter
*, int);
287 int t4vf_free_vi(struct adapter
*, int);
288 int t4vf_enable_vi(struct adapter
*, unsigned int, bool, bool);
289 int t4vf_identify_port(struct adapter
*, unsigned int, unsigned int);
291 int t4vf_set_rxmode(struct adapter
*, unsigned int, int, int, int, int, int,
293 int t4vf_alloc_mac_filt(struct adapter
*, unsigned int, bool, unsigned int,
294 const u8
**, u16
*, u64
*, bool);
295 int t4vf_change_mac(struct adapter
*, unsigned int, int, const u8
*, bool);
296 int t4vf_set_addr_hash(struct adapter
*, unsigned int, bool, u64
, bool);
297 int t4vf_get_port_stats(struct adapter
*, int, struct t4vf_port_stats
*);
299 int t4vf_iq_free(struct adapter
*, unsigned int, unsigned int, unsigned int,
301 int t4vf_eth_eq_free(struct adapter
*, unsigned int);
303 int t4vf_handle_fw_rpl(struct adapter
*, const __be64
*);
305 #endif /* __T4VF_COMMON_H__ */