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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / ethernet / nvidia / forcedeth.c
blob70cf97fe67f2d0e63439d8d684f0244a212caa22
1 /*
2 * forcedeth: Ethernet driver for NVIDIA nForce media access controllers.
3 *
4 * Note: This driver is a cleanroom reimplementation based on reverse
5 * engineered documentation written by Carl-Daniel Hailfinger
6 * and Andrew de Quincey.
7 *
8 * NVIDIA, nForce and other NVIDIA marks are trademarks or registered
9 * trademarks of NVIDIA Corporation in the United States and other
10 * countries.
11 *
12 * Copyright (C) 2003,4,5 Manfred Spraul
13 * Copyright (C) 2004 Andrew de Quincey (wol support)
14 * Copyright (C) 2004 Carl-Daniel Hailfinger (invalid MAC handling, insane
15 * IRQ rate fixes, bigendian fixes, cleanups, verification)
16 * Copyright (c) 2004,2005,2006,2007,2008,2009 NVIDIA Corporation
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
22 *
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
27 *
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, see <http://www.gnu.org/licenses/>.
30 *
31 * Known bugs:
32 * We suspect that on some hardware no TX done interrupts are generated.
33 * This means recovery from netif_stop_queue only happens if the hw timer
34 * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT)
35 * and the timer is active in the IRQMask, or if a rx packet arrives by chance.
36 * If your hardware reliably generates tx done interrupts, then you can remove
37 * DEV_NEED_TIMERIRQ from the driver_data flags.
38 * DEV_NEED_TIMERIRQ will not harm you on sane hardware, only generating a few
39 * superfluous timer interrupts from the nic.
40 */
41
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44 #define FORCEDETH_VERSION "0.64"
45 #define DRV_NAME "forcedeth"
46
47 #include <linux/module.h>
48 #include <linux/types.h>
49 #include <linux/pci.h>
50 #include <linux/interrupt.h>
51 #include <linux/netdevice.h>
52 #include <linux/etherdevice.h>
53 #include <linux/delay.h>
54 #include <linux/sched.h>
55 #include <linux/spinlock.h>
56 #include <linux/ethtool.h>
57 #include <linux/timer.h>
58 #include <linux/skbuff.h>
59 #include <linux/mii.h>
60 #include <linux/random.h>
61 #include <linux/if_vlan.h>
62 #include <linux/dma-mapping.h>
63 #include <linux/slab.h>
64 #include <linux/uaccess.h>
65 #include <linux/prefetch.h>
66 #include <linux/u64_stats_sync.h>
67 #include <linux/io.h>
68
69 #include <asm/irq.h>
70
71 #define TX_WORK_PER_LOOP 64
72 #define RX_WORK_PER_LOOP 64
73
74 /*
75 * Hardware access:
76 */
77
78 #define DEV_NEED_TIMERIRQ 0x0000001 /* set the timer irq flag in the irq mask */
79 #define DEV_NEED_LINKTIMER 0x0000002 /* poll link settings. Relies on the timer irq */
80 #define DEV_HAS_LARGEDESC 0x0000004 /* device supports jumbo frames and needs packet format 2 */
81 #define DEV_HAS_HIGH_DMA 0x0000008 /* device supports 64bit dma */
82 #define DEV_HAS_CHECKSUM 0x0000010 /* device supports tx and rx checksum offloads */
83 #define DEV_HAS_VLAN 0x0000020 /* device supports vlan tagging and striping */
84 #define DEV_HAS_MSI 0x0000040 /* device supports MSI */
85 #define DEV_HAS_MSI_X 0x0000080 /* device supports MSI-X */
86 #define DEV_HAS_POWER_CNTRL 0x0000100 /* device supports power savings */
87 #define DEV_HAS_STATISTICS_V1 0x0000200 /* device supports hw statistics version 1 */
88 #define DEV_HAS_STATISTICS_V2 0x0000400 /* device supports hw statistics version 2 */
89 #define DEV_HAS_STATISTICS_V3 0x0000800 /* device supports hw statistics version 3 */
90 #define DEV_HAS_STATISTICS_V12 0x0000600 /* device supports hw statistics version 1 and 2 */
91 #define DEV_HAS_STATISTICS_V123 0x0000e00 /* device supports hw statistics version 1, 2, and 3 */
92 #define DEV_HAS_TEST_EXTENDED 0x0001000 /* device supports extended diagnostic test */
93 #define DEV_HAS_MGMT_UNIT 0x0002000 /* device supports management unit */
94 #define DEV_HAS_CORRECT_MACADDR 0x0004000 /* device supports correct mac address order */
95 #define DEV_HAS_COLLISION_FIX 0x0008000 /* device supports tx collision fix */
96 #define DEV_HAS_PAUSEFRAME_TX_V1 0x0010000 /* device supports tx pause frames version 1 */
97 #define DEV_HAS_PAUSEFRAME_TX_V2 0x0020000 /* device supports tx pause frames version 2 */
98 #define DEV_HAS_PAUSEFRAME_TX_V3 0x0040000 /* device supports tx pause frames version 3 */
99 #define DEV_NEED_TX_LIMIT 0x0080000 /* device needs to limit tx */
100 #define DEV_NEED_TX_LIMIT2 0x0180000 /* device needs to limit tx, expect for some revs */
101 #define DEV_HAS_GEAR_MODE 0x0200000 /* device supports gear mode */
102 #define DEV_NEED_PHY_INIT_FIX 0x0400000 /* device needs specific phy workaround */
103 #define DEV_NEED_LOW_POWER_FIX 0x0800000 /* device needs special power up workaround */
104 #define DEV_NEED_MSI_FIX 0x1000000 /* device needs msi workaround */
105
106 enum {
107 NvRegIrqStatus = 0x000,
108 #define NVREG_IRQSTAT_MIIEVENT 0x040
109 #define NVREG_IRQSTAT_MASK 0x83ff
110 NvRegIrqMask = 0x004,
111 #define NVREG_IRQ_RX_ERROR 0x0001
112 #define NVREG_IRQ_RX 0x0002
113 #define NVREG_IRQ_RX_NOBUF 0x0004
114 #define NVREG_IRQ_TX_ERR 0x0008
115 #define NVREG_IRQ_TX_OK 0x0010
116 #define NVREG_IRQ_TIMER 0x0020
117 #define NVREG_IRQ_LINK 0x0040
118 #define NVREG_IRQ_RX_FORCED 0x0080
119 #define NVREG_IRQ_TX_FORCED 0x0100
120 #define NVREG_IRQ_RECOVER_ERROR 0x8200
121 #define NVREG_IRQMASK_THROUGHPUT 0x00df
122 #define NVREG_IRQMASK_CPU 0x0060
123 #define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED)
124 #define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED)
125 #define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR)
126
127 NvRegUnknownSetupReg6 = 0x008,
128 #define NVREG_UNKSETUP6_VAL 3
129
130 /*
131 * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
132 * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
133 */
134 NvRegPollingInterval = 0x00c,
135 #define NVREG_POLL_DEFAULT_THROUGHPUT 65535 /* backup tx cleanup if loop max reached */
136 #define NVREG_POLL_DEFAULT_CPU 13
137 NvRegMSIMap0 = 0x020,
138 NvRegMSIMap1 = 0x024,
139 NvRegMSIIrqMask = 0x030,
140 #define NVREG_MSI_VECTOR_0_ENABLED 0x01
141 NvRegMisc1 = 0x080,
142 #define NVREG_MISC1_PAUSE_TX 0x01
143 #define NVREG_MISC1_HD 0x02
144 #define NVREG_MISC1_FORCE 0x3b0f3c
145
146 NvRegMacReset = 0x34,
147 #define NVREG_MAC_RESET_ASSERT 0x0F3
148 NvRegTransmitterControl = 0x084,
149 #define NVREG_XMITCTL_START 0x01
150 #define NVREG_XMITCTL_MGMT_ST 0x40000000
151 #define NVREG_XMITCTL_SYNC_MASK 0x000f0000
152 #define NVREG_XMITCTL_SYNC_NOT_READY 0x0
153 #define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000
154 #define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00
155 #define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0
156 #define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000
157 #define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000
158 #define NVREG_XMITCTL_HOST_LOADED 0x00004000
159 #define NVREG_XMITCTL_TX_PATH_EN 0x01000000
160 #define NVREG_XMITCTL_DATA_START 0x00100000
161 #define NVREG_XMITCTL_DATA_READY 0x00010000
162 #define NVREG_XMITCTL_DATA_ERROR 0x00020000
163 NvRegTransmitterStatus = 0x088,
164 #define NVREG_XMITSTAT_BUSY 0x01
165
166 NvRegPacketFilterFlags = 0x8c,
167 #define NVREG_PFF_PAUSE_RX 0x08
168 #define NVREG_PFF_ALWAYS 0x7F0000
169 #define NVREG_PFF_PROMISC 0x80
170 #define NVREG_PFF_MYADDR 0x20
171 #define NVREG_PFF_LOOPBACK 0x10
172
173 NvRegOffloadConfig = 0x90,
174 #define NVREG_OFFLOAD_HOMEPHY 0x601
175 #define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
176 NvRegReceiverControl = 0x094,
177 #define NVREG_RCVCTL_START 0x01
178 #define NVREG_RCVCTL_RX_PATH_EN 0x01000000
179 NvRegReceiverStatus = 0x98,
180 #define NVREG_RCVSTAT_BUSY 0x01
181
182 NvRegSlotTime = 0x9c,
183 #define NVREG_SLOTTIME_LEGBF_ENABLED 0x80000000
184 #define NVREG_SLOTTIME_10_100_FULL 0x00007f00
185 #define NVREG_SLOTTIME_1000_FULL 0x0003ff00
186 #define NVREG_SLOTTIME_HALF 0x0000ff00
187 #define NVREG_SLOTTIME_DEFAULT 0x00007f00
188 #define NVREG_SLOTTIME_MASK 0x000000ff
189
190 NvRegTxDeferral = 0xA0,
191 #define NVREG_TX_DEFERRAL_DEFAULT 0x15050f
192 #define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f
193 #define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f
194 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f
195 #define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f
196 #define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000
197 NvRegRxDeferral = 0xA4,
198 #define NVREG_RX_DEFERRAL_DEFAULT 0x16
199 NvRegMacAddrA = 0xA8,
200 NvRegMacAddrB = 0xAC,
201 NvRegMulticastAddrA = 0xB0,
202 #define NVREG_MCASTADDRA_FORCE 0x01
203 NvRegMulticastAddrB = 0xB4,
204 NvRegMulticastMaskA = 0xB8,
205 #define NVREG_MCASTMASKA_NONE 0xffffffff
206 NvRegMulticastMaskB = 0xBC,
207 #define NVREG_MCASTMASKB_NONE 0xffff
208
209 NvRegPhyInterface = 0xC0,
210 #define PHY_RGMII 0x10000000
211 NvRegBackOffControl = 0xC4,
212 #define NVREG_BKOFFCTRL_DEFAULT 0x70000000
213 #define NVREG_BKOFFCTRL_SEED_MASK 0x000003ff
214 #define NVREG_BKOFFCTRL_SELECT 24
215 #define NVREG_BKOFFCTRL_GEAR 12
216
217 NvRegTxRingPhysAddr = 0x100,
218 NvRegRxRingPhysAddr = 0x104,
219 NvRegRingSizes = 0x108,
220 #define NVREG_RINGSZ_TXSHIFT 0
221 #define NVREG_RINGSZ_RXSHIFT 16
222 NvRegTransmitPoll = 0x10c,
223 #define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000
224 NvRegLinkSpeed = 0x110,
225 #define NVREG_LINKSPEED_FORCE 0x10000
226 #define NVREG_LINKSPEED_10 1000
227 #define NVREG_LINKSPEED_100 100
228 #define NVREG_LINKSPEED_1000 50
229 #define NVREG_LINKSPEED_MASK (0xFFF)
230 NvRegUnknownSetupReg5 = 0x130,
231 #define NVREG_UNKSETUP5_BIT31 (1<<31)
232 NvRegTxWatermark = 0x13c,
233 #define NVREG_TX_WM_DESC1_DEFAULT 0x0200010
234 #define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000
235 #define NVREG_TX_WM_DESC2_3_1000 0xfe08000
236 NvRegTxRxControl = 0x144,
237 #define NVREG_TXRXCTL_KICK 0x0001
238 #define NVREG_TXRXCTL_BIT1 0x0002
239 #define NVREG_TXRXCTL_BIT2 0x0004
240 #define NVREG_TXRXCTL_IDLE 0x0008
241 #define NVREG_TXRXCTL_RESET 0x0010
242 #define NVREG_TXRXCTL_RXCHECK 0x0400
243 #define NVREG_TXRXCTL_DESC_1 0
244 #define NVREG_TXRXCTL_DESC_2 0x002100
245 #define NVREG_TXRXCTL_DESC_3 0xc02200
246 #define NVREG_TXRXCTL_VLANSTRIP 0x00040
247 #define NVREG_TXRXCTL_VLANINS 0x00080
248 NvRegTxRingPhysAddrHigh = 0x148,
249 NvRegRxRingPhysAddrHigh = 0x14C,
250 NvRegTxPauseFrame = 0x170,
251 #define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080
252 #define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010
253 #define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0
254 #define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880
255 NvRegTxPauseFrameLimit = 0x174,
256 #define NVREG_TX_PAUSEFRAMELIMIT_ENABLE 0x00010000
257 NvRegMIIStatus = 0x180,
258 #define NVREG_MIISTAT_ERROR 0x0001
259 #define NVREG_MIISTAT_LINKCHANGE 0x0008
260 #define NVREG_MIISTAT_MASK_RW 0x0007
261 #define NVREG_MIISTAT_MASK_ALL 0x000f
262 NvRegMIIMask = 0x184,
263 #define NVREG_MII_LINKCHANGE 0x0008
264
265 NvRegAdapterControl = 0x188,
266 #define NVREG_ADAPTCTL_START 0x02
267 #define NVREG_ADAPTCTL_LINKUP 0x04
268 #define NVREG_ADAPTCTL_PHYVALID 0x40000
269 #define NVREG_ADAPTCTL_RUNNING 0x100000
270 #define NVREG_ADAPTCTL_PHYSHIFT 24
271 NvRegMIISpeed = 0x18c,
272 #define NVREG_MIISPEED_BIT8 (1<<8)
273 #define NVREG_MIIDELAY 5
274 NvRegMIIControl = 0x190,
275 #define NVREG_MIICTL_INUSE 0x08000
276 #define NVREG_MIICTL_WRITE 0x00400
277 #define NVREG_MIICTL_ADDRSHIFT 5
278 NvRegMIIData = 0x194,
279 NvRegTxUnicast = 0x1a0,
280 NvRegTxMulticast = 0x1a4,
281 NvRegTxBroadcast = 0x1a8,
282 NvRegWakeUpFlags = 0x200,
283 #define NVREG_WAKEUPFLAGS_VAL 0x7770
284 #define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
285 #define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
286 #define NVREG_WAKEUPFLAGS_D3SHIFT 12
287 #define NVREG_WAKEUPFLAGS_D2SHIFT 8
288 #define NVREG_WAKEUPFLAGS_D1SHIFT 4
289 #define NVREG_WAKEUPFLAGS_D0SHIFT 0
290 #define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
291 #define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
292 #define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
293 #define NVREG_WAKEUPFLAGS_ENABLE 0x1111
294
295 NvRegMgmtUnitGetVersion = 0x204,
296 #define NVREG_MGMTUNITGETVERSION 0x01
297 NvRegMgmtUnitVersion = 0x208,
298 #define NVREG_MGMTUNITVERSION 0x08
299 NvRegPowerCap = 0x268,
300 #define NVREG_POWERCAP_D3SUPP (1<<30)
301 #define NVREG_POWERCAP_D2SUPP (1<<26)
302 #define NVREG_POWERCAP_D1SUPP (1<<25)
303 NvRegPowerState = 0x26c,
304 #define NVREG_POWERSTATE_POWEREDUP 0x8000
305 #define NVREG_POWERSTATE_VALID 0x0100
306 #define NVREG_POWERSTATE_MASK 0x0003
307 #define NVREG_POWERSTATE_D0 0x0000
308 #define NVREG_POWERSTATE_D1 0x0001
309 #define NVREG_POWERSTATE_D2 0x0002
310 #define NVREG_POWERSTATE_D3 0x0003
311 NvRegMgmtUnitControl = 0x278,
312 #define NVREG_MGMTUNITCONTROL_INUSE 0x20000
313 NvRegTxCnt = 0x280,
314 NvRegTxZeroReXmt = 0x284,
315 NvRegTxOneReXmt = 0x288,
316 NvRegTxManyReXmt = 0x28c,
317 NvRegTxLateCol = 0x290,
318 NvRegTxUnderflow = 0x294,
319 NvRegTxLossCarrier = 0x298,
320 NvRegTxExcessDef = 0x29c,
321 NvRegTxRetryErr = 0x2a0,
322 NvRegRxFrameErr = 0x2a4,
323 NvRegRxExtraByte = 0x2a8,
324 NvRegRxLateCol = 0x2ac,
325 NvRegRxRunt = 0x2b0,
326 NvRegRxFrameTooLong = 0x2b4,
327 NvRegRxOverflow = 0x2b8,
328 NvRegRxFCSErr = 0x2bc,
329 NvRegRxFrameAlignErr = 0x2c0,
330 NvRegRxLenErr = 0x2c4,
331 NvRegRxUnicast = 0x2c8,
332 NvRegRxMulticast = 0x2cc,
333 NvRegRxBroadcast = 0x2d0,
334 NvRegTxDef = 0x2d4,
335 NvRegTxFrame = 0x2d8,
336 NvRegRxCnt = 0x2dc,
337 NvRegTxPause = 0x2e0,
338 NvRegRxPause = 0x2e4,
339 NvRegRxDropFrame = 0x2e8,
340 NvRegVlanControl = 0x300,
341 #define NVREG_VLANCONTROL_ENABLE 0x2000
342 NvRegMSIXMap0 = 0x3e0,
343 NvRegMSIXMap1 = 0x3e4,
344 NvRegMSIXIrqStatus = 0x3f0,
345
346 NvRegPowerState2 = 0x600,
347 #define NVREG_POWERSTATE2_POWERUP_MASK 0x0F15
348 #define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001
349 #define NVREG_POWERSTATE2_PHY_RESET 0x0004
350 #define NVREG_POWERSTATE2_GATE_CLOCKS 0x0F00
351 };
352
353 /* Big endian: should work, but is untested */
354 struct ring_desc {
355 __le32 buf;
356 __le32 flaglen;
357 };
358
359 struct ring_desc_ex {
360 __le32 bufhigh;
361 __le32 buflow;
362 __le32 txvlan;
363 __le32 flaglen;
364 };
365
366 union ring_type {
367 struct ring_desc *orig;
368 struct ring_desc_ex *ex;
369 };
370
371 #define FLAG_MASK_V1 0xffff0000
372 #define FLAG_MASK_V2 0xffffc000
373 #define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
374 #define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
375
376 #define NV_TX_LASTPACKET (1<<16)
377 #define NV_TX_RETRYERROR (1<<19)
378 #define NV_TX_RETRYCOUNT_MASK (0xF<<20)
379 #define NV_TX_FORCED_INTERRUPT (1<<24)
380 #define NV_TX_DEFERRED (1<<26)
381 #define NV_TX_CARRIERLOST (1<<27)
382 #define NV_TX_LATECOLLISION (1<<28)
383 #define NV_TX_UNDERFLOW (1<<29)
384 #define NV_TX_ERROR (1<<30)
385 #define NV_TX_VALID (1<<31)
386
387 #define NV_TX2_LASTPACKET (1<<29)
388 #define NV_TX2_RETRYERROR (1<<18)
389 #define NV_TX2_RETRYCOUNT_MASK (0xF<<19)
390 #define NV_TX2_FORCED_INTERRUPT (1<<30)
391 #define NV_TX2_DEFERRED (1<<25)
392 #define NV_TX2_CARRIERLOST (1<<26)
393 #define NV_TX2_LATECOLLISION (1<<27)
394 #define NV_TX2_UNDERFLOW (1<<28)
395 /* error and valid are the same for both */
396 #define NV_TX2_ERROR (1<<30)
397 #define NV_TX2_VALID (1<<31)
398 #define NV_TX2_TSO (1<<28)
399 #define NV_TX2_TSO_SHIFT 14
400 #define NV_TX2_TSO_MAX_SHIFT 14
401 #define NV_TX2_TSO_MAX_SIZE (1<<NV_TX2_TSO_MAX_SHIFT)
402 #define NV_TX2_CHECKSUM_L3 (1<<27)
403 #define NV_TX2_CHECKSUM_L4 (1<<26)
404
405 #define NV_TX3_VLAN_TAG_PRESENT (1<<18)
406
407 #define NV_RX_DESCRIPTORVALID (1<<16)
408 #define NV_RX_MISSEDFRAME (1<<17)
409 #define NV_RX_SUBSTRACT1 (1<<18)
410 #define NV_RX_ERROR1 (1<<23)
411 #define NV_RX_ERROR2 (1<<24)
412 #define NV_RX_ERROR3 (1<<25)
413 #define NV_RX_ERROR4 (1<<26)
414 #define NV_RX_CRCERR (1<<27)
415 #define NV_RX_OVERFLOW (1<<28)
416 #define NV_RX_FRAMINGERR (1<<29)
417 #define NV_RX_ERROR (1<<30)
418 #define NV_RX_AVAIL (1<<31)
419 #define NV_RX_ERROR_MASK (NV_RX_ERROR1|NV_RX_ERROR2|NV_RX_ERROR3|NV_RX_ERROR4|NV_RX_CRCERR|NV_RX_OVERFLOW|NV_RX_FRAMINGERR)
420
421 #define NV_RX2_CHECKSUMMASK (0x1C000000)
422 #define NV_RX2_CHECKSUM_IP (0x10000000)
423 #define NV_RX2_CHECKSUM_IP_TCP (0x14000000)
424 #define NV_RX2_CHECKSUM_IP_UDP (0x18000000)
425 #define NV_RX2_DESCRIPTORVALID (1<<29)
426 #define NV_RX2_SUBSTRACT1 (1<<25)
427 #define NV_RX2_ERROR1 (1<<18)
428 #define NV_RX2_ERROR2 (1<<19)
429 #define NV_RX2_ERROR3 (1<<20)
430 #define NV_RX2_ERROR4 (1<<21)
431 #define NV_RX2_CRCERR (1<<22)
432 #define NV_RX2_OVERFLOW (1<<23)
433 #define NV_RX2_FRAMINGERR (1<<24)
434 /* error and avail are the same for both */
435 #define NV_RX2_ERROR (1<<30)
436 #define NV_RX2_AVAIL (1<<31)
437 #define NV_RX2_ERROR_MASK (NV_RX2_ERROR1|NV_RX2_ERROR2|NV_RX2_ERROR3|NV_RX2_ERROR4|NV_RX2_CRCERR|NV_RX2_OVERFLOW|NV_RX2_FRAMINGERR)
438
439 #define NV_RX3_VLAN_TAG_PRESENT (1<<16)
440 #define NV_RX3_VLAN_TAG_MASK (0x0000FFFF)
441
442 /* Miscellaneous hardware related defines: */
443 #define NV_PCI_REGSZ_VER1 0x270
444 #define NV_PCI_REGSZ_VER2 0x2d4
445 #define NV_PCI_REGSZ_VER3 0x604
446 #define NV_PCI_REGSZ_MAX 0x604
447
448 /* various timeout delays: all in usec */
449 #define NV_TXRX_RESET_DELAY 4
450 #define NV_TXSTOP_DELAY1 10
451 #define NV_TXSTOP_DELAY1MAX 500000
452 #define NV_TXSTOP_DELAY2 100
453 #define NV_RXSTOP_DELAY1 10
454 #define NV_RXSTOP_DELAY1MAX 500000
455 #define NV_RXSTOP_DELAY2 100
456 #define NV_SETUP5_DELAY 5
457 #define NV_SETUP5_DELAYMAX 50000
458 #define NV_POWERUP_DELAY 5
459 #define NV_POWERUP_DELAYMAX 5000
460 #define NV_MIIBUSY_DELAY 50
461 #define NV_MIIPHY_DELAY 10
462 #define NV_MIIPHY_DELAYMAX 10000
463 #define NV_MAC_RESET_DELAY 64
464
465 #define NV_WAKEUPPATTERNS 5
466 #define NV_WAKEUPMASKENTRIES 4
467
468 /* General driver defaults */
469 #define NV_WATCHDOG_TIMEO (5*HZ)
470
471 #define RX_RING_DEFAULT 512
472 #define TX_RING_DEFAULT 256
473 #define RX_RING_MIN 128
474 #define TX_RING_MIN 64
475 #define RING_MAX_DESC_VER_1 1024
476 #define RING_MAX_DESC_VER_2_3 16384
477
478 /* rx/tx mac addr + type + vlan + align + slack*/
479 #define NV_RX_HEADERS (64)
480 /* even more slack. */
481 #define NV_RX_ALLOC_PAD (64)
482
483 /* maximum mtu size */
484 #define NV_PKTLIMIT_1 ETH_DATA_LEN /* hard limit not known */
485 #define NV_PKTLIMIT_2 9100 /* Actual limit according to NVidia: 9202 */
486
487 #define OOM_REFILL (1+HZ/20)
488 #define POLL_WAIT (1+HZ/100)
489 #define LINK_TIMEOUT (3*HZ)
490 #define STATS_INTERVAL (10*HZ)
491
492 /*
493 * desc_ver values:
494 * The nic supports three different descriptor types:
495 * - DESC_VER_1: Original
496 * - DESC_VER_2: support for jumbo frames.
497 * - DESC_VER_3: 64-bit format.
498 */
499 #define DESC_VER_1 1
500 #define DESC_VER_2 2
501 #define DESC_VER_3 3
502
503 /* PHY defines */
504 #define PHY_OUI_MARVELL 0x5043
505 #define PHY_OUI_CICADA 0x03f1
506 #define PHY_OUI_VITESSE 0x01c1
507 #define PHY_OUI_REALTEK 0x0732
508 #define PHY_OUI_REALTEK2 0x0020
509 #define PHYID1_OUI_MASK 0x03ff
510 #define PHYID1_OUI_SHFT 6
511 #define PHYID2_OUI_MASK 0xfc00
512 #define PHYID2_OUI_SHFT 10
513 #define PHYID2_MODEL_MASK 0x03f0
514 #define PHY_MODEL_REALTEK_8211 0x0110
515 #define PHY_REV_MASK 0x0001
516 #define PHY_REV_REALTEK_8211B 0x0000
517 #define PHY_REV_REALTEK_8211C 0x0001
518 #define PHY_MODEL_REALTEK_8201 0x0200
519 #define PHY_MODEL_MARVELL_E3016 0x0220
520 #define PHY_MARVELL_E3016_INITMASK 0x0300
521 #define PHY_CICADA_INIT1 0x0f000
522 #define PHY_CICADA_INIT2 0x0e00
523 #define PHY_CICADA_INIT3 0x01000
524 #define PHY_CICADA_INIT4 0x0200
525 #define PHY_CICADA_INIT5 0x0004
526 #define PHY_CICADA_INIT6 0x02000
527 #define PHY_VITESSE_INIT_REG1 0x1f
528 #define PHY_VITESSE_INIT_REG2 0x10
529 #define PHY_VITESSE_INIT_REG3 0x11
530 #define PHY_VITESSE_INIT_REG4 0x12
531 #define PHY_VITESSE_INIT_MSK1 0xc
532 #define PHY_VITESSE_INIT_MSK2 0x0180
533 #define PHY_VITESSE_INIT1 0x52b5
534 #define PHY_VITESSE_INIT2 0xaf8a
535 #define PHY_VITESSE_INIT3 0x8
536 #define PHY_VITESSE_INIT4 0x8f8a
537 #define PHY_VITESSE_INIT5 0xaf86
538 #define PHY_VITESSE_INIT6 0x8f86
539 #define PHY_VITESSE_INIT7 0xaf82
540 #define PHY_VITESSE_INIT8 0x0100
541 #define PHY_VITESSE_INIT9 0x8f82
542 #define PHY_VITESSE_INIT10 0x0
543 #define PHY_REALTEK_INIT_REG1 0x1f
544 #define PHY_REALTEK_INIT_REG2 0x19
545 #define PHY_REALTEK_INIT_REG3 0x13
546 #define PHY_REALTEK_INIT_REG4 0x14
547 #define PHY_REALTEK_INIT_REG5 0x18
548 #define PHY_REALTEK_INIT_REG6 0x11
549 #define PHY_REALTEK_INIT_REG7 0x01
550 #define PHY_REALTEK_INIT1 0x0000
551 #define PHY_REALTEK_INIT2 0x8e00
552 #define PHY_REALTEK_INIT3 0x0001
553 #define PHY_REALTEK_INIT4 0xad17
554 #define PHY_REALTEK_INIT5 0xfb54
555 #define PHY_REALTEK_INIT6 0xf5c7
556 #define PHY_REALTEK_INIT7 0x1000
557 #define PHY_REALTEK_INIT8 0x0003
558 #define PHY_REALTEK_INIT9 0x0008
559 #define PHY_REALTEK_INIT10 0x0005
560 #define PHY_REALTEK_INIT11 0x0200
561 #define PHY_REALTEK_INIT_MSK1 0x0003
562
563 #define PHY_GIGABIT 0x0100
564
565 #define PHY_TIMEOUT 0x1
566 #define PHY_ERROR 0x2
567
568 #define PHY_100 0x1
569 #define PHY_1000 0x2
570 #define PHY_HALF 0x100
571
572 #define NV_PAUSEFRAME_RX_CAPABLE 0x0001
573 #define NV_PAUSEFRAME_TX_CAPABLE 0x0002
574 #define NV_PAUSEFRAME_RX_ENABLE 0x0004
575 #define NV_PAUSEFRAME_TX_ENABLE 0x0008
576 #define NV_PAUSEFRAME_RX_REQ 0x0010
577 #define NV_PAUSEFRAME_TX_REQ 0x0020
578 #define NV_PAUSEFRAME_AUTONEG 0x0040
579
580 /* MSI/MSI-X defines */
581 #define NV_MSI_X_MAX_VECTORS 8
582 #define NV_MSI_X_VECTORS_MASK 0x000f
583 #define NV_MSI_CAPABLE 0x0010
584 #define NV_MSI_X_CAPABLE 0x0020
585 #define NV_MSI_ENABLED 0x0040
586 #define NV_MSI_X_ENABLED 0x0080
587
588 #define NV_MSI_X_VECTOR_ALL 0x0
589 #define NV_MSI_X_VECTOR_RX 0x0
590 #define NV_MSI_X_VECTOR_TX 0x1
591 #define NV_MSI_X_VECTOR_OTHER 0x2
592
593 #define NV_MSI_PRIV_OFFSET 0x68
594 #define NV_MSI_PRIV_VALUE 0xffffffff
595
596 #define NV_RESTART_TX 0x1
597 #define NV_RESTART_RX 0x2
598
599 #define NV_TX_LIMIT_COUNT 16
600
601 #define NV_DYNAMIC_THRESHOLD 4
602 #define NV_DYNAMIC_MAX_QUIET_COUNT 2048
603
604 /* statistics */
605 struct nv_ethtool_str {
606 char name[ETH_GSTRING_LEN];
607 };
608
609 static const struct nv_ethtool_str nv_estats_str[] = {
610 { "tx_bytes" }, /* includes Ethernet FCS CRC */
611 { "tx_zero_rexmt" },
612 { "tx_one_rexmt" },
613 { "tx_many_rexmt" },
614 { "tx_late_collision" },
615 { "tx_fifo_errors" },
616 { "tx_carrier_errors" },
617 { "tx_excess_deferral" },
618 { "tx_retry_error" },
619 { "rx_frame_error" },
620 { "rx_extra_byte" },
621 { "rx_late_collision" },
622 { "rx_runt" },
623 { "rx_frame_too_long" },
624 { "rx_over_errors" },
625 { "rx_crc_errors" },
626 { "rx_frame_align_error" },
627 { "rx_length_error" },
628 { "rx_unicast" },
629 { "rx_multicast" },
630 { "rx_broadcast" },
631 { "rx_packets" },
632 { "rx_errors_total" },
633 { "tx_errors_total" },
634
635 /* version 2 stats */
636 { "tx_deferral" },
637 { "tx_packets" },
638 { "rx_bytes" }, /* includes Ethernet FCS CRC */
639 { "tx_pause" },
640 { "rx_pause" },
641 { "rx_drop_frame" },
642
643 /* version 3 stats */
644 { "tx_unicast" },
645 { "tx_multicast" },
646 { "tx_broadcast" }
647 };
648
649 struct nv_ethtool_stats {
650 u64 tx_bytes; /* should be ifconfig->tx_bytes + 4*tx_packets */
651 u64 tx_zero_rexmt;
652 u64 tx_one_rexmt;
653 u64 tx_many_rexmt;
654 u64 tx_late_collision;
655 u64 tx_fifo_errors;
656 u64 tx_carrier_errors;
657 u64 tx_excess_deferral;
658 u64 tx_retry_error;
659 u64 rx_frame_error;
660 u64 rx_extra_byte;
661 u64 rx_late_collision;
662 u64 rx_runt;
663 u64 rx_frame_too_long;
664 u64 rx_over_errors;
665 u64 rx_crc_errors;
666 u64 rx_frame_align_error;
667 u64 rx_length_error;
668 u64 rx_unicast;
669 u64 rx_multicast;
670 u64 rx_broadcast;
671 u64 rx_packets; /* should be ifconfig->rx_packets */
672 u64 rx_errors_total;
673 u64 tx_errors_total;
674
675 /* version 2 stats */
676 u64 tx_deferral;
677 u64 tx_packets; /* should be ifconfig->tx_packets */
678 u64 rx_bytes; /* should be ifconfig->rx_bytes + 4*rx_packets */
679 u64 tx_pause;
680 u64 rx_pause;
681 u64 rx_drop_frame;
682
683 /* version 3 stats */
684 u64 tx_unicast;
685 u64 tx_multicast;
686 u64 tx_broadcast;
687 };
688
689 #define NV_DEV_STATISTICS_V3_COUNT (sizeof(struct nv_ethtool_stats)/sizeof(u64))
690 #define NV_DEV_STATISTICS_V2_COUNT (NV_DEV_STATISTICS_V3_COUNT - 3)
691 #define NV_DEV_STATISTICS_V1_COUNT (NV_DEV_STATISTICS_V2_COUNT - 6)
692
693 /* diagnostics */
694 #define NV_TEST_COUNT_BASE 3
695 #define NV_TEST_COUNT_EXTENDED 4
696
697 static const struct nv_ethtool_str nv_etests_str[] = {
698 { "link (online/offline)" },
699 { "register (offline) " },
700 { "interrupt (offline) " },
701 { "loopback (offline) " }
702 };
703
704 struct register_test {
705 __u32 reg;
706 __u32 mask;
707 };
708
709 static const struct register_test nv_registers_test[] = {
710 { NvRegUnknownSetupReg6, 0x01 },
711 { NvRegMisc1, 0x03c },
712 { NvRegOffloadConfig, 0x03ff },
713 { NvRegMulticastAddrA, 0xffffffff },
714 { NvRegTxWatermark, 0x0ff },
715 { NvRegWakeUpFlags, 0x07777 },
716 { 0, 0 }
717 };
718
719 struct nv_skb_map {
720 struct sk_buff *skb;
721 dma_addr_t dma;
722 unsigned int dma_len:31;
723 unsigned int dma_single:1;
724 struct ring_desc_ex *first_tx_desc;
725 struct nv_skb_map *next_tx_ctx;
726 };
727
728 /*
729 * SMP locking:
730 * All hardware access under netdev_priv(dev)->lock, except the performance
731 * critical parts:
732 * - rx is (pseudo-) lockless: it relies on the single-threading provided
733 * by the arch code for interrupts.
734 * - tx setup is lockless: it relies on netif_tx_lock. Actual submission
735 * needs netdev_priv(dev)->lock :-(
736 * - set_multicast_list: preparation lockless, relies on netif_tx_lock.
737 *
738 * Hardware stats updates are protected by hwstats_lock:
739 * - updated by nv_do_stats_poll (timer). This is meant to avoid
740 * integer wraparound in the NIC stats registers, at low frequency
741 * (0.1 Hz)
742 * - updated by nv_get_ethtool_stats + nv_get_stats64
743 *
744 * Software stats are accessed only through 64b synchronization points
745 * and are not subject to other synchronization techniques (single
746 * update thread on the TX or RX paths).
747 */
748
749 /* in dev: base, irq */
750 struct fe_priv {
751 spinlock_t lock;
752
753 struct net_device *dev;
754 struct napi_struct napi;
755
756 /* hardware stats are updated in syscall and timer */
757 spinlock_t hwstats_lock;
758 struct nv_ethtool_stats estats;
759
760 int in_shutdown;
761 u32 linkspeed;
762 int duplex;
763 int autoneg;
764 int fixed_mode;
765 int phyaddr;
766 int wolenabled;
767 unsigned int phy_oui;
768 unsigned int phy_model;
769 unsigned int phy_rev;
770 u16 gigabit;
771 int intr_test;
772 int recover_error;
773 int quiet_count;
774
775 /* General data: RO fields */
776 dma_addr_t ring_addr;
777 struct pci_dev *pci_dev;
778 u32 orig_mac[2];
779 u32 events;
780 u32 irqmask;
781 u32 desc_ver;
782 u32 txrxctl_bits;
783 u32 vlanctl_bits;
784 u32 driver_data;
785 u32 device_id;
786 u32 register_size;
787 u32 mac_in_use;
788 int mgmt_version;
789 int mgmt_sema;
790
791 void __iomem *base;
792
793 /* rx specific fields.
794 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
795 */
796 union ring_type get_rx, put_rx, first_rx, last_rx;
797 struct nv_skb_map *get_rx_ctx, *put_rx_ctx;
798 struct nv_skb_map *first_rx_ctx, *last_rx_ctx;
799 struct nv_skb_map *rx_skb;
800
801 union ring_type rx_ring;
802 unsigned int rx_buf_sz;
803 unsigned int pkt_limit;
804 struct timer_list oom_kick;
805 struct timer_list nic_poll;
806 struct timer_list stats_poll;
807 u32 nic_poll_irq;
808 int rx_ring_size;
809
810 /* RX software stats */
811 struct u64_stats_sync swstats_rx_syncp;
812 u64 stat_rx_packets;
813 u64 stat_rx_bytes; /* not always available in HW */
814 u64 stat_rx_missed_errors;
815 u64 stat_rx_dropped;
816
817 /* media detection workaround.
818 * Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
819 */
820 int need_linktimer;
821 unsigned long link_timeout;
822 /*
823 * tx specific fields.
824 */
825 union ring_type get_tx, put_tx, first_tx, last_tx;
826 struct nv_skb_map *get_tx_ctx, *put_tx_ctx;
827 struct nv_skb_map *first_tx_ctx, *last_tx_ctx;
828 struct nv_skb_map *tx_skb;
829
830 union ring_type tx_ring;
831 u32 tx_flags;
832 int tx_ring_size;
833 int tx_limit;
834 u32 tx_pkts_in_progress;
835 struct nv_skb_map *tx_change_owner;
836 struct nv_skb_map *tx_end_flip;
837 int tx_stop;
838
839 /* TX software stats */
840 struct u64_stats_sync swstats_tx_syncp;
841 u64 stat_tx_packets; /* not always available in HW */
842 u64 stat_tx_bytes;
843 u64 stat_tx_dropped;
844
845 /* msi/msi-x fields */
846 u32 msi_flags;
847 struct msix_entry msi_x_entry[NV_MSI_X_MAX_VECTORS];
848
849 /* flow control */
850 u32 pause_flags;
851
852 /* power saved state */
853 u32 saved_config_space[NV_PCI_REGSZ_MAX/4];
854
855 /* for different msi-x irq type */
856 char name_rx[IFNAMSIZ + 3]; /* -rx */
857 char name_tx[IFNAMSIZ + 3]; /* -tx */
858 char name_other[IFNAMSIZ + 6]; /* -other */
859 };
860
861 /*
862 * Maximum number of loops until we assume that a bit in the irq mask
863 * is stuck. Overridable with module param.
864 */
865 static int max_interrupt_work = 4;
866
867 /*
868 * Optimization can be either throuput mode or cpu mode
869 *
870 * Throughput Mode: Every tx and rx packet will generate an interrupt.
871 * CPU Mode: Interrupts are controlled by a timer.
872 */
873 enum {
874 NV_OPTIMIZATION_MODE_THROUGHPUT,
875 NV_OPTIMIZATION_MODE_CPU,
876 NV_OPTIMIZATION_MODE_DYNAMIC
877 };
878 static int optimization_mode = NV_OPTIMIZATION_MODE_DYNAMIC;
879
880 /*
881 * Poll interval for timer irq
882 *
883 * This interval determines how frequent an interrupt is generated.
884 * The is value is determined by [(time_in_micro_secs * 100) / (2^10)]
885 * Min = 0, and Max = 65535
886 */
887 static int poll_interval = -1;
888
889 /*
890 * MSI interrupts
891 */
892 enum {
893 NV_MSI_INT_DISABLED,
894 NV_MSI_INT_ENABLED
895 };
896 static int msi = NV_MSI_INT_ENABLED;
897
898 /*
899 * MSIX interrupts
900 */
901 enum {
902 NV_MSIX_INT_DISABLED,
903 NV_MSIX_INT_ENABLED
904 };
905 static int msix = NV_MSIX_INT_ENABLED;
906
907 /*
908 * DMA 64bit
909 */
910 enum {
911 NV_DMA_64BIT_DISABLED,
912 NV_DMA_64BIT_ENABLED
913 };
914 static int dma_64bit = NV_DMA_64BIT_ENABLED;
915
916 /*
917 * Debug output control for tx_timeout
918 */
919 static bool debug_tx_timeout = false;
920
921 /*
922 * Crossover Detection
923 * Realtek 8201 phy + some OEM boards do not work properly.
924 */
925 enum {
926 NV_CROSSOVER_DETECTION_DISABLED,
927 NV_CROSSOVER_DETECTION_ENABLED
928 };
929 static int phy_cross = NV_CROSSOVER_DETECTION_DISABLED;
930
931 /*
932 * Power down phy when interface is down (persists through reboot;
933 * older Linux and other OSes may not power it up again)
934 */
935 static int phy_power_down;
936
937 static inline struct fe_priv *get_nvpriv(struct net_device *dev)
938 {
939 return netdev_priv(dev);
940 }
941
942 static inline u8 __iomem *get_hwbase(struct net_device *dev)
943 {
944 return ((struct fe_priv *)netdev_priv(dev))->base;
945 }
946
947 static inline void pci_push(u8 __iomem *base)
948 {
949 /* force out pending posted writes */
950 readl(base);
951 }
952
953 static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
954 {
955 return le32_to_cpu(prd->flaglen)
956 & ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
957 }
958
959 static inline u32 nv_descr_getlength_ex(struct ring_desc_ex *prd, u32 v)
960 {
961 return le32_to_cpu(prd->flaglen) & LEN_MASK_V2;
962 }
963
964 static bool nv_optimized(struct fe_priv *np)
965 {
966 if (np->desc_ver == DESC_VER_1 || np->desc_ver == DESC_VER_2)
967 return false;
968 return true;
969 }
970
971 static int reg_delay(struct net_device *dev, int offset, u32 mask, u32 target,
972 int delay, int delaymax)
973 {
974 u8 __iomem *base = get_hwbase(dev);
975
976 pci_push(base);
977 do {
978 udelay(delay);
979 delaymax -= delay;
980 if (delaymax < 0)
981 return 1;
982 } while ((readl(base + offset) & mask) != target);
983 return 0;
984 }
985
986 #define NV_SETUP_RX_RING 0x01
987 #define NV_SETUP_TX_RING 0x02
988
989 static inline u32 dma_low(dma_addr_t addr)
990 {
991 return addr;
992 }
993
994 static inline u32 dma_high(dma_addr_t addr)
995 {
996 return addr>>31>>1; /* 0 if 32bit, shift down by 32 if 64bit */
997 }
998
999 static void setup_hw_rings(struct net_device *dev, int rxtx_flags)
1000 {
1001 struct fe_priv *np = get_nvpriv(dev);
1002 u8 __iomem *base = get_hwbase(dev);
1003
1004 if (!nv_optimized(np)) {
1005 if (rxtx_flags & NV_SETUP_RX_RING)
1006 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1007 if (rxtx_flags & NV_SETUP_TX_RING)
1008 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc)), base + NvRegTxRingPhysAddr);
1009 } else {
1010 if (rxtx_flags & NV_SETUP_RX_RING) {
1011 writel(dma_low(np->ring_addr), base + NvRegRxRingPhysAddr);
1012 writel(dma_high(np->ring_addr), base + NvRegRxRingPhysAddrHigh);
1013 }
1014 if (rxtx_flags & NV_SETUP_TX_RING) {
1015 writel(dma_low(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddr);
1016 writel(dma_high(np->ring_addr + np->rx_ring_size*sizeof(struct ring_desc_ex)), base + NvRegTxRingPhysAddrHigh);
1017 }
1018 }
1019 }
1020
1021 static void free_rings(struct net_device *dev)
1022 {
1023 struct fe_priv *np = get_nvpriv(dev);
1024
1025 if (!nv_optimized(np)) {
1026 if (np->rx_ring.orig)
1027 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
1028 np->rx_ring.orig, np->ring_addr);
1029 } else {
1030 if (np->rx_ring.ex)
1031 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
1032 np->rx_ring.ex, np->ring_addr);
1033 }
1034 kfree(np->rx_skb);
1035 kfree(np->tx_skb);
1036 }
1037
1038 static int using_multi_irqs(struct net_device *dev)
1039 {
1040 struct fe_priv *np = get_nvpriv(dev);
1041
1042 if (!(np->msi_flags & NV_MSI_X_ENABLED) ||
1043 ((np->msi_flags & NV_MSI_X_ENABLED) &&
1044 ((np->msi_flags & NV_MSI_X_VECTORS_MASK) == 0x1)))
1045 return 0;
1046 else
1047 return 1;
1048 }
1049
1050 static void nv_txrx_gate(struct net_device *dev, bool gate)
1051 {
1052 struct fe_priv *np = get_nvpriv(dev);
1053 u8 __iomem *base = get_hwbase(dev);
1054 u32 powerstate;
1055
1056 if (!np->mac_in_use &&
1057 (np->driver_data & DEV_HAS_POWER_CNTRL)) {
1058 powerstate = readl(base + NvRegPowerState2);
1059 if (gate)
1060 powerstate |= NVREG_POWERSTATE2_GATE_CLOCKS;
1061 else
1062 powerstate &= ~NVREG_POWERSTATE2_GATE_CLOCKS;
1063 writel(powerstate, base + NvRegPowerState2);
1064 }
1065 }
1066
1067 static void nv_enable_irq(struct net_device *dev)
1068 {
1069 struct fe_priv *np = get_nvpriv(dev);
1070
1071 if (!using_multi_irqs(dev)) {
1072 if (np->msi_flags & NV_MSI_X_ENABLED)
1073 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1074 else
1075 enable_irq(np->pci_dev->irq);
1076 } else {
1077 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1078 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1079 enable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1080 }
1081 }
1082
1083 static void nv_disable_irq(struct net_device *dev)
1084 {
1085 struct fe_priv *np = get_nvpriv(dev);
1086
1087 if (!using_multi_irqs(dev)) {
1088 if (np->msi_flags & NV_MSI_X_ENABLED)
1089 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
1090 else
1091 disable_irq(np->pci_dev->irq);
1092 } else {
1093 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
1094 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
1095 disable_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
1096 }
1097 }
1098
1099 /* In MSIX mode, a write to irqmask behaves as XOR */
1100 static void nv_enable_hw_interrupts(struct net_device *dev, u32 mask)
1101 {
1102 u8 __iomem *base = get_hwbase(dev);
1103
1104 writel(mask, base + NvRegIrqMask);
1105 }
1106
1107 static void nv_disable_hw_interrupts(struct net_device *dev, u32 mask)
1108 {
1109 struct fe_priv *np = get_nvpriv(dev);
1110 u8 __iomem *base = get_hwbase(dev);
1111
1112 if (np->msi_flags & NV_MSI_X_ENABLED) {
1113 writel(mask, base + NvRegIrqMask);
1114 } else {
1115 if (np->msi_flags & NV_MSI_ENABLED)
1116 writel(0, base + NvRegMSIIrqMask);
1117 writel(0, base + NvRegIrqMask);
1118 }
1119 }
1120
1121 static void nv_napi_enable(struct net_device *dev)
1122 {
1123 struct fe_priv *np = get_nvpriv(dev);
1124
1125 napi_enable(&np->napi);
1126 }
1127
1128 static void nv_napi_disable(struct net_device *dev)
1129 {
1130 struct fe_priv *np = get_nvpriv(dev);
1131
1132 napi_disable(&np->napi);
1133 }
1134
1135 #define MII_READ (-1)
1136 /* mii_rw: read/write a register on the PHY.
1137 *
1138 * Caller must guarantee serialization
1139 */
1140 static int mii_rw(struct net_device *dev, int addr, int miireg, int value)
1141 {
1142 u8 __iomem *base = get_hwbase(dev);
1143 u32 reg;
1144 int retval;
1145
1146 writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus);
1147
1148 reg = readl(base + NvRegMIIControl);
1149 if (reg & NVREG_MIICTL_INUSE) {
1150 writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
1151 udelay(NV_MIIBUSY_DELAY);
1152 }
1153
1154 reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg;
1155 if (value != MII_READ) {
1156 writel(value, base + NvRegMIIData);
1157 reg |= NVREG_MIICTL_WRITE;
1158 }
1159 writel(reg, base + NvRegMIIControl);
1160
1161 if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
1162 NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX)) {
1163 retval = -1;
1164 } else if (value != MII_READ) {
1165 /* it was a write operation - fewer failures are detectable */
1166 retval = 0;
1167 } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
1168 retval = -1;
1169 } else {
1170 retval = readl(base + NvRegMIIData);
1171 }
1172
1173 return retval;
1174 }
1175
1176 static int phy_reset(struct net_device *dev, u32 bmcr_setup)
1177 {
1178 struct fe_priv *np = netdev_priv(dev);
1179 u32 miicontrol;
1180 unsigned int tries = 0;
1181
1182 miicontrol = BMCR_RESET | bmcr_setup;
1183 if (mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol))
1184 return -1;
1185
1186 /* wait for 500ms */
1187 msleep(500);
1188
1189 /* must wait till reset is deasserted */
1190 while (miicontrol & BMCR_RESET) {
1191 usleep_range(10000, 20000);
1192 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1193 /* FIXME: 100 tries seem excessive */
1194 if (tries++ > 100)
1195 return -1;
1196 }
1197 return 0;
1198 }
1199
1200 static int init_realtek_8211b(struct net_device *dev, struct fe_priv *np)
1201 {
1202 static const struct {
1203 int reg;
1204 int init;
1205 } ri[] = {
1206 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1207 { PHY_REALTEK_INIT_REG2, PHY_REALTEK_INIT2 },
1208 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3 },
1209 { PHY_REALTEK_INIT_REG3, PHY_REALTEK_INIT4 },
1210 { PHY_REALTEK_INIT_REG4, PHY_REALTEK_INIT5 },
1211 { PHY_REALTEK_INIT_REG5, PHY_REALTEK_INIT6 },
1212 { PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1 },
1213 };
1214 int i;
1215
1216 for (i = 0; i < ARRAY_SIZE(ri); i++) {
1217 if (mii_rw(dev, np->phyaddr, ri[i].reg, ri[i].init))
1218 return PHY_ERROR;
1219 }
1220
1221 return 0;
1222 }
1223
1224 static int init_realtek_8211c(struct net_device *dev, struct fe_priv *np)
1225 {
1226 u32 reg;
1227 u8 __iomem *base = get_hwbase(dev);
1228 u32 powerstate = readl(base + NvRegPowerState2);
1229
1230 /* need to perform hw phy reset */
1231 powerstate |= NVREG_POWERSTATE2_PHY_RESET;
1232 writel(powerstate, base + NvRegPowerState2);
1233 msleep(25);
1234
1235 powerstate &= ~NVREG_POWERSTATE2_PHY_RESET;
1236 writel(powerstate, base + NvRegPowerState2);
1237 msleep(25);
1238
1239 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, MII_READ);
1240 reg |= PHY_REALTEK_INIT9;
1241 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG6, reg))
1242 return PHY_ERROR;
1243 if (mii_rw(dev, np->phyaddr,
1244 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT10))
1245 return PHY_ERROR;
1246 reg = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, MII_READ);
1247 if (!(reg & PHY_REALTEK_INIT11)) {
1248 reg |= PHY_REALTEK_INIT11;
1249 if (mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG7, reg))
1250 return PHY_ERROR;
1251 }
1252 if (mii_rw(dev, np->phyaddr,
1253 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1254 return PHY_ERROR;
1255
1256 return 0;
1257 }
1258
1259 static int init_realtek_8201(struct net_device *dev, struct fe_priv *np)
1260 {
1261 u32 phy_reserved;
1262
1263 if (np->driver_data & DEV_NEED_PHY_INIT_FIX) {
1264 phy_reserved = mii_rw(dev, np->phyaddr,
1265 PHY_REALTEK_INIT_REG6, MII_READ);
1266 phy_reserved |= PHY_REALTEK_INIT7;
1267 if (mii_rw(dev, np->phyaddr,
1268 PHY_REALTEK_INIT_REG6, phy_reserved))
1269 return PHY_ERROR;
1270 }
1271
1272 return 0;
1273 }
1274
1275 static int init_realtek_8201_cross(struct net_device *dev, struct fe_priv *np)
1276 {
1277 u32 phy_reserved;
1278
1279 if (phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
1280 if (mii_rw(dev, np->phyaddr,
1281 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3))
1282 return PHY_ERROR;
1283 phy_reserved = mii_rw(dev, np->phyaddr,
1284 PHY_REALTEK_INIT_REG2, MII_READ);
1285 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
1286 phy_reserved |= PHY_REALTEK_INIT3;
1287 if (mii_rw(dev, np->phyaddr,
1288 PHY_REALTEK_INIT_REG2, phy_reserved))
1289 return PHY_ERROR;
1290 if (mii_rw(dev, np->phyaddr,
1291 PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1))
1292 return PHY_ERROR;
1293 }
1294
1295 return 0;
1296 }
1297
1298 static int init_cicada(struct net_device *dev, struct fe_priv *np,
1299 u32 phyinterface)
1300 {
1301 u32 phy_reserved;
1302
1303 if (phyinterface & PHY_RGMII) {
1304 phy_reserved = mii_rw(dev, np->phyaddr, MII_RESV1, MII_READ);
1305 phy_reserved &= ~(PHY_CICADA_INIT1 | PHY_CICADA_INIT2);
1306 phy_reserved |= (PHY_CICADA_INIT3 | PHY_CICADA_INIT4);
1307 if (mii_rw(dev, np->phyaddr, MII_RESV1, phy_reserved))
1308 return PHY_ERROR;
1309 phy_reserved = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1310 phy_reserved |= PHY_CICADA_INIT5;
1311 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, phy_reserved))
1312 return PHY_ERROR;
1313 }
1314 phy_reserved = mii_rw(dev, np->phyaddr, MII_SREVISION, MII_READ);
1315 phy_reserved |= PHY_CICADA_INIT6;
1316 if (mii_rw(dev, np->phyaddr, MII_SREVISION, phy_reserved))
1317 return PHY_ERROR;
1318
1319 return 0;
1320 }
1321
1322 static int init_vitesse(struct net_device *dev, struct fe_priv *np)
1323 {
1324 u32 phy_reserved;
1325
1326 if (mii_rw(dev, np->phyaddr,
1327 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT1))
1328 return PHY_ERROR;
1329 if (mii_rw(dev, np->phyaddr,
1330 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT2))
1331 return PHY_ERROR;
1332 phy_reserved = mii_rw(dev, np->phyaddr,
1333 PHY_VITESSE_INIT_REG4, MII_READ);
1334 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1335 return PHY_ERROR;
1336 phy_reserved = mii_rw(dev, np->phyaddr,
1337 PHY_VITESSE_INIT_REG3, MII_READ);
1338 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1339 phy_reserved |= PHY_VITESSE_INIT3;
1340 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1341 return PHY_ERROR;
1342 if (mii_rw(dev, np->phyaddr,
1343 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT4))
1344 return PHY_ERROR;
1345 if (mii_rw(dev, np->phyaddr,
1346 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT5))
1347 return PHY_ERROR;
1348 phy_reserved = mii_rw(dev, np->phyaddr,
1349 PHY_VITESSE_INIT_REG4, MII_READ);
1350 phy_reserved &= ~PHY_VITESSE_INIT_MSK1;
1351 phy_reserved |= PHY_VITESSE_INIT3;
1352 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1353 return PHY_ERROR;
1354 phy_reserved = mii_rw(dev, np->phyaddr,
1355 PHY_VITESSE_INIT_REG3, MII_READ);
1356 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1357 return PHY_ERROR;
1358 if (mii_rw(dev, np->phyaddr,
1359 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT6))
1360 return PHY_ERROR;
1361 if (mii_rw(dev, np->phyaddr,
1362 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT7))
1363 return PHY_ERROR;
1364 phy_reserved = mii_rw(dev, np->phyaddr,
1365 PHY_VITESSE_INIT_REG4, MII_READ);
1366 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG4, phy_reserved))
1367 return PHY_ERROR;
1368 phy_reserved = mii_rw(dev, np->phyaddr,
1369 PHY_VITESSE_INIT_REG3, MII_READ);
1370 phy_reserved &= ~PHY_VITESSE_INIT_MSK2;
1371 phy_reserved |= PHY_VITESSE_INIT8;
1372 if (mii_rw(dev, np->phyaddr, PHY_VITESSE_INIT_REG3, phy_reserved))
1373 return PHY_ERROR;
1374 if (mii_rw(dev, np->phyaddr,
1375 PHY_VITESSE_INIT_REG2, PHY_VITESSE_INIT9))
1376 return PHY_ERROR;
1377 if (mii_rw(dev, np->phyaddr,
1378 PHY_VITESSE_INIT_REG1, PHY_VITESSE_INIT10))
1379 return PHY_ERROR;
1380
1381 return 0;
1382 }
1383
1384 static int phy_init(struct net_device *dev)
1385 {
1386 struct fe_priv *np = get_nvpriv(dev);
1387 u8 __iomem *base = get_hwbase(dev);
1388 u32 phyinterface;
1389 u32 mii_status, mii_control, mii_control_1000, reg;
1390
1391 /* phy errata for E3016 phy */
1392 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
1393 reg = mii_rw(dev, np->phyaddr, MII_NCONFIG, MII_READ);
1394 reg &= ~PHY_MARVELL_E3016_INITMASK;
1395 if (mii_rw(dev, np->phyaddr, MII_NCONFIG, reg)) {
1396 netdev_info(dev, "%s: phy write to errata reg failed\n",
1397 pci_name(np->pci_dev));
1398 return PHY_ERROR;
1399 }
1400 }
1401 if (np->phy_oui == PHY_OUI_REALTEK) {
1402 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1403 np->phy_rev == PHY_REV_REALTEK_8211B) {
1404 if (init_realtek_8211b(dev, np)) {
1405 netdev_info(dev, "%s: phy init failed\n",
1406 pci_name(np->pci_dev));
1407 return PHY_ERROR;
1408 }
1409 } else if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1410 np->phy_rev == PHY_REV_REALTEK_8211C) {
1411 if (init_realtek_8211c(dev, np)) {
1412 netdev_info(dev, "%s: phy init failed\n",
1413 pci_name(np->pci_dev));
1414 return PHY_ERROR;
1415 }
1416 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1417 if (init_realtek_8201(dev, np)) {
1418 netdev_info(dev, "%s: phy init failed\n",
1419 pci_name(np->pci_dev));
1420 return PHY_ERROR;
1421 }
1422 }
1423 }
1424
1425 /* set advertise register */
1426 reg = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
1427 reg |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
1428 ADVERTISE_100HALF | ADVERTISE_100FULL |
1429 ADVERTISE_PAUSE_ASYM | ADVERTISE_PAUSE_CAP);
1430 if (mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg)) {
1431 netdev_info(dev, "%s: phy write to advertise failed\n",
1432 pci_name(np->pci_dev));
1433 return PHY_ERROR;
1434 }
1435
1436 /* get phy interface type */
1437 phyinterface = readl(base + NvRegPhyInterface);
1438
1439 /* see if gigabit phy */
1440 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
1441 if (mii_status & PHY_GIGABIT) {
1442 np->gigabit = PHY_GIGABIT;
1443 mii_control_1000 = mii_rw(dev, np->phyaddr,
1444 MII_CTRL1000, MII_READ);
1445 mii_control_1000 &= ~ADVERTISE_1000HALF;
1446 if (phyinterface & PHY_RGMII)
1447 mii_control_1000 |= ADVERTISE_1000FULL;
1448 else
1449 mii_control_1000 &= ~ADVERTISE_1000FULL;
1450
1451 if (mii_rw(dev, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
1452 netdev_info(dev, "%s: phy init failed\n",
1453 pci_name(np->pci_dev));
1454 return PHY_ERROR;
1455 }
1456 } else
1457 np->gigabit = 0;
1458
1459 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1460 mii_control |= BMCR_ANENABLE;
1461
1462 if (np->phy_oui == PHY_OUI_REALTEK &&
1463 np->phy_model == PHY_MODEL_REALTEK_8211 &&
1464 np->phy_rev == PHY_REV_REALTEK_8211C) {
1465 /* start autoneg since we already performed hw reset above */
1466 mii_control |= BMCR_ANRESTART;
1467 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control)) {
1468 netdev_info(dev, "%s: phy init failed\n",
1469 pci_name(np->pci_dev));
1470 return PHY_ERROR;
1471 }
1472 } else {
1473 /* reset the phy
1474 * (certain phys need bmcr to be setup with reset)
1475 */
1476 if (phy_reset(dev, mii_control)) {
1477 netdev_info(dev, "%s: phy reset failed\n",
1478 pci_name(np->pci_dev));
1479 return PHY_ERROR;
1480 }
1481 }
1482
1483 /* phy vendor specific configuration */
1484 if ((np->phy_oui == PHY_OUI_CICADA)) {
1485 if (init_cicada(dev, np, phyinterface)) {
1486 netdev_info(dev, "%s: phy init failed\n",
1487 pci_name(np->pci_dev));
1488 return PHY_ERROR;
1489 }
1490 } else if (np->phy_oui == PHY_OUI_VITESSE) {
1491 if (init_vitesse(dev, np)) {
1492 netdev_info(dev, "%s: phy init failed\n",
1493 pci_name(np->pci_dev));
1494 return PHY_ERROR;
1495 }
1496 } else if (np->phy_oui == PHY_OUI_REALTEK) {
1497 if (np->phy_model == PHY_MODEL_REALTEK_8211 &&
1498 np->phy_rev == PHY_REV_REALTEK_8211B) {
1499 /* reset could have cleared these out, set them back */
1500 if (init_realtek_8211b(dev, np)) {
1501 netdev_info(dev, "%s: phy init failed\n",
1502 pci_name(np->pci_dev));
1503 return PHY_ERROR;
1504 }
1505 } else if (np->phy_model == PHY_MODEL_REALTEK_8201) {
1506 if (init_realtek_8201(dev, np) ||
1507 init_realtek_8201_cross(dev, np)) {
1508 netdev_info(dev, "%s: phy init failed\n",
1509 pci_name(np->pci_dev));
1510 return PHY_ERROR;
1511 }
1512 }
1513 }
1514
1515 /* some phys clear out pause advertisement on reset, set it back */
1516 mii_rw(dev, np->phyaddr, MII_ADVERTISE, reg);
1517
1518 /* restart auto negotiation, power down phy */
1519 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
1520 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
1521 if (phy_power_down)
1522 mii_control |= BMCR_PDOWN;
1523 if (mii_rw(dev, np->phyaddr, MII_BMCR, mii_control))
1524 return PHY_ERROR;
1525
1526 return 0;
1527 }
1528
1529 static void nv_start_rx(struct net_device *dev)
1530 {
1531 struct fe_priv *np = netdev_priv(dev);
1532 u8 __iomem *base = get_hwbase(dev);
1533 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1534
1535 /* Already running? Stop it. */
1536 if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) {
1537 rx_ctrl &= ~NVREG_RCVCTL_START;
1538 writel(rx_ctrl, base + NvRegReceiverControl);
1539 pci_push(base);
1540 }
1541 writel(np->linkspeed, base + NvRegLinkSpeed);
1542 pci_push(base);
1543 rx_ctrl |= NVREG_RCVCTL_START;
1544 if (np->mac_in_use)
1545 rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN;
1546 writel(rx_ctrl, base + NvRegReceiverControl);
1547 pci_push(base);
1548 }
1549
1550 static void nv_stop_rx(struct net_device *dev)
1551 {
1552 struct fe_priv *np = netdev_priv(dev);
1553 u8 __iomem *base = get_hwbase(dev);
1554 u32 rx_ctrl = readl(base + NvRegReceiverControl);
1555
1556 if (!np->mac_in_use)
1557 rx_ctrl &= ~NVREG_RCVCTL_START;
1558 else
1559 rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN;
1560 writel(rx_ctrl, base + NvRegReceiverControl);
1561 if (reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
1562 NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX))
1563 netdev_info(dev, "%s: ReceiverStatus remained busy\n",
1564 __func__);
1565
1566 udelay(NV_RXSTOP_DELAY2);
1567 if (!np->mac_in_use)
1568 writel(0, base + NvRegLinkSpeed);
1569 }
1570
1571 static void nv_start_tx(struct net_device *dev)
1572 {
1573 struct fe_priv *np = netdev_priv(dev);
1574 u8 __iomem *base = get_hwbase(dev);
1575 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1576
1577 tx_ctrl |= NVREG_XMITCTL_START;
1578 if (np->mac_in_use)
1579 tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN;
1580 writel(tx_ctrl, base + NvRegTransmitterControl);
1581 pci_push(base);
1582 }
1583
1584 static void nv_stop_tx(struct net_device *dev)
1585 {
1586 struct fe_priv *np = netdev_priv(dev);
1587 u8 __iomem *base = get_hwbase(dev);
1588 u32 tx_ctrl = readl(base + NvRegTransmitterControl);
1589
1590 if (!np->mac_in_use)
1591 tx_ctrl &= ~NVREG_XMITCTL_START;
1592 else
1593 tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN;
1594 writel(tx_ctrl, base + NvRegTransmitterControl);
1595 if (reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
1596 NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX))
1597 netdev_info(dev, "%s: TransmitterStatus remained busy\n",
1598 __func__);
1599
1600 udelay(NV_TXSTOP_DELAY2);
1601 if (!np->mac_in_use)
1602 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV,
1603 base + NvRegTransmitPoll);
1604 }
1605
1606 static void nv_start_rxtx(struct net_device *dev)
1607 {
1608 nv_start_rx(dev);
1609 nv_start_tx(dev);
1610 }
1611
1612 static void nv_stop_rxtx(struct net_device *dev)
1613 {
1614 nv_stop_rx(dev);
1615 nv_stop_tx(dev);
1616 }
1617
1618 static void nv_txrx_reset(struct net_device *dev)
1619 {
1620 struct fe_priv *np = netdev_priv(dev);
1621 u8 __iomem *base = get_hwbase(dev);
1622
1623 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1624 pci_push(base);
1625 udelay(NV_TXRX_RESET_DELAY);
1626 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1627 pci_push(base);
1628 }
1629
1630 static void nv_mac_reset(struct net_device *dev)
1631 {
1632 struct fe_priv *np = netdev_priv(dev);
1633 u8 __iomem *base = get_hwbase(dev);
1634 u32 temp1, temp2, temp3;
1635
1636 writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl);
1637 pci_push(base);
1638
1639 /* save registers since they will be cleared on reset */
1640 temp1 = readl(base + NvRegMacAddrA);
1641 temp2 = readl(base + NvRegMacAddrB);
1642 temp3 = readl(base + NvRegTransmitPoll);
1643
1644 writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset);
1645 pci_push(base);
1646 udelay(NV_MAC_RESET_DELAY);
1647 writel(0, base + NvRegMacReset);
1648 pci_push(base);
1649 udelay(NV_MAC_RESET_DELAY);
1650
1651 /* restore saved registers */
1652 writel(temp1, base + NvRegMacAddrA);
1653 writel(temp2, base + NvRegMacAddrB);
1654 writel(temp3, base + NvRegTransmitPoll);
1655
1656 writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl);
1657 pci_push(base);
1658 }
1659
1660 /* Caller must appropriately lock netdev_priv(dev)->hwstats_lock */
1661 static void nv_update_stats(struct net_device *dev)
1662 {
1663 struct fe_priv *np = netdev_priv(dev);
1664 u8 __iomem *base = get_hwbase(dev);
1665
1666 /* If it happens that this is run in top-half context, then
1667 * replace the spin_lock of hwstats_lock with
1668 * spin_lock_irqsave() in calling functions. */
1669 WARN_ONCE(in_irq(), "forcedeth: estats spin_lock(_bh) from top-half");
1670 assert_spin_locked(&np->hwstats_lock);
1671
1672 /* query hardware */
1673 np->estats.tx_bytes += readl(base + NvRegTxCnt);
1674 np->estats.tx_zero_rexmt += readl(base + NvRegTxZeroReXmt);
1675 np->estats.tx_one_rexmt += readl(base + NvRegTxOneReXmt);
1676 np->estats.tx_many_rexmt += readl(base + NvRegTxManyReXmt);
1677 np->estats.tx_late_collision += readl(base + NvRegTxLateCol);
1678 np->estats.tx_fifo_errors += readl(base + NvRegTxUnderflow);
1679 np->estats.tx_carrier_errors += readl(base + NvRegTxLossCarrier);
1680 np->estats.tx_excess_deferral += readl(base + NvRegTxExcessDef);
1681 np->estats.tx_retry_error += readl(base + NvRegTxRetryErr);
1682 np->estats.rx_frame_error += readl(base + NvRegRxFrameErr);
1683 np->estats.rx_extra_byte += readl(base + NvRegRxExtraByte);
1684 np->estats.rx_late_collision += readl(base + NvRegRxLateCol);
1685 np->estats.rx_runt += readl(base + NvRegRxRunt);
1686 np->estats.rx_frame_too_long += readl(base + NvRegRxFrameTooLong);
1687 np->estats.rx_over_errors += readl(base + NvRegRxOverflow);
1688 np->estats.rx_crc_errors += readl(base + NvRegRxFCSErr);
1689 np->estats.rx_frame_align_error += readl(base + NvRegRxFrameAlignErr);
1690 np->estats.rx_length_error += readl(base + NvRegRxLenErr);
1691 np->estats.rx_unicast += readl(base + NvRegRxUnicast);
1692 np->estats.rx_multicast += readl(base + NvRegRxMulticast);
1693 np->estats.rx_broadcast += readl(base + NvRegRxBroadcast);
1694 np->estats.rx_packets =
1695 np->estats.rx_unicast +
1696 np->estats.rx_multicast +
1697 np->estats.rx_broadcast;
1698 np->estats.rx_errors_total =
1699 np->estats.rx_crc_errors +
1700 np->estats.rx_over_errors +
1701 np->estats.rx_frame_error +
1702 (np->estats.rx_frame_align_error - np->estats.rx_extra_byte) +
1703 np->estats.rx_late_collision +
1704 np->estats.rx_runt +
1705 np->estats.rx_frame_too_long;
1706 np->estats.tx_errors_total =
1707 np->estats.tx_late_collision +
1708 np->estats.tx_fifo_errors +
1709 np->estats.tx_carrier_errors +
1710 np->estats.tx_excess_deferral +
1711 np->estats.tx_retry_error;
1712
1713 if (np->driver_data & DEV_HAS_STATISTICS_V2) {
1714 np->estats.tx_deferral += readl(base + NvRegTxDef);
1715 np->estats.tx_packets += readl(base + NvRegTxFrame);
1716 np->estats.rx_bytes += readl(base + NvRegRxCnt);
1717 np->estats.tx_pause += readl(base + NvRegTxPause);
1718 np->estats.rx_pause += readl(base + NvRegRxPause);
1719 np->estats.rx_drop_frame += readl(base + NvRegRxDropFrame);
1720 np->estats.rx_errors_total += np->estats.rx_drop_frame;
1721 }
1722
1723 if (np->driver_data & DEV_HAS_STATISTICS_V3) {
1724 np->estats.tx_unicast += readl(base + NvRegTxUnicast);
1725 np->estats.tx_multicast += readl(base + NvRegTxMulticast);
1726 np->estats.tx_broadcast += readl(base + NvRegTxBroadcast);
1727 }
1728 }
1729
1730 /*
1731 * nv_get_stats64: dev->ndo_get_stats64 function
1732 * Get latest stats value from the nic.
1733 * Called with read_lock(&dev_base_lock) held for read -
1734 * only synchronized against unregister_netdevice.
1735 */
1736 static struct rtnl_link_stats64*
1737 nv_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *storage)
1738 __acquires(&netdev_priv(dev)->hwstats_lock)
1739 __releases(&netdev_priv(dev)->hwstats_lock)
1740 {
1741 struct fe_priv *np = netdev_priv(dev);
1742 unsigned int syncp_start;
1743
1744 /*
1745 * Note: because HW stats are not always available and for
1746 * consistency reasons, the following ifconfig stats are
1747 * managed by software: rx_bytes, tx_bytes, rx_packets and
1748 * tx_packets. The related hardware stats reported by ethtool
1749 * should be equivalent to these ifconfig stats, with 4
1750 * additional bytes per packet (Ethernet FCS CRC), except for
1751 * tx_packets when TSO kicks in.
1752 */
1753
1754 /* software stats */
1755 do {
1756 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_rx_syncp);
1757 storage->rx_packets = np->stat_rx_packets;
1758 storage->rx_bytes = np->stat_rx_bytes;
1759 storage->rx_dropped = np->stat_rx_dropped;
1760 storage->rx_missed_errors = np->stat_rx_missed_errors;
1761 } while (u64_stats_fetch_retry_bh(&np->swstats_rx_syncp, syncp_start));
1762
1763 do {
1764 syncp_start = u64_stats_fetch_begin_bh(&np->swstats_tx_syncp);
1765 storage->tx_packets = np->stat_tx_packets;
1766 storage->tx_bytes = np->stat_tx_bytes;
1767 storage->tx_dropped = np->stat_tx_dropped;
1768 } while (u64_stats_fetch_retry_bh(&np->swstats_tx_syncp, syncp_start));
1769
1770 /* If the nic supports hw counters then retrieve latest values */
1771 if (np->driver_data & DEV_HAS_STATISTICS_V123) {
1772 spin_lock_bh(&np->hwstats_lock);
1773
1774 nv_update_stats(dev);
1775
1776 /* generic stats */
1777 storage->rx_errors = np->estats.rx_errors_total;
1778 storage->tx_errors = np->estats.tx_errors_total;
1779
1780 /* meaningful only when NIC supports stats v3 */
1781 storage->multicast = np->estats.rx_multicast;
1782
1783 /* detailed rx_errors */
1784 storage->rx_length_errors = np->estats.rx_length_error;
1785 storage->rx_over_errors = np->estats.rx_over_errors;
1786 storage->rx_crc_errors = np->estats.rx_crc_errors;
1787 storage->rx_frame_errors = np->estats.rx_frame_align_error;
1788 storage->rx_fifo_errors = np->estats.rx_drop_frame;
1789
1790 /* detailed tx_errors */
1791 storage->tx_carrier_errors = np->estats.tx_carrier_errors;
1792 storage->tx_fifo_errors = np->estats.tx_fifo_errors;
1793
1794 spin_unlock_bh(&np->hwstats_lock);
1795 }
1796
1797 return storage;
1798 }
1799
1800 /*
1801 * nv_alloc_rx: fill rx ring entries.
1802 * Return 1 if the allocations for the skbs failed and the
1803 * rx engine is without Available descriptors
1804 */
1805 static int nv_alloc_rx(struct net_device *dev)
1806 {
1807 struct fe_priv *np = netdev_priv(dev);
1808 struct ring_desc *less_rx;
1809
1810 less_rx = np->get_rx.orig;
1811 if (less_rx-- == np->first_rx.orig)
1812 less_rx = np->last_rx.orig;
1813
1814 while (np->put_rx.orig != less_rx) {
1815 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1816 if (skb) {
1817 np->put_rx_ctx->skb = skb;
1818 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1819 skb->data,
1820 skb_tailroom(skb),
1821 PCI_DMA_FROMDEVICE);
1822 if (pci_dma_mapping_error(np->pci_dev,
1823 np->put_rx_ctx->dma)) {
1824 kfree_skb(skb);
1825 goto packet_dropped;
1826 }
1827 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1828 np->put_rx.orig->buf = cpu_to_le32(np->put_rx_ctx->dma);
1829 wmb();
1830 np->put_rx.orig->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX_AVAIL);
1831 if (unlikely(np->put_rx.orig++ == np->last_rx.orig))
1832 np->put_rx.orig = np->first_rx.orig;
1833 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1834 np->put_rx_ctx = np->first_rx_ctx;
1835 } else {
1836 packet_dropped:
1837 u64_stats_update_begin(&np->swstats_rx_syncp);
1838 np->stat_rx_dropped++;
1839 u64_stats_update_end(&np->swstats_rx_syncp);
1840 return 1;
1841 }
1842 }
1843 return 0;
1844 }
1845
1846 static int nv_alloc_rx_optimized(struct net_device *dev)
1847 {
1848 struct fe_priv *np = netdev_priv(dev);
1849 struct ring_desc_ex *less_rx;
1850
1851 less_rx = np->get_rx.ex;
1852 if (less_rx-- == np->first_rx.ex)
1853 less_rx = np->last_rx.ex;
1854
1855 while (np->put_rx.ex != less_rx) {
1856 struct sk_buff *skb = netdev_alloc_skb(dev, np->rx_buf_sz + NV_RX_ALLOC_PAD);
1857 if (skb) {
1858 np->put_rx_ctx->skb = skb;
1859 np->put_rx_ctx->dma = pci_map_single(np->pci_dev,
1860 skb->data,
1861 skb_tailroom(skb),
1862 PCI_DMA_FROMDEVICE);
1863 if (pci_dma_mapping_error(np->pci_dev,
1864 np->put_rx_ctx->dma)) {
1865 kfree_skb(skb);
1866 goto packet_dropped;
1867 }
1868 np->put_rx_ctx->dma_len = skb_tailroom(skb);
1869 np->put_rx.ex->bufhigh = cpu_to_le32(dma_high(np->put_rx_ctx->dma));
1870 np->put_rx.ex->buflow = cpu_to_le32(dma_low(np->put_rx_ctx->dma));
1871 wmb();
1872 np->put_rx.ex->flaglen = cpu_to_le32(np->rx_buf_sz | NV_RX2_AVAIL);
1873 if (unlikely(np->put_rx.ex++ == np->last_rx.ex))
1874 np->put_rx.ex = np->first_rx.ex;
1875 if (unlikely(np->put_rx_ctx++ == np->last_rx_ctx))
1876 np->put_rx_ctx = np->first_rx_ctx;
1877 } else {
1878 packet_dropped:
1879 u64_stats_update_begin(&np->swstats_rx_syncp);
1880 np->stat_rx_dropped++;
1881 u64_stats_update_end(&np->swstats_rx_syncp);
1882 return 1;
1883 }
1884 }
1885 return 0;
1886 }
1887
1888 /* If rx bufs are exhausted called after 50ms to attempt to refresh */
1889 static void nv_do_rx_refill(unsigned long data)
1890 {
1891 struct net_device *dev = (struct net_device *) data;
1892 struct fe_priv *np = netdev_priv(dev);
1893
1894 /* Just reschedule NAPI rx processing */
1895 napi_schedule(&np->napi);
1896 }
1897
1898 static void nv_init_rx(struct net_device *dev)
1899 {
1900 struct fe_priv *np = netdev_priv(dev);
1901 int i;
1902
1903 np->get_rx = np->put_rx = np->first_rx = np->rx_ring;
1904
1905 if (!nv_optimized(np))
1906 np->last_rx.orig = &np->rx_ring.orig[np->rx_ring_size-1];
1907 else
1908 np->last_rx.ex = &np->rx_ring.ex[np->rx_ring_size-1];
1909 np->get_rx_ctx = np->put_rx_ctx = np->first_rx_ctx = np->rx_skb;
1910 np->last_rx_ctx = &np->rx_skb[np->rx_ring_size-1];
1911
1912 for (i = 0; i < np->rx_ring_size; i++) {
1913 if (!nv_optimized(np)) {
1914 np->rx_ring.orig[i].flaglen = 0;
1915 np->rx_ring.orig[i].buf = 0;
1916 } else {
1917 np->rx_ring.ex[i].flaglen = 0;
1918 np->rx_ring.ex[i].txvlan = 0;
1919 np->rx_ring.ex[i].bufhigh = 0;
1920 np->rx_ring.ex[i].buflow = 0;
1921 }
1922 np->rx_skb[i].skb = NULL;
1923 np->rx_skb[i].dma = 0;
1924 }
1925 }
1926
1927 static void nv_init_tx(struct net_device *dev)
1928 {
1929 struct fe_priv *np = netdev_priv(dev);
1930 int i;
1931
1932 np->get_tx = np->put_tx = np->first_tx = np->tx_ring;
1933
1934 if (!nv_optimized(np))
1935 np->last_tx.orig = &np->tx_ring.orig[np->tx_ring_size-1];
1936 else
1937 np->last_tx.ex = &np->tx_ring.ex[np->tx_ring_size-1];
1938 np->get_tx_ctx = np->put_tx_ctx = np->first_tx_ctx = np->tx_skb;
1939 np->last_tx_ctx = &np->tx_skb[np->tx_ring_size-1];
1940 netdev_reset_queue(np->dev);
1941 np->tx_pkts_in_progress = 0;
1942 np->tx_change_owner = NULL;
1943 np->tx_end_flip = NULL;
1944 np->tx_stop = 0;
1945
1946 for (i = 0; i < np->tx_ring_size; i++) {
1947 if (!nv_optimized(np)) {
1948 np->tx_ring.orig[i].flaglen = 0;
1949 np->tx_ring.orig[i].buf = 0;
1950 } else {
1951 np->tx_ring.ex[i].flaglen = 0;
1952 np->tx_ring.ex[i].txvlan = 0;
1953 np->tx_ring.ex[i].bufhigh = 0;
1954 np->tx_ring.ex[i].buflow = 0;
1955 }
1956 np->tx_skb[i].skb = NULL;
1957 np->tx_skb[i].dma = 0;
1958 np->tx_skb[i].dma_len = 0;
1959 np->tx_skb[i].dma_single = 0;
1960 np->tx_skb[i].first_tx_desc = NULL;
1961 np->tx_skb[i].next_tx_ctx = NULL;
1962 }
1963 }
1964
1965 static int nv_init_ring(struct net_device *dev)
1966 {
1967 struct fe_priv *np = netdev_priv(dev);
1968
1969 nv_init_tx(dev);
1970 nv_init_rx(dev);
1971
1972 if (!nv_optimized(np))
1973 return nv_alloc_rx(dev);
1974 else
1975 return nv_alloc_rx_optimized(dev);
1976 }
1977
1978 static void nv_unmap_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1979 {
1980 if (tx_skb->dma) {
1981 if (tx_skb->dma_single)
1982 pci_unmap_single(np->pci_dev, tx_skb->dma,
1983 tx_skb->dma_len,
1984 PCI_DMA_TODEVICE);
1985 else
1986 pci_unmap_page(np->pci_dev, tx_skb->dma,
1987 tx_skb->dma_len,
1988 PCI_DMA_TODEVICE);
1989 tx_skb->dma = 0;
1990 }
1991 }
1992
1993 static int nv_release_txskb(struct fe_priv *np, struct nv_skb_map *tx_skb)
1994 {
1995 nv_unmap_txskb(np, tx_skb);
1996 if (tx_skb->skb) {
1997 dev_kfree_skb_any(tx_skb->skb);
1998 tx_skb->skb = NULL;
1999 return 1;
2000 }
2001 return 0;
2002 }
2003
2004 static void nv_drain_tx(struct net_device *dev)
2005 {
2006 struct fe_priv *np = netdev_priv(dev);
2007 unsigned int i;
2008
2009 for (i = 0; i < np->tx_ring_size; i++) {
2010 if (!nv_optimized(np)) {
2011 np->tx_ring.orig[i].flaglen = 0;
2012 np->tx_ring.orig[i].buf = 0;
2013 } else {
2014 np->tx_ring.ex[i].flaglen = 0;
2015 np->tx_ring.ex[i].txvlan = 0;
2016 np->tx_ring.ex[i].bufhigh = 0;
2017 np->tx_ring.ex[i].buflow = 0;
2018 }
2019 if (nv_release_txskb(np, &np->tx_skb[i])) {
2020 u64_stats_update_begin(&np->swstats_tx_syncp);
2021 np->stat_tx_dropped++;
2022 u64_stats_update_end(&np->swstats_tx_syncp);
2023 }
2024 np->tx_skb[i].dma = 0;
2025 np->tx_skb[i].dma_len = 0;
2026 np->tx_skb[i].dma_single = 0;
2027 np->tx_skb[i].first_tx_desc = NULL;
2028 np->tx_skb[i].next_tx_ctx = NULL;
2029 }
2030 np->tx_pkts_in_progress = 0;
2031 np->tx_change_owner = NULL;
2032 np->tx_end_flip = NULL;
2033 }
2034
2035 static void nv_drain_rx(struct net_device *dev)
2036 {
2037 struct fe_priv *np = netdev_priv(dev);
2038 int i;
2039
2040 for (i = 0; i < np->rx_ring_size; i++) {
2041 if (!nv_optimized(np)) {
2042 np->rx_ring.orig[i].flaglen = 0;
2043 np->rx_ring.orig[i].buf = 0;
2044 } else {
2045 np->rx_ring.ex[i].flaglen = 0;
2046 np->rx_ring.ex[i].txvlan = 0;
2047 np->rx_ring.ex[i].bufhigh = 0;
2048 np->rx_ring.ex[i].buflow = 0;
2049 }
2050 wmb();
2051 if (np->rx_skb[i].skb) {
2052 pci_unmap_single(np->pci_dev, np->rx_skb[i].dma,
2053 (skb_end_pointer(np->rx_skb[i].skb) -
2054 np->rx_skb[i].skb->data),
2055 PCI_DMA_FROMDEVICE);
2056 dev_kfree_skb(np->rx_skb[i].skb);
2057 np->rx_skb[i].skb = NULL;
2058 }
2059 }
2060 }
2061
2062 static void nv_drain_rxtx(struct net_device *dev)
2063 {
2064 nv_drain_tx(dev);
2065 nv_drain_rx(dev);
2066 }
2067
2068 static inline u32 nv_get_empty_tx_slots(struct fe_priv *np)
2069 {
2070 return (u32)(np->tx_ring_size - ((np->tx_ring_size + (np->put_tx_ctx - np->get_tx_ctx)) % np->tx_ring_size));
2071 }
2072
2073 static void nv_legacybackoff_reseed(struct net_device *dev)
2074 {
2075 u8 __iomem *base = get_hwbase(dev);
2076 u32 reg;
2077 u32 low;
2078 int tx_status = 0;
2079
2080 reg = readl(base + NvRegSlotTime) & ~NVREG_SLOTTIME_MASK;
2081 get_random_bytes(&low, sizeof(low));
2082 reg |= low & NVREG_SLOTTIME_MASK;
2083
2084 /* Need to stop tx before change takes effect.
2085 * Caller has already gained np->lock.
2086 */
2087 tx_status = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START;
2088 if (tx_status)
2089 nv_stop_tx(dev);
2090 nv_stop_rx(dev);
2091 writel(reg, base + NvRegSlotTime);
2092 if (tx_status)
2093 nv_start_tx(dev);
2094 nv_start_rx(dev);
2095 }
2096
2097 /* Gear Backoff Seeds */
2098 #define BACKOFF_SEEDSET_ROWS 8
2099 #define BACKOFF_SEEDSET_LFSRS 15
2100
2101 /* Known Good seed sets */
2102 static const u32 main_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2103 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2104 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 385, 761, 790, 974},
2105 {145, 155, 165, 175, 185, 196, 235, 245, 255, 265, 275, 285, 660, 690, 874},
2106 {245, 255, 265, 575, 385, 298, 335, 345, 355, 366, 375, 386, 761, 790, 974},
2107 {266, 265, 276, 585, 397, 208, 345, 355, 365, 376, 385, 396, 771, 700, 984},
2108 {266, 265, 276, 586, 397, 208, 346, 355, 365, 376, 285, 396, 771, 700, 984},
2109 {366, 365, 376, 686, 497, 308, 447, 455, 466, 476, 485, 496, 871, 800, 84},
2110 {466, 465, 476, 786, 597, 408, 547, 555, 566, 576, 585, 597, 971, 900, 184} };
2111
2112 static const u32 gear_seedset[BACKOFF_SEEDSET_ROWS][BACKOFF_SEEDSET_LFSRS] = {
2113 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2114 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2115 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 397},
2116 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2117 {251, 262, 273, 324, 319, 508, 375, 364, 341, 371, 398, 193, 375, 30, 295},
2118 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2119 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395},
2120 {351, 375, 373, 469, 551, 639, 477, 464, 441, 472, 498, 293, 476, 130, 395} };
2121
2122 static void nv_gear_backoff_reseed(struct net_device *dev)
2123 {
2124 u8 __iomem *base = get_hwbase(dev);
2125 u32 miniseed1, miniseed2, miniseed2_reversed, miniseed3, miniseed3_reversed;
2126 u32 temp, seedset, combinedSeed;
2127 int i;
2128
2129 /* Setup seed for free running LFSR */
2130 /* We are going to read the time stamp counter 3 times
2131 and swizzle bits around to increase randomness */
2132 get_random_bytes(&miniseed1, sizeof(miniseed1));
2133 miniseed1 &= 0x0fff;
2134 if (miniseed1 == 0)
2135 miniseed1 = 0xabc;
2136
2137 get_random_bytes(&miniseed2, sizeof(miniseed2));
2138 miniseed2 &= 0x0fff;
2139 if (miniseed2 == 0)
2140 miniseed2 = 0xabc;
2141 miniseed2_reversed =
2142 ((miniseed2 & 0xF00) >> 8) |
2143 (miniseed2 & 0x0F0) |
2144 ((miniseed2 & 0x00F) << 8);
2145
2146 get_random_bytes(&miniseed3, sizeof(miniseed3));
2147 miniseed3 &= 0x0fff;
2148 if (miniseed3 == 0)
2149 miniseed3 = 0xabc;
2150 miniseed3_reversed =
2151 ((miniseed3 & 0xF00) >> 8) |
2152 (miniseed3 & 0x0F0) |
2153 ((miniseed3 & 0x00F) << 8);
2154
2155 combinedSeed = ((miniseed1 ^ miniseed2_reversed) << 12) |
2156 (miniseed2 ^ miniseed3_reversed);
2157
2158 /* Seeds can not be zero */
2159 if ((combinedSeed & NVREG_BKOFFCTRL_SEED_MASK) == 0)
2160 combinedSeed |= 0x08;
2161 if ((combinedSeed & (NVREG_BKOFFCTRL_SEED_MASK << NVREG_BKOFFCTRL_GEAR)) == 0)
2162 combinedSeed |= 0x8000;
2163
2164 /* No need to disable tx here */
2165 temp = NVREG_BKOFFCTRL_DEFAULT | (0 << NVREG_BKOFFCTRL_SELECT);
2166 temp |= combinedSeed & NVREG_BKOFFCTRL_SEED_MASK;
2167 temp |= combinedSeed >> NVREG_BKOFFCTRL_GEAR;
2168 writel(temp, base + NvRegBackOffControl);
2169
2170 /* Setup seeds for all gear LFSRs. */
2171 get_random_bytes(&seedset, sizeof(seedset));
2172 seedset = seedset % BACKOFF_SEEDSET_ROWS;
2173 for (i = 1; i <= BACKOFF_SEEDSET_LFSRS; i++) {
2174 temp = NVREG_BKOFFCTRL_DEFAULT | (i << NVREG_BKOFFCTRL_SELECT);
2175 temp |= main_seedset[seedset][i-1] & 0x3ff;
2176 temp |= ((gear_seedset[seedset][i-1] & 0x3ff) << NVREG_BKOFFCTRL_GEAR);
2177 writel(temp, base + NvRegBackOffControl);
2178 }
2179 }
2180
2181 /*
2182 * nv_start_xmit: dev->hard_start_xmit function
2183 * Called with netif_tx_lock held.
2184 */
2185 static netdev_tx_t nv_start_xmit(struct sk_buff *skb, struct net_device *dev)
2186 {
2187 struct fe_priv *np = netdev_priv(dev);
2188 u32 tx_flags = 0;
2189 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
2190 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2191 unsigned int i;
2192 u32 offset = 0;
2193 u32 bcnt;
2194 u32 size = skb_headlen(skb);
2195 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2196 u32 empty_slots;
2197 struct ring_desc *put_tx;
2198 struct ring_desc *start_tx;
2199 struct ring_desc *prev_tx;
2200 struct nv_skb_map *prev_tx_ctx;
2201 struct nv_skb_map *tmp_tx_ctx = NULL, *start_tx_ctx = NULL;
2202 unsigned long flags;
2203
2204 /* add fragments to entries count */
2205 for (i = 0; i < fragments; i++) {
2206 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2207
2208 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2209 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2210 }
2211
2212 spin_lock_irqsave(&np->lock, flags);
2213 empty_slots = nv_get_empty_tx_slots(np);
2214 if (unlikely(empty_slots <= entries)) {
2215 netif_stop_queue(dev);
2216 np->tx_stop = 1;
2217 spin_unlock_irqrestore(&np->lock, flags);
2218 return NETDEV_TX_BUSY;
2219 }
2220 spin_unlock_irqrestore(&np->lock, flags);
2221
2222 start_tx = put_tx = np->put_tx.orig;
2223
2224 /* setup the header buffer */
2225 do {
2226 prev_tx = put_tx;
2227 prev_tx_ctx = np->put_tx_ctx;
2228 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2229 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2230 PCI_DMA_TODEVICE);
2231 if (pci_dma_mapping_error(np->pci_dev,
2232 np->put_tx_ctx->dma)) {
2233 /* on DMA mapping error - drop the packet */
2234 kfree_skb(skb);
2235 u64_stats_update_begin(&np->swstats_tx_syncp);
2236 np->stat_tx_dropped++;
2237 u64_stats_update_end(&np->swstats_tx_syncp);
2238 return NETDEV_TX_OK;
2239 }
2240 np->put_tx_ctx->dma_len = bcnt;
2241 np->put_tx_ctx->dma_single = 1;
2242 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2243 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2244
2245 tx_flags = np->tx_flags;
2246 offset += bcnt;
2247 size -= bcnt;
2248 if (unlikely(put_tx++ == np->last_tx.orig))
2249 put_tx = np->first_tx.orig;
2250 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2251 np->put_tx_ctx = np->first_tx_ctx;
2252 } while (size);
2253
2254 /* setup the fragments */
2255 for (i = 0; i < fragments; i++) {
2256 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2257 u32 frag_size = skb_frag_size(frag);
2258 offset = 0;
2259
2260 do {
2261 prev_tx = put_tx;
2262 prev_tx_ctx = np->put_tx_ctx;
2263 if (!start_tx_ctx)
2264 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2265
2266 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2267 np->put_tx_ctx->dma = skb_frag_dma_map(
2268 &np->pci_dev->dev,
2269 frag, offset,
2270 bcnt,
2271 DMA_TO_DEVICE);
2272 if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) {
2273
2274 /* Unwind the mapped fragments */
2275 do {
2276 nv_unmap_txskb(np, start_tx_ctx);
2277 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2278 tmp_tx_ctx = np->first_tx_ctx;
2279 } while (tmp_tx_ctx != np->put_tx_ctx);
2280 kfree_skb(skb);
2281 np->put_tx_ctx = start_tx_ctx;
2282 u64_stats_update_begin(&np->swstats_tx_syncp);
2283 np->stat_tx_dropped++;
2284 u64_stats_update_end(&np->swstats_tx_syncp);
2285 return NETDEV_TX_OK;
2286 }
2287
2288 np->put_tx_ctx->dma_len = bcnt;
2289 np->put_tx_ctx->dma_single = 0;
2290 put_tx->buf = cpu_to_le32(np->put_tx_ctx->dma);
2291 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2292
2293 offset += bcnt;
2294 frag_size -= bcnt;
2295 if (unlikely(put_tx++ == np->last_tx.orig))
2296 put_tx = np->first_tx.orig;
2297 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2298 np->put_tx_ctx = np->first_tx_ctx;
2299 } while (frag_size);
2300 }
2301
2302 /* set last fragment flag */
2303 prev_tx->flaglen |= cpu_to_le32(tx_flags_extra);
2304
2305 /* save skb in this slot's context area */
2306 prev_tx_ctx->skb = skb;
2307
2308 if (skb_is_gso(skb))
2309 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2310 else
2311 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2312 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2313
2314 spin_lock_irqsave(&np->lock, flags);
2315
2316 /* set tx flags */
2317 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2318
2319 netdev_sent_queue(np->dev, skb->len);
2320
2321 skb_tx_timestamp(skb);
2322
2323 np->put_tx.orig = put_tx;
2324
2325 spin_unlock_irqrestore(&np->lock, flags);
2326
2327 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2328 return NETDEV_TX_OK;
2329 }
2330
2331 static netdev_tx_t nv_start_xmit_optimized(struct sk_buff *skb,
2332 struct net_device *dev)
2333 {
2334 struct fe_priv *np = netdev_priv(dev);
2335 u32 tx_flags = 0;
2336 u32 tx_flags_extra;
2337 unsigned int fragments = skb_shinfo(skb)->nr_frags;
2338 unsigned int i;
2339 u32 offset = 0;
2340 u32 bcnt;
2341 u32 size = skb_headlen(skb);
2342 u32 entries = (size >> NV_TX2_TSO_MAX_SHIFT) + ((size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2343 u32 empty_slots;
2344 struct ring_desc_ex *put_tx;
2345 struct ring_desc_ex *start_tx;
2346 struct ring_desc_ex *prev_tx;
2347 struct nv_skb_map *prev_tx_ctx;
2348 struct nv_skb_map *start_tx_ctx = NULL;
2349 struct nv_skb_map *tmp_tx_ctx = NULL;
2350 unsigned long flags;
2351
2352 /* add fragments to entries count */
2353 for (i = 0; i < fragments; i++) {
2354 u32 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[i]);
2355
2356 entries += (frag_size >> NV_TX2_TSO_MAX_SHIFT) +
2357 ((frag_size & (NV_TX2_TSO_MAX_SIZE-1)) ? 1 : 0);
2358 }
2359
2360 spin_lock_irqsave(&np->lock, flags);
2361 empty_slots = nv_get_empty_tx_slots(np);
2362 if (unlikely(empty_slots <= entries)) {
2363 netif_stop_queue(dev);
2364 np->tx_stop = 1;
2365 spin_unlock_irqrestore(&np->lock, flags);
2366 return NETDEV_TX_BUSY;
2367 }
2368 spin_unlock_irqrestore(&np->lock, flags);
2369
2370 start_tx = put_tx = np->put_tx.ex;
2371 start_tx_ctx = np->put_tx_ctx;
2372
2373 /* setup the header buffer */
2374 do {
2375 prev_tx = put_tx;
2376 prev_tx_ctx = np->put_tx_ctx;
2377 bcnt = (size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : size;
2378 np->put_tx_ctx->dma = pci_map_single(np->pci_dev, skb->data + offset, bcnt,
2379 PCI_DMA_TODEVICE);
2380 if (pci_dma_mapping_error(np->pci_dev,
2381 np->put_tx_ctx->dma)) {
2382 /* on DMA mapping error - drop the packet */
2383 kfree_skb(skb);
2384 u64_stats_update_begin(&np->swstats_tx_syncp);
2385 np->stat_tx_dropped++;
2386 u64_stats_update_end(&np->swstats_tx_syncp);
2387 return NETDEV_TX_OK;
2388 }
2389 np->put_tx_ctx->dma_len = bcnt;
2390 np->put_tx_ctx->dma_single = 1;
2391 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2392 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2393 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2394
2395 tx_flags = NV_TX2_VALID;
2396 offset += bcnt;
2397 size -= bcnt;
2398 if (unlikely(put_tx++ == np->last_tx.ex))
2399 put_tx = np->first_tx.ex;
2400 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2401 np->put_tx_ctx = np->first_tx_ctx;
2402 } while (size);
2403
2404 /* setup the fragments */
2405 for (i = 0; i < fragments; i++) {
2406 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2407 u32 frag_size = skb_frag_size(frag);
2408 offset = 0;
2409
2410 do {
2411 prev_tx = put_tx;
2412 prev_tx_ctx = np->put_tx_ctx;
2413 bcnt = (frag_size > NV_TX2_TSO_MAX_SIZE) ? NV_TX2_TSO_MAX_SIZE : frag_size;
2414 if (!start_tx_ctx)
2415 start_tx_ctx = tmp_tx_ctx = np->put_tx_ctx;
2416 np->put_tx_ctx->dma = skb_frag_dma_map(
2417 &np->pci_dev->dev,
2418 frag, offset,
2419 bcnt,
2420 DMA_TO_DEVICE);
2421
2422 if (dma_mapping_error(&np->pci_dev->dev, np->put_tx_ctx->dma)) {
2423
2424 /* Unwind the mapped fragments */
2425 do {
2426 nv_unmap_txskb(np, start_tx_ctx);
2427 if (unlikely(tmp_tx_ctx++ == np->last_tx_ctx))
2428 tmp_tx_ctx = np->first_tx_ctx;
2429 } while (tmp_tx_ctx != np->put_tx_ctx);
2430 kfree_skb(skb);
2431 np->put_tx_ctx = start_tx_ctx;
2432 u64_stats_update_begin(&np->swstats_tx_syncp);
2433 np->stat_tx_dropped++;
2434 u64_stats_update_end(&np->swstats_tx_syncp);
2435 return NETDEV_TX_OK;
2436 }
2437 np->put_tx_ctx->dma_len = bcnt;
2438 np->put_tx_ctx->dma_single = 0;
2439 put_tx->bufhigh = cpu_to_le32(dma_high(np->put_tx_ctx->dma));
2440 put_tx->buflow = cpu_to_le32(dma_low(np->put_tx_ctx->dma));
2441 put_tx->flaglen = cpu_to_le32((bcnt-1) | tx_flags);
2442
2443 offset += bcnt;
2444 frag_size -= bcnt;
2445 if (unlikely(put_tx++ == np->last_tx.ex))
2446 put_tx = np->first_tx.ex;
2447 if (unlikely(np->put_tx_ctx++ == np->last_tx_ctx))
2448 np->put_tx_ctx = np->first_tx_ctx;
2449 } while (frag_size);
2450 }
2451
2452 /* set last fragment flag */
2453 prev_tx->flaglen |= cpu_to_le32(NV_TX2_LASTPACKET);
2454
2455 /* save skb in this slot's context area */
2456 prev_tx_ctx->skb = skb;
2457
2458 if (skb_is_gso(skb))
2459 tx_flags_extra = NV_TX2_TSO | (skb_shinfo(skb)->gso_size << NV_TX2_TSO_SHIFT);
2460 else
2461 tx_flags_extra = skb->ip_summed == CHECKSUM_PARTIAL ?
2462 NV_TX2_CHECKSUM_L3 | NV_TX2_CHECKSUM_L4 : 0;
2463
2464 /* vlan tag */
2465 if (vlan_tx_tag_present(skb))
2466 start_tx->txvlan = cpu_to_le32(NV_TX3_VLAN_TAG_PRESENT |
2467 vlan_tx_tag_get(skb));
2468 else
2469 start_tx->txvlan = 0;
2470
2471 spin_lock_irqsave(&np->lock, flags);
2472
2473 if (np->tx_limit) {
2474 /* Limit the number of outstanding tx. Setup all fragments, but
2475 * do not set the VALID bit on the first descriptor. Save a pointer
2476 * to that descriptor and also for next skb_map element.
2477 */
2478
2479 if (np->tx_pkts_in_progress == NV_TX_LIMIT_COUNT) {
2480 if (!np->tx_change_owner)
2481 np->tx_change_owner = start_tx_ctx;
2482
2483 /* remove VALID bit */
2484 tx_flags &= ~NV_TX2_VALID;
2485 start_tx_ctx->first_tx_desc = start_tx;
2486 start_tx_ctx->next_tx_ctx = np->put_tx_ctx;
2487 np->tx_end_flip = np->put_tx_ctx;
2488 } else {
2489 np->tx_pkts_in_progress++;
2490 }
2491 }
2492
2493 /* set tx flags */
2494 start_tx->flaglen |= cpu_to_le32(tx_flags | tx_flags_extra);
2495
2496 netdev_sent_queue(np->dev, skb->len);
2497
2498 skb_tx_timestamp(skb);
2499
2500 np->put_tx.ex = put_tx;
2501
2502 spin_unlock_irqrestore(&np->lock, flags);
2503
2504 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2505 return NETDEV_TX_OK;
2506 }
2507
2508 static inline void nv_tx_flip_ownership(struct net_device *dev)
2509 {
2510 struct fe_priv *np = netdev_priv(dev);
2511
2512 np->tx_pkts_in_progress--;
2513 if (np->tx_change_owner) {
2514 np->tx_change_owner->first_tx_desc->flaglen |=
2515 cpu_to_le32(NV_TX2_VALID);
2516 np->tx_pkts_in_progress++;
2517
2518 np->tx_change_owner = np->tx_change_owner->next_tx_ctx;
2519 if (np->tx_change_owner == np->tx_end_flip)
2520 np->tx_change_owner = NULL;
2521
2522 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
2523 }
2524 }
2525
2526 /*
2527 * nv_tx_done: check for completed packets, release the skbs.
2528 *
2529 * Caller must own np->lock.
2530 */
2531 static int nv_tx_done(struct net_device *dev, int limit)
2532 {
2533 struct fe_priv *np = netdev_priv(dev);
2534 u32 flags;
2535 int tx_work = 0;
2536 struct ring_desc *orig_get_tx = np->get_tx.orig;
2537 unsigned int bytes_compl = 0;
2538
2539 while ((np->get_tx.orig != np->put_tx.orig) &&
2540 !((flags = le32_to_cpu(np->get_tx.orig->flaglen)) & NV_TX_VALID) &&
2541 (tx_work < limit)) {
2542
2543 nv_unmap_txskb(np, np->get_tx_ctx);
2544
2545 if (np->desc_ver == DESC_VER_1) {
2546 if (flags & NV_TX_LASTPACKET) {
2547 if (flags & NV_TX_ERROR) {
2548 if ((flags & NV_TX_RETRYERROR)
2549 && !(flags & NV_TX_RETRYCOUNT_MASK))
2550 nv_legacybackoff_reseed(dev);
2551 } else {
2552 u64_stats_update_begin(&np->swstats_tx_syncp);
2553 np->stat_tx_packets++;
2554 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2555 u64_stats_update_end(&np->swstats_tx_syncp);
2556 }
2557 bytes_compl += np->get_tx_ctx->skb->len;
2558 dev_kfree_skb_any(np->get_tx_ctx->skb);
2559 np->get_tx_ctx->skb = NULL;
2560 tx_work++;
2561 }
2562 } else {
2563 if (flags & NV_TX2_LASTPACKET) {
2564 if (flags & NV_TX2_ERROR) {
2565 if ((flags & NV_TX2_RETRYERROR)
2566 && !(flags & NV_TX2_RETRYCOUNT_MASK))
2567 nv_legacybackoff_reseed(dev);
2568 } else {
2569 u64_stats_update_begin(&np->swstats_tx_syncp);
2570 np->stat_tx_packets++;
2571 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2572 u64_stats_update_end(&np->swstats_tx_syncp);
2573 }
2574 bytes_compl += np->get_tx_ctx->skb->len;
2575 dev_kfree_skb_any(np->get_tx_ctx->skb);
2576 np->get_tx_ctx->skb = NULL;
2577 tx_work++;
2578 }
2579 }
2580 if (unlikely(np->get_tx.orig++ == np->last_tx.orig))
2581 np->get_tx.orig = np->first_tx.orig;
2582 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2583 np->get_tx_ctx = np->first_tx_ctx;
2584 }
2585
2586 netdev_completed_queue(np->dev, tx_work, bytes_compl);
2587
2588 if (unlikely((np->tx_stop == 1) && (np->get_tx.orig != orig_get_tx))) {
2589 np->tx_stop = 0;
2590 netif_wake_queue(dev);
2591 }
2592 return tx_work;
2593 }
2594
2595 static int nv_tx_done_optimized(struct net_device *dev, int limit)
2596 {
2597 struct fe_priv *np = netdev_priv(dev);
2598 u32 flags;
2599 int tx_work = 0;
2600 struct ring_desc_ex *orig_get_tx = np->get_tx.ex;
2601 unsigned long bytes_cleaned = 0;
2602
2603 while ((np->get_tx.ex != np->put_tx.ex) &&
2604 !((flags = le32_to_cpu(np->get_tx.ex->flaglen)) & NV_TX2_VALID) &&
2605 (tx_work < limit)) {
2606
2607 nv_unmap_txskb(np, np->get_tx_ctx);
2608
2609 if (flags & NV_TX2_LASTPACKET) {
2610 if (flags & NV_TX2_ERROR) {
2611 if ((flags & NV_TX2_RETRYERROR)
2612 && !(flags & NV_TX2_RETRYCOUNT_MASK)) {
2613 if (np->driver_data & DEV_HAS_GEAR_MODE)
2614 nv_gear_backoff_reseed(dev);
2615 else
2616 nv_legacybackoff_reseed(dev);
2617 }
2618 } else {
2619 u64_stats_update_begin(&np->swstats_tx_syncp);
2620 np->stat_tx_packets++;
2621 np->stat_tx_bytes += np->get_tx_ctx->skb->len;
2622 u64_stats_update_end(&np->swstats_tx_syncp);
2623 }
2624
2625 bytes_cleaned += np->get_tx_ctx->skb->len;
2626 dev_kfree_skb_any(np->get_tx_ctx->skb);
2627 np->get_tx_ctx->skb = NULL;
2628 tx_work++;
2629
2630 if (np->tx_limit)
2631 nv_tx_flip_ownership(dev);
2632 }
2633
2634 if (unlikely(np->get_tx.ex++ == np->last_tx.ex))
2635 np->get_tx.ex = np->first_tx.ex;
2636 if (unlikely(np->get_tx_ctx++ == np->last_tx_ctx))
2637 np->get_tx_ctx = np->first_tx_ctx;
2638 }
2639
2640 netdev_completed_queue(np->dev, tx_work, bytes_cleaned);
2641
2642 if (unlikely((np->tx_stop == 1) && (np->get_tx.ex != orig_get_tx))) {
2643 np->tx_stop = 0;
2644 netif_wake_queue(dev);
2645 }
2646 return tx_work;
2647 }
2648
2649 /*
2650 * nv_tx_timeout: dev->tx_timeout function
2651 * Called with netif_tx_lock held.
2652 */
2653 static void nv_tx_timeout(struct net_device *dev)
2654 {
2655 struct fe_priv *np = netdev_priv(dev);
2656 u8 __iomem *base = get_hwbase(dev);
2657 u32 status;
2658 union ring_type put_tx;
2659 int saved_tx_limit;
2660
2661 if (np->msi_flags & NV_MSI_X_ENABLED)
2662 status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
2663 else
2664 status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
2665
2666 netdev_warn(dev, "Got tx_timeout. irq status: %08x\n", status);
2667
2668 if (unlikely(debug_tx_timeout)) {
2669 int i;
2670
2671 netdev_info(dev, "Ring at %lx\n", (unsigned long)np->ring_addr);
2672 netdev_info(dev, "Dumping tx registers\n");
2673 for (i = 0; i <= np->register_size; i += 32) {
2674 netdev_info(dev,
2675 "%3x: %08x %08x %08x %08x "
2676 "%08x %08x %08x %08x\n",
2677 i,
2678 readl(base + i + 0), readl(base + i + 4),
2679 readl(base + i + 8), readl(base + i + 12),
2680 readl(base + i + 16), readl(base + i + 20),
2681 readl(base + i + 24), readl(base + i + 28));
2682 }
2683 netdev_info(dev, "Dumping tx ring\n");
2684 for (i = 0; i < np->tx_ring_size; i += 4) {
2685 if (!nv_optimized(np)) {
2686 netdev_info(dev,
2687 "%03x: %08x %08x // %08x %08x "
2688 "// %08x %08x // %08x %08x\n",
2689 i,
2690 le32_to_cpu(np->tx_ring.orig[i].buf),
2691 le32_to_cpu(np->tx_ring.orig[i].flaglen),
2692 le32_to_cpu(np->tx_ring.orig[i+1].buf),
2693 le32_to_cpu(np->tx_ring.orig[i+1].flaglen),
2694 le32_to_cpu(np->tx_ring.orig[i+2].buf),
2695 le32_to_cpu(np->tx_ring.orig[i+2].flaglen),
2696 le32_to_cpu(np->tx_ring.orig[i+3].buf),
2697 le32_to_cpu(np->tx_ring.orig[i+3].flaglen));
2698 } else {
2699 netdev_info(dev,
2700 "%03x: %08x %08x %08x "
2701 "// %08x %08x %08x "
2702 "// %08x %08x %08x "
2703 "// %08x %08x %08x\n",
2704 i,
2705 le32_to_cpu(np->tx_ring.ex[i].bufhigh),
2706 le32_to_cpu(np->tx_ring.ex[i].buflow),
2707 le32_to_cpu(np->tx_ring.ex[i].flaglen),
2708 le32_to_cpu(np->tx_ring.ex[i+1].bufhigh),
2709 le32_to_cpu(np->tx_ring.ex[i+1].buflow),
2710 le32_to_cpu(np->tx_ring.ex[i+1].flaglen),
2711 le32_to_cpu(np->tx_ring.ex[i+2].bufhigh),
2712 le32_to_cpu(np->tx_ring.ex[i+2].buflow),
2713 le32_to_cpu(np->tx_ring.ex[i+2].flaglen),
2714 le32_to_cpu(np->tx_ring.ex[i+3].bufhigh),
2715 le32_to_cpu(np->tx_ring.ex[i+3].buflow),
2716 le32_to_cpu(np->tx_ring.ex[i+3].flaglen));
2717 }
2718 }
2719 }
2720
2721 spin_lock_irq(&np->lock);
2722
2723 /* 1) stop tx engine */
2724 nv_stop_tx(dev);
2725
2726 /* 2) complete any outstanding tx and do not give HW any limited tx pkts */
2727 saved_tx_limit = np->tx_limit;
2728 np->tx_limit = 0; /* prevent giving HW any limited pkts */
2729 np->tx_stop = 0; /* prevent waking tx queue */
2730 if (!nv_optimized(np))
2731 nv_tx_done(dev, np->tx_ring_size);
2732 else
2733 nv_tx_done_optimized(dev, np->tx_ring_size);
2734
2735 /* save current HW position */
2736 if (np->tx_change_owner)
2737 put_tx.ex = np->tx_change_owner->first_tx_desc;
2738 else
2739 put_tx = np->put_tx;
2740
2741 /* 3) clear all tx state */
2742 nv_drain_tx(dev);
2743 nv_init_tx(dev);
2744
2745 /* 4) restore state to current HW position */
2746 np->get_tx = np->put_tx = put_tx;
2747 np->tx_limit = saved_tx_limit;
2748
2749 /* 5) restart tx engine */
2750 nv_start_tx(dev);
2751 netif_wake_queue(dev);
2752 spin_unlock_irq(&np->lock);
2753 }
2754
2755 /*
2756 * Called when the nic notices a mismatch between the actual data len on the
2757 * wire and the len indicated in the 802 header
2758 */
2759 static int nv_getlen(struct net_device *dev, void *packet, int datalen)
2760 {
2761 int hdrlen; /* length of the 802 header */
2762 int protolen; /* length as stored in the proto field */
2763
2764 /* 1) calculate len according to header */
2765 if (((struct vlan_ethhdr *)packet)->h_vlan_proto == htons(ETH_P_8021Q)) {
2766 protolen = ntohs(((struct vlan_ethhdr *)packet)->h_vlan_encapsulated_proto);
2767 hdrlen = VLAN_HLEN;
2768 } else {
2769 protolen = ntohs(((struct ethhdr *)packet)->h_proto);
2770 hdrlen = ETH_HLEN;
2771 }
2772 if (protolen > ETH_DATA_LEN)
2773 return datalen; /* Value in proto field not a len, no checks possible */
2774
2775 protolen += hdrlen;
2776 /* consistency checks: */
2777 if (datalen > ETH_ZLEN) {
2778 if (datalen >= protolen) {
2779 /* more data on wire than in 802 header, trim of
2780 * additional data.
2781 */
2782 return protolen;
2783 } else {
2784 /* less data on wire than mentioned in header.
2785 * Discard the packet.
2786 */
2787 return -1;
2788 }
2789 } else {
2790 /* short packet. Accept only if 802 values are also short */
2791 if (protolen > ETH_ZLEN) {
2792 return -1;
2793 }
2794 return datalen;
2795 }
2796 }
2797
2798 static int nv_rx_process(struct net_device *dev, int limit)
2799 {
2800 struct fe_priv *np = netdev_priv(dev);
2801 u32 flags;
2802 int rx_work = 0;
2803 struct sk_buff *skb;
2804 int len;
2805
2806 while ((np->get_rx.orig != np->put_rx.orig) &&
2807 !((flags = le32_to_cpu(np->get_rx.orig->flaglen)) & NV_RX_AVAIL) &&
2808 (rx_work < limit)) {
2809
2810 /*
2811 * the packet is for us - immediately tear down the pci mapping.
2812 * TODO: check if a prefetch of the first cacheline improves
2813 * the performance.
2814 */
2815 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2816 np->get_rx_ctx->dma_len,
2817 PCI_DMA_FROMDEVICE);
2818 skb = np->get_rx_ctx->skb;
2819 np->get_rx_ctx->skb = NULL;
2820
2821 /* look at what we actually got: */
2822 if (np->desc_ver == DESC_VER_1) {
2823 if (likely(flags & NV_RX_DESCRIPTORVALID)) {
2824 len = flags & LEN_MASK_V1;
2825 if (unlikely(flags & NV_RX_ERROR)) {
2826 if ((flags & NV_RX_ERROR_MASK) == NV_RX_ERROR4) {
2827 len = nv_getlen(dev, skb->data, len);
2828 if (len < 0) {
2829 dev_kfree_skb(skb);
2830 goto next_pkt;
2831 }
2832 }
2833 /* framing errors are soft errors */
2834 else if ((flags & NV_RX_ERROR_MASK) == NV_RX_FRAMINGERR) {
2835 if (flags & NV_RX_SUBSTRACT1)
2836 len--;
2837 }
2838 /* the rest are hard errors */
2839 else {
2840 if (flags & NV_RX_MISSEDFRAME) {
2841 u64_stats_update_begin(&np->swstats_rx_syncp);
2842 np->stat_rx_missed_errors++;
2843 u64_stats_update_end(&np->swstats_rx_syncp);
2844 }
2845 dev_kfree_skb(skb);
2846 goto next_pkt;
2847 }
2848 }
2849 } else {
2850 dev_kfree_skb(skb);
2851 goto next_pkt;
2852 }
2853 } else {
2854 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2855 len = flags & LEN_MASK_V2;
2856 if (unlikely(flags & NV_RX2_ERROR)) {
2857 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2858 len = nv_getlen(dev, skb->data, len);
2859 if (len < 0) {
2860 dev_kfree_skb(skb);
2861 goto next_pkt;
2862 }
2863 }
2864 /* framing errors are soft errors */
2865 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2866 if (flags & NV_RX2_SUBSTRACT1)
2867 len--;
2868 }
2869 /* the rest are hard errors */
2870 else {
2871 dev_kfree_skb(skb);
2872 goto next_pkt;
2873 }
2874 }
2875 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2876 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2877 skb->ip_summed = CHECKSUM_UNNECESSARY;
2878 } else {
2879 dev_kfree_skb(skb);
2880 goto next_pkt;
2881 }
2882 }
2883 /* got a valid packet - forward it to the network core */
2884 skb_put(skb, len);
2885 skb->protocol = eth_type_trans(skb, dev);
2886 napi_gro_receive(&np->napi, skb);
2887 u64_stats_update_begin(&np->swstats_rx_syncp);
2888 np->stat_rx_packets++;
2889 np->stat_rx_bytes += len;
2890 u64_stats_update_end(&np->swstats_rx_syncp);
2891 next_pkt:
2892 if (unlikely(np->get_rx.orig++ == np->last_rx.orig))
2893 np->get_rx.orig = np->first_rx.orig;
2894 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2895 np->get_rx_ctx = np->first_rx_ctx;
2896
2897 rx_work++;
2898 }
2899
2900 return rx_work;
2901 }
2902
2903 static int nv_rx_process_optimized(struct net_device *dev, int limit)
2904 {
2905 struct fe_priv *np = netdev_priv(dev);
2906 u32 flags;
2907 u32 vlanflags = 0;
2908 int rx_work = 0;
2909 struct sk_buff *skb;
2910 int len;
2911
2912 while ((np->get_rx.ex != np->put_rx.ex) &&
2913 !((flags = le32_to_cpu(np->get_rx.ex->flaglen)) & NV_RX2_AVAIL) &&
2914 (rx_work < limit)) {
2915
2916 /*
2917 * the packet is for us - immediately tear down the pci mapping.
2918 * TODO: check if a prefetch of the first cacheline improves
2919 * the performance.
2920 */
2921 pci_unmap_single(np->pci_dev, np->get_rx_ctx->dma,
2922 np->get_rx_ctx->dma_len,
2923 PCI_DMA_FROMDEVICE);
2924 skb = np->get_rx_ctx->skb;
2925 np->get_rx_ctx->skb = NULL;
2926
2927 /* look at what we actually got: */
2928 if (likely(flags & NV_RX2_DESCRIPTORVALID)) {
2929 len = flags & LEN_MASK_V2;
2930 if (unlikely(flags & NV_RX2_ERROR)) {
2931 if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_ERROR4) {
2932 len = nv_getlen(dev, skb->data, len);
2933 if (len < 0) {
2934 dev_kfree_skb(skb);
2935 goto next_pkt;
2936 }
2937 }
2938 /* framing errors are soft errors */
2939 else if ((flags & NV_RX2_ERROR_MASK) == NV_RX2_FRAMINGERR) {
2940 if (flags & NV_RX2_SUBSTRACT1)
2941 len--;
2942 }
2943 /* the rest are hard errors */
2944 else {
2945 dev_kfree_skb(skb);
2946 goto next_pkt;
2947 }
2948 }
2949
2950 if (((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_TCP) || /*ip and tcp */
2951 ((flags & NV_RX2_CHECKSUMMASK) == NV_RX2_CHECKSUM_IP_UDP)) /*ip and udp */
2952 skb->ip_summed = CHECKSUM_UNNECESSARY;
2953
2954 /* got a valid packet - forward it to the network core */
2955 skb_put(skb, len);
2956 skb->protocol = eth_type_trans(skb, dev);
2957 prefetch(skb->data);
2958
2959 vlanflags = le32_to_cpu(np->get_rx.ex->buflow);
2960
2961 /*
2962 * There's need to check for NETIF_F_HW_VLAN_CTAG_RX
2963 * here. Even if vlan rx accel is disabled,
2964 * NV_RX3_VLAN_TAG_PRESENT is pseudo randomly set.
2965 */
2966 if (dev->features & NETIF_F_HW_VLAN_CTAG_RX &&
2967 vlanflags & NV_RX3_VLAN_TAG_PRESENT) {
2968 u16 vid = vlanflags & NV_RX3_VLAN_TAG_MASK;
2969
2970 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
2971 }
2972 napi_gro_receive(&np->napi, skb);
2973 u64_stats_update_begin(&np->swstats_rx_syncp);
2974 np->stat_rx_packets++;
2975 np->stat_rx_bytes += len;
2976 u64_stats_update_end(&np->swstats_rx_syncp);
2977 } else {
2978 dev_kfree_skb(skb);
2979 }
2980 next_pkt:
2981 if (unlikely(np->get_rx.ex++ == np->last_rx.ex))
2982 np->get_rx.ex = np->first_rx.ex;
2983 if (unlikely(np->get_rx_ctx++ == np->last_rx_ctx))
2984 np->get_rx_ctx = np->first_rx_ctx;
2985
2986 rx_work++;
2987 }
2988
2989 return rx_work;
2990 }
2991
2992 static void set_bufsize(struct net_device *dev)
2993 {
2994 struct fe_priv *np = netdev_priv(dev);
2995
2996 if (dev->mtu <= ETH_DATA_LEN)
2997 np->rx_buf_sz = ETH_DATA_LEN + NV_RX_HEADERS;
2998 else
2999 np->rx_buf_sz = dev->mtu + NV_RX_HEADERS;
3000 }
3001
3002 /*
3003 * nv_change_mtu: dev->change_mtu function
3004 * Called with dev_base_lock held for read.
3005 */
3006 static int nv_change_mtu(struct net_device *dev, int new_mtu)
3007 {
3008 struct fe_priv *np = netdev_priv(dev);
3009 int old_mtu;
3010
3011 if (new_mtu < 64 || new_mtu > np->pkt_limit)
3012 return -EINVAL;
3013
3014 old_mtu = dev->mtu;
3015 dev->mtu = new_mtu;
3016
3017 /* return early if the buffer sizes will not change */
3018 if (old_mtu <= ETH_DATA_LEN && new_mtu <= ETH_DATA_LEN)
3019 return 0;
3020 if (old_mtu == new_mtu)
3021 return 0;
3022
3023 /* synchronized against open : rtnl_lock() held by caller */
3024 if (netif_running(dev)) {
3025 u8 __iomem *base = get_hwbase(dev);
3026 /*
3027 * It seems that the nic preloads valid ring entries into an
3028 * internal buffer. The procedure for flushing everything is
3029 * guessed, there is probably a simpler approach.
3030 * Changing the MTU is a rare event, it shouldn't matter.
3031 */
3032 nv_disable_irq(dev);
3033 nv_napi_disable(dev);
3034 netif_tx_lock_bh(dev);
3035 netif_addr_lock(dev);
3036 spin_lock(&np->lock);
3037 /* stop engines */
3038 nv_stop_rxtx(dev);
3039 nv_txrx_reset(dev);
3040 /* drain rx queue */
3041 nv_drain_rxtx(dev);
3042 /* reinit driver view of the rx queue */
3043 set_bufsize(dev);
3044 if (nv_init_ring(dev)) {
3045 if (!np->in_shutdown)
3046 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3047 }
3048 /* reinit nic view of the rx queue */
3049 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
3050 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
3051 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
3052 base + NvRegRingSizes);
3053 pci_push(base);
3054 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
3055 pci_push(base);
3056
3057 /* restart rx engine */
3058 nv_start_rxtx(dev);
3059 spin_unlock(&np->lock);
3060 netif_addr_unlock(dev);
3061 netif_tx_unlock_bh(dev);
3062 nv_napi_enable(dev);
3063 nv_enable_irq(dev);
3064 }
3065 return 0;
3066 }
3067
3068 static void nv_copy_mac_to_hw(struct net_device *dev)
3069 {
3070 u8 __iomem *base = get_hwbase(dev);
3071 u32 mac[2];
3072
3073 mac[0] = (dev->dev_addr[0] << 0) + (dev->dev_addr[1] << 8) +
3074 (dev->dev_addr[2] << 16) + (dev->dev_addr[3] << 24);
3075 mac[1] = (dev->dev_addr[4] << 0) + (dev->dev_addr[5] << 8);
3076
3077 writel(mac[0], base + NvRegMacAddrA);
3078 writel(mac[1], base + NvRegMacAddrB);
3079 }
3080
3081 /*
3082 * nv_set_mac_address: dev->set_mac_address function
3083 * Called with rtnl_lock() held.
3084 */
3085 static int nv_set_mac_address(struct net_device *dev, void *addr)
3086 {
3087 struct fe_priv *np = netdev_priv(dev);
3088 struct sockaddr *macaddr = (struct sockaddr *)addr;
3089
3090 if (!is_valid_ether_addr(macaddr->sa_data))
3091 return -EADDRNOTAVAIL;
3092
3093 /* synchronized against open : rtnl_lock() held by caller */
3094 memcpy(dev->dev_addr, macaddr->sa_data, ETH_ALEN);
3095
3096 if (netif_running(dev)) {
3097 netif_tx_lock_bh(dev);
3098 netif_addr_lock(dev);
3099 spin_lock_irq(&np->lock);
3100
3101 /* stop rx engine */
3102 nv_stop_rx(dev);
3103
3104 /* set mac address */
3105 nv_copy_mac_to_hw(dev);
3106
3107 /* restart rx engine */
3108 nv_start_rx(dev);
3109 spin_unlock_irq(&np->lock);
3110 netif_addr_unlock(dev);
3111 netif_tx_unlock_bh(dev);
3112 } else {
3113 nv_copy_mac_to_hw(dev);
3114 }
3115 return 0;
3116 }
3117
3118 /*
3119 * nv_set_multicast: dev->set_multicast function
3120 * Called with netif_tx_lock held.
3121 */
3122 static void nv_set_multicast(struct net_device *dev)
3123 {
3124 struct fe_priv *np = netdev_priv(dev);
3125 u8 __iomem *base = get_hwbase(dev);
3126 u32 addr[2];
3127 u32 mask[2];
3128 u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX;
3129
3130 memset(addr, 0, sizeof(addr));
3131 memset(mask, 0, sizeof(mask));
3132
3133 if (dev->flags & IFF_PROMISC) {
3134 pff |= NVREG_PFF_PROMISC;
3135 } else {
3136 pff |= NVREG_PFF_MYADDR;
3137
3138 if (dev->flags & IFF_ALLMULTI || !netdev_mc_empty(dev)) {
3139 u32 alwaysOff[2];
3140 u32 alwaysOn[2];
3141
3142 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0xffffffff;
3143 if (dev->flags & IFF_ALLMULTI) {
3144 alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
3145 } else {
3146 struct netdev_hw_addr *ha;
3147
3148 netdev_for_each_mc_addr(ha, dev) {
3149 unsigned char *hw_addr = ha->addr;
3150 u32 a, b;
3151
3152 a = le32_to_cpu(*(__le32 *) hw_addr);
3153 b = le16_to_cpu(*(__le16 *) (&hw_addr[4]));
3154 alwaysOn[0] &= a;
3155 alwaysOff[0] &= ~a;
3156 alwaysOn[1] &= b;
3157 alwaysOff[1] &= ~b;
3158 }
3159 }
3160 addr[0] = alwaysOn[0];
3161 addr[1] = alwaysOn[1];
3162 mask[0] = alwaysOn[0] | alwaysOff[0];
3163 mask[1] = alwaysOn[1] | alwaysOff[1];
3164 } else {
3165 mask[0] = NVREG_MCASTMASKA_NONE;
3166 mask[1] = NVREG_MCASTMASKB_NONE;
3167 }
3168 }
3169 addr[0] |= NVREG_MCASTADDRA_FORCE;
3170 pff |= NVREG_PFF_ALWAYS;
3171 spin_lock_irq(&np->lock);
3172 nv_stop_rx(dev);
3173 writel(addr[0], base + NvRegMulticastAddrA);
3174 writel(addr[1], base + NvRegMulticastAddrB);
3175 writel(mask[0], base + NvRegMulticastMaskA);
3176 writel(mask[1], base + NvRegMulticastMaskB);
3177 writel(pff, base + NvRegPacketFilterFlags);
3178 nv_start_rx(dev);
3179 spin_unlock_irq(&np->lock);
3180 }
3181
3182 static void nv_update_pause(struct net_device *dev, u32 pause_flags)
3183 {
3184 struct fe_priv *np = netdev_priv(dev);
3185 u8 __iomem *base = get_hwbase(dev);
3186
3187 np->pause_flags &= ~(NV_PAUSEFRAME_TX_ENABLE | NV_PAUSEFRAME_RX_ENABLE);
3188
3189 if (np->pause_flags & NV_PAUSEFRAME_RX_CAPABLE) {
3190 u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX;
3191 if (pause_flags & NV_PAUSEFRAME_RX_ENABLE) {
3192 writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags);
3193 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3194 } else {
3195 writel(pff, base + NvRegPacketFilterFlags);
3196 }
3197 }
3198 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE) {
3199 u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX;
3200 if (pause_flags & NV_PAUSEFRAME_TX_ENABLE) {
3201 u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1;
3202 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V2)
3203 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2;
3204 if (np->driver_data & DEV_HAS_PAUSEFRAME_TX_V3) {
3205 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3;
3206 /* limit the number of tx pause frames to a default of 8 */
3207 writel(readl(base + NvRegTxPauseFrameLimit)|NVREG_TX_PAUSEFRAMELIMIT_ENABLE, base + NvRegTxPauseFrameLimit);
3208 }
3209 writel(pause_enable, base + NvRegTxPauseFrame);
3210 writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1);
3211 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3212 } else {
3213 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
3214 writel(regmisc, base + NvRegMisc1);
3215 }
3216 }
3217 }
3218
3219 static void nv_force_linkspeed(struct net_device *dev, int speed, int duplex)
3220 {
3221 struct fe_priv *np = netdev_priv(dev);
3222 u8 __iomem *base = get_hwbase(dev);
3223 u32 phyreg, txreg;
3224 int mii_status;
3225
3226 np->linkspeed = NVREG_LINKSPEED_FORCE|speed;
3227 np->duplex = duplex;
3228
3229 /* see if gigabit phy */
3230 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3231 if (mii_status & PHY_GIGABIT) {
3232 np->gigabit = PHY_GIGABIT;
3233 phyreg = readl(base + NvRegSlotTime);
3234 phyreg &= ~(0x3FF00);
3235 if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
3236 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3237 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
3238 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3239 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3240 phyreg |= NVREG_SLOTTIME_1000_FULL;
3241 writel(phyreg, base + NvRegSlotTime);
3242 }
3243
3244 phyreg = readl(base + NvRegPhyInterface);
3245 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3246 if (np->duplex == 0)
3247 phyreg |= PHY_HALF;
3248 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3249 phyreg |= PHY_100;
3250 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3251 NVREG_LINKSPEED_1000)
3252 phyreg |= PHY_1000;
3253 writel(phyreg, base + NvRegPhyInterface);
3254
3255 if (phyreg & PHY_RGMII) {
3256 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3257 NVREG_LINKSPEED_1000)
3258 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3259 else
3260 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3261 } else {
3262 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3263 }
3264 writel(txreg, base + NvRegTxDeferral);
3265
3266 if (np->desc_ver == DESC_VER_1) {
3267 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3268 } else {
3269 if ((np->linkspeed & NVREG_LINKSPEED_MASK) ==
3270 NVREG_LINKSPEED_1000)
3271 txreg = NVREG_TX_WM_DESC2_3_1000;
3272 else
3273 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3274 }
3275 writel(txreg, base + NvRegTxWatermark);
3276
3277 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3278 base + NvRegMisc1);
3279 pci_push(base);
3280 writel(np->linkspeed, base + NvRegLinkSpeed);
3281 pci_push(base);
3282
3283 return;
3284 }
3285
3286 /**
3287 * nv_update_linkspeed - Setup the MAC according to the link partner
3288 * @dev: Network device to be configured
3289 *
3290 * The function queries the PHY and checks if there is a link partner.
3291 * If yes, then it sets up the MAC accordingly. Otherwise, the MAC is
3292 * set to 10 MBit HD.
3293 *
3294 * The function returns 0 if there is no link partner and 1 if there is
3295 * a good link partner.
3296 */
3297 static int nv_update_linkspeed(struct net_device *dev)
3298 {
3299 struct fe_priv *np = netdev_priv(dev);
3300 u8 __iomem *base = get_hwbase(dev);
3301 int adv = 0;
3302 int lpa = 0;
3303 int adv_lpa, adv_pause, lpa_pause;
3304 int newls = np->linkspeed;
3305 int newdup = np->duplex;
3306 int mii_status;
3307 u32 bmcr;
3308 int retval = 0;
3309 u32 control_1000, status_1000, phyreg, pause_flags, txreg;
3310 u32 txrxFlags = 0;
3311 u32 phy_exp;
3312
3313 /* If device loopback is enabled, set carrier on and enable max link
3314 * speed.
3315 */
3316 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
3317 if (bmcr & BMCR_LOOPBACK) {
3318 if (netif_running(dev)) {
3319 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000, 1);
3320 if (!netif_carrier_ok(dev))
3321 netif_carrier_on(dev);
3322 }
3323 return 1;
3324 }
3325
3326 /* BMSR_LSTATUS is latched, read it twice:
3327 * we want the current value.
3328 */
3329 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3330 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
3331
3332 if (!(mii_status & BMSR_LSTATUS)) {
3333 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3334 newdup = 0;
3335 retval = 0;
3336 goto set_speed;
3337 }
3338
3339 if (np->autoneg == 0) {
3340 if (np->fixed_mode & LPA_100FULL) {
3341 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3342 newdup = 1;
3343 } else if (np->fixed_mode & LPA_100HALF) {
3344 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3345 newdup = 0;
3346 } else if (np->fixed_mode & LPA_10FULL) {
3347 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3348 newdup = 1;
3349 } else {
3350 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3351 newdup = 0;
3352 }
3353 retval = 1;
3354 goto set_speed;
3355 }
3356 /* check auto negotiation is complete */
3357 if (!(mii_status & BMSR_ANEGCOMPLETE)) {
3358 /* still in autonegotiation - configure nic for 10 MBit HD and wait. */
3359 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3360 newdup = 0;
3361 retval = 0;
3362 goto set_speed;
3363 }
3364
3365 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
3366 lpa = mii_rw(dev, np->phyaddr, MII_LPA, MII_READ);
3367
3368 retval = 1;
3369 if (np->gigabit == PHY_GIGABIT) {
3370 control_1000 = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
3371 status_1000 = mii_rw(dev, np->phyaddr, MII_STAT1000, MII_READ);
3372
3373 if ((control_1000 & ADVERTISE_1000FULL) &&
3374 (status_1000 & LPA_1000FULL)) {
3375 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000;
3376 newdup = 1;
3377 goto set_speed;
3378 }
3379 }
3380
3381 /* FIXME: handle parallel detection properly */
3382 adv_lpa = lpa & adv;
3383 if (adv_lpa & LPA_100FULL) {
3384 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3385 newdup = 1;
3386 } else if (adv_lpa & LPA_100HALF) {
3387 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100;
3388 newdup = 0;
3389 } else if (adv_lpa & LPA_10FULL) {
3390 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3391 newdup = 1;
3392 } else if (adv_lpa & LPA_10HALF) {
3393 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3394 newdup = 0;
3395 } else {
3396 newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
3397 newdup = 0;
3398 }
3399
3400 set_speed:
3401 if (np->duplex == newdup && np->linkspeed == newls)
3402 return retval;
3403
3404 np->duplex = newdup;
3405 np->linkspeed = newls;
3406
3407 /* The transmitter and receiver must be restarted for safe update */
3408 if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) {
3409 txrxFlags |= NV_RESTART_TX;
3410 nv_stop_tx(dev);
3411 }
3412 if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
3413 txrxFlags |= NV_RESTART_RX;
3414 nv_stop_rx(dev);
3415 }
3416
3417 if (np->gigabit == PHY_GIGABIT) {
3418 phyreg = readl(base + NvRegSlotTime);
3419 phyreg &= ~(0x3FF00);
3420 if (((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) ||
3421 ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100))
3422 phyreg |= NVREG_SLOTTIME_10_100_FULL;
3423 else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
3424 phyreg |= NVREG_SLOTTIME_1000_FULL;
3425 writel(phyreg, base + NvRegSlotTime);
3426 }
3427
3428 phyreg = readl(base + NvRegPhyInterface);
3429 phyreg &= ~(PHY_HALF|PHY_100|PHY_1000);
3430 if (np->duplex == 0)
3431 phyreg |= PHY_HALF;
3432 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100)
3433 phyreg |= PHY_100;
3434 else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3435 phyreg |= PHY_1000;
3436 writel(phyreg, base + NvRegPhyInterface);
3437
3438 phy_exp = mii_rw(dev, np->phyaddr, MII_EXPANSION, MII_READ) & EXPANSION_NWAY; /* autoneg capable */
3439 if (phyreg & PHY_RGMII) {
3440 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) {
3441 txreg = NVREG_TX_DEFERRAL_RGMII_1000;
3442 } else {
3443 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX)) {
3444 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10)
3445 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10;
3446 else
3447 txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100;
3448 } else {
3449 txreg = NVREG_TX_DEFERRAL_RGMII_10_100;
3450 }
3451 }
3452 } else {
3453 if (!phy_exp && !np->duplex && (np->driver_data & DEV_HAS_COLLISION_FIX))
3454 txreg = NVREG_TX_DEFERRAL_MII_STRETCH;
3455 else
3456 txreg = NVREG_TX_DEFERRAL_DEFAULT;
3457 }
3458 writel(txreg, base + NvRegTxDeferral);
3459
3460 if (np->desc_ver == DESC_VER_1) {
3461 txreg = NVREG_TX_WM_DESC1_DEFAULT;
3462 } else {
3463 if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000)
3464 txreg = NVREG_TX_WM_DESC2_3_1000;
3465 else
3466 txreg = NVREG_TX_WM_DESC2_3_DEFAULT;
3467 }
3468 writel(txreg, base + NvRegTxWatermark);
3469
3470 writel(NVREG_MISC1_FORCE | (np->duplex ? 0 : NVREG_MISC1_HD),
3471 base + NvRegMisc1);
3472 pci_push(base);
3473 writel(np->linkspeed, base + NvRegLinkSpeed);
3474 pci_push(base);
3475
3476 pause_flags = 0;
3477 /* setup pause frame */
3478 if (netif_running(dev) && (np->duplex != 0)) {
3479 if (np->autoneg && np->pause_flags & NV_PAUSEFRAME_AUTONEG) {
3480 adv_pause = adv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3481 lpa_pause = lpa & (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
3482
3483 switch (adv_pause) {
3484 case ADVERTISE_PAUSE_CAP:
3485 if (lpa_pause & LPA_PAUSE_CAP) {
3486 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3487 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3488 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3489 }
3490 break;
3491 case ADVERTISE_PAUSE_ASYM:
3492 if (lpa_pause == (LPA_PAUSE_CAP | LPA_PAUSE_ASYM))
3493 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3494 break;
3495 case ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM:
3496 if (lpa_pause & LPA_PAUSE_CAP) {
3497 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3498 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
3499 pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
3500 }
3501 if (lpa_pause == LPA_PAUSE_ASYM)
3502 pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
3503 break;
3504 }
3505 } else {
3506 pause_flags = np->pause_flags;
3507 }
3508 }
3509 nv_update_pause(dev, pause_flags);
3510
3511 if (txrxFlags & NV_RESTART_TX)
3512 nv_start_tx(dev);
3513 if (txrxFlags & NV_RESTART_RX)
3514 nv_start_rx(dev);
3515
3516 return retval;
3517 }
3518
3519 static void nv_linkchange(struct net_device *dev)
3520 {
3521 if (nv_update_linkspeed(dev)) {
3522 if (!netif_carrier_ok(dev)) {
3523 netif_carrier_on(dev);
3524 netdev_info(dev, "link up\n");
3525 nv_txrx_gate(dev, false);
3526 nv_start_rx(dev);
3527 }
3528 } else {
3529 if (netif_carrier_ok(dev)) {
3530 netif_carrier_off(dev);
3531 netdev_info(dev, "link down\n");
3532 nv_txrx_gate(dev, true);
3533 nv_stop_rx(dev);
3534 }
3535 }
3536 }
3537
3538 static void nv_link_irq(struct net_device *dev)
3539 {
3540 u8 __iomem *base = get_hwbase(dev);
3541 u32 miistat;
3542
3543 miistat = readl(base + NvRegMIIStatus);
3544 writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus);
3545
3546 if (miistat & (NVREG_MIISTAT_LINKCHANGE))
3547 nv_linkchange(dev);
3548 }
3549
3550 static void nv_msi_workaround(struct fe_priv *np)
3551 {
3552
3553 /* Need to toggle the msi irq mask within the ethernet device,
3554 * otherwise, future interrupts will not be detected.
3555 */
3556 if (np->msi_flags & NV_MSI_ENABLED) {
3557 u8 __iomem *base = np->base;
3558
3559 writel(0, base + NvRegMSIIrqMask);
3560 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
3561 }
3562 }
3563
3564 static inline int nv_change_interrupt_mode(struct net_device *dev, int total_work)
3565 {
3566 struct fe_priv *np = netdev_priv(dev);
3567
3568 if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC) {
3569 if (total_work > NV_DYNAMIC_THRESHOLD) {
3570 /* transition to poll based interrupts */
3571 np->quiet_count = 0;
3572 if (np->irqmask != NVREG_IRQMASK_CPU) {
3573 np->irqmask = NVREG_IRQMASK_CPU;
3574 return 1;
3575 }
3576 } else {
3577 if (np->quiet_count < NV_DYNAMIC_MAX_QUIET_COUNT) {
3578 np->quiet_count++;
3579 } else {
3580 /* reached a period of low activity, switch
3581 to per tx/rx packet interrupts */
3582 if (np->irqmask != NVREG_IRQMASK_THROUGHPUT) {
3583 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
3584 return 1;
3585 }
3586 }
3587 }
3588 }
3589 return 0;
3590 }
3591
3592 static irqreturn_t nv_nic_irq(int foo, void *data)
3593 {
3594 struct net_device *dev = (struct net_device *) data;
3595 struct fe_priv *np = netdev_priv(dev);
3596 u8 __iomem *base = get_hwbase(dev);
3597
3598 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3599 np->events = readl(base + NvRegIrqStatus);
3600 writel(np->events, base + NvRegIrqStatus);
3601 } else {
3602 np->events = readl(base + NvRegMSIXIrqStatus);
3603 writel(np->events, base + NvRegMSIXIrqStatus);
3604 }
3605 if (!(np->events & np->irqmask))
3606 return IRQ_NONE;
3607
3608 nv_msi_workaround(np);
3609
3610 if (napi_schedule_prep(&np->napi)) {
3611 /*
3612 * Disable further irq's (msix not enabled with napi)
3613 */
3614 writel(0, base + NvRegIrqMask);
3615 __napi_schedule(&np->napi);
3616 }
3617
3618 return IRQ_HANDLED;
3619 }
3620
3621 /* All _optimized functions are used to help increase performance
3622 * (reduce CPU and increase throughput). They use descripter version 3,
3623 * compiler directives, and reduce memory accesses.
3624 */
3625 static irqreturn_t nv_nic_irq_optimized(int foo, void *data)
3626 {
3627 struct net_device *dev = (struct net_device *) data;
3628 struct fe_priv *np = netdev_priv(dev);
3629 u8 __iomem *base = get_hwbase(dev);
3630
3631 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3632 np->events = readl(base + NvRegIrqStatus);
3633 writel(np->events, base + NvRegIrqStatus);
3634 } else {
3635 np->events = readl(base + NvRegMSIXIrqStatus);
3636 writel(np->events, base + NvRegMSIXIrqStatus);
3637 }
3638 if (!(np->events & np->irqmask))
3639 return IRQ_NONE;
3640
3641 nv_msi_workaround(np);
3642
3643 if (napi_schedule_prep(&np->napi)) {
3644 /*
3645 * Disable further irq's (msix not enabled with napi)
3646 */
3647 writel(0, base + NvRegIrqMask);
3648 __napi_schedule(&np->napi);
3649 }
3650
3651 return IRQ_HANDLED;
3652 }
3653
3654 static irqreturn_t nv_nic_irq_tx(int foo, void *data)
3655 {
3656 struct net_device *dev = (struct net_device *) data;
3657 struct fe_priv *np = netdev_priv(dev);
3658 u8 __iomem *base = get_hwbase(dev);
3659 u32 events;
3660 int i;
3661 unsigned long flags;
3662
3663 for (i = 0;; i++) {
3664 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL;
3665 writel(events, base + NvRegMSIXIrqStatus);
3666 netdev_dbg(dev, "tx irq events: %08x\n", events);
3667 if (!(events & np->irqmask))
3668 break;
3669
3670 spin_lock_irqsave(&np->lock, flags);
3671 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3672 spin_unlock_irqrestore(&np->lock, flags);
3673
3674 if (unlikely(i > max_interrupt_work)) {
3675 spin_lock_irqsave(&np->lock, flags);
3676 /* disable interrupts on the nic */
3677 writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask);
3678 pci_push(base);
3679
3680 if (!np->in_shutdown) {
3681 np->nic_poll_irq |= NVREG_IRQ_TX_ALL;
3682 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3683 }
3684 spin_unlock_irqrestore(&np->lock, flags);
3685 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3686 __func__, i);
3687 break;
3688 }
3689
3690 }
3691
3692 return IRQ_RETVAL(i);
3693 }
3694
3695 static int nv_napi_poll(struct napi_struct *napi, int budget)
3696 {
3697 struct fe_priv *np = container_of(napi, struct fe_priv, napi);
3698 struct net_device *dev = np->dev;
3699 u8 __iomem *base = get_hwbase(dev);
3700 unsigned long flags;
3701 int retcode;
3702 int rx_count, tx_work = 0, rx_work = 0;
3703
3704 do {
3705 if (!nv_optimized(np)) {
3706 spin_lock_irqsave(&np->lock, flags);
3707 tx_work += nv_tx_done(dev, np->tx_ring_size);
3708 spin_unlock_irqrestore(&np->lock, flags);
3709
3710 rx_count = nv_rx_process(dev, budget - rx_work);
3711 retcode = nv_alloc_rx(dev);
3712 } else {
3713 spin_lock_irqsave(&np->lock, flags);
3714 tx_work += nv_tx_done_optimized(dev, np->tx_ring_size);
3715 spin_unlock_irqrestore(&np->lock, flags);
3716
3717 rx_count = nv_rx_process_optimized(dev,
3718 budget - rx_work);
3719 retcode = nv_alloc_rx_optimized(dev);
3720 }
3721 } while (retcode == 0 &&
3722 rx_count > 0 && (rx_work += rx_count) < budget);
3723
3724 if (retcode) {
3725 spin_lock_irqsave(&np->lock, flags);
3726 if (!np->in_shutdown)
3727 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3728 spin_unlock_irqrestore(&np->lock, flags);
3729 }
3730
3731 nv_change_interrupt_mode(dev, tx_work + rx_work);
3732
3733 if (unlikely(np->events & NVREG_IRQ_LINK)) {
3734 spin_lock_irqsave(&np->lock, flags);
3735 nv_link_irq(dev);
3736 spin_unlock_irqrestore(&np->lock, flags);
3737 }
3738 if (unlikely(np->need_linktimer && time_after(jiffies, np->link_timeout))) {
3739 spin_lock_irqsave(&np->lock, flags);
3740 nv_linkchange(dev);
3741 spin_unlock_irqrestore(&np->lock, flags);
3742 np->link_timeout = jiffies + LINK_TIMEOUT;
3743 }
3744 if (unlikely(np->events & NVREG_IRQ_RECOVER_ERROR)) {
3745 spin_lock_irqsave(&np->lock, flags);
3746 if (!np->in_shutdown) {
3747 np->nic_poll_irq = np->irqmask;
3748 np->recover_error = 1;
3749 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3750 }
3751 spin_unlock_irqrestore(&np->lock, flags);
3752 napi_complete(napi);
3753 return rx_work;
3754 }
3755
3756 if (rx_work < budget) {
3757 /* re-enable interrupts
3758 (msix not enabled in napi) */
3759 napi_complete(napi);
3760
3761 writel(np->irqmask, base + NvRegIrqMask);
3762 }
3763 return rx_work;
3764 }
3765
3766 static irqreturn_t nv_nic_irq_rx(int foo, void *data)
3767 {
3768 struct net_device *dev = (struct net_device *) data;
3769 struct fe_priv *np = netdev_priv(dev);
3770 u8 __iomem *base = get_hwbase(dev);
3771 u32 events;
3772 int i;
3773 unsigned long flags;
3774
3775 for (i = 0;; i++) {
3776 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL;
3777 writel(events, base + NvRegMSIXIrqStatus);
3778 netdev_dbg(dev, "rx irq events: %08x\n", events);
3779 if (!(events & np->irqmask))
3780 break;
3781
3782 if (nv_rx_process_optimized(dev, RX_WORK_PER_LOOP)) {
3783 if (unlikely(nv_alloc_rx_optimized(dev))) {
3784 spin_lock_irqsave(&np->lock, flags);
3785 if (!np->in_shutdown)
3786 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
3787 spin_unlock_irqrestore(&np->lock, flags);
3788 }
3789 }
3790
3791 if (unlikely(i > max_interrupt_work)) {
3792 spin_lock_irqsave(&np->lock, flags);
3793 /* disable interrupts on the nic */
3794 writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask);
3795 pci_push(base);
3796
3797 if (!np->in_shutdown) {
3798 np->nic_poll_irq |= NVREG_IRQ_RX_ALL;
3799 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3800 }
3801 spin_unlock_irqrestore(&np->lock, flags);
3802 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3803 __func__, i);
3804 break;
3805 }
3806 }
3807
3808 return IRQ_RETVAL(i);
3809 }
3810
3811 static irqreturn_t nv_nic_irq_other(int foo, void *data)
3812 {
3813 struct net_device *dev = (struct net_device *) data;
3814 struct fe_priv *np = netdev_priv(dev);
3815 u8 __iomem *base = get_hwbase(dev);
3816 u32 events;
3817 int i;
3818 unsigned long flags;
3819
3820 for (i = 0;; i++) {
3821 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER;
3822 writel(events, base + NvRegMSIXIrqStatus);
3823 netdev_dbg(dev, "irq events: %08x\n", events);
3824 if (!(events & np->irqmask))
3825 break;
3826
3827 /* check tx in case we reached max loop limit in tx isr */
3828 spin_lock_irqsave(&np->lock, flags);
3829 nv_tx_done_optimized(dev, TX_WORK_PER_LOOP);
3830 spin_unlock_irqrestore(&np->lock, flags);
3831
3832 if (events & NVREG_IRQ_LINK) {
3833 spin_lock_irqsave(&np->lock, flags);
3834 nv_link_irq(dev);
3835 spin_unlock_irqrestore(&np->lock, flags);
3836 }
3837 if (np->need_linktimer && time_after(jiffies, np->link_timeout)) {
3838 spin_lock_irqsave(&np->lock, flags);
3839 nv_linkchange(dev);
3840 spin_unlock_irqrestore(&np->lock, flags);
3841 np->link_timeout = jiffies + LINK_TIMEOUT;
3842 }
3843 if (events & NVREG_IRQ_RECOVER_ERROR) {
3844 spin_lock_irqsave(&np->lock, flags);
3845 /* disable interrupts on the nic */
3846 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3847 pci_push(base);
3848
3849 if (!np->in_shutdown) {
3850 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3851 np->recover_error = 1;
3852 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3853 }
3854 spin_unlock_irqrestore(&np->lock, flags);
3855 break;
3856 }
3857 if (unlikely(i > max_interrupt_work)) {
3858 spin_lock_irqsave(&np->lock, flags);
3859 /* disable interrupts on the nic */
3860 writel(NVREG_IRQ_OTHER, base + NvRegIrqMask);
3861 pci_push(base);
3862
3863 if (!np->in_shutdown) {
3864 np->nic_poll_irq |= NVREG_IRQ_OTHER;
3865 mod_timer(&np->nic_poll, jiffies + POLL_WAIT);
3866 }
3867 spin_unlock_irqrestore(&np->lock, flags);
3868 netdev_dbg(dev, "%s: too many iterations (%d)\n",
3869 __func__, i);
3870 break;
3871 }
3872
3873 }
3874
3875 return IRQ_RETVAL(i);
3876 }
3877
3878 static irqreturn_t nv_nic_irq_test(int foo, void *data)
3879 {
3880 struct net_device *dev = (struct net_device *) data;
3881 struct fe_priv *np = netdev_priv(dev);
3882 u8 __iomem *base = get_hwbase(dev);
3883 u32 events;
3884
3885 if (!(np->msi_flags & NV_MSI_X_ENABLED)) {
3886 events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK;
3887 writel(events & NVREG_IRQ_TIMER, base + NvRegIrqStatus);
3888 } else {
3889 events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK;
3890 writel(events & NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus);
3891 }
3892 pci_push(base);
3893 if (!(events & NVREG_IRQ_TIMER))
3894 return IRQ_RETVAL(0);
3895
3896 nv_msi_workaround(np);
3897
3898 spin_lock(&np->lock);
3899 np->intr_test = 1;
3900 spin_unlock(&np->lock);
3901
3902 return IRQ_RETVAL(1);
3903 }
3904
3905 static void set_msix_vector_map(struct net_device *dev, u32 vector, u32 irqmask)
3906 {
3907 u8 __iomem *base = get_hwbase(dev);
3908 int i;
3909 u32 msixmap = 0;
3910
3911 /* Each interrupt bit can be mapped to a MSIX vector (4 bits).
3912 * MSIXMap0 represents the first 8 interrupts and MSIXMap1 represents
3913 * the remaining 8 interrupts.
3914 */
3915 for (i = 0; i < 8; i++) {
3916 if ((irqmask >> i) & 0x1)
3917 msixmap |= vector << (i << 2);
3918 }
3919 writel(readl(base + NvRegMSIXMap0) | msixmap, base + NvRegMSIXMap0);
3920
3921 msixmap = 0;
3922 for (i = 0; i < 8; i++) {
3923 if ((irqmask >> (i + 8)) & 0x1)
3924 msixmap |= vector << (i << 2);
3925 }
3926 writel(readl(base + NvRegMSIXMap1) | msixmap, base + NvRegMSIXMap1);
3927 }
3928
3929 static int nv_request_irq(struct net_device *dev, int intr_test)
3930 {
3931 struct fe_priv *np = get_nvpriv(dev);
3932 u8 __iomem *base = get_hwbase(dev);
3933 int ret = 1;
3934 int i;
3935 irqreturn_t (*handler)(int foo, void *data);
3936
3937 if (intr_test) {
3938 handler = nv_nic_irq_test;
3939 } else {
3940 if (nv_optimized(np))
3941 handler = nv_nic_irq_optimized;
3942 else
3943 handler = nv_nic_irq;
3944 }
3945
3946 if (np->msi_flags & NV_MSI_X_CAPABLE) {
3947 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
3948 np->msi_x_entry[i].entry = i;
3949 ret = pci_enable_msix(np->pci_dev, np->msi_x_entry, (np->msi_flags & NV_MSI_X_VECTORS_MASK));
3950 if (ret == 0) {
3951 np->msi_flags |= NV_MSI_X_ENABLED;
3952 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT && !intr_test) {
3953 /* Request irq for rx handling */
3954 sprintf(np->name_rx, "%s-rx", dev->name);
3955 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector,
3956 nv_nic_irq_rx, IRQF_SHARED, np->name_rx, dev) != 0) {
3957 netdev_info(dev,
3958 "request_irq failed for rx %d\n",
3959 ret);
3960 pci_disable_msix(np->pci_dev);
3961 np->msi_flags &= ~NV_MSI_X_ENABLED;
3962 goto out_err;
3963 }
3964 /* Request irq for tx handling */
3965 sprintf(np->name_tx, "%s-tx", dev->name);
3966 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector,
3967 nv_nic_irq_tx, IRQF_SHARED, np->name_tx, dev) != 0) {
3968 netdev_info(dev,
3969 "request_irq failed for tx %d\n",
3970 ret);
3971 pci_disable_msix(np->pci_dev);
3972 np->msi_flags &= ~NV_MSI_X_ENABLED;
3973 goto out_free_rx;
3974 }
3975 /* Request irq for link and timer handling */
3976 sprintf(np->name_other, "%s-other", dev->name);
3977 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector,
3978 nv_nic_irq_other, IRQF_SHARED, np->name_other, dev) != 0) {
3979 netdev_info(dev,
3980 "request_irq failed for link %d\n",
3981 ret);
3982 pci_disable_msix(np->pci_dev);
3983 np->msi_flags &= ~NV_MSI_X_ENABLED;
3984 goto out_free_tx;
3985 }
3986 /* map interrupts to their respective vector */
3987 writel(0, base + NvRegMSIXMap0);
3988 writel(0, base + NvRegMSIXMap1);
3989 set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL);
3990 set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL);
3991 set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER);
3992 } else {
3993 /* Request irq for all interrupts */
3994 if (request_irq(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector, handler, IRQF_SHARED, dev->name, dev) != 0) {
3995 netdev_info(dev,
3996 "request_irq failed %d\n",
3997 ret);
3998 pci_disable_msix(np->pci_dev);
3999 np->msi_flags &= ~NV_MSI_X_ENABLED;
4000 goto out_err;
4001 }
4002
4003 /* map interrupts to vector 0 */
4004 writel(0, base + NvRegMSIXMap0);
4005 writel(0, base + NvRegMSIXMap1);
4006 }
4007 netdev_info(dev, "MSI-X enabled\n");
4008 }
4009 }
4010 if (ret != 0 && np->msi_flags & NV_MSI_CAPABLE) {
4011 ret = pci_enable_msi(np->pci_dev);
4012 if (ret == 0) {
4013 np->msi_flags |= NV_MSI_ENABLED;
4014 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0) {
4015 netdev_info(dev, "request_irq failed %d\n",
4016 ret);
4017 pci_disable_msi(np->pci_dev);
4018 np->msi_flags &= ~NV_MSI_ENABLED;
4019 goto out_err;
4020 }
4021
4022 /* map interrupts to vector 0 */
4023 writel(0, base + NvRegMSIMap0);
4024 writel(0, base + NvRegMSIMap1);
4025 /* enable msi vector 0 */
4026 writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask);
4027 netdev_info(dev, "MSI enabled\n");
4028 }
4029 }
4030 if (ret != 0) {
4031 if (request_irq(np->pci_dev->irq, handler, IRQF_SHARED, dev->name, dev) != 0)
4032 goto out_err;
4033
4034 }
4035
4036 return 0;
4037 out_free_tx:
4038 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector, dev);
4039 out_free_rx:
4040 free_irq(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector, dev);
4041 out_err:
4042 return 1;
4043 }
4044
4045 static void nv_free_irq(struct net_device *dev)
4046 {
4047 struct fe_priv *np = get_nvpriv(dev);
4048 int i;
4049
4050 if (np->msi_flags & NV_MSI_X_ENABLED) {
4051 for (i = 0; i < (np->msi_flags & NV_MSI_X_VECTORS_MASK); i++)
4052 free_irq(np->msi_x_entry[i].vector, dev);
4053 pci_disable_msix(np->pci_dev);
4054 np->msi_flags &= ~NV_MSI_X_ENABLED;
4055 } else {
4056 free_irq(np->pci_dev->irq, dev);
4057 if (np->msi_flags & NV_MSI_ENABLED) {
4058 pci_disable_msi(np->pci_dev);
4059 np->msi_flags &= ~NV_MSI_ENABLED;
4060 }
4061 }
4062 }
4063
4064 static void nv_do_nic_poll(unsigned long data)
4065 {
4066 struct net_device *dev = (struct net_device *) data;
4067 struct fe_priv *np = netdev_priv(dev);
4068 u8 __iomem *base = get_hwbase(dev);
4069 u32 mask = 0;
4070
4071 /*
4072 * First disable irq(s) and then
4073 * reenable interrupts on the nic, we have to do this before calling
4074 * nv_nic_irq because that may decide to do otherwise
4075 */
4076
4077 if (!using_multi_irqs(dev)) {
4078 if (np->msi_flags & NV_MSI_X_ENABLED)
4079 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4080 else
4081 disable_irq_lockdep(np->pci_dev->irq);
4082 mask = np->irqmask;
4083 } else {
4084 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4085 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4086 mask |= NVREG_IRQ_RX_ALL;
4087 }
4088 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4089 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4090 mask |= NVREG_IRQ_TX_ALL;
4091 }
4092 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4093 disable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4094 mask |= NVREG_IRQ_OTHER;
4095 }
4096 }
4097 /* disable_irq() contains synchronize_irq, thus no irq handler can run now */
4098
4099 if (np->recover_error) {
4100 np->recover_error = 0;
4101 netdev_info(dev, "MAC in recoverable error state\n");
4102 if (netif_running(dev)) {
4103 netif_tx_lock_bh(dev);
4104 netif_addr_lock(dev);
4105 spin_lock(&np->lock);
4106 /* stop engines */
4107 nv_stop_rxtx(dev);
4108 if (np->driver_data & DEV_HAS_POWER_CNTRL)
4109 nv_mac_reset(dev);
4110 nv_txrx_reset(dev);
4111 /* drain rx queue */
4112 nv_drain_rxtx(dev);
4113 /* reinit driver view of the rx queue */
4114 set_bufsize(dev);
4115 if (nv_init_ring(dev)) {
4116 if (!np->in_shutdown)
4117 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4118 }
4119 /* reinit nic view of the rx queue */
4120 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4121 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4122 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4123 base + NvRegRingSizes);
4124 pci_push(base);
4125 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4126 pci_push(base);
4127 /* clear interrupts */
4128 if (!(np->msi_flags & NV_MSI_X_ENABLED))
4129 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
4130 else
4131 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
4132
4133 /* restart rx engine */
4134 nv_start_rxtx(dev);
4135 spin_unlock(&np->lock);
4136 netif_addr_unlock(dev);
4137 netif_tx_unlock_bh(dev);
4138 }
4139 }
4140
4141 writel(mask, base + NvRegIrqMask);
4142 pci_push(base);
4143
4144 if (!using_multi_irqs(dev)) {
4145 np->nic_poll_irq = 0;
4146 if (nv_optimized(np))
4147 nv_nic_irq_optimized(0, dev);
4148 else
4149 nv_nic_irq(0, dev);
4150 if (np->msi_flags & NV_MSI_X_ENABLED)
4151 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_ALL].vector);
4152 else
4153 enable_irq_lockdep(np->pci_dev->irq);
4154 } else {
4155 if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) {
4156 np->nic_poll_irq &= ~NVREG_IRQ_RX_ALL;
4157 nv_nic_irq_rx(0, dev);
4158 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_RX].vector);
4159 }
4160 if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) {
4161 np->nic_poll_irq &= ~NVREG_IRQ_TX_ALL;
4162 nv_nic_irq_tx(0, dev);
4163 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_TX].vector);
4164 }
4165 if (np->nic_poll_irq & NVREG_IRQ_OTHER) {
4166 np->nic_poll_irq &= ~NVREG_IRQ_OTHER;
4167 nv_nic_irq_other(0, dev);
4168 enable_irq_lockdep(np->msi_x_entry[NV_MSI_X_VECTOR_OTHER].vector);
4169 }
4170 }
4171
4172 }
4173
4174 #ifdef CONFIG_NET_POLL_CONTROLLER
4175 static void nv_poll_controller(struct net_device *dev)
4176 {
4177 nv_do_nic_poll((unsigned long) dev);
4178 }
4179 #endif
4180
4181 static void nv_do_stats_poll(unsigned long data)
4182 __acquires(&netdev_priv(dev)->hwstats_lock)
4183 __releases(&netdev_priv(dev)->hwstats_lock)
4184 {
4185 struct net_device *dev = (struct net_device *) data;
4186 struct fe_priv *np = netdev_priv(dev);
4187
4188 /* If lock is currently taken, the stats are being refreshed
4189 * and hence fresh enough */
4190 if (spin_trylock(&np->hwstats_lock)) {
4191 nv_update_stats(dev);
4192 spin_unlock(&np->hwstats_lock);
4193 }
4194
4195 if (!np->in_shutdown)
4196 mod_timer(&np->stats_poll,
4197 round_jiffies(jiffies + STATS_INTERVAL));
4198 }
4199
4200 static void nv_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
4201 {
4202 struct fe_priv *np = netdev_priv(dev);
4203 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
4204 strlcpy(info->version, FORCEDETH_VERSION, sizeof(info->version));
4205 strlcpy(info->bus_info, pci_name(np->pci_dev), sizeof(info->bus_info));
4206 }
4207
4208 static void nv_get_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4209 {
4210 struct fe_priv *np = netdev_priv(dev);
4211 wolinfo->supported = WAKE_MAGIC;
4212
4213 spin_lock_irq(&np->lock);
4214 if (np->wolenabled)
4215 wolinfo->wolopts = WAKE_MAGIC;
4216 spin_unlock_irq(&np->lock);
4217 }
4218
4219 static int nv_set_wol(struct net_device *dev, struct ethtool_wolinfo *wolinfo)
4220 {
4221 struct fe_priv *np = netdev_priv(dev);
4222 u8 __iomem *base = get_hwbase(dev);
4223 u32 flags = 0;
4224
4225 if (wolinfo->wolopts == 0) {
4226 np->wolenabled = 0;
4227 } else if (wolinfo->wolopts & WAKE_MAGIC) {
4228 np->wolenabled = 1;
4229 flags = NVREG_WAKEUPFLAGS_ENABLE;
4230 }
4231 if (netif_running(dev)) {
4232 spin_lock_irq(&np->lock);
4233 writel(flags, base + NvRegWakeUpFlags);
4234 spin_unlock_irq(&np->lock);
4235 }
4236 device_set_wakeup_enable(&np->pci_dev->dev, np->wolenabled);
4237 return 0;
4238 }
4239
4240 static int nv_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4241 {
4242 struct fe_priv *np = netdev_priv(dev);
4243 u32 speed;
4244 int adv;
4245
4246 spin_lock_irq(&np->lock);
4247 ecmd->port = PORT_MII;
4248 if (!netif_running(dev)) {
4249 /* We do not track link speed / duplex setting if the
4250 * interface is disabled. Force a link check */
4251 if (nv_update_linkspeed(dev)) {
4252 if (!netif_carrier_ok(dev))
4253 netif_carrier_on(dev);
4254 } else {
4255 if (netif_carrier_ok(dev))
4256 netif_carrier_off(dev);
4257 }
4258 }
4259
4260 if (netif_carrier_ok(dev)) {
4261 switch (np->linkspeed & (NVREG_LINKSPEED_MASK)) {
4262 case NVREG_LINKSPEED_10:
4263 speed = SPEED_10;
4264 break;
4265 case NVREG_LINKSPEED_100:
4266 speed = SPEED_100;
4267 break;
4268 case NVREG_LINKSPEED_1000:
4269 speed = SPEED_1000;
4270 break;
4271 default:
4272 speed = -1;
4273 break;
4274 }
4275 ecmd->duplex = DUPLEX_HALF;
4276 if (np->duplex)
4277 ecmd->duplex = DUPLEX_FULL;
4278 } else {
4279 speed = -1;
4280 ecmd->duplex = -1;
4281 }
4282 ethtool_cmd_speed_set(ecmd, speed);
4283 ecmd->autoneg = np->autoneg;
4284
4285 ecmd->advertising = ADVERTISED_MII;
4286 if (np->autoneg) {
4287 ecmd->advertising |= ADVERTISED_Autoneg;
4288 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4289 if (adv & ADVERTISE_10HALF)
4290 ecmd->advertising |= ADVERTISED_10baseT_Half;
4291 if (adv & ADVERTISE_10FULL)
4292 ecmd->advertising |= ADVERTISED_10baseT_Full;
4293 if (adv & ADVERTISE_100HALF)
4294 ecmd->advertising |= ADVERTISED_100baseT_Half;
4295 if (adv & ADVERTISE_100FULL)
4296 ecmd->advertising |= ADVERTISED_100baseT_Full;
4297 if (np->gigabit == PHY_GIGABIT) {
4298 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4299 if (adv & ADVERTISE_1000FULL)
4300 ecmd->advertising |= ADVERTISED_1000baseT_Full;
4301 }
4302 }
4303 ecmd->supported = (SUPPORTED_Autoneg |
4304 SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
4305 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
4306 SUPPORTED_MII);
4307 if (np->gigabit == PHY_GIGABIT)
4308 ecmd->supported |= SUPPORTED_1000baseT_Full;
4309
4310 ecmd->phy_address = np->phyaddr;
4311 ecmd->transceiver = XCVR_EXTERNAL;
4312
4313 /* ignore maxtxpkt, maxrxpkt for now */
4314 spin_unlock_irq(&np->lock);
4315 return 0;
4316 }
4317
4318 static int nv_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
4319 {
4320 struct fe_priv *np = netdev_priv(dev);
4321 u32 speed = ethtool_cmd_speed(ecmd);
4322
4323 if (ecmd->port != PORT_MII)
4324 return -EINVAL;
4325 if (ecmd->transceiver != XCVR_EXTERNAL)
4326 return -EINVAL;
4327 if (ecmd->phy_address != np->phyaddr) {
4328 /* TODO: support switching between multiple phys. Should be
4329 * trivial, but not enabled due to lack of test hardware. */
4330 return -EINVAL;
4331 }
4332 if (ecmd->autoneg == AUTONEG_ENABLE) {
4333 u32 mask;
4334
4335 mask = ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
4336 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full;
4337 if (np->gigabit == PHY_GIGABIT)
4338 mask |= ADVERTISED_1000baseT_Full;
4339
4340 if ((ecmd->advertising & mask) == 0)
4341 return -EINVAL;
4342
4343 } else if (ecmd->autoneg == AUTONEG_DISABLE) {
4344 /* Note: autonegotiation disable, speed 1000 intentionally
4345 * forbidden - no one should need that. */
4346
4347 if (speed != SPEED_10 && speed != SPEED_100)
4348 return -EINVAL;
4349 if (ecmd->duplex != DUPLEX_HALF && ecmd->duplex != DUPLEX_FULL)
4350 return -EINVAL;
4351 } else {
4352 return -EINVAL;
4353 }
4354
4355 netif_carrier_off(dev);
4356 if (netif_running(dev)) {
4357 unsigned long flags;
4358
4359 nv_disable_irq(dev);
4360 netif_tx_lock_bh(dev);
4361 netif_addr_lock(dev);
4362 /* with plain spinlock lockdep complains */
4363 spin_lock_irqsave(&np->lock, flags);
4364 /* stop engines */
4365 /* FIXME:
4366 * this can take some time, and interrupts are disabled
4367 * due to spin_lock_irqsave, but let's hope no daemon
4368 * is going to change the settings very often...
4369 * Worst case:
4370 * NV_RXSTOP_DELAY1MAX + NV_TXSTOP_DELAY1MAX
4371 * + some minor delays, which is up to a second approximately
4372 */
4373 nv_stop_rxtx(dev);
4374 spin_unlock_irqrestore(&np->lock, flags);
4375 netif_addr_unlock(dev);
4376 netif_tx_unlock_bh(dev);
4377 }
4378
4379 if (ecmd->autoneg == AUTONEG_ENABLE) {
4380 int adv, bmcr;
4381
4382 np->autoneg = 1;
4383
4384 /* advertise only what has been requested */
4385 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4386 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4387 if (ecmd->advertising & ADVERTISED_10baseT_Half)
4388 adv |= ADVERTISE_10HALF;
4389 if (ecmd->advertising & ADVERTISED_10baseT_Full)
4390 adv |= ADVERTISE_10FULL;
4391 if (ecmd->advertising & ADVERTISED_100baseT_Half)
4392 adv |= ADVERTISE_100HALF;
4393 if (ecmd->advertising & ADVERTISED_100baseT_Full)
4394 adv |= ADVERTISE_100FULL;
4395 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4396 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4397 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4398 adv |= ADVERTISE_PAUSE_ASYM;
4399 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4400
4401 if (np->gigabit == PHY_GIGABIT) {
4402 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4403 adv &= ~ADVERTISE_1000FULL;
4404 if (ecmd->advertising & ADVERTISED_1000baseT_Full)
4405 adv |= ADVERTISE_1000FULL;
4406 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4407 }
4408
4409 if (netif_running(dev))
4410 netdev_info(dev, "link down\n");
4411 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4412 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4413 bmcr |= BMCR_ANENABLE;
4414 /* reset the phy in order for settings to stick,
4415 * and cause autoneg to start */
4416 if (phy_reset(dev, bmcr)) {
4417 netdev_info(dev, "phy reset failed\n");
4418 return -EINVAL;
4419 }
4420 } else {
4421 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4422 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4423 }
4424 } else {
4425 int adv, bmcr;
4426
4427 np->autoneg = 0;
4428
4429 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4430 adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4 | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4431 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_HALF)
4432 adv |= ADVERTISE_10HALF;
4433 if (speed == SPEED_10 && ecmd->duplex == DUPLEX_FULL)
4434 adv |= ADVERTISE_10FULL;
4435 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_HALF)
4436 adv |= ADVERTISE_100HALF;
4437 if (speed == SPEED_100 && ecmd->duplex == DUPLEX_FULL)
4438 adv |= ADVERTISE_100FULL;
4439 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4440 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) {/* for rx we set both advertisements but disable tx pause */
4441 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4442 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4443 }
4444 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ) {
4445 adv |= ADVERTISE_PAUSE_ASYM;
4446 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4447 }
4448 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4449 np->fixed_mode = adv;
4450
4451 if (np->gigabit == PHY_GIGABIT) {
4452 adv = mii_rw(dev, np->phyaddr, MII_CTRL1000, MII_READ);
4453 adv &= ~ADVERTISE_1000FULL;
4454 mii_rw(dev, np->phyaddr, MII_CTRL1000, adv);
4455 }
4456
4457 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4458 bmcr &= ~(BMCR_ANENABLE|BMCR_SPEED100|BMCR_SPEED1000|BMCR_FULLDPLX);
4459 if (np->fixed_mode & (ADVERTISE_10FULL|ADVERTISE_100FULL))
4460 bmcr |= BMCR_FULLDPLX;
4461 if (np->fixed_mode & (ADVERTISE_100HALF|ADVERTISE_100FULL))
4462 bmcr |= BMCR_SPEED100;
4463 if (np->phy_oui == PHY_OUI_MARVELL) {
4464 /* reset the phy in order for forced mode settings to stick */
4465 if (phy_reset(dev, bmcr)) {
4466 netdev_info(dev, "phy reset failed\n");
4467 return -EINVAL;
4468 }
4469 } else {
4470 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4471 if (netif_running(dev)) {
4472 /* Wait a bit and then reconfigure the nic. */
4473 udelay(10);
4474 nv_linkchange(dev);
4475 }
4476 }
4477 }
4478
4479 if (netif_running(dev)) {
4480 nv_start_rxtx(dev);
4481 nv_enable_irq(dev);
4482 }
4483
4484 return 0;
4485 }
4486
4487 #define FORCEDETH_REGS_VER 1
4488
4489 static int nv_get_regs_len(struct net_device *dev)
4490 {
4491 struct fe_priv *np = netdev_priv(dev);
4492 return np->register_size;
4493 }
4494
4495 static void nv_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *buf)
4496 {
4497 struct fe_priv *np = netdev_priv(dev);
4498 u8 __iomem *base = get_hwbase(dev);
4499 u32 *rbuf = buf;
4500 int i;
4501
4502 regs->version = FORCEDETH_REGS_VER;
4503 spin_lock_irq(&np->lock);
4504 for (i = 0; i < np->register_size/sizeof(u32); i++)
4505 rbuf[i] = readl(base + i*sizeof(u32));
4506 spin_unlock_irq(&np->lock);
4507 }
4508
4509 static int nv_nway_reset(struct net_device *dev)
4510 {
4511 struct fe_priv *np = netdev_priv(dev);
4512 int ret;
4513
4514 if (np->autoneg) {
4515 int bmcr;
4516
4517 netif_carrier_off(dev);
4518 if (netif_running(dev)) {
4519 nv_disable_irq(dev);
4520 netif_tx_lock_bh(dev);
4521 netif_addr_lock(dev);
4522 spin_lock(&np->lock);
4523 /* stop engines */
4524 nv_stop_rxtx(dev);
4525 spin_unlock(&np->lock);
4526 netif_addr_unlock(dev);
4527 netif_tx_unlock_bh(dev);
4528 netdev_info(dev, "link down\n");
4529 }
4530
4531 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4532 if (np->phy_model == PHY_MODEL_MARVELL_E3016) {
4533 bmcr |= BMCR_ANENABLE;
4534 /* reset the phy in order for settings to stick*/
4535 if (phy_reset(dev, bmcr)) {
4536 netdev_info(dev, "phy reset failed\n");
4537 return -EINVAL;
4538 }
4539 } else {
4540 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4541 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4542 }
4543
4544 if (netif_running(dev)) {
4545 nv_start_rxtx(dev);
4546 nv_enable_irq(dev);
4547 }
4548 ret = 0;
4549 } else {
4550 ret = -EINVAL;
4551 }
4552
4553 return ret;
4554 }
4555
4556 static void nv_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4557 {
4558 struct fe_priv *np = netdev_priv(dev);
4559
4560 ring->rx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4561 ring->tx_max_pending = (np->desc_ver == DESC_VER_1) ? RING_MAX_DESC_VER_1 : RING_MAX_DESC_VER_2_3;
4562
4563 ring->rx_pending = np->rx_ring_size;
4564 ring->tx_pending = np->tx_ring_size;
4565 }
4566
4567 static int nv_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
4568 {
4569 struct fe_priv *np = netdev_priv(dev);
4570 u8 __iomem *base = get_hwbase(dev);
4571 u8 *rxtx_ring, *rx_skbuff, *tx_skbuff;
4572 dma_addr_t ring_addr;
4573
4574 if (ring->rx_pending < RX_RING_MIN ||
4575 ring->tx_pending < TX_RING_MIN ||
4576 ring->rx_mini_pending != 0 ||
4577 ring->rx_jumbo_pending != 0 ||
4578 (np->desc_ver == DESC_VER_1 &&
4579 (ring->rx_pending > RING_MAX_DESC_VER_1 ||
4580 ring->tx_pending > RING_MAX_DESC_VER_1)) ||
4581 (np->desc_ver != DESC_VER_1 &&
4582 (ring->rx_pending > RING_MAX_DESC_VER_2_3 ||
4583 ring->tx_pending > RING_MAX_DESC_VER_2_3))) {
4584 return -EINVAL;
4585 }
4586
4587 /* allocate new rings */
4588 if (!nv_optimized(np)) {
4589 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4590 sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4591 &ring_addr);
4592 } else {
4593 rxtx_ring = pci_alloc_consistent(np->pci_dev,
4594 sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4595 &ring_addr);
4596 }
4597 rx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->rx_pending, GFP_KERNEL);
4598 tx_skbuff = kmalloc(sizeof(struct nv_skb_map) * ring->tx_pending, GFP_KERNEL);
4599 if (!rxtx_ring || !rx_skbuff || !tx_skbuff) {
4600 /* fall back to old rings */
4601 if (!nv_optimized(np)) {
4602 if (rxtx_ring)
4603 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc) * (ring->rx_pending + ring->tx_pending),
4604 rxtx_ring, ring_addr);
4605 } else {
4606 if (rxtx_ring)
4607 pci_free_consistent(np->pci_dev, sizeof(struct ring_desc_ex) * (ring->rx_pending + ring->tx_pending),
4608 rxtx_ring, ring_addr);
4609 }
4610
4611 kfree(rx_skbuff);
4612 kfree(tx_skbuff);
4613 goto exit;
4614 }
4615
4616 if (netif_running(dev)) {
4617 nv_disable_irq(dev);
4618 nv_napi_disable(dev);
4619 netif_tx_lock_bh(dev);
4620 netif_addr_lock(dev);
4621 spin_lock(&np->lock);
4622 /* stop engines */
4623 nv_stop_rxtx(dev);
4624 nv_txrx_reset(dev);
4625 /* drain queues */
4626 nv_drain_rxtx(dev);
4627 /* delete queues */
4628 free_rings(dev);
4629 }
4630
4631 /* set new values */
4632 np->rx_ring_size = ring->rx_pending;
4633 np->tx_ring_size = ring->tx_pending;
4634
4635 if (!nv_optimized(np)) {
4636 np->rx_ring.orig = (struct ring_desc *)rxtx_ring;
4637 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
4638 } else {
4639 np->rx_ring.ex = (struct ring_desc_ex *)rxtx_ring;
4640 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
4641 }
4642 np->rx_skb = (struct nv_skb_map *)rx_skbuff;
4643 np->tx_skb = (struct nv_skb_map *)tx_skbuff;
4644 np->ring_addr = ring_addr;
4645
4646 memset(np->rx_skb, 0, sizeof(struct nv_skb_map) * np->rx_ring_size);
4647 memset(np->tx_skb, 0, sizeof(struct nv_skb_map) * np->tx_ring_size);
4648
4649 if (netif_running(dev)) {
4650 /* reinit driver view of the queues */
4651 set_bufsize(dev);
4652 if (nv_init_ring(dev)) {
4653 if (!np->in_shutdown)
4654 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
4655 }
4656
4657 /* reinit nic view of the queues */
4658 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
4659 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
4660 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
4661 base + NvRegRingSizes);
4662 pci_push(base);
4663 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4664 pci_push(base);
4665
4666 /* restart engines */
4667 nv_start_rxtx(dev);
4668 spin_unlock(&np->lock);
4669 netif_addr_unlock(dev);
4670 netif_tx_unlock_bh(dev);
4671 nv_napi_enable(dev);
4672 nv_enable_irq(dev);
4673 }
4674 return 0;
4675 exit:
4676 return -ENOMEM;
4677 }
4678
4679 static void nv_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4680 {
4681 struct fe_priv *np = netdev_priv(dev);
4682
4683 pause->autoneg = (np->pause_flags & NV_PAUSEFRAME_AUTONEG) != 0;
4684 pause->rx_pause = (np->pause_flags & NV_PAUSEFRAME_RX_ENABLE) != 0;
4685 pause->tx_pause = (np->pause_flags & NV_PAUSEFRAME_TX_ENABLE) != 0;
4686 }
4687
4688 static int nv_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam* pause)
4689 {
4690 struct fe_priv *np = netdev_priv(dev);
4691 int adv, bmcr;
4692
4693 if ((!np->autoneg && np->duplex == 0) ||
4694 (np->autoneg && !pause->autoneg && np->duplex == 0)) {
4695 netdev_info(dev, "can not set pause settings when forced link is in half duplex\n");
4696 return -EINVAL;
4697 }
4698 if (pause->tx_pause && !(np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)) {
4699 netdev_info(dev, "hardware does not support tx pause frames\n");
4700 return -EINVAL;
4701 }
4702
4703 netif_carrier_off(dev);
4704 if (netif_running(dev)) {
4705 nv_disable_irq(dev);
4706 netif_tx_lock_bh(dev);
4707 netif_addr_lock(dev);
4708 spin_lock(&np->lock);
4709 /* stop engines */
4710 nv_stop_rxtx(dev);
4711 spin_unlock(&np->lock);
4712 netif_addr_unlock(dev);
4713 netif_tx_unlock_bh(dev);
4714 }
4715
4716 np->pause_flags &= ~(NV_PAUSEFRAME_RX_REQ|NV_PAUSEFRAME_TX_REQ);
4717 if (pause->rx_pause)
4718 np->pause_flags |= NV_PAUSEFRAME_RX_REQ;
4719 if (pause->tx_pause)
4720 np->pause_flags |= NV_PAUSEFRAME_TX_REQ;
4721
4722 if (np->autoneg && pause->autoneg) {
4723 np->pause_flags |= NV_PAUSEFRAME_AUTONEG;
4724
4725 adv = mii_rw(dev, np->phyaddr, MII_ADVERTISE, MII_READ);
4726 adv &= ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
4727 if (np->pause_flags & NV_PAUSEFRAME_RX_REQ) /* for rx we set both advertisements but disable tx pause */
4728 adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
4729 if (np->pause_flags & NV_PAUSEFRAME_TX_REQ)
4730 adv |= ADVERTISE_PAUSE_ASYM;
4731 mii_rw(dev, np->phyaddr, MII_ADVERTISE, adv);
4732
4733 if (netif_running(dev))
4734 netdev_info(dev, "link down\n");
4735 bmcr = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4736 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
4737 mii_rw(dev, np->phyaddr, MII_BMCR, bmcr);
4738 } else {
4739 np->pause_flags &= ~(NV_PAUSEFRAME_AUTONEG|NV_PAUSEFRAME_RX_ENABLE|NV_PAUSEFRAME_TX_ENABLE);
4740 if (pause->rx_pause)
4741 np->pause_flags |= NV_PAUSEFRAME_RX_ENABLE;
4742 if (pause->tx_pause)
4743 np->pause_flags |= NV_PAUSEFRAME_TX_ENABLE;
4744
4745 if (!netif_running(dev))
4746 nv_update_linkspeed(dev);
4747 else
4748 nv_update_pause(dev, np->pause_flags);
4749 }
4750
4751 if (netif_running(dev)) {
4752 nv_start_rxtx(dev);
4753 nv_enable_irq(dev);
4754 }
4755 return 0;
4756 }
4757
4758 static int nv_set_loopback(struct net_device *dev, netdev_features_t features)
4759 {
4760 struct fe_priv *np = netdev_priv(dev);
4761 unsigned long flags;
4762 u32 miicontrol;
4763 int err, retval = 0;
4764
4765 spin_lock_irqsave(&np->lock, flags);
4766 miicontrol = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
4767 if (features & NETIF_F_LOOPBACK) {
4768 if (miicontrol & BMCR_LOOPBACK) {
4769 spin_unlock_irqrestore(&np->lock, flags);
4770 netdev_info(dev, "Loopback already enabled\n");
4771 return 0;
4772 }
4773 nv_disable_irq(dev);
4774 /* Turn on loopback mode */
4775 miicontrol |= BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
4776 err = mii_rw(dev, np->phyaddr, MII_BMCR, miicontrol);
4777 if (err) {
4778 retval = PHY_ERROR;
4779 spin_unlock_irqrestore(&np->lock, flags);
4780 phy_init(dev);
4781 } else {
4782 if (netif_running(dev)) {
4783 /* Force 1000 Mbps full-duplex */
4784 nv_force_linkspeed(dev, NVREG_LINKSPEED_1000,
4785 1);
4786 /* Force link up */
4787 netif_carrier_on(dev);
4788 }
4789 spin_unlock_irqrestore(&np->lock, flags);
4790 netdev_info(dev,
4791 "Internal PHY loopback mode enabled.\n");
4792 }
4793 } else {
4794 if (!(miicontrol & BMCR_LOOPBACK)) {
4795 spin_unlock_irqrestore(&np->lock, flags);
4796 netdev_info(dev, "Loopback already disabled\n");
4797 return 0;
4798 }
4799 nv_disable_irq(dev);
4800 /* Turn off loopback */
4801 spin_unlock_irqrestore(&np->lock, flags);
4802 netdev_info(dev, "Internal PHY loopback mode disabled.\n");
4803 phy_init(dev);
4804 }
4805 msleep(500);
4806 spin_lock_irqsave(&np->lock, flags);
4807 nv_enable_irq(dev);
4808 spin_unlock_irqrestore(&np->lock, flags);
4809
4810 return retval;
4811 }
4812
4813 static netdev_features_t nv_fix_features(struct net_device *dev,
4814 netdev_features_t features)
4815 {
4816 /* vlan is dependent on rx checksum offload */
4817 if (features & (NETIF_F_HW_VLAN_CTAG_TX|NETIF_F_HW_VLAN_CTAG_RX))
4818 features |= NETIF_F_RXCSUM;
4819
4820 return features;
4821 }
4822
4823 static void nv_vlan_mode(struct net_device *dev, netdev_features_t features)
4824 {
4825 struct fe_priv *np = get_nvpriv(dev);
4826
4827 spin_lock_irq(&np->lock);
4828
4829 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4830 np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP;
4831 else
4832 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP;
4833
4834 if (features & NETIF_F_HW_VLAN_CTAG_TX)
4835 np->txrxctl_bits |= NVREG_TXRXCTL_VLANINS;
4836 else
4837 np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS;
4838
4839 writel(np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
4840
4841 spin_unlock_irq(&np->lock);
4842 }
4843
4844 static int nv_set_features(struct net_device *dev, netdev_features_t features)
4845 {
4846 struct fe_priv *np = netdev_priv(dev);
4847 u8 __iomem *base = get_hwbase(dev);
4848 netdev_features_t changed = dev->features ^ features;
4849 int retval;
4850
4851 if ((changed & NETIF_F_LOOPBACK) && netif_running(dev)) {
4852 retval = nv_set_loopback(dev, features);
4853 if (retval != 0)
4854 return retval;
4855 }
4856
4857 if (changed & NETIF_F_RXCSUM) {
4858 spin_lock_irq(&np->lock);
4859
4860 if (features & NETIF_F_RXCSUM)
4861 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
4862 else
4863 np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK;
4864
4865 if (netif_running(dev))
4866 writel(np->txrxctl_bits, base + NvRegTxRxControl);
4867
4868 spin_unlock_irq(&np->lock);
4869 }
4870
4871 if (changed & (NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX))
4872 nv_vlan_mode(dev, features);
4873
4874 return 0;
4875 }
4876
4877 static int nv_get_sset_count(struct net_device *dev, int sset)
4878 {
4879 struct fe_priv *np = netdev_priv(dev);
4880
4881 switch (sset) {
4882 case ETH_SS_TEST:
4883 if (np->driver_data & DEV_HAS_TEST_EXTENDED)
4884 return NV_TEST_COUNT_EXTENDED;
4885 else
4886 return NV_TEST_COUNT_BASE;
4887 case ETH_SS_STATS:
4888 if (np->driver_data & DEV_HAS_STATISTICS_V3)
4889 return NV_DEV_STATISTICS_V3_COUNT;
4890 else if (np->driver_data & DEV_HAS_STATISTICS_V2)
4891 return NV_DEV_STATISTICS_V2_COUNT;
4892 else if (np->driver_data & DEV_HAS_STATISTICS_V1)
4893 return NV_DEV_STATISTICS_V1_COUNT;
4894 else
4895 return 0;
4896 default:
4897 return -EOPNOTSUPP;
4898 }
4899 }
4900
4901 static void nv_get_ethtool_stats(struct net_device *dev,
4902 struct ethtool_stats *estats, u64 *buffer)
4903 __acquires(&netdev_priv(dev)->hwstats_lock)
4904 __releases(&netdev_priv(dev)->hwstats_lock)
4905 {
4906 struct fe_priv *np = netdev_priv(dev);
4907
4908 spin_lock_bh(&np->hwstats_lock);
4909 nv_update_stats(dev);
4910 memcpy(buffer, &np->estats,
4911 nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(u64));
4912 spin_unlock_bh(&np->hwstats_lock);
4913 }
4914
4915 static int nv_link_test(struct net_device *dev)
4916 {
4917 struct fe_priv *np = netdev_priv(dev);
4918 int mii_status;
4919
4920 mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4921 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
4922
4923 /* check phy link status */
4924 if (!(mii_status & BMSR_LSTATUS))
4925 return 0;
4926 else
4927 return 1;
4928 }
4929
4930 static int nv_register_test(struct net_device *dev)
4931 {
4932 u8 __iomem *base = get_hwbase(dev);
4933 int i = 0;
4934 u32 orig_read, new_read;
4935
4936 do {
4937 orig_read = readl(base + nv_registers_test[i].reg);
4938
4939 /* xor with mask to toggle bits */
4940 orig_read ^= nv_registers_test[i].mask;
4941
4942 writel(orig_read, base + nv_registers_test[i].reg);
4943
4944 new_read = readl(base + nv_registers_test[i].reg);
4945
4946 if ((new_read & nv_registers_test[i].mask) != (orig_read & nv_registers_test[i].mask))
4947 return 0;
4948
4949 /* restore original value */
4950 orig_read ^= nv_registers_test[i].mask;
4951 writel(orig_read, base + nv_registers_test[i].reg);
4952
4953 } while (nv_registers_test[++i].reg != 0);
4954
4955 return 1;
4956 }
4957
4958 static int nv_interrupt_test(struct net_device *dev)
4959 {
4960 struct fe_priv *np = netdev_priv(dev);
4961 u8 __iomem *base = get_hwbase(dev);
4962 int ret = 1;
4963 int testcnt;
4964 u32 save_msi_flags, save_poll_interval = 0;
4965
4966 if (netif_running(dev)) {
4967 /* free current irq */
4968 nv_free_irq(dev);
4969 save_poll_interval = readl(base+NvRegPollingInterval);
4970 }
4971
4972 /* flag to test interrupt handler */
4973 np->intr_test = 0;
4974
4975 /* setup test irq */
4976 save_msi_flags = np->msi_flags;
4977 np->msi_flags &= ~NV_MSI_X_VECTORS_MASK;
4978 np->msi_flags |= 0x001; /* setup 1 vector */
4979 if (nv_request_irq(dev, 1))
4980 return 0;
4981
4982 /* setup timer interrupt */
4983 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
4984 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
4985
4986 nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4987
4988 /* wait for at least one interrupt */
4989 msleep(100);
4990
4991 spin_lock_irq(&np->lock);
4992
4993 /* flag should be set within ISR */
4994 testcnt = np->intr_test;
4995 if (!testcnt)
4996 ret = 2;
4997
4998 nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER);
4999 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5000 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5001 else
5002 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5003
5004 spin_unlock_irq(&np->lock);
5005
5006 nv_free_irq(dev);
5007
5008 np->msi_flags = save_msi_flags;
5009
5010 if (netif_running(dev)) {
5011 writel(save_poll_interval, base + NvRegPollingInterval);
5012 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5013 /* restore original irq */
5014 if (nv_request_irq(dev, 0))
5015 return 0;
5016 }
5017
5018 return ret;
5019 }
5020
5021 static int nv_loopback_test(struct net_device *dev)
5022 {
5023 struct fe_priv *np = netdev_priv(dev);
5024 u8 __iomem *base = get_hwbase(dev);
5025 struct sk_buff *tx_skb, *rx_skb;
5026 dma_addr_t test_dma_addr;
5027 u32 tx_flags_extra = (np->desc_ver == DESC_VER_1 ? NV_TX_LASTPACKET : NV_TX2_LASTPACKET);
5028 u32 flags;
5029 int len, i, pkt_len;
5030 u8 *pkt_data;
5031 u32 filter_flags = 0;
5032 u32 misc1_flags = 0;
5033 int ret = 1;
5034
5035 if (netif_running(dev)) {
5036 nv_disable_irq(dev);
5037 filter_flags = readl(base + NvRegPacketFilterFlags);
5038 misc1_flags = readl(base + NvRegMisc1);
5039 } else {
5040 nv_txrx_reset(dev);
5041 }
5042
5043 /* reinit driver view of the rx queue */
5044 set_bufsize(dev);
5045 nv_init_ring(dev);
5046
5047 /* setup hardware for loopback */
5048 writel(NVREG_MISC1_FORCE, base + NvRegMisc1);
5049 writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags);
5050
5051 /* reinit nic view of the rx queue */
5052 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5053 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5054 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5055 base + NvRegRingSizes);
5056 pci_push(base);
5057
5058 /* restart rx engine */
5059 nv_start_rxtx(dev);
5060
5061 /* setup packet for tx */
5062 pkt_len = ETH_DATA_LEN;
5063 tx_skb = netdev_alloc_skb(dev, pkt_len);
5064 if (!tx_skb) {
5065 ret = 0;
5066 goto out;
5067 }
5068 test_dma_addr = pci_map_single(np->pci_dev, tx_skb->data,
5069 skb_tailroom(tx_skb),
5070 PCI_DMA_FROMDEVICE);
5071 if (pci_dma_mapping_error(np->pci_dev,
5072 test_dma_addr)) {
5073 dev_kfree_skb_any(tx_skb);
5074 goto out;
5075 }
5076 pkt_data = skb_put(tx_skb, pkt_len);
5077 for (i = 0; i < pkt_len; i++)
5078 pkt_data[i] = (u8)(i & 0xff);
5079
5080 if (!nv_optimized(np)) {
5081 np->tx_ring.orig[0].buf = cpu_to_le32(test_dma_addr);
5082 np->tx_ring.orig[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5083 } else {
5084 np->tx_ring.ex[0].bufhigh = cpu_to_le32(dma_high(test_dma_addr));
5085 np->tx_ring.ex[0].buflow = cpu_to_le32(dma_low(test_dma_addr));
5086 np->tx_ring.ex[0].flaglen = cpu_to_le32((pkt_len-1) | np->tx_flags | tx_flags_extra);
5087 }
5088 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5089 pci_push(get_hwbase(dev));
5090
5091 msleep(500);
5092
5093 /* check for rx of the packet */
5094 if (!nv_optimized(np)) {
5095 flags = le32_to_cpu(np->rx_ring.orig[0].flaglen);
5096 len = nv_descr_getlength(&np->rx_ring.orig[0], np->desc_ver);
5097
5098 } else {
5099 flags = le32_to_cpu(np->rx_ring.ex[0].flaglen);
5100 len = nv_descr_getlength_ex(&np->rx_ring.ex[0], np->desc_ver);
5101 }
5102
5103 if (flags & NV_RX_AVAIL) {
5104 ret = 0;
5105 } else if (np->desc_ver == DESC_VER_1) {
5106 if (flags & NV_RX_ERROR)
5107 ret = 0;
5108 } else {
5109 if (flags & NV_RX2_ERROR)
5110 ret = 0;
5111 }
5112
5113 if (ret) {
5114 if (len != pkt_len) {
5115 ret = 0;
5116 } else {
5117 rx_skb = np->rx_skb[0].skb;
5118 for (i = 0; i < pkt_len; i++) {
5119 if (rx_skb->data[i] != (u8)(i & 0xff)) {
5120 ret = 0;
5121 break;
5122 }
5123 }
5124 }
5125 }
5126
5127 pci_unmap_single(np->pci_dev, test_dma_addr,
5128 (skb_end_pointer(tx_skb) - tx_skb->data),
5129 PCI_DMA_TODEVICE);
5130 dev_kfree_skb_any(tx_skb);
5131 out:
5132 /* stop engines */
5133 nv_stop_rxtx(dev);
5134 nv_txrx_reset(dev);
5135 /* drain rx queue */
5136 nv_drain_rxtx(dev);
5137
5138 if (netif_running(dev)) {
5139 writel(misc1_flags, base + NvRegMisc1);
5140 writel(filter_flags, base + NvRegPacketFilterFlags);
5141 nv_enable_irq(dev);
5142 }
5143
5144 return ret;
5145 }
5146
5147 static void nv_self_test(struct net_device *dev, struct ethtool_test *test, u64 *buffer)
5148 {
5149 struct fe_priv *np = netdev_priv(dev);
5150 u8 __iomem *base = get_hwbase(dev);
5151 int result, count;
5152
5153 count = nv_get_sset_count(dev, ETH_SS_TEST);
5154 memset(buffer, 0, count * sizeof(u64));
5155
5156 if (!nv_link_test(dev)) {
5157 test->flags |= ETH_TEST_FL_FAILED;
5158 buffer[0] = 1;
5159 }
5160
5161 if (test->flags & ETH_TEST_FL_OFFLINE) {
5162 if (netif_running(dev)) {
5163 netif_stop_queue(dev);
5164 nv_napi_disable(dev);
5165 netif_tx_lock_bh(dev);
5166 netif_addr_lock(dev);
5167 spin_lock_irq(&np->lock);
5168 nv_disable_hw_interrupts(dev, np->irqmask);
5169 if (!(np->msi_flags & NV_MSI_X_ENABLED))
5170 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5171 else
5172 writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus);
5173 /* stop engines */
5174 nv_stop_rxtx(dev);
5175 nv_txrx_reset(dev);
5176 /* drain rx queue */
5177 nv_drain_rxtx(dev);
5178 spin_unlock_irq(&np->lock);
5179 netif_addr_unlock(dev);
5180 netif_tx_unlock_bh(dev);
5181 }
5182
5183 if (!nv_register_test(dev)) {
5184 test->flags |= ETH_TEST_FL_FAILED;
5185 buffer[1] = 1;
5186 }
5187
5188 result = nv_interrupt_test(dev);
5189 if (result != 1) {
5190 test->flags |= ETH_TEST_FL_FAILED;
5191 buffer[2] = 1;
5192 }
5193 if (result == 0) {
5194 /* bail out */
5195 return;
5196 }
5197
5198 if (count > NV_TEST_COUNT_BASE && !nv_loopback_test(dev)) {
5199 test->flags |= ETH_TEST_FL_FAILED;
5200 buffer[3] = 1;
5201 }
5202
5203 if (netif_running(dev)) {
5204 /* reinit driver view of the rx queue */
5205 set_bufsize(dev);
5206 if (nv_init_ring(dev)) {
5207 if (!np->in_shutdown)
5208 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5209 }
5210 /* reinit nic view of the rx queue */
5211 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5212 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5213 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5214 base + NvRegRingSizes);
5215 pci_push(base);
5216 writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl);
5217 pci_push(base);
5218 /* restart rx engine */
5219 nv_start_rxtx(dev);
5220 netif_start_queue(dev);
5221 nv_napi_enable(dev);
5222 nv_enable_hw_interrupts(dev, np->irqmask);
5223 }
5224 }
5225 }
5226
5227 static void nv_get_strings(struct net_device *dev, u32 stringset, u8 *buffer)
5228 {
5229 switch (stringset) {
5230 case ETH_SS_STATS:
5231 memcpy(buffer, &nv_estats_str, nv_get_sset_count(dev, ETH_SS_STATS)*sizeof(struct nv_ethtool_str));
5232 break;
5233 case ETH_SS_TEST:
5234 memcpy(buffer, &nv_etests_str, nv_get_sset_count(dev, ETH_SS_TEST)*sizeof(struct nv_ethtool_str));
5235 break;
5236 }
5237 }
5238
5239 static const struct ethtool_ops ops = {
5240 .get_drvinfo = nv_get_drvinfo,
5241 .get_link = ethtool_op_get_link,
5242 .get_wol = nv_get_wol,
5243 .set_wol = nv_set_wol,
5244 .get_settings = nv_get_settings,
5245 .set_settings = nv_set_settings,
5246 .get_regs_len = nv_get_regs_len,
5247 .get_regs = nv_get_regs,
5248 .nway_reset = nv_nway_reset,
5249 .get_ringparam = nv_get_ringparam,
5250 .set_ringparam = nv_set_ringparam,
5251 .get_pauseparam = nv_get_pauseparam,
5252 .set_pauseparam = nv_set_pauseparam,
5253 .get_strings = nv_get_strings,
5254 .get_ethtool_stats = nv_get_ethtool_stats,
5255 .get_sset_count = nv_get_sset_count,
5256 .self_test = nv_self_test,
5257 .get_ts_info = ethtool_op_get_ts_info,
5258 };
5259
5260 /* The mgmt unit and driver use a semaphore to access the phy during init */
5261 static int nv_mgmt_acquire_sema(struct net_device *dev)
5262 {
5263 struct fe_priv *np = netdev_priv(dev);
5264 u8 __iomem *base = get_hwbase(dev);
5265 int i;
5266 u32 tx_ctrl, mgmt_sema;
5267
5268 for (i = 0; i < 10; i++) {
5269 mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK;
5270 if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE)
5271 break;
5272 msleep(500);
5273 }
5274
5275 if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE)
5276 return 0;
5277
5278 for (i = 0; i < 2; i++) {
5279 tx_ctrl = readl(base + NvRegTransmitterControl);
5280 tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ;
5281 writel(tx_ctrl, base + NvRegTransmitterControl);
5282
5283 /* verify that semaphore was acquired */
5284 tx_ctrl = readl(base + NvRegTransmitterControl);
5285 if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) &&
5286 ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) {
5287 np->mgmt_sema = 1;
5288 return 1;
5289 } else
5290 udelay(50);
5291 }
5292
5293 return 0;
5294 }
5295
5296 static void nv_mgmt_release_sema(struct net_device *dev)
5297 {
5298 struct fe_priv *np = netdev_priv(dev);
5299 u8 __iomem *base = get_hwbase(dev);
5300 u32 tx_ctrl;
5301
5302 if (np->driver_data & DEV_HAS_MGMT_UNIT) {
5303 if (np->mgmt_sema) {
5304 tx_ctrl = readl(base + NvRegTransmitterControl);
5305 tx_ctrl &= ~NVREG_XMITCTL_HOST_SEMA_ACQ;
5306 writel(tx_ctrl, base + NvRegTransmitterControl);
5307 }
5308 }
5309 }
5310
5311
5312 static int nv_mgmt_get_version(struct net_device *dev)
5313 {
5314 struct fe_priv *np = netdev_priv(dev);
5315 u8 __iomem *base = get_hwbase(dev);
5316 u32 data_ready = readl(base + NvRegTransmitterControl);
5317 u32 data_ready2 = 0;
5318 unsigned long start;
5319 int ready = 0;
5320
5321 writel(NVREG_MGMTUNITGETVERSION, base + NvRegMgmtUnitGetVersion);
5322 writel(data_ready ^ NVREG_XMITCTL_DATA_START, base + NvRegTransmitterControl);
5323 start = jiffies;
5324 while (time_before(jiffies, start + 5*HZ)) {
5325 data_ready2 = readl(base + NvRegTransmitterControl);
5326 if ((data_ready & NVREG_XMITCTL_DATA_READY) != (data_ready2 & NVREG_XMITCTL_DATA_READY)) {
5327 ready = 1;
5328 break;
5329 }
5330 schedule_timeout_uninterruptible(1);
5331 }
5332
5333 if (!ready || (data_ready2 & NVREG_XMITCTL_DATA_ERROR))
5334 return 0;
5335
5336 np->mgmt_version = readl(base + NvRegMgmtUnitVersion) & NVREG_MGMTUNITVERSION;
5337
5338 return 1;
5339 }
5340
5341 static int nv_open(struct net_device *dev)
5342 {
5343 struct fe_priv *np = netdev_priv(dev);
5344 u8 __iomem *base = get_hwbase(dev);
5345 int ret = 1;
5346 int oom, i;
5347 u32 low;
5348
5349 /* power up phy */
5350 mii_rw(dev, np->phyaddr, MII_BMCR,
5351 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ) & ~BMCR_PDOWN);
5352
5353 nv_txrx_gate(dev, false);
5354 /* erase previous misconfiguration */
5355 if (np->driver_data & DEV_HAS_POWER_CNTRL)
5356 nv_mac_reset(dev);
5357 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5358 writel(0, base + NvRegMulticastAddrB);
5359 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5360 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5361 writel(0, base + NvRegPacketFilterFlags);
5362
5363 writel(0, base + NvRegTransmitterControl);
5364 writel(0, base + NvRegReceiverControl);
5365
5366 writel(0, base + NvRegAdapterControl);
5367
5368 if (np->pause_flags & NV_PAUSEFRAME_TX_CAPABLE)
5369 writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame);
5370
5371 /* initialize descriptor rings */
5372 set_bufsize(dev);
5373 oom = nv_init_ring(dev);
5374
5375 writel(0, base + NvRegLinkSpeed);
5376 writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5377 nv_txrx_reset(dev);
5378 writel(0, base + NvRegUnknownSetupReg6);
5379
5380 np->in_shutdown = 0;
5381
5382 /* give hw rings */
5383 setup_hw_rings(dev, NV_SETUP_RX_RING | NV_SETUP_TX_RING);
5384 writel(((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT),
5385 base + NvRegRingSizes);
5386
5387 writel(np->linkspeed, base + NvRegLinkSpeed);
5388 if (np->desc_ver == DESC_VER_1)
5389 writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark);
5390 else
5391 writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark);
5392 writel(np->txrxctl_bits, base + NvRegTxRxControl);
5393 writel(np->vlanctl_bits, base + NvRegVlanControl);
5394 pci_push(base);
5395 writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl);
5396 if (reg_delay(dev, NvRegUnknownSetupReg5,
5397 NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31,
5398 NV_SETUP5_DELAY, NV_SETUP5_DELAYMAX))
5399 netdev_info(dev,
5400 "%s: SetupReg5, Bit 31 remained off\n", __func__);
5401
5402 writel(0, base + NvRegMIIMask);
5403 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5404 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5405
5406 writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1);
5407 writel(readl(base + NvRegTransmitterStatus), base + NvRegTransmitterStatus);
5408 writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
5409 writel(np->rx_buf_sz, base + NvRegOffloadConfig);
5410
5411 writel(readl(base + NvRegReceiverStatus), base + NvRegReceiverStatus);
5412
5413 get_random_bytes(&low, sizeof(low));
5414 low &= NVREG_SLOTTIME_MASK;
5415 if (np->desc_ver == DESC_VER_1) {
5416 writel(low|NVREG_SLOTTIME_DEFAULT, base + NvRegSlotTime);
5417 } else {
5418 if (!(np->driver_data & DEV_HAS_GEAR_MODE)) {
5419 /* setup legacy backoff */
5420 writel(NVREG_SLOTTIME_LEGBF_ENABLED|NVREG_SLOTTIME_10_100_FULL|low, base + NvRegSlotTime);
5421 } else {
5422 writel(NVREG_SLOTTIME_10_100_FULL, base + NvRegSlotTime);
5423 nv_gear_backoff_reseed(dev);
5424 }
5425 }
5426 writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral);
5427 writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral);
5428 if (poll_interval == -1) {
5429 if (optimization_mode == NV_OPTIMIZATION_MODE_THROUGHPUT)
5430 writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval);
5431 else
5432 writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval);
5433 } else
5434 writel(poll_interval & 0xFFFF, base + NvRegPollingInterval);
5435 writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
5436 writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING,
5437 base + NvRegAdapterControl);
5438 writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed);
5439 writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask);
5440 if (np->wolenabled)
5441 writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags);
5442
5443 i = readl(base + NvRegPowerState);
5444 if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
5445 writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState);
5446
5447 pci_push(base);
5448 udelay(10);
5449 writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState);
5450
5451 nv_disable_hw_interrupts(dev, np->irqmask);
5452 pci_push(base);
5453 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5454 writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
5455 pci_push(base);
5456
5457 if (nv_request_irq(dev, 0))
5458 goto out_drain;
5459
5460 /* ask for interrupts */
5461 nv_enable_hw_interrupts(dev, np->irqmask);
5462
5463 spin_lock_irq(&np->lock);
5464 writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
5465 writel(0, base + NvRegMulticastAddrB);
5466 writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA);
5467 writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB);
5468 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5469 /* One manual link speed update: Interrupts are enabled, future link
5470 * speed changes cause interrupts and are handled by nv_link_irq().
5471 */
5472 {
5473 u32 miistat;
5474 miistat = readl(base + NvRegMIIStatus);
5475 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5476 }
5477 /* set linkspeed to invalid value, thus force nv_update_linkspeed
5478 * to init hw */
5479 np->linkspeed = 0;
5480 ret = nv_update_linkspeed(dev);
5481 nv_start_rxtx(dev);
5482 netif_start_queue(dev);
5483 nv_napi_enable(dev);
5484
5485 if (ret) {
5486 netif_carrier_on(dev);
5487 } else {
5488 netdev_info(dev, "no link during initialization\n");
5489 netif_carrier_off(dev);
5490 }
5491 if (oom)
5492 mod_timer(&np->oom_kick, jiffies + OOM_REFILL);
5493
5494 /* start statistics timer */
5495 if (np->driver_data & (DEV_HAS_STATISTICS_V1|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5496 mod_timer(&np->stats_poll,
5497 round_jiffies(jiffies + STATS_INTERVAL));
5498
5499 spin_unlock_irq(&np->lock);
5500
5501 /* If the loopback feature was set while the device was down, make sure
5502 * that it's set correctly now.
5503 */
5504 if (dev->features & NETIF_F_LOOPBACK)
5505 nv_set_loopback(dev, dev->features);
5506
5507 return 0;
5508 out_drain:
5509 nv_drain_rxtx(dev);
5510 return ret;
5511 }
5512
5513 static int nv_close(struct net_device *dev)
5514 {
5515 struct fe_priv *np = netdev_priv(dev);
5516 u8 __iomem *base;
5517
5518 spin_lock_irq(&np->lock);
5519 np->in_shutdown = 1;
5520 spin_unlock_irq(&np->lock);
5521 nv_napi_disable(dev);
5522 synchronize_irq(np->pci_dev->irq);
5523
5524 del_timer_sync(&np->oom_kick);
5525 del_timer_sync(&np->nic_poll);
5526 del_timer_sync(&np->stats_poll);
5527
5528 netif_stop_queue(dev);
5529 spin_lock_irq(&np->lock);
5530 nv_update_pause(dev, 0); /* otherwise stop_tx bricks NIC */
5531 nv_stop_rxtx(dev);
5532 nv_txrx_reset(dev);
5533
5534 /* disable interrupts on the nic or we will lock up */
5535 base = get_hwbase(dev);
5536 nv_disable_hw_interrupts(dev, np->irqmask);
5537 pci_push(base);
5538
5539 spin_unlock_irq(&np->lock);
5540
5541 nv_free_irq(dev);
5542
5543 nv_drain_rxtx(dev);
5544
5545 if (np->wolenabled || !phy_power_down) {
5546 nv_txrx_gate(dev, false);
5547 writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags);
5548 nv_start_rx(dev);
5549 } else {
5550 /* power down phy */
5551 mii_rw(dev, np->phyaddr, MII_BMCR,
5552 mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ)|BMCR_PDOWN);
5553 nv_txrx_gate(dev, true);
5554 }
5555
5556 /* FIXME: power down nic */
5557
5558 return 0;
5559 }
5560
5561 static const struct net_device_ops nv_netdev_ops = {
5562 .ndo_open = nv_open,
5563 .ndo_stop = nv_close,
5564 .ndo_get_stats64 = nv_get_stats64,
5565 .ndo_start_xmit = nv_start_xmit,
5566 .ndo_tx_timeout = nv_tx_timeout,
5567 .ndo_change_mtu = nv_change_mtu,
5568 .ndo_fix_features = nv_fix_features,
5569 .ndo_set_features = nv_set_features,
5570 .ndo_validate_addr = eth_validate_addr,
5571 .ndo_set_mac_address = nv_set_mac_address,
5572 .ndo_set_rx_mode = nv_set_multicast,
5573 #ifdef CONFIG_NET_POLL_CONTROLLER
5574 .ndo_poll_controller = nv_poll_controller,
5575 #endif
5576 };
5577
5578 static const struct net_device_ops nv_netdev_ops_optimized = {
5579 .ndo_open = nv_open,
5580 .ndo_stop = nv_close,
5581 .ndo_get_stats64 = nv_get_stats64,
5582 .ndo_start_xmit = nv_start_xmit_optimized,
5583 .ndo_tx_timeout = nv_tx_timeout,
5584 .ndo_change_mtu = nv_change_mtu,
5585 .ndo_fix_features = nv_fix_features,
5586 .ndo_set_features = nv_set_features,
5587 .ndo_validate_addr = eth_validate_addr,
5588 .ndo_set_mac_address = nv_set_mac_address,
5589 .ndo_set_rx_mode = nv_set_multicast,
5590 #ifdef CONFIG_NET_POLL_CONTROLLER
5591 .ndo_poll_controller = nv_poll_controller,
5592 #endif
5593 };
5594
5595 static int nv_probe(struct pci_dev *pci_dev, const struct pci_device_id *id)
5596 {
5597 struct net_device *dev;
5598 struct fe_priv *np;
5599 unsigned long addr;
5600 u8 __iomem *base;
5601 int err, i;
5602 u32 powerstate, txreg;
5603 u32 phystate_orig = 0, phystate;
5604 int phyinitialized = 0;
5605 static int printed_version;
5606
5607 if (!printed_version++)
5608 pr_info("Reverse Engineered nForce ethernet driver. Version %s.\n",
5609 FORCEDETH_VERSION);
5610
5611 dev = alloc_etherdev(sizeof(struct fe_priv));
5612 err = -ENOMEM;
5613 if (!dev)
5614 goto out;
5615
5616 np = netdev_priv(dev);
5617 np->dev = dev;
5618 np->pci_dev = pci_dev;
5619 spin_lock_init(&np->lock);
5620 spin_lock_init(&np->hwstats_lock);
5621 SET_NETDEV_DEV(dev, &pci_dev->dev);
5622 u64_stats_init(&np->swstats_rx_syncp);
5623 u64_stats_init(&np->swstats_tx_syncp);
5624
5625 init_timer(&np->oom_kick);
5626 np->oom_kick.data = (unsigned long) dev;
5627 np->oom_kick.function = nv_do_rx_refill; /* timer handler */
5628 init_timer(&np->nic_poll);
5629 np->nic_poll.data = (unsigned long) dev;
5630 np->nic_poll.function = nv_do_nic_poll; /* timer handler */
5631 init_timer_deferrable(&np->stats_poll);
5632 np->stats_poll.data = (unsigned long) dev;
5633 np->stats_poll.function = nv_do_stats_poll; /* timer handler */
5634
5635 err = pci_enable_device(pci_dev);
5636 if (err)
5637 goto out_free;
5638
5639 pci_set_master(pci_dev);
5640
5641 err = pci_request_regions(pci_dev, DRV_NAME);
5642 if (err < 0)
5643 goto out_disable;
5644
5645 if (id->driver_data & (DEV_HAS_VLAN|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V2|DEV_HAS_STATISTICS_V3))
5646 np->register_size = NV_PCI_REGSZ_VER3;
5647 else if (id->driver_data & DEV_HAS_STATISTICS_V1)
5648 np->register_size = NV_PCI_REGSZ_VER2;
5649 else
5650 np->register_size = NV_PCI_REGSZ_VER1;
5651
5652 err = -EINVAL;
5653 addr = 0;
5654 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5655 if (pci_resource_flags(pci_dev, i) & IORESOURCE_MEM &&
5656 pci_resource_len(pci_dev, i) >= np->register_size) {
5657 addr = pci_resource_start(pci_dev, i);
5658 break;
5659 }
5660 }
5661 if (i == DEVICE_COUNT_RESOURCE) {
5662 dev_info(&pci_dev->dev, "Couldn't find register window\n");
5663 goto out_relreg;
5664 }
5665
5666 /* copy of driver data */
5667 np->driver_data = id->driver_data;
5668 /* copy of device id */
5669 np->device_id = id->device;
5670
5671 /* handle different descriptor versions */
5672 if (id->driver_data & DEV_HAS_HIGH_DMA) {
5673 /* packet format 3: supports 40-bit addressing */
5674 np->desc_ver = DESC_VER_3;
5675 np->txrxctl_bits = NVREG_TXRXCTL_DESC_3;
5676 if (dma_64bit) {
5677 if (pci_set_dma_mask(pci_dev, DMA_BIT_MASK(39)))
5678 dev_info(&pci_dev->dev,
5679 "64-bit DMA failed, using 32-bit addressing\n");
5680 else
5681 dev->features |= NETIF_F_HIGHDMA;
5682 if (pci_set_consistent_dma_mask(pci_dev, DMA_BIT_MASK(39))) {
5683 dev_info(&pci_dev->dev,
5684 "64-bit DMA (consistent) failed, using 32-bit ring buffers\n");
5685 }
5686 }
5687 } else if (id->driver_data & DEV_HAS_LARGEDESC) {
5688 /* packet format 2: supports jumbo frames */
5689 np->desc_ver = DESC_VER_2;
5690 np->txrxctl_bits = NVREG_TXRXCTL_DESC_2;
5691 } else {
5692 /* original packet format */
5693 np->desc_ver = DESC_VER_1;
5694 np->txrxctl_bits = NVREG_TXRXCTL_DESC_1;
5695 }
5696
5697 np->pkt_limit = NV_PKTLIMIT_1;
5698 if (id->driver_data & DEV_HAS_LARGEDESC)
5699 np->pkt_limit = NV_PKTLIMIT_2;
5700
5701 if (id->driver_data & DEV_HAS_CHECKSUM) {
5702 np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK;
5703 dev->hw_features |= NETIF_F_IP_CSUM | NETIF_F_SG |
5704 NETIF_F_TSO | NETIF_F_RXCSUM;
5705 }
5706
5707 np->vlanctl_bits = 0;
5708 if (id->driver_data & DEV_HAS_VLAN) {
5709 np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE;
5710 dev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX |
5711 NETIF_F_HW_VLAN_CTAG_TX;
5712 }
5713
5714 dev->features |= dev->hw_features;
5715
5716 /* Add loopback capability to the device. */
5717 dev->hw_features |= NETIF_F_LOOPBACK;
5718
5719 np->pause_flags = NV_PAUSEFRAME_RX_CAPABLE | NV_PAUSEFRAME_RX_REQ | NV_PAUSEFRAME_AUTONEG;
5720 if ((id->driver_data & DEV_HAS_PAUSEFRAME_TX_V1) ||
5721 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V2) ||
5722 (id->driver_data & DEV_HAS_PAUSEFRAME_TX_V3)) {
5723 np->pause_flags |= NV_PAUSEFRAME_TX_CAPABLE | NV_PAUSEFRAME_TX_REQ;
5724 }
5725
5726 err = -ENOMEM;
5727 np->base = ioremap(addr, np->register_size);
5728 if (!np->base)
5729 goto out_relreg;
5730
5731 np->rx_ring_size = RX_RING_DEFAULT;
5732 np->tx_ring_size = TX_RING_DEFAULT;
5733
5734 if (!nv_optimized(np)) {
5735 np->rx_ring.orig = pci_alloc_consistent(pci_dev,
5736 sizeof(struct ring_desc) * (np->rx_ring_size + np->tx_ring_size),
5737 &np->ring_addr);
5738 if (!np->rx_ring.orig)
5739 goto out_unmap;
5740 np->tx_ring.orig = &np->rx_ring.orig[np->rx_ring_size];
5741 } else {
5742 np->rx_ring.ex = pci_alloc_consistent(pci_dev,
5743 sizeof(struct ring_desc_ex) * (np->rx_ring_size + np->tx_ring_size),
5744 &np->ring_addr);
5745 if (!np->rx_ring.ex)
5746 goto out_unmap;
5747 np->tx_ring.ex = &np->rx_ring.ex[np->rx_ring_size];
5748 }
5749 np->rx_skb = kcalloc(np->rx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5750 np->tx_skb = kcalloc(np->tx_ring_size, sizeof(struct nv_skb_map), GFP_KERNEL);
5751 if (!np->rx_skb || !np->tx_skb)
5752 goto out_freering;
5753
5754 if (!nv_optimized(np))
5755 dev->netdev_ops = &nv_netdev_ops;
5756 else
5757 dev->netdev_ops = &nv_netdev_ops_optimized;
5758
5759 netif_napi_add(dev, &np->napi, nv_napi_poll, RX_WORK_PER_LOOP);
5760 SET_ETHTOOL_OPS(dev, &ops);
5761 dev->watchdog_timeo = NV_WATCHDOG_TIMEO;
5762
5763 pci_set_drvdata(pci_dev, dev);
5764
5765 /* read the mac address */
5766 base = get_hwbase(dev);
5767 np->orig_mac[0] = readl(base + NvRegMacAddrA);
5768 np->orig_mac[1] = readl(base + NvRegMacAddrB);
5769
5770 /* check the workaround bit for correct mac address order */
5771 txreg = readl(base + NvRegTransmitPoll);
5772 if (id->driver_data & DEV_HAS_CORRECT_MACADDR) {
5773 /* mac address is already in correct order */
5774 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5775 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5776 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5777 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5778 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5779 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5780 } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) {
5781 /* mac address is already in correct order */
5782 dev->dev_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
5783 dev->dev_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
5784 dev->dev_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
5785 dev->dev_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
5786 dev->dev_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
5787 dev->dev_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
5788 /*
5789 * Set orig mac address back to the reversed version.
5790 * This flag will be cleared during low power transition.
5791 * Therefore, we should always put back the reversed address.
5792 */
5793 np->orig_mac[0] = (dev->dev_addr[5] << 0) + (dev->dev_addr[4] << 8) +
5794 (dev->dev_addr[3] << 16) + (dev->dev_addr[2] << 24);
5795 np->orig_mac[1] = (dev->dev_addr[1] << 0) + (dev->dev_addr[0] << 8);
5796 } else {
5797 /* need to reverse mac address to correct order */
5798 dev->dev_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
5799 dev->dev_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
5800 dev->dev_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
5801 dev->dev_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
5802 dev->dev_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
5803 dev->dev_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
5804 writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll);
5805 dev_dbg(&pci_dev->dev,
5806 "%s: set workaround bit for reversed mac addr\n",
5807 __func__);
5808 }
5809
5810 if (!is_valid_ether_addr(dev->dev_addr)) {
5811 /*
5812 * Bad mac address. At least one bios sets the mac address
5813 * to 01:23:45:67:89:ab
5814 */
5815 dev_err(&pci_dev->dev,
5816 "Invalid MAC address detected: %pM - Please complain to your hardware vendor.\n",
5817 dev->dev_addr);
5818 eth_hw_addr_random(dev);
5819 dev_err(&pci_dev->dev,
5820 "Using random MAC address: %pM\n", dev->dev_addr);
5821 }
5822
5823 /* set mac address */
5824 nv_copy_mac_to_hw(dev);
5825
5826 /* disable WOL */
5827 writel(0, base + NvRegWakeUpFlags);
5828 np->wolenabled = 0;
5829 device_set_wakeup_enable(&pci_dev->dev, false);
5830
5831 if (id->driver_data & DEV_HAS_POWER_CNTRL) {
5832
5833 /* take phy and nic out of low power mode */
5834 powerstate = readl(base + NvRegPowerState2);
5835 powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK;
5836 if ((id->driver_data & DEV_NEED_LOW_POWER_FIX) &&
5837 pci_dev->revision >= 0xA3)
5838 powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3;
5839 writel(powerstate, base + NvRegPowerState2);
5840 }
5841
5842 if (np->desc_ver == DESC_VER_1)
5843 np->tx_flags = NV_TX_VALID;
5844 else
5845 np->tx_flags = NV_TX2_VALID;
5846
5847 np->msi_flags = 0;
5848 if ((id->driver_data & DEV_HAS_MSI) && msi)
5849 np->msi_flags |= NV_MSI_CAPABLE;
5850
5851 if ((id->driver_data & DEV_HAS_MSI_X) && msix) {
5852 /* msix has had reported issues when modifying irqmask
5853 as in the case of napi, therefore, disable for now
5854 */
5855 #if 0
5856 np->msi_flags |= NV_MSI_X_CAPABLE;
5857 #endif
5858 }
5859
5860 if (optimization_mode == NV_OPTIMIZATION_MODE_CPU) {
5861 np->irqmask = NVREG_IRQMASK_CPU;
5862 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5863 np->msi_flags |= 0x0001;
5864 } else if (optimization_mode == NV_OPTIMIZATION_MODE_DYNAMIC &&
5865 !(id->driver_data & DEV_NEED_TIMERIRQ)) {
5866 /* start off in throughput mode */
5867 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5868 /* remove support for msix mode */
5869 np->msi_flags &= ~NV_MSI_X_CAPABLE;
5870 } else {
5871 optimization_mode = NV_OPTIMIZATION_MODE_THROUGHPUT;
5872 np->irqmask = NVREG_IRQMASK_THROUGHPUT;
5873 if (np->msi_flags & NV_MSI_X_CAPABLE) /* set number of vectors */
5874 np->msi_flags |= 0x0003;
5875 }
5876
5877 if (id->driver_data & DEV_NEED_TIMERIRQ)
5878 np->irqmask |= NVREG_IRQ_TIMER;
5879 if (id->driver_data & DEV_NEED_LINKTIMER) {
5880 np->need_linktimer = 1;
5881 np->link_timeout = jiffies + LINK_TIMEOUT;
5882 } else {
5883 np->need_linktimer = 0;
5884 }
5885
5886 /* Limit the number of tx's outstanding for hw bug */
5887 if (id->driver_data & DEV_NEED_TX_LIMIT) {
5888 np->tx_limit = 1;
5889 if (((id->driver_data & DEV_NEED_TX_LIMIT2) == DEV_NEED_TX_LIMIT2) &&
5890 pci_dev->revision >= 0xA2)
5891 np->tx_limit = 0;
5892 }
5893
5894 /* clear phy state and temporarily halt phy interrupts */
5895 writel(0, base + NvRegMIIMask);
5896 phystate = readl(base + NvRegAdapterControl);
5897 if (phystate & NVREG_ADAPTCTL_RUNNING) {
5898 phystate_orig = 1;
5899 phystate &= ~NVREG_ADAPTCTL_RUNNING;
5900 writel(phystate, base + NvRegAdapterControl);
5901 }
5902 writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus);
5903
5904 if (id->driver_data & DEV_HAS_MGMT_UNIT) {
5905 /* management unit running on the mac? */
5906 if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST) &&
5907 (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) &&
5908 nv_mgmt_acquire_sema(dev) &&
5909 nv_mgmt_get_version(dev)) {
5910 np->mac_in_use = 1;
5911 if (np->mgmt_version > 0)
5912 np->mac_in_use = readl(base + NvRegMgmtUnitControl) & NVREG_MGMTUNITCONTROL_INUSE;
5913 /* management unit setup the phy already? */
5914 if (np->mac_in_use &&
5915 ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) ==
5916 NVREG_XMITCTL_SYNC_PHY_INIT)) {
5917 /* phy is inited by mgmt unit */
5918 phyinitialized = 1;
5919 } else {
5920 /* we need to init the phy */
5921 }
5922 }
5923 }
5924
5925 /* find a suitable phy */
5926 for (i = 1; i <= 32; i++) {
5927 int id1, id2;
5928 int phyaddr = i & 0x1F;
5929
5930 spin_lock_irq(&np->lock);
5931 id1 = mii_rw(dev, phyaddr, MII_PHYSID1, MII_READ);
5932 spin_unlock_irq(&np->lock);
5933 if (id1 < 0 || id1 == 0xffff)
5934 continue;
5935 spin_lock_irq(&np->lock);
5936 id2 = mii_rw(dev, phyaddr, MII_PHYSID2, MII_READ);
5937 spin_unlock_irq(&np->lock);
5938 if (id2 < 0 || id2 == 0xffff)
5939 continue;
5940
5941 np->phy_model = id2 & PHYID2_MODEL_MASK;
5942 id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
5943 id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
5944 np->phyaddr = phyaddr;
5945 np->phy_oui = id1 | id2;
5946
5947 /* Realtek hardcoded phy id1 to all zero's on certain phys */
5948 if (np->phy_oui == PHY_OUI_REALTEK2)
5949 np->phy_oui = PHY_OUI_REALTEK;
5950 /* Setup phy revision for Realtek */
5951 if (np->phy_oui == PHY_OUI_REALTEK && np->phy_model == PHY_MODEL_REALTEK_8211)
5952 np->phy_rev = mii_rw(dev, phyaddr, MII_RESV1, MII_READ) & PHY_REV_MASK;
5953
5954 break;
5955 }
5956 if (i == 33) {
5957 dev_info(&pci_dev->dev, "open: Could not find a valid PHY\n");
5958 goto out_error;
5959 }
5960
5961 if (!phyinitialized) {
5962 /* reset it */
5963 phy_init(dev);
5964 } else {
5965 /* see if it is a gigabit phy */
5966 u32 mii_status = mii_rw(dev, np->phyaddr, MII_BMSR, MII_READ);
5967 if (mii_status & PHY_GIGABIT)
5968 np->gigabit = PHY_GIGABIT;
5969 }
5970
5971 /* set default link speed settings */
5972 np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10;
5973 np->duplex = 0;
5974 np->autoneg = 1;
5975
5976 err = register_netdev(dev);
5977 if (err) {
5978 dev_info(&pci_dev->dev, "unable to register netdev: %d\n", err);
5979 goto out_error;
5980 }
5981
5982 netif_carrier_off(dev);
5983
5984 /* Some NICs freeze when TX pause is enabled while NIC is
5985 * down, and this stays across warm reboots. The sequence
5986 * below should be enough to recover from that state.
5987 */
5988 nv_update_pause(dev, 0);
5989 nv_start_tx(dev);
5990 nv_stop_tx(dev);
5991
5992 if (id->driver_data & DEV_HAS_VLAN)
5993 nv_vlan_mode(dev, dev->features);
5994
5995 dev_info(&pci_dev->dev, "ifname %s, PHY OUI 0x%x @ %d, addr %pM\n",
5996 dev->name, np->phy_oui, np->phyaddr, dev->dev_addr);
5997
5998 dev_info(&pci_dev->dev, "%s%s%s%s%s%s%s%s%s%s%sdesc-v%u\n",
5999 dev->features & NETIF_F_HIGHDMA ? "highdma " : "",
6000 dev->features & (NETIF_F_IP_CSUM | NETIF_F_SG) ?
6001 "csum " : "",
6002 dev->features & (NETIF_F_HW_VLAN_CTAG_RX |
6003 NETIF_F_HW_VLAN_CTAG_TX) ?
6004 "vlan " : "",
6005 dev->features & (NETIF_F_LOOPBACK) ?
6006 "loopback " : "",
6007 id->driver_data & DEV_HAS_POWER_CNTRL ? "pwrctl " : "",
6008 id->driver_data & DEV_HAS_MGMT_UNIT ? "mgmt " : "",
6009 id->driver_data & DEV_NEED_TIMERIRQ ? "timirq " : "",
6010 np->gigabit == PHY_GIGABIT ? "gbit " : "",
6011 np->need_linktimer ? "lnktim " : "",
6012 np->msi_flags & NV_MSI_CAPABLE ? "msi " : "",
6013 np->msi_flags & NV_MSI_X_CAPABLE ? "msi-x " : "",
6014 np->desc_ver);
6015
6016 return 0;
6017
6018 out_error:
6019 if (phystate_orig)
6020 writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl);
6021 out_freering:
6022 free_rings(dev);
6023 out_unmap:
6024 iounmap(get_hwbase(dev));
6025 out_relreg:
6026 pci_release_regions(pci_dev);
6027 out_disable:
6028 pci_disable_device(pci_dev);
6029 out_free:
6030 free_netdev(dev);
6031 out:
6032 return err;
6033 }
6034
6035 static void nv_restore_phy(struct net_device *dev)
6036 {
6037 struct fe_priv *np = netdev_priv(dev);
6038 u16 phy_reserved, mii_control;
6039
6040 if (np->phy_oui == PHY_OUI_REALTEK &&
6041 np->phy_model == PHY_MODEL_REALTEK_8201 &&
6042 phy_cross == NV_CROSSOVER_DETECTION_DISABLED) {
6043 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT3);
6044 phy_reserved = mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, MII_READ);
6045 phy_reserved &= ~PHY_REALTEK_INIT_MSK1;
6046 phy_reserved |= PHY_REALTEK_INIT8;
6047 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG2, phy_reserved);
6048 mii_rw(dev, np->phyaddr, PHY_REALTEK_INIT_REG1, PHY_REALTEK_INIT1);
6049
6050 /* restart auto negotiation */
6051 mii_control = mii_rw(dev, np->phyaddr, MII_BMCR, MII_READ);
6052 mii_control |= (BMCR_ANRESTART | BMCR_ANENABLE);
6053 mii_rw(dev, np->phyaddr, MII_BMCR, mii_control);
6054 }
6055 }
6056
6057 static void nv_restore_mac_addr(struct pci_dev *pci_dev)
6058 {
6059 struct net_device *dev = pci_get_drvdata(pci_dev);
6060 struct fe_priv *np = netdev_priv(dev);
6061 u8 __iomem *base = get_hwbase(dev);
6062
6063 /* special op: write back the misordered MAC address - otherwise
6064 * the next nv_probe would see a wrong address.
6065 */
6066 writel(np->orig_mac[0], base + NvRegMacAddrA);
6067 writel(np->orig_mac[1], base + NvRegMacAddrB);
6068 writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV,
6069 base + NvRegTransmitPoll);
6070 }
6071
6072 static void nv_remove(struct pci_dev *pci_dev)
6073 {
6074 struct net_device *dev = pci_get_drvdata(pci_dev);
6075
6076 unregister_netdev(dev);
6077
6078 nv_restore_mac_addr(pci_dev);
6079
6080 /* restore any phy related changes */
6081 nv_restore_phy(dev);
6082
6083 nv_mgmt_release_sema(dev);
6084
6085 /* free all structures */
6086 free_rings(dev);
6087 iounmap(get_hwbase(dev));
6088 pci_release_regions(pci_dev);
6089 pci_disable_device(pci_dev);
6090 free_netdev(dev);
6091 }
6092
6093 #ifdef CONFIG_PM_SLEEP
6094 static int nv_suspend(struct device *device)
6095 {
6096 struct pci_dev *pdev = to_pci_dev(device);
6097 struct net_device *dev = pci_get_drvdata(pdev);
6098 struct fe_priv *np = netdev_priv(dev);
6099 u8 __iomem *base = get_hwbase(dev);
6100 int i;
6101
6102 if (netif_running(dev)) {
6103 /* Gross. */
6104 nv_close(dev);
6105 }
6106 netif_device_detach(dev);
6107
6108 /* save non-pci configuration space */
6109 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6110 np->saved_config_space[i] = readl(base + i*sizeof(u32));
6111
6112 return 0;
6113 }
6114
6115 static int nv_resume(struct device *device)
6116 {
6117 struct pci_dev *pdev = to_pci_dev(device);
6118 struct net_device *dev = pci_get_drvdata(pdev);
6119 struct fe_priv *np = netdev_priv(dev);
6120 u8 __iomem *base = get_hwbase(dev);
6121 int i, rc = 0;
6122
6123 /* restore non-pci configuration space */
6124 for (i = 0; i <= np->register_size/sizeof(u32); i++)
6125 writel(np->saved_config_space[i], base+i*sizeof(u32));
6126
6127 if (np->driver_data & DEV_NEED_MSI_FIX)
6128 pci_write_config_dword(pdev, NV_MSI_PRIV_OFFSET, NV_MSI_PRIV_VALUE);
6129
6130 /* restore phy state, including autoneg */
6131 phy_init(dev);
6132
6133 netif_device_attach(dev);
6134 if (netif_running(dev)) {
6135 rc = nv_open(dev);
6136 nv_set_multicast(dev);
6137 }
6138 return rc;
6139 }
6140
6141 static SIMPLE_DEV_PM_OPS(nv_pm_ops, nv_suspend, nv_resume);
6142 #define NV_PM_OPS (&nv_pm_ops)
6143
6144 #else
6145 #define NV_PM_OPS NULL
6146 #endif /* CONFIG_PM_SLEEP */
6147
6148 #ifdef CONFIG_PM
6149 static void nv_shutdown(struct pci_dev *pdev)
6150 {
6151 struct net_device *dev = pci_get_drvdata(pdev);
6152 struct fe_priv *np = netdev_priv(dev);
6153
6154 if (netif_running(dev))
6155 nv_close(dev);
6156
6157 /*
6158 * Restore the MAC so a kernel started by kexec won't get confused.
6159 * If we really go for poweroff, we must not restore the MAC,
6160 * otherwise the MAC for WOL will be reversed at least on some boards.
6161 */
6162 if (system_state != SYSTEM_POWER_OFF)
6163 nv_restore_mac_addr(pdev);
6164
6165 pci_disable_device(pdev);
6166 /*
6167 * Apparently it is not possible to reinitialise from D3 hot,
6168 * only put the device into D3 if we really go for poweroff.
6169 */
6170 if (system_state == SYSTEM_POWER_OFF) {
6171 pci_wake_from_d3(pdev, np->wolenabled);
6172 pci_set_power_state(pdev, PCI_D3hot);
6173 }
6174 }
6175 #else
6176 #define nv_shutdown NULL
6177 #endif /* CONFIG_PM */
6178
6179 static DEFINE_PCI_DEVICE_TABLE(pci_tbl) = {
6180 { /* nForce Ethernet Controller */
6181 PCI_DEVICE(0x10DE, 0x01C3),
6182 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6183 },
6184 { /* nForce2 Ethernet Controller */
6185 PCI_DEVICE(0x10DE, 0x0066),
6186 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6187 },
6188 { /* nForce3 Ethernet Controller */
6189 PCI_DEVICE(0x10DE, 0x00D6),
6190 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER,
6191 },
6192 { /* nForce3 Ethernet Controller */
6193 PCI_DEVICE(0x10DE, 0x0086),
6194 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6195 },
6196 { /* nForce3 Ethernet Controller */
6197 PCI_DEVICE(0x10DE, 0x008C),
6198 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6199 },
6200 { /* nForce3 Ethernet Controller */
6201 PCI_DEVICE(0x10DE, 0x00E6),
6202 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6203 },
6204 { /* nForce3 Ethernet Controller */
6205 PCI_DEVICE(0x10DE, 0x00DF),
6206 .driver_data = DEV_NEED_TIMERIRQ|DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM,
6207 },
6208 { /* CK804 Ethernet Controller */
6209 PCI_DEVICE(0x10DE, 0x0056),
6210 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6211 },
6212 { /* CK804 Ethernet Controller */
6213 PCI_DEVICE(0x10DE, 0x0057),
6214 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6215 },
6216 { /* MCP04 Ethernet Controller */
6217 PCI_DEVICE(0x10DE, 0x0037),
6218 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6219 },
6220 { /* MCP04 Ethernet Controller */
6221 PCI_DEVICE(0x10DE, 0x0038),
6222 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_STATISTICS_V1|DEV_NEED_TX_LIMIT,
6223 },
6224 { /* MCP51 Ethernet Controller */
6225 PCI_DEVICE(0x10DE, 0x0268),
6226 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6227 },
6228 { /* MCP51 Ethernet Controller */
6229 PCI_DEVICE(0x10DE, 0x0269),
6230 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_STATISTICS_V1|DEV_NEED_LOW_POWER_FIX,
6231 },
6232 { /* MCP55 Ethernet Controller */
6233 PCI_DEVICE(0x10DE, 0x0372),
6234 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6235 },
6236 { /* MCP55 Ethernet Controller */
6237 PCI_DEVICE(0x10DE, 0x0373),
6238 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_VLAN|DEV_HAS_MSI|DEV_HAS_MSI_X|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_NEED_TX_LIMIT|DEV_NEED_MSI_FIX,
6239 },
6240 { /* MCP61 Ethernet Controller */
6241 PCI_DEVICE(0x10DE, 0x03E5),
6242 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6243 },
6244 { /* MCP61 Ethernet Controller */
6245 PCI_DEVICE(0x10DE, 0x03E6),
6246 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6247 },
6248 { /* MCP61 Ethernet Controller */
6249 PCI_DEVICE(0x10DE, 0x03EE),
6250 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6251 },
6252 { /* MCP61 Ethernet Controller */
6253 PCI_DEVICE(0x10DE, 0x03EF),
6254 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_MSI_FIX,
6255 },
6256 { /* MCP65 Ethernet Controller */
6257 PCI_DEVICE(0x10DE, 0x0450),
6258 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6259 },
6260 { /* MCP65 Ethernet Controller */
6261 PCI_DEVICE(0x10DE, 0x0451),
6262 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6263 },
6264 { /* MCP65 Ethernet Controller */
6265 PCI_DEVICE(0x10DE, 0x0452),
6266 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6267 },
6268 { /* MCP65 Ethernet Controller */
6269 PCI_DEVICE(0x10DE, 0x0453),
6270 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_NEED_TX_LIMIT|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6271 },
6272 { /* MCP67 Ethernet Controller */
6273 PCI_DEVICE(0x10DE, 0x054C),
6274 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6275 },
6276 { /* MCP67 Ethernet Controller */
6277 PCI_DEVICE(0x10DE, 0x054D),
6278 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6279 },
6280 { /* MCP67 Ethernet Controller */
6281 PCI_DEVICE(0x10DE, 0x054E),
6282 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6283 },
6284 { /* MCP67 Ethernet Controller */
6285 PCI_DEVICE(0x10DE, 0x054F),
6286 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6287 },
6288 { /* MCP73 Ethernet Controller */
6289 PCI_DEVICE(0x10DE, 0x07DC),
6290 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6291 },
6292 { /* MCP73 Ethernet Controller */
6293 PCI_DEVICE(0x10DE, 0x07DD),
6294 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6295 },
6296 { /* MCP73 Ethernet Controller */
6297 PCI_DEVICE(0x10DE, 0x07DE),
6298 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6299 },
6300 { /* MCP73 Ethernet Controller */
6301 PCI_DEVICE(0x10DE, 0x07DF),
6302 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_HIGH_DMA|DEV_HAS_POWER_CNTRL|DEV_HAS_MSI|DEV_HAS_PAUSEFRAME_TX_V1|DEV_HAS_STATISTICS_V12|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_MSI_FIX,
6303 },
6304 { /* MCP77 Ethernet Controller */
6305 PCI_DEVICE(0x10DE, 0x0760),
6306 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6307 },
6308 { /* MCP77 Ethernet Controller */
6309 PCI_DEVICE(0x10DE, 0x0761),
6310 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6311 },
6312 { /* MCP77 Ethernet Controller */
6313 PCI_DEVICE(0x10DE, 0x0762),
6314 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6315 },
6316 { /* MCP77 Ethernet Controller */
6317 PCI_DEVICE(0x10DE, 0x0763),
6318 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V2|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_MGMT_UNIT|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6319 },
6320 { /* MCP79 Ethernet Controller */
6321 PCI_DEVICE(0x10DE, 0x0AB0),
6322 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6323 },
6324 { /* MCP79 Ethernet Controller */
6325 PCI_DEVICE(0x10DE, 0x0AB1),
6326 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6327 },
6328 { /* MCP79 Ethernet Controller */
6329 PCI_DEVICE(0x10DE, 0x0AB2),
6330 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6331 },
6332 { /* MCP79 Ethernet Controller */
6333 PCI_DEVICE(0x10DE, 0x0AB3),
6334 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_NEED_TX_LIMIT2|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX|DEV_NEED_MSI_FIX,
6335 },
6336 { /* MCP89 Ethernet Controller */
6337 PCI_DEVICE(0x10DE, 0x0D7D),
6338 .driver_data = DEV_NEED_LINKTIMER|DEV_HAS_LARGEDESC|DEV_HAS_CHECKSUM|DEV_HAS_HIGH_DMA|DEV_HAS_MSI|DEV_HAS_POWER_CNTRL|DEV_HAS_PAUSEFRAME_TX_V3|DEV_HAS_STATISTICS_V123|DEV_HAS_TEST_EXTENDED|DEV_HAS_CORRECT_MACADDR|DEV_HAS_COLLISION_FIX|DEV_HAS_GEAR_MODE|DEV_NEED_PHY_INIT_FIX,
6339 },
6340 {0,},
6341 };
6342
6343 static struct pci_driver forcedeth_pci_driver = {
6344 .name = DRV_NAME,
6345 .id_table = pci_tbl,
6346 .probe = nv_probe,
6347 .remove = nv_remove,
6348 .shutdown = nv_shutdown,
6349 .driver.pm = NV_PM_OPS,
6350 };
6351
6352 module_param(max_interrupt_work, int, 0);
6353 MODULE_PARM_DESC(max_interrupt_work, "forcedeth maximum events handled per interrupt");
6354 module_param(optimization_mode, int, 0);
6355 MODULE_PARM_DESC(optimization_mode, "In throughput mode (0), every tx & rx packet will generate an interrupt. In CPU mode (1), interrupts are controlled by a timer. In dynamic mode (2), the mode toggles between throughput and CPU mode based on network load.");
6356 module_param(poll_interval, int, 0);
6357 MODULE_PARM_DESC(poll_interval, "Interval determines how frequent timer interrupt is generated by [(time_in_micro_secs * 100) / (2^10)]. Min is 0 and Max is 65535.");
6358 module_param(msi, int, 0);
6359 MODULE_PARM_DESC(msi, "MSI interrupts are enabled by setting to 1 and disabled by setting to 0.");
6360 module_param(msix, int, 0);
6361 MODULE_PARM_DESC(msix, "MSIX interrupts are enabled by setting to 1 and disabled by setting to 0.");
6362 module_param(dma_64bit, int, 0);
6363 MODULE_PARM_DESC(dma_64bit, "High DMA is enabled by setting to 1 and disabled by setting to 0.");
6364 module_param(phy_cross, int, 0);
6365 MODULE_PARM_DESC(phy_cross, "Phy crossover detection for Realtek 8201 phy is enabled by setting to 1 and disabled by setting to 0.");
6366 module_param(phy_power_down, int, 0);
6367 MODULE_PARM_DESC(phy_power_down, "Power down phy and disable link when interface is down (1), or leave phy powered up (0).");
6368 module_param(debug_tx_timeout, bool, 0);
6369 MODULE_PARM_DESC(debug_tx_timeout,
6370 "Dump tx related registers and ring when tx_timeout happens");
6371
6372 module_pci_driver(forcedeth_pci_driver);
6373 MODULE_AUTHOR("Manfred Spraul <manfred@colorfullife.com>");
6374 MODULE_DESCRIPTION("Reverse Engineered nForce ethernet driver");
6375 MODULE_LICENSE("GPL");
6376 MODULE_DEVICE_TABLE(pci, pci_tbl);
Linux with added FPC-III support