?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / ethernet / rdc / r6040.c
blob819b74cefd64653d4bad2dfe18971dfd64744f59
1 /*
2 * RDC R6040 Fast Ethernet MAC support
3 *
4 * Copyright (C) 2004 Sten Wang <sten.wang@rdc.com.tw>
5 * Copyright (C) 2007
6 * Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>
7 * Copyright (C) 2007-2012 Florian Fainelli <florian@openwrt.org>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version 2
12 * of the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the
21 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
22 * Boston, MA 02110-1301, USA.
23 */
24
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/string.h>
29 #include <linux/timer.h>
30 #include <linux/errno.h>
31 #include <linux/ioport.h>
32 #include <linux/interrupt.h>
33 #include <linux/pci.h>
34 #include <linux/netdevice.h>
35 #include <linux/etherdevice.h>
36 #include <linux/skbuff.h>
37 #include <linux/delay.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/crc32.h>
41 #include <linux/spinlock.h>
42 #include <linux/bitops.h>
43 #include <linux/io.h>
44 #include <linux/irq.h>
45 #include <linux/uaccess.h>
46 #include <linux/phy.h>
47
48 #include <asm/processor.h>
49
50 #define DRV_NAME "r6040"
51 #define DRV_VERSION "0.28"
52 #define DRV_RELDATE "07Oct2011"
53
54 /* Time in jiffies before concluding the transmitter is hung. */
55 #define TX_TIMEOUT (6000 * HZ / 1000)
56
57 /* RDC MAC I/O Size */
58 #define R6040_IO_SIZE 256
59
60 /* MAX RDC MAC */
61 #define MAX_MAC 2
62
63 /* MAC registers */
64 #define MCR0 0x00 /* Control register 0 */
65 #define MCR0_RCVEN 0x0002 /* Receive enable */
66 #define MCR0_PROMISC 0x0020 /* Promiscuous mode */
67 #define MCR0_HASH_EN 0x0100 /* Enable multicast hash table function */
68 #define MCR0_XMTEN 0x1000 /* Transmission enable */
69 #define MCR0_FD 0x8000 /* Full/Half duplex */
70 #define MCR1 0x04 /* Control register 1 */
71 #define MAC_RST 0x0001 /* Reset the MAC */
72 #define MBCR 0x08 /* Bus control */
73 #define MT_ICR 0x0C /* TX interrupt control */
74 #define MR_ICR 0x10 /* RX interrupt control */
75 #define MTPR 0x14 /* TX poll command register */
76 #define TM2TX 0x0001 /* Trigger MAC to transmit */
77 #define MR_BSR 0x18 /* RX buffer size */
78 #define MR_DCR 0x1A /* RX descriptor control */
79 #define MLSR 0x1C /* Last status */
80 #define TX_FIFO_UNDR 0x0200 /* TX FIFO under-run */
81 #define TX_EXCEEDC 0x2000 /* Transmit exceed collision */
82 #define TX_LATEC 0x4000 /* Transmit late collision */
83 #define MMDIO 0x20 /* MDIO control register */
84 #define MDIO_WRITE 0x4000 /* MDIO write */
85 #define MDIO_READ 0x2000 /* MDIO read */
86 #define MMRD 0x24 /* MDIO read data register */
87 #define MMWD 0x28 /* MDIO write data register */
88 #define MTD_SA0 0x2C /* TX descriptor start address 0 */
89 #define MTD_SA1 0x30 /* TX descriptor start address 1 */
90 #define MRD_SA0 0x34 /* RX descriptor start address 0 */
91 #define MRD_SA1 0x38 /* RX descriptor start address 1 */
92 #define MISR 0x3C /* Status register */
93 #define MIER 0x40 /* INT enable register */
94 #define MSK_INT 0x0000 /* Mask off interrupts */
95 #define RX_FINISH 0x0001 /* RX finished */
96 #define RX_NO_DESC 0x0002 /* No RX descriptor available */
97 #define RX_FIFO_FULL 0x0004 /* RX FIFO full */
98 #define RX_EARLY 0x0008 /* RX early */
99 #define TX_FINISH 0x0010 /* TX finished */
100 #define TX_EARLY 0x0080 /* TX early */
101 #define EVENT_OVRFL 0x0100 /* Event counter overflow */
102 #define LINK_CHANGED 0x0200 /* PHY link changed */
103 #define ME_CISR 0x44 /* Event counter INT status */
104 #define ME_CIER 0x48 /* Event counter INT enable */
105 #define MR_CNT 0x50 /* Successfully received packet counter */
106 #define ME_CNT0 0x52 /* Event counter 0 */
107 #define ME_CNT1 0x54 /* Event counter 1 */
108 #define ME_CNT2 0x56 /* Event counter 2 */
109 #define ME_CNT3 0x58 /* Event counter 3 */
110 #define MT_CNT 0x5A /* Successfully transmit packet counter */
111 #define ME_CNT4 0x5C /* Event counter 4 */
112 #define MP_CNT 0x5E /* Pause frame counter register */
113 #define MAR0 0x60 /* Hash table 0 */
114 #define MAR1 0x62 /* Hash table 1 */
115 #define MAR2 0x64 /* Hash table 2 */
116 #define MAR3 0x66 /* Hash table 3 */
117 #define MID_0L 0x68 /* Multicast address MID0 Low */
118 #define MID_0M 0x6A /* Multicast address MID0 Medium */
119 #define MID_0H 0x6C /* Multicast address MID0 High */
120 #define MID_1L 0x70 /* MID1 Low */
121 #define MID_1M 0x72 /* MID1 Medium */
122 #define MID_1H 0x74 /* MID1 High */
123 #define MID_2L 0x78 /* MID2 Low */
124 #define MID_2M 0x7A /* MID2 Medium */
125 #define MID_2H 0x7C /* MID2 High */
126 #define MID_3L 0x80 /* MID3 Low */
127 #define MID_3M 0x82 /* MID3 Medium */
128 #define MID_3H 0x84 /* MID3 High */
129 #define PHY_CC 0x88 /* PHY status change configuration register */
130 #define SCEN 0x8000 /* PHY status change enable */
131 #define PHYAD_SHIFT 8 /* PHY address shift */
132 #define TMRDIV_SHIFT 0 /* Timer divider shift */
133 #define PHY_ST 0x8A /* PHY status register */
134 #define MAC_SM 0xAC /* MAC status machine */
135 #define MAC_SM_RST 0x0002 /* MAC status machine reset */
136 #define MAC_ID 0xBE /* Identifier register */
137
138 #define TX_DCNT 0x80 /* TX descriptor count */
139 #define RX_DCNT 0x80 /* RX descriptor count */
140 #define MAX_BUF_SIZE 0x600
141 #define RX_DESC_SIZE (RX_DCNT * sizeof(struct r6040_descriptor))
142 #define TX_DESC_SIZE (TX_DCNT * sizeof(struct r6040_descriptor))
143 #define MBCR_DEFAULT 0x012A /* MAC Bus Control Register */
144 #define MCAST_MAX 3 /* Max number multicast addresses to filter */
145
146 #define MAC_DEF_TIMEOUT 2048 /* Default MAC read/write operation timeout */
147
148 /* Descriptor status */
149 #define DSC_OWNER_MAC 0x8000 /* MAC is the owner of this descriptor */
150 #define DSC_RX_OK 0x4000 /* RX was successful */
151 #define DSC_RX_ERR 0x0800 /* RX PHY error */
152 #define DSC_RX_ERR_DRI 0x0400 /* RX dribble packet */
153 #define DSC_RX_ERR_BUF 0x0200 /* RX length exceeds buffer size */
154 #define DSC_RX_ERR_LONG 0x0100 /* RX length > maximum packet length */
155 #define DSC_RX_ERR_RUNT 0x0080 /* RX packet length < 64 byte */
156 #define DSC_RX_ERR_CRC 0x0040 /* RX CRC error */
157 #define DSC_RX_BCAST 0x0020 /* RX broadcast (no error) */
158 #define DSC_RX_MCAST 0x0010 /* RX multicast (no error) */
159 #define DSC_RX_MCH_HIT 0x0008 /* RX multicast hit in hash table (no error) */
160 #define DSC_RX_MIDH_HIT 0x0004 /* RX MID table hit (no error) */
161 #define DSC_RX_IDX_MID_MASK 3 /* RX mask for the index of matched MIDx */
162
163 MODULE_AUTHOR("Sten Wang <sten.wang@rdc.com.tw>,"
164 "Daniel Gimpelevich <daniel@gimpelevich.san-francisco.ca.us>,"
165 "Florian Fainelli <florian@openwrt.org>");
166 MODULE_LICENSE("GPL");
167 MODULE_DESCRIPTION("RDC R6040 NAPI PCI FastEthernet driver");
168 MODULE_VERSION(DRV_VERSION " " DRV_RELDATE);
169
170 /* RX and TX interrupts that we handle */
171 #define RX_INTS (RX_FIFO_FULL | RX_NO_DESC | RX_FINISH)
172 #define TX_INTS (TX_FINISH)
173 #define INT_MASK (RX_INTS | TX_INTS)
174
175 struct r6040_descriptor {
176 u16 status, len; /* 0-3 */
177 __le32 buf; /* 4-7 */
178 __le32 ndesc; /* 8-B */
179 u32 rev1; /* C-F */
180 char *vbufp; /* 10-13 */
181 struct r6040_descriptor *vndescp; /* 14-17 */
182 struct sk_buff *skb_ptr; /* 18-1B */
183 u32 rev2; /* 1C-1F */
184 } __aligned(32);
185
186 struct r6040_private {
187 spinlock_t lock; /* driver lock */
188 struct pci_dev *pdev;
189 struct r6040_descriptor *rx_insert_ptr;
190 struct r6040_descriptor *rx_remove_ptr;
191 struct r6040_descriptor *tx_insert_ptr;
192 struct r6040_descriptor *tx_remove_ptr;
193 struct r6040_descriptor *rx_ring;
194 struct r6040_descriptor *tx_ring;
195 dma_addr_t rx_ring_dma;
196 dma_addr_t tx_ring_dma;
197 u16 tx_free_desc;
198 u16 mcr0;
199 struct net_device *dev;
200 struct mii_bus *mii_bus;
201 struct napi_struct napi;
202 void __iomem *base;
203 struct phy_device *phydev;
204 int old_link;
205 int old_duplex;
206 };
207
208 static char version[] = DRV_NAME
209 ": RDC R6040 NAPI net driver,"
210 "version "DRV_VERSION " (" DRV_RELDATE ")";
211
212 /* Read a word data from PHY Chip */
213 static int r6040_phy_read(void __iomem *ioaddr, int phy_addr, int reg)
214 {
215 int limit = MAC_DEF_TIMEOUT;
216 u16 cmd;
217
218 iowrite16(MDIO_READ + reg + (phy_addr << 8), ioaddr + MMDIO);
219 /* Wait for the read bit to be cleared */
220 while (limit--) {
221 cmd = ioread16(ioaddr + MMDIO);
222 if (!(cmd & MDIO_READ))
223 break;
224 udelay(1);
225 }
226
227 if (limit < 0)
228 return -ETIMEDOUT;
229
230 return ioread16(ioaddr + MMRD);
231 }
232
233 /* Write a word data from PHY Chip */
234 static int r6040_phy_write(void __iomem *ioaddr,
235 int phy_addr, int reg, u16 val)
236 {
237 int limit = MAC_DEF_TIMEOUT;
238 u16 cmd;
239
240 iowrite16(val, ioaddr + MMWD);
241 /* Write the command to the MDIO bus */
242 iowrite16(MDIO_WRITE + reg + (phy_addr << 8), ioaddr + MMDIO);
243 /* Wait for the write bit to be cleared */
244 while (limit--) {
245 cmd = ioread16(ioaddr + MMDIO);
246 if (!(cmd & MDIO_WRITE))
247 break;
248 udelay(1);
249 }
250
251 return (limit < 0) ? -ETIMEDOUT : 0;
252 }
253
254 static int r6040_mdiobus_read(struct mii_bus *bus, int phy_addr, int reg)
255 {
256 struct net_device *dev = bus->priv;
257 struct r6040_private *lp = netdev_priv(dev);
258 void __iomem *ioaddr = lp->base;
259
260 return r6040_phy_read(ioaddr, phy_addr, reg);
261 }
262
263 static int r6040_mdiobus_write(struct mii_bus *bus, int phy_addr,
264 int reg, u16 value)
265 {
266 struct net_device *dev = bus->priv;
267 struct r6040_private *lp = netdev_priv(dev);
268 void __iomem *ioaddr = lp->base;
269
270 return r6040_phy_write(ioaddr, phy_addr, reg, value);
271 }
272
273 static int r6040_mdiobus_reset(struct mii_bus *bus)
274 {
275 return 0;
276 }
277
278 static void r6040_free_txbufs(struct net_device *dev)
279 {
280 struct r6040_private *lp = netdev_priv(dev);
281 int i;
282
283 for (i = 0; i < TX_DCNT; i++) {
284 if (lp->tx_insert_ptr->skb_ptr) {
285 pci_unmap_single(lp->pdev,
286 le32_to_cpu(lp->tx_insert_ptr->buf),
287 MAX_BUF_SIZE, PCI_DMA_TODEVICE);
288 dev_kfree_skb(lp->tx_insert_ptr->skb_ptr);
289 lp->tx_insert_ptr->skb_ptr = NULL;
290 }
291 lp->tx_insert_ptr = lp->tx_insert_ptr->vndescp;
292 }
293 }
294
295 static void r6040_free_rxbufs(struct net_device *dev)
296 {
297 struct r6040_private *lp = netdev_priv(dev);
298 int i;
299
300 for (i = 0; i < RX_DCNT; i++) {
301 if (lp->rx_insert_ptr->skb_ptr) {
302 pci_unmap_single(lp->pdev,
303 le32_to_cpu(lp->rx_insert_ptr->buf),
304 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
305 dev_kfree_skb(lp->rx_insert_ptr->skb_ptr);
306 lp->rx_insert_ptr->skb_ptr = NULL;
307 }
308 lp->rx_insert_ptr = lp->rx_insert_ptr->vndescp;
309 }
310 }
311
312 static void r6040_init_ring_desc(struct r6040_descriptor *desc_ring,
313 dma_addr_t desc_dma, int size)
314 {
315 struct r6040_descriptor *desc = desc_ring;
316 dma_addr_t mapping = desc_dma;
317
318 while (size-- > 0) {
319 mapping += sizeof(*desc);
320 desc->ndesc = cpu_to_le32(mapping);
321 desc->vndescp = desc + 1;
322 desc++;
323 }
324 desc--;
325 desc->ndesc = cpu_to_le32(desc_dma);
326 desc->vndescp = desc_ring;
327 }
328
329 static void r6040_init_txbufs(struct net_device *dev)
330 {
331 struct r6040_private *lp = netdev_priv(dev);
332
333 lp->tx_free_desc = TX_DCNT;
334
335 lp->tx_remove_ptr = lp->tx_insert_ptr = lp->tx_ring;
336 r6040_init_ring_desc(lp->tx_ring, lp->tx_ring_dma, TX_DCNT);
337 }
338
339 static int r6040_alloc_rxbufs(struct net_device *dev)
340 {
341 struct r6040_private *lp = netdev_priv(dev);
342 struct r6040_descriptor *desc;
343 struct sk_buff *skb;
344 int rc;
345
346 lp->rx_remove_ptr = lp->rx_insert_ptr = lp->rx_ring;
347 r6040_init_ring_desc(lp->rx_ring, lp->rx_ring_dma, RX_DCNT);
348
349 /* Allocate skbs for the rx descriptors */
350 desc = lp->rx_ring;
351 do {
352 skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
353 if (!skb) {
354 rc = -ENOMEM;
355 goto err_exit;
356 }
357 desc->skb_ptr = skb;
358 desc->buf = cpu_to_le32(pci_map_single(lp->pdev,
359 desc->skb_ptr->data,
360 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
361 desc->status = DSC_OWNER_MAC;
362 desc = desc->vndescp;
363 } while (desc != lp->rx_ring);
364
365 return 0;
366
367 err_exit:
368 /* Deallocate all previously allocated skbs */
369 r6040_free_rxbufs(dev);
370 return rc;
371 }
372
373 static void r6040_reset_mac(struct r6040_private *lp)
374 {
375 void __iomem *ioaddr = lp->base;
376 int limit = MAC_DEF_TIMEOUT;
377 u16 cmd;
378
379 iowrite16(MAC_RST, ioaddr + MCR1);
380 while (limit--) {
381 cmd = ioread16(ioaddr + MCR1);
382 if (cmd & MAC_RST)
383 break;
384 }
385
386 /* Reset internal state machine */
387 iowrite16(MAC_SM_RST, ioaddr + MAC_SM);
388 iowrite16(0, ioaddr + MAC_SM);
389 mdelay(5);
390 }
391
392 static void r6040_init_mac_regs(struct net_device *dev)
393 {
394 struct r6040_private *lp = netdev_priv(dev);
395 void __iomem *ioaddr = lp->base;
396
397 /* Mask Off Interrupt */
398 iowrite16(MSK_INT, ioaddr + MIER);
399
400 /* Reset RDC MAC */
401 r6040_reset_mac(lp);
402
403 /* MAC Bus Control Register */
404 iowrite16(MBCR_DEFAULT, ioaddr + MBCR);
405
406 /* Buffer Size Register */
407 iowrite16(MAX_BUF_SIZE, ioaddr + MR_BSR);
408
409 /* Write TX ring start address */
410 iowrite16(lp->tx_ring_dma, ioaddr + MTD_SA0);
411 iowrite16(lp->tx_ring_dma >> 16, ioaddr + MTD_SA1);
412
413 /* Write RX ring start address */
414 iowrite16(lp->rx_ring_dma, ioaddr + MRD_SA0);
415 iowrite16(lp->rx_ring_dma >> 16, ioaddr + MRD_SA1);
416
417 /* Set interrupt waiting time and packet numbers */
418 iowrite16(0, ioaddr + MT_ICR);
419 iowrite16(0, ioaddr + MR_ICR);
420
421 /* Enable interrupts */
422 iowrite16(INT_MASK, ioaddr + MIER);
423
424 /* Enable TX and RX */
425 iowrite16(lp->mcr0 | MCR0_RCVEN, ioaddr);
426
427 /* Let TX poll the descriptors
428 * we may got called by r6040_tx_timeout which has left
429 * some unsent tx buffers */
430 iowrite16(TM2TX, ioaddr + MTPR);
431 }
432
433 static void r6040_tx_timeout(struct net_device *dev)
434 {
435 struct r6040_private *priv = netdev_priv(dev);
436 void __iomem *ioaddr = priv->base;
437
438 netdev_warn(dev, "transmit timed out, int enable %4.4x "
439 "status %4.4x\n",
440 ioread16(ioaddr + MIER),
441 ioread16(ioaddr + MISR));
442
443 dev->stats.tx_errors++;
444
445 /* Reset MAC and re-init all registers */
446 r6040_init_mac_regs(dev);
447 }
448
449 static struct net_device_stats *r6040_get_stats(struct net_device *dev)
450 {
451 struct r6040_private *priv = netdev_priv(dev);
452 void __iomem *ioaddr = priv->base;
453 unsigned long flags;
454
455 spin_lock_irqsave(&priv->lock, flags);
456 dev->stats.rx_crc_errors += ioread8(ioaddr + ME_CNT1);
457 dev->stats.multicast += ioread8(ioaddr + ME_CNT0);
458 spin_unlock_irqrestore(&priv->lock, flags);
459
460 return &dev->stats;
461 }
462
463 /* Stop RDC MAC and Free the allocated resource */
464 static void r6040_down(struct net_device *dev)
465 {
466 struct r6040_private *lp = netdev_priv(dev);
467 void __iomem *ioaddr = lp->base;
468 u16 *adrp;
469
470 /* Stop MAC */
471 iowrite16(MSK_INT, ioaddr + MIER); /* Mask Off Interrupt */
472
473 /* Reset RDC MAC */
474 r6040_reset_mac(lp);
475
476 /* Restore MAC Address to MIDx */
477 adrp = (u16 *) dev->dev_addr;
478 iowrite16(adrp[0], ioaddr + MID_0L);
479 iowrite16(adrp[1], ioaddr + MID_0M);
480 iowrite16(adrp[2], ioaddr + MID_0H);
481
482 phy_stop(lp->phydev);
483 }
484
485 static int r6040_close(struct net_device *dev)
486 {
487 struct r6040_private *lp = netdev_priv(dev);
488 struct pci_dev *pdev = lp->pdev;
489
490 spin_lock_irq(&lp->lock);
491 napi_disable(&lp->napi);
492 netif_stop_queue(dev);
493 r6040_down(dev);
494
495 free_irq(dev->irq, dev);
496
497 /* Free RX buffer */
498 r6040_free_rxbufs(dev);
499
500 /* Free TX buffer */
501 r6040_free_txbufs(dev);
502
503 spin_unlock_irq(&lp->lock);
504
505 /* Free Descriptor memory */
506 if (lp->rx_ring) {
507 pci_free_consistent(pdev,
508 RX_DESC_SIZE, lp->rx_ring, lp->rx_ring_dma);
509 lp->rx_ring = NULL;
510 }
511
512 if (lp->tx_ring) {
513 pci_free_consistent(pdev,
514 TX_DESC_SIZE, lp->tx_ring, lp->tx_ring_dma);
515 lp->tx_ring = NULL;
516 }
517
518 return 0;
519 }
520
521 static int r6040_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
522 {
523 struct r6040_private *lp = netdev_priv(dev);
524
525 if (!lp->phydev)
526 return -EINVAL;
527
528 return phy_mii_ioctl(lp->phydev, rq, cmd);
529 }
530
531 static int r6040_rx(struct net_device *dev, int limit)
532 {
533 struct r6040_private *priv = netdev_priv(dev);
534 struct r6040_descriptor *descptr = priv->rx_remove_ptr;
535 struct sk_buff *skb_ptr, *new_skb;
536 int count = 0;
537 u16 err;
538
539 /* Limit not reached and the descriptor belongs to the CPU */
540 while (count < limit && !(descptr->status & DSC_OWNER_MAC)) {
541 /* Read the descriptor status */
542 err = descptr->status;
543 /* Global error status set */
544 if (err & DSC_RX_ERR) {
545 /* RX dribble */
546 if (err & DSC_RX_ERR_DRI)
547 dev->stats.rx_frame_errors++;
548 /* Buffer length exceeded */
549 if (err & DSC_RX_ERR_BUF)
550 dev->stats.rx_length_errors++;
551 /* Packet too long */
552 if (err & DSC_RX_ERR_LONG)
553 dev->stats.rx_length_errors++;
554 /* Packet < 64 bytes */
555 if (err & DSC_RX_ERR_RUNT)
556 dev->stats.rx_length_errors++;
557 /* CRC error */
558 if (err & DSC_RX_ERR_CRC) {
559 spin_lock(&priv->lock);
560 dev->stats.rx_crc_errors++;
561 spin_unlock(&priv->lock);
562 }
563 goto next_descr;
564 }
565
566 /* Packet successfully received */
567 new_skb = netdev_alloc_skb(dev, MAX_BUF_SIZE);
568 if (!new_skb) {
569 dev->stats.rx_dropped++;
570 goto next_descr;
571 }
572 skb_ptr = descptr->skb_ptr;
573 skb_ptr->dev = priv->dev;
574
575 /* Do not count the CRC */
576 skb_put(skb_ptr, descptr->len - 4);
577 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
578 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE);
579 skb_ptr->protocol = eth_type_trans(skb_ptr, priv->dev);
580
581 /* Send to upper layer */
582 netif_receive_skb(skb_ptr);
583 dev->stats.rx_packets++;
584 dev->stats.rx_bytes += descptr->len - 4;
585
586 /* put new skb into descriptor */
587 descptr->skb_ptr = new_skb;
588 descptr->buf = cpu_to_le32(pci_map_single(priv->pdev,
589 descptr->skb_ptr->data,
590 MAX_BUF_SIZE, PCI_DMA_FROMDEVICE));
591
592 next_descr:
593 /* put the descriptor back to the MAC */
594 descptr->status = DSC_OWNER_MAC;
595 descptr = descptr->vndescp;
596 count++;
597 }
598 priv->rx_remove_ptr = descptr;
599
600 return count;
601 }
602
603 static void r6040_tx(struct net_device *dev)
604 {
605 struct r6040_private *priv = netdev_priv(dev);
606 struct r6040_descriptor *descptr;
607 void __iomem *ioaddr = priv->base;
608 struct sk_buff *skb_ptr;
609 u16 err;
610
611 spin_lock(&priv->lock);
612 descptr = priv->tx_remove_ptr;
613 while (priv->tx_free_desc < TX_DCNT) {
614 /* Check for errors */
615 err = ioread16(ioaddr + MLSR);
616
617 if (err & TX_FIFO_UNDR)
618 dev->stats.tx_fifo_errors++;
619 if (err & (TX_EXCEEDC | TX_LATEC))
620 dev->stats.tx_carrier_errors++;
621
622 if (descptr->status & DSC_OWNER_MAC)
623 break; /* Not complete */
624 skb_ptr = descptr->skb_ptr;
625 pci_unmap_single(priv->pdev, le32_to_cpu(descptr->buf),
626 skb_ptr->len, PCI_DMA_TODEVICE);
627 /* Free buffer */
628 dev_kfree_skb_irq(skb_ptr);
629 descptr->skb_ptr = NULL;
630 /* To next descriptor */
631 descptr = descptr->vndescp;
632 priv->tx_free_desc++;
633 }
634 priv->tx_remove_ptr = descptr;
635
636 if (priv->tx_free_desc)
637 netif_wake_queue(dev);
638 spin_unlock(&priv->lock);
639 }
640
641 static int r6040_poll(struct napi_struct *napi, int budget)
642 {
643 struct r6040_private *priv =
644 container_of(napi, struct r6040_private, napi);
645 struct net_device *dev = priv->dev;
646 void __iomem *ioaddr = priv->base;
647 int work_done;
648
649 work_done = r6040_rx(dev, budget);
650
651 if (work_done < budget) {
652 napi_complete(napi);
653 /* Enable RX interrupt */
654 iowrite16(ioread16(ioaddr + MIER) | RX_INTS, ioaddr + MIER);
655 }
656 return work_done;
657 }
658
659 /* The RDC interrupt handler. */
660 static irqreturn_t r6040_interrupt(int irq, void *dev_id)
661 {
662 struct net_device *dev = dev_id;
663 struct r6040_private *lp = netdev_priv(dev);
664 void __iomem *ioaddr = lp->base;
665 u16 misr, status;
666
667 /* Save MIER */
668 misr = ioread16(ioaddr + MIER);
669 /* Mask off RDC MAC interrupt */
670 iowrite16(MSK_INT, ioaddr + MIER);
671 /* Read MISR status and clear */
672 status = ioread16(ioaddr + MISR);
673
674 if (status == 0x0000 || status == 0xffff) {
675 /* Restore RDC MAC interrupt */
676 iowrite16(misr, ioaddr + MIER);
677 return IRQ_NONE;
678 }
679
680 /* RX interrupt request */
681 if (status & RX_INTS) {
682 if (status & RX_NO_DESC) {
683 /* RX descriptor unavailable */
684 dev->stats.rx_dropped++;
685 dev->stats.rx_missed_errors++;
686 }
687 if (status & RX_FIFO_FULL)
688 dev->stats.rx_fifo_errors++;
689
690 if (likely(napi_schedule_prep(&lp->napi))) {
691 /* Mask off RX interrupt */
692 misr &= ~RX_INTS;
693 __napi_schedule(&lp->napi);
694 }
695 }
696
697 /* TX interrupt request */
698 if (status & TX_INTS)
699 r6040_tx(dev);
700
701 /* Restore RDC MAC interrupt */
702 iowrite16(misr, ioaddr + MIER);
703
704 return IRQ_HANDLED;
705 }
706
707 #ifdef CONFIG_NET_POLL_CONTROLLER
708 static void r6040_poll_controller(struct net_device *dev)
709 {
710 disable_irq(dev->irq);
711 r6040_interrupt(dev->irq, dev);
712 enable_irq(dev->irq);
713 }
714 #endif
715
716 /* Init RDC MAC */
717 static int r6040_up(struct net_device *dev)
718 {
719 struct r6040_private *lp = netdev_priv(dev);
720 void __iomem *ioaddr = lp->base;
721 int ret;
722
723 /* Initialise and alloc RX/TX buffers */
724 r6040_init_txbufs(dev);
725 ret = r6040_alloc_rxbufs(dev);
726 if (ret)
727 return ret;
728
729 /* improve performance (by RDC guys) */
730 r6040_phy_write(ioaddr, 30, 17,
731 (r6040_phy_read(ioaddr, 30, 17) | 0x4000));
732 r6040_phy_write(ioaddr, 30, 17,
733 ~((~r6040_phy_read(ioaddr, 30, 17)) | 0x2000));
734 r6040_phy_write(ioaddr, 0, 19, 0x0000);
735 r6040_phy_write(ioaddr, 0, 30, 0x01F0);
736
737 /* Initialize all MAC registers */
738 r6040_init_mac_regs(dev);
739
740 phy_start(lp->phydev);
741
742 return 0;
743 }
744
745
746 /* Read/set MAC address routines */
747 static void r6040_mac_address(struct net_device *dev)
748 {
749 struct r6040_private *lp = netdev_priv(dev);
750 void __iomem *ioaddr = lp->base;
751 u16 *adrp;
752
753 /* Reset MAC */
754 r6040_reset_mac(lp);
755
756 /* Restore MAC Address */
757 adrp = (u16 *) dev->dev_addr;
758 iowrite16(adrp[0], ioaddr + MID_0L);
759 iowrite16(adrp[1], ioaddr + MID_0M);
760 iowrite16(adrp[2], ioaddr + MID_0H);
761 }
762
763 static int r6040_open(struct net_device *dev)
764 {
765 struct r6040_private *lp = netdev_priv(dev);
766 int ret;
767
768 /* Request IRQ and Register interrupt handler */
769 ret = request_irq(dev->irq, r6040_interrupt,
770 IRQF_SHARED, dev->name, dev);
771 if (ret)
772 goto out;
773
774 /* Set MAC address */
775 r6040_mac_address(dev);
776
777 /* Allocate Descriptor memory */
778 lp->rx_ring =
779 pci_alloc_consistent(lp->pdev, RX_DESC_SIZE, &lp->rx_ring_dma);
780 if (!lp->rx_ring) {
781 ret = -ENOMEM;
782 goto err_free_irq;
783 }
784
785 lp->tx_ring =
786 pci_alloc_consistent(lp->pdev, TX_DESC_SIZE, &lp->tx_ring_dma);
787 if (!lp->tx_ring) {
788 ret = -ENOMEM;
789 goto err_free_rx_ring;
790 }
791
792 ret = r6040_up(dev);
793 if (ret)
794 goto err_free_tx_ring;
795
796 napi_enable(&lp->napi);
797 netif_start_queue(dev);
798
799 return 0;
800
801 err_free_tx_ring:
802 pci_free_consistent(lp->pdev, TX_DESC_SIZE, lp->tx_ring,
803 lp->tx_ring_dma);
804 err_free_rx_ring:
805 pci_free_consistent(lp->pdev, RX_DESC_SIZE, lp->rx_ring,
806 lp->rx_ring_dma);
807 err_free_irq:
808 free_irq(dev->irq, dev);
809 out:
810 return ret;
811 }
812
813 static netdev_tx_t r6040_start_xmit(struct sk_buff *skb,
814 struct net_device *dev)
815 {
816 struct r6040_private *lp = netdev_priv(dev);
817 struct r6040_descriptor *descptr;
818 void __iomem *ioaddr = lp->base;
819 unsigned long flags;
820
821 /* Critical Section */
822 spin_lock_irqsave(&lp->lock, flags);
823
824 /* TX resource check */
825 if (!lp->tx_free_desc) {
826 spin_unlock_irqrestore(&lp->lock, flags);
827 netif_stop_queue(dev);
828 netdev_err(dev, ": no tx descriptor\n");
829 return NETDEV_TX_BUSY;
830 }
831
832 /* Statistic Counter */
833 dev->stats.tx_packets++;
834 dev->stats.tx_bytes += skb->len;
835 /* Set TX descriptor & Transmit it */
836 lp->tx_free_desc--;
837 descptr = lp->tx_insert_ptr;
838 if (skb->len < ETH_ZLEN)
839 descptr->len = ETH_ZLEN;
840 else
841 descptr->len = skb->len;
842
843 descptr->skb_ptr = skb;
844 descptr->buf = cpu_to_le32(pci_map_single(lp->pdev,
845 skb->data, skb->len, PCI_DMA_TODEVICE));
846 descptr->status = DSC_OWNER_MAC;
847
848 skb_tx_timestamp(skb);
849
850 /* Trigger the MAC to check the TX descriptor */
851 iowrite16(TM2TX, ioaddr + MTPR);
852 lp->tx_insert_ptr = descptr->vndescp;
853
854 /* If no tx resource, stop */
855 if (!lp->tx_free_desc)
856 netif_stop_queue(dev);
857
858 spin_unlock_irqrestore(&lp->lock, flags);
859
860 return NETDEV_TX_OK;
861 }
862
863 static void r6040_multicast_list(struct net_device *dev)
864 {
865 struct r6040_private *lp = netdev_priv(dev);
866 void __iomem *ioaddr = lp->base;
867 unsigned long flags;
868 struct netdev_hw_addr *ha;
869 int i;
870 u16 *adrp;
871 u16 hash_table[4] = { 0 };
872
873 spin_lock_irqsave(&lp->lock, flags);
874
875 /* Keep our MAC Address */
876 adrp = (u16 *)dev->dev_addr;
877 iowrite16(adrp[0], ioaddr + MID_0L);
878 iowrite16(adrp[1], ioaddr + MID_0M);
879 iowrite16(adrp[2], ioaddr + MID_0H);
880
881 /* Clear AMCP & PROM bits */
882 lp->mcr0 = ioread16(ioaddr + MCR0) & ~(MCR0_PROMISC | MCR0_HASH_EN);
883
884 /* Promiscuous mode */
885 if (dev->flags & IFF_PROMISC)
886 lp->mcr0 |= MCR0_PROMISC;
887
888 /* Enable multicast hash table function to
889 * receive all multicast packets. */
890 else if (dev->flags & IFF_ALLMULTI) {
891 lp->mcr0 |= MCR0_HASH_EN;
892
893 for (i = 0; i < MCAST_MAX ; i++) {
894 iowrite16(0, ioaddr + MID_1L + 8 * i);
895 iowrite16(0, ioaddr + MID_1M + 8 * i);
896 iowrite16(0, ioaddr + MID_1H + 8 * i);
897 }
898
899 for (i = 0; i < 4; i++)
900 hash_table[i] = 0xffff;
901 }
902 /* Use internal multicast address registers if the number of
903 * multicast addresses is not greater than MCAST_MAX. */
904 else if (netdev_mc_count(dev) <= MCAST_MAX) {
905 i = 0;
906 netdev_for_each_mc_addr(ha, dev) {
907 u16 *adrp = (u16 *) ha->addr;
908 iowrite16(adrp[0], ioaddr + MID_1L + 8 * i);
909 iowrite16(adrp[1], ioaddr + MID_1M + 8 * i);
910 iowrite16(adrp[2], ioaddr + MID_1H + 8 * i);
911 i++;
912 }
913 while (i < MCAST_MAX) {
914 iowrite16(0, ioaddr + MID_1L + 8 * i);
915 iowrite16(0, ioaddr + MID_1M + 8 * i);
916 iowrite16(0, ioaddr + MID_1H + 8 * i);
917 i++;
918 }
919 }
920 /* Otherwise, Enable multicast hash table function. */
921 else {
922 u32 crc;
923
924 lp->mcr0 |= MCR0_HASH_EN;
925
926 for (i = 0; i < MCAST_MAX ; i++) {
927 iowrite16(0, ioaddr + MID_1L + 8 * i);
928 iowrite16(0, ioaddr + MID_1M + 8 * i);
929 iowrite16(0, ioaddr + MID_1H + 8 * i);
930 }
931
932 /* Build multicast hash table */
933 netdev_for_each_mc_addr(ha, dev) {
934 u8 *addrs = ha->addr;
935
936 crc = ether_crc(ETH_ALEN, addrs);
937 crc >>= 26;
938 hash_table[crc >> 4] |= 1 << (crc & 0xf);
939 }
940 }
941
942 iowrite16(lp->mcr0, ioaddr + MCR0);
943
944 /* Fill the MAC hash tables with their values */
945 if (lp->mcr0 & MCR0_HASH_EN) {
946 iowrite16(hash_table[0], ioaddr + MAR0);
947 iowrite16(hash_table[1], ioaddr + MAR1);
948 iowrite16(hash_table[2], ioaddr + MAR2);
949 iowrite16(hash_table[3], ioaddr + MAR3);
950 }
951
952 spin_unlock_irqrestore(&lp->lock, flags);
953 }
954
955 static void netdev_get_drvinfo(struct net_device *dev,
956 struct ethtool_drvinfo *info)
957 {
958 struct r6040_private *rp = netdev_priv(dev);
959
960 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
961 strlcpy(info->version, DRV_VERSION, sizeof(info->version));
962 strlcpy(info->bus_info, pci_name(rp->pdev), sizeof(info->bus_info));
963 }
964
965 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
966 {
967 struct r6040_private *rp = netdev_priv(dev);
968
969 return phy_ethtool_gset(rp->phydev, cmd);
970 }
971
972 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
973 {
974 struct r6040_private *rp = netdev_priv(dev);
975
976 return phy_ethtool_sset(rp->phydev, cmd);
977 }
978
979 static const struct ethtool_ops netdev_ethtool_ops = {
980 .get_drvinfo = netdev_get_drvinfo,
981 .get_settings = netdev_get_settings,
982 .set_settings = netdev_set_settings,
983 .get_link = ethtool_op_get_link,
984 .get_ts_info = ethtool_op_get_ts_info,
985 };
986
987 static const struct net_device_ops r6040_netdev_ops = {
988 .ndo_open = r6040_open,
989 .ndo_stop = r6040_close,
990 .ndo_start_xmit = r6040_start_xmit,
991 .ndo_get_stats = r6040_get_stats,
992 .ndo_set_rx_mode = r6040_multicast_list,
993 .ndo_change_mtu = eth_change_mtu,
994 .ndo_validate_addr = eth_validate_addr,
995 .ndo_set_mac_address = eth_mac_addr,
996 .ndo_do_ioctl = r6040_ioctl,
997 .ndo_tx_timeout = r6040_tx_timeout,
998 #ifdef CONFIG_NET_POLL_CONTROLLER
999 .ndo_poll_controller = r6040_poll_controller,
1000 #endif
1001 };
1002
1003 static void r6040_adjust_link(struct net_device *dev)
1004 {
1005 struct r6040_private *lp = netdev_priv(dev);
1006 struct phy_device *phydev = lp->phydev;
1007 int status_changed = 0;
1008 void __iomem *ioaddr = lp->base;
1009
1010 BUG_ON(!phydev);
1011
1012 if (lp->old_link != phydev->link) {
1013 status_changed = 1;
1014 lp->old_link = phydev->link;
1015 }
1016
1017 /* reflect duplex change */
1018 if (phydev->link && (lp->old_duplex != phydev->duplex)) {
1019 lp->mcr0 |= (phydev->duplex == DUPLEX_FULL ? MCR0_FD : 0);
1020 iowrite16(lp->mcr0, ioaddr);
1021
1022 status_changed = 1;
1023 lp->old_duplex = phydev->duplex;
1024 }
1025
1026 if (status_changed) {
1027 pr_info("%s: link %s", dev->name, phydev->link ?
1028 "UP" : "DOWN");
1029 if (phydev->link)
1030 pr_cont(" - %d/%s", phydev->speed,
1031 DUPLEX_FULL == phydev->duplex ? "full" : "half");
1032 pr_cont("\n");
1033 }
1034 }
1035
1036 static int r6040_mii_probe(struct net_device *dev)
1037 {
1038 struct r6040_private *lp = netdev_priv(dev);
1039 struct phy_device *phydev = NULL;
1040
1041 phydev = phy_find_first(lp->mii_bus);
1042 if (!phydev) {
1043 dev_err(&lp->pdev->dev, "no PHY found\n");
1044 return -ENODEV;
1045 }
1046
1047 phydev = phy_connect(dev, dev_name(&phydev->dev), &r6040_adjust_link,
1048 PHY_INTERFACE_MODE_MII);
1049
1050 if (IS_ERR(phydev)) {
1051 dev_err(&lp->pdev->dev, "could not attach to PHY\n");
1052 return PTR_ERR(phydev);
1053 }
1054
1055 /* mask with MAC supported features */
1056 phydev->supported &= (SUPPORTED_10baseT_Half
1057 | SUPPORTED_10baseT_Full
1058 | SUPPORTED_100baseT_Half
1059 | SUPPORTED_100baseT_Full
1060 | SUPPORTED_Autoneg
1061 | SUPPORTED_MII
1062 | SUPPORTED_TP);
1063
1064 phydev->advertising = phydev->supported;
1065 lp->phydev = phydev;
1066 lp->old_link = 0;
1067 lp->old_duplex = -1;
1068
1069 dev_info(&lp->pdev->dev, "attached PHY driver [%s] "
1070 "(mii_bus:phy_addr=%s)\n",
1071 phydev->drv->name, dev_name(&phydev->dev));
1072
1073 return 0;
1074 }
1075
1076 static int r6040_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1077 {
1078 struct net_device *dev;
1079 struct r6040_private *lp;
1080 void __iomem *ioaddr;
1081 int err, io_size = R6040_IO_SIZE;
1082 static int card_idx = -1;
1083 int bar = 0;
1084 u16 *adrp;
1085 int i;
1086
1087 pr_info("%s\n", version);
1088
1089 err = pci_enable_device(pdev);
1090 if (err)
1091 goto err_out;
1092
1093 /* this should always be supported */
1094 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1095 if (err) {
1096 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1097 "not supported by the card\n");
1098 goto err_out_disable_dev;
1099 }
1100 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1101 if (err) {
1102 dev_err(&pdev->dev, "32-bit PCI DMA addresses"
1103 "not supported by the card\n");
1104 goto err_out_disable_dev;
1105 }
1106
1107 /* IO Size check */
1108 if (pci_resource_len(pdev, bar) < io_size) {
1109 dev_err(&pdev->dev, "Insufficient PCI resources, aborting\n");
1110 err = -EIO;
1111 goto err_out_disable_dev;
1112 }
1113
1114 pci_set_master(pdev);
1115
1116 dev = alloc_etherdev(sizeof(struct r6040_private));
1117 if (!dev) {
1118 err = -ENOMEM;
1119 goto err_out_disable_dev;
1120 }
1121 SET_NETDEV_DEV(dev, &pdev->dev);
1122 lp = netdev_priv(dev);
1123
1124 err = pci_request_regions(pdev, DRV_NAME);
1125
1126 if (err) {
1127 dev_err(&pdev->dev, "Failed to request PCI regions\n");
1128 goto err_out_free_dev;
1129 }
1130
1131 ioaddr = pci_iomap(pdev, bar, io_size);
1132 if (!ioaddr) {
1133 dev_err(&pdev->dev, "ioremap failed for device\n");
1134 err = -EIO;
1135 goto err_out_free_res;
1136 }
1137
1138 /* If PHY status change register is still set to zero it means the
1139 * bootloader didn't initialize it, so we set it to:
1140 * - enable phy status change
1141 * - enable all phy addresses
1142 * - set to lowest timer divider */
1143 if (ioread16(ioaddr + PHY_CC) == 0)
1144 iowrite16(SCEN | PHY_MAX_ADDR << PHYAD_SHIFT |
1145 7 << TMRDIV_SHIFT, ioaddr + PHY_CC);
1146
1147 /* Init system & device */
1148 lp->base = ioaddr;
1149 dev->irq = pdev->irq;
1150
1151 spin_lock_init(&lp->lock);
1152 pci_set_drvdata(pdev, dev);
1153
1154 /* Set MAC address */
1155 card_idx++;
1156
1157 adrp = (u16 *)dev->dev_addr;
1158 adrp[0] = ioread16(ioaddr + MID_0L);
1159 adrp[1] = ioread16(ioaddr + MID_0M);
1160 adrp[2] = ioread16(ioaddr + MID_0H);
1161
1162 /* Some bootloader/BIOSes do not initialize
1163 * MAC address, warn about that */
1164 if (!(adrp[0] || adrp[1] || adrp[2])) {
1165 netdev_warn(dev, "MAC address not initialized, "
1166 "generating random\n");
1167 eth_hw_addr_random(dev);
1168 }
1169
1170 /* Link new device into r6040_root_dev */
1171 lp->pdev = pdev;
1172 lp->dev = dev;
1173
1174 /* Init RDC private data */
1175 lp->mcr0 = MCR0_XMTEN | MCR0_RCVEN;
1176
1177 /* The RDC-specific entries in the device structure. */
1178 dev->netdev_ops = &r6040_netdev_ops;
1179 dev->ethtool_ops = &netdev_ethtool_ops;
1180 dev->watchdog_timeo = TX_TIMEOUT;
1181
1182 netif_napi_add(dev, &lp->napi, r6040_poll, 64);
1183
1184 lp->mii_bus = mdiobus_alloc();
1185 if (!lp->mii_bus) {
1186 dev_err(&pdev->dev, "mdiobus_alloc() failed\n");
1187 err = -ENOMEM;
1188 goto err_out_unmap;
1189 }
1190
1191 lp->mii_bus->priv = dev;
1192 lp->mii_bus->read = r6040_mdiobus_read;
1193 lp->mii_bus->write = r6040_mdiobus_write;
1194 lp->mii_bus->reset = r6040_mdiobus_reset;
1195 lp->mii_bus->name = "r6040_eth_mii";
1196 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1197 dev_name(&pdev->dev), card_idx);
1198 lp->mii_bus->irq = kmalloc_array(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
1199 if (!lp->mii_bus->irq) {
1200 err = -ENOMEM;
1201 goto err_out_mdio;
1202 }
1203
1204 for (i = 0; i < PHY_MAX_ADDR; i++)
1205 lp->mii_bus->irq[i] = PHY_POLL;
1206
1207 err = mdiobus_register(lp->mii_bus);
1208 if (err) {
1209 dev_err(&pdev->dev, "failed to register MII bus\n");
1210 goto err_out_mdio_irq;
1211 }
1212
1213 err = r6040_mii_probe(dev);
1214 if (err) {
1215 dev_err(&pdev->dev, "failed to probe MII bus\n");
1216 goto err_out_mdio_unregister;
1217 }
1218
1219 /* Register net device. After this dev->name assign */
1220 err = register_netdev(dev);
1221 if (err) {
1222 dev_err(&pdev->dev, "Failed to register net device\n");
1223 goto err_out_mdio_unregister;
1224 }
1225 return 0;
1226
1227 err_out_mdio_unregister:
1228 mdiobus_unregister(lp->mii_bus);
1229 err_out_mdio_irq:
1230 kfree(lp->mii_bus->irq);
1231 err_out_mdio:
1232 mdiobus_free(lp->mii_bus);
1233 err_out_unmap:
1234 netif_napi_del(&lp->napi);
1235 pci_iounmap(pdev, ioaddr);
1236 err_out_free_res:
1237 pci_release_regions(pdev);
1238 err_out_free_dev:
1239 free_netdev(dev);
1240 err_out_disable_dev:
1241 pci_disable_device(pdev);
1242 err_out:
1243 return err;
1244 }
1245
1246 static void r6040_remove_one(struct pci_dev *pdev)
1247 {
1248 struct net_device *dev = pci_get_drvdata(pdev);
1249 struct r6040_private *lp = netdev_priv(dev);
1250
1251 unregister_netdev(dev);
1252 mdiobus_unregister(lp->mii_bus);
1253 kfree(lp->mii_bus->irq);
1254 mdiobus_free(lp->mii_bus);
1255 netif_napi_del(&lp->napi);
1256 pci_iounmap(pdev, lp->base);
1257 pci_release_regions(pdev);
1258 free_netdev(dev);
1259 pci_disable_device(pdev);
1260 }
1261
1262
1263 static DEFINE_PCI_DEVICE_TABLE(r6040_pci_tbl) = {
1264 { PCI_DEVICE(PCI_VENDOR_ID_RDC, 0x6040) },
1265 { 0 }
1266 };
1267 MODULE_DEVICE_TABLE(pci, r6040_pci_tbl);
1268
1269 static struct pci_driver r6040_driver = {
1270 .name = DRV_NAME,
1271 .id_table = r6040_pci_tbl,
1272 .probe = r6040_init_one,
1273 .remove = r6040_remove_one,
1274 };
1275
1276 module_pci_driver(r6040_driver);
Linux with added FPC-III support