drivers/net/ethernet/renesas/sh_eth.h

   1 /*  SuperH Ethernet device driver
   2  *
   3  *  Copyright (C) 2006-2012 Nobuhiro Iwamatsu
   4  *  Copyright (C) 2008-2012 Renesas Solutions Corp.
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms and conditions of the GNU General Public License,
   8  *  version 2, as published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  *  more details.
  14  *
  15  *  The full GNU General Public License is included in this distribution in
  16  *  the file called "COPYING".
  17  */
  18
  19 #ifndef __SH_ETH_H__
  20 #define __SH_ETH_H__
  21
  22 #define CARDNAME        "sh-eth"
  23 #define TX_TIMEOUT      (5*HZ)
  24 #define TX_RING_SIZE    64      /* Tx ring size */
  25 #define RX_RING_SIZE    64      /* Rx ring size */
  26 #define TX_RING_MIN     64
  27 #define RX_RING_MIN     64
  28 #define TX_RING_MAX     1024
  29 #define RX_RING_MAX     1024
  30 #define ETHERSMALL              60
  31 #define PKT_BUF_SZ              1538
  32 #define SH_ETH_TSU_TIMEOUT_MS   500
  33 #define SH_ETH_TSU_CAM_ENTRIES  32
  34
  35 enum {
  36         /* E-DMAC registers */
  37         EDSR = 0,
  38         EDMR,
  39         EDTRR,
  40         EDRRR,
  41         EESR,
  42         EESIPR,
  43         TDLAR,
  44         TDFAR,
  45         TDFXR,
  46         TDFFR,
  47         RDLAR,
  48         RDFAR,
  49         RDFXR,
  50         RDFFR,
  51         TRSCER,
  52         RMFCR,
  53         TFTR,
  54         FDR,
  55         RMCR,
  56         EDOCR,
  57         TFUCR,
  58         RFOCR,
  59         RMIIMODE,
  60         FCFTR,
  61         RPADIR,
  62         TRIMD,
  63         RBWAR,
  64         TBRAR,
  65
  66         /* Ether registers */
  67         ECMR,
  68         ECSR,
  69         ECSIPR,
  70         PIR,
  71         PSR,
  72         RDMLR,
  73         PIPR,
  74         RFLR,
  75         IPGR,
  76         APR,
  77         MPR,
  78         PFTCR,
  79         PFRCR,
  80         RFCR,
  81         RFCF,
  82         TPAUSER,
  83         TPAUSECR,
  84         BCFR,
  85         BCFRR,
  86         GECMR,
  87         BCULR,
  88         MAHR,
  89         MALR,
  90         TROCR,
  91         CDCR,
  92         LCCR,
  93         CNDCR,
  94         CEFCR,
  95         FRECR,
  96         TSFRCR,
  97         TLFRCR,
  98         CERCR,
  99         CEECR,
 100         MAFCR,
 101         RTRATE,
 102         CSMR,
 103         RMII_MII,
 104
 105         /* TSU Absolute address */
 106         ARSTR,
 107         TSU_CTRST,
 108         TSU_FWEN0,
 109         TSU_FWEN1,
 110         TSU_FCM,
 111         TSU_BSYSL0,
 112         TSU_BSYSL1,
 113         TSU_PRISL0,
 114         TSU_PRISL1,
 115         TSU_FWSL0,
 116         TSU_FWSL1,
 117         TSU_FWSLC,
 118         TSU_QTAG0,
 119         TSU_QTAG1,
 120         TSU_QTAGM0,
 121         TSU_QTAGM1,
 122         TSU_FWSR,
 123         TSU_FWINMK,
 124         TSU_ADQT0,
 125         TSU_ADQT1,
 126         TSU_VTAG0,
 127         TSU_VTAG1,
 128         TSU_ADSBSY,
 129         TSU_TEN,
 130         TSU_POST1,
 131         TSU_POST2,
 132         TSU_POST3,
 133         TSU_POST4,
 134         TSU_ADRH0,
 135         TSU_ADRL0,
 136         TSU_ADRH31,
 137         TSU_ADRL31,
 138
 139         TXNLCR0,
 140         TXALCR0,
 141         RXNLCR0,
 142         RXALCR0,
 143         FWNLCR0,
 144         FWALCR0,
 145         TXNLCR1,
 146         TXALCR1,
 147         RXNLCR1,
 148         RXALCR1,
 149         FWNLCR1,
 150         FWALCR1,
 151
 152         /* This value must be written at last. */
 153         SH_ETH_MAX_REGISTER_OFFSET,
 154 };
 155
 156 enum {
 157         SH_ETH_REG_GIGABIT,
 158         SH_ETH_REG_FAST_RZ,
 159         SH_ETH_REG_FAST_RCAR,
 160         SH_ETH_REG_FAST_SH4,
 161         SH_ETH_REG_FAST_SH3_SH2
 162 };
 163
 164 /* Driver's parameters */
 165 #if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
 166 #define SH4_SKB_RX_ALIGN        32
 167 #else
 168 #define SH2_SH3_SKB_RX_ALIGN    2
 169 #endif
 170
 171 /* Register's bits
 172  */
 173 /* EDSR : sh7734, sh7757, sh7763, r8a7740, and r7s72100 only */
 174 enum EDSR_BIT {
 175         EDSR_ENT = 0x01, EDSR_ENR = 0x02,
 176 };
 177 #define EDSR_ENALL (EDSR_ENT|EDSR_ENR)
 178
 179 /* GECMR : sh7734, sh7763 and r8a7740 only */
 180 enum GECMR_BIT {
 181         GECMR_10 = 0x0, GECMR_100 = 0x04, GECMR_1000 = 0x01,
 182 };
 183
 184 /* EDMR */
 185 enum DMAC_M_BIT {
 186         EDMR_EL = 0x40, /* Litte endian */
 187         EDMR_DL1 = 0x20, EDMR_DL0 = 0x10,
 188         EDMR_SRST_GETHER = 0x03,
 189         EDMR_SRST_ETHER = 0x01,
 190 };
 191
 192 /* EDTRR */
 193 enum DMAC_T_BIT {
 194         EDTRR_TRNS_GETHER = 0x03,
 195         EDTRR_TRNS_ETHER = 0x01,
 196 };
 197
 198 /* EDRRR */
 199 enum EDRRR_R_BIT {
 200         EDRRR_R = 0x01,
 201 };
 202
 203 /* TPAUSER */
 204 enum TPAUSER_BIT {
 205         TPAUSER_TPAUSE = 0x0000ffff,
 206         TPAUSER_UNLIMITED = 0,
 207 };
 208
 209 /* BCFR */
 210 enum BCFR_BIT {
 211         BCFR_RPAUSE = 0x0000ffff,
 212         BCFR_UNLIMITED = 0,
 213 };
 214
 215 /* PIR */
 216 enum PIR_BIT {
 217         PIR_MDI = 0x08, PIR_MDO = 0x04, PIR_MMD = 0x02, PIR_MDC = 0x01,
 218 };
 219
 220 /* PSR */
 221 enum PHY_STATUS_BIT { PHY_ST_LINK = 0x01, };
 222
 223 /* EESR */
 224 enum EESR_BIT {
 225         EESR_TWB1       = 0x80000000,
 226         EESR_TWB        = 0x40000000,   /* same as TWB0 */
 227         EESR_TC1        = 0x20000000,
 228         EESR_TUC        = 0x10000000,
 229         EESR_ROC        = 0x08000000,
 230         EESR_TABT       = 0x04000000,
 231         EESR_RABT       = 0x02000000,
 232         EESR_RFRMER     = 0x01000000,   /* same as RFCOF */
 233         EESR_ADE        = 0x00800000,
 234         EESR_ECI        = 0x00400000,
 235         EESR_FTC        = 0x00200000,   /* same as TC or TC0 */
 236         EESR_TDE        = 0x00100000,
 237         EESR_TFE        = 0x00080000,   /* same as TFUF */
 238         EESR_FRC        = 0x00040000,   /* same as FR */
 239         EESR_RDE        = 0x00020000,
 240         EESR_RFE        = 0x00010000,
 241         EESR_CND        = 0x00000800,
 242         EESR_DLC        = 0x00000400,
 243         EESR_CD         = 0x00000200,
 244         EESR_RTO        = 0x00000100,
 245         EESR_RMAF       = 0x00000080,
 246         EESR_CEEF       = 0x00000040,
 247         EESR_CELF       = 0x00000020,
 248         EESR_RRF        = 0x00000010,
 249         EESR_RTLF       = 0x00000008,
 250         EESR_RTSF       = 0x00000004,
 251         EESR_PRE        = 0x00000002,
 252         EESR_CERF       = 0x00000001,
 253 };
 254
 255 #define EESR_RX_CHECK           (EESR_FRC  | /* Frame recv */           \
 256                                  EESR_RMAF | /* Multicast address recv */ \
 257                                  EESR_RRF  | /* Bit frame recv */       \
 258                                  EESR_RTLF | /* Long frame recv */      \
 259                                  EESR_RTSF | /* Short frame recv */     \
 260                                  EESR_PRE  | /* PHY-LSI recv error */   \
 261                                  EESR_CERF)  /* Recv frame CRC error */
 262
 263 #define DEFAULT_TX_CHECK        (EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | \
 264                                  EESR_RTO)
 265 #define DEFAULT_EESR_ERR_CHECK  (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE | \
 266                                  EESR_RDE | EESR_RFRMER | EESR_ADE | \
 267                                  EESR_TFE | EESR_TDE | EESR_ECI)
 268
 269 /* EESIPR */
 270 enum DMAC_IM_BIT {
 271         DMAC_M_TWB = 0x40000000, DMAC_M_TABT = 0x04000000,
 272         DMAC_M_RABT = 0x02000000,
 273         DMAC_M_RFRMER = 0x01000000, DMAC_M_ADF = 0x00800000,
 274         DMAC_M_ECI = 0x00400000, DMAC_M_FTC = 0x00200000,
 275         DMAC_M_TDE = 0x00100000, DMAC_M_TFE = 0x00080000,
 276         DMAC_M_FRC = 0x00040000, DMAC_M_RDE = 0x00020000,
 277         DMAC_M_RFE = 0x00010000, DMAC_M_TINT4 = 0x00000800,
 278         DMAC_M_TINT3 = 0x00000400, DMAC_M_TINT2 = 0x00000200,
 279         DMAC_M_TINT1 = 0x00000100, DMAC_M_RINT8 = 0x00000080,
 280         DMAC_M_RINT5 = 0x00000010, DMAC_M_RINT4 = 0x00000008,
 281         DMAC_M_RINT3 = 0x00000004, DMAC_M_RINT2 = 0x00000002,
 282         DMAC_M_RINT1 = 0x00000001,
 283 };
 284
 285 /* Receive descriptor bit */
 286 enum RD_STS_BIT {
 287         RD_RACT = 0x80000000, RD_RDEL = 0x40000000,
 288         RD_RFP1 = 0x20000000, RD_RFP0 = 0x10000000,
 289         RD_RFE = 0x08000000, RD_RFS10 = 0x00000200,
 290         RD_RFS9 = 0x00000100, RD_RFS8 = 0x00000080,
 291         RD_RFS7 = 0x00000040, RD_RFS6 = 0x00000020,
 292         RD_RFS5 = 0x00000010, RD_RFS4 = 0x00000008,
 293         RD_RFS3 = 0x00000004, RD_RFS2 = 0x00000002,
 294         RD_RFS1 = 0x00000001,
 295 };
 296 #define RDF1ST  RD_RFP1
 297 #define RDFEND  RD_RFP0
 298 #define RD_RFP  (RD_RFP1|RD_RFP0)
 299
 300 /* FCFTR */
 301 enum FCFTR_BIT {
 302         FCFTR_RFF2 = 0x00040000, FCFTR_RFF1 = 0x00020000,
 303         FCFTR_RFF0 = 0x00010000, FCFTR_RFD2 = 0x00000004,
 304         FCFTR_RFD1 = 0x00000002, FCFTR_RFD0 = 0x00000001,
 305 };
 306 #define DEFAULT_FIFO_F_D_RFF    (FCFTR_RFF2 | FCFTR_RFF1 | FCFTR_RFF0)
 307 #define DEFAULT_FIFO_F_D_RFD    (FCFTR_RFD2 | FCFTR_RFD1 | FCFTR_RFD0)
 308
 309 /* Transmit descriptor bit */
 310 enum TD_STS_BIT {
 311         TD_TACT = 0x80000000, TD_TDLE = 0x40000000,
 312         TD_TFP1 = 0x20000000, TD_TFP0 = 0x10000000,
 313         TD_TFE  = 0x08000000, TD_TWBI = 0x04000000,
 314 };
 315 #define TDF1ST  TD_TFP1
 316 #define TDFEND  TD_TFP0
 317 #define TD_TFP  (TD_TFP1|TD_TFP0)
 318
 319 /* RMCR */
 320 enum RMCR_BIT {
 321         RMCR_RNC = 0x00000001,
 322 };
 323 #define DEFAULT_RMCR_VALUE      0x00000000
 324
 325 /* ECMR */
 326 enum FELIC_MODE_BIT {
 327         ECMR_TRCCM = 0x04000000, ECMR_RCSC = 0x00800000,
 328         ECMR_DPAD = 0x00200000, ECMR_RZPF = 0x00100000,
 329         ECMR_ZPF = 0x00080000, ECMR_PFR = 0x00040000, ECMR_RXF = 0x00020000,
 330         ECMR_TXF = 0x00010000, ECMR_MCT = 0x00002000, ECMR_PRCEF = 0x00001000,
 331         ECMR_PMDE = 0x00000200, ECMR_RE = 0x00000040, ECMR_TE = 0x00000020,
 332         ECMR_RTM = 0x00000010, ECMR_ILB = 0x00000008, ECMR_ELB = 0x00000004,
 333         ECMR_DM = 0x00000002, ECMR_PRM = 0x00000001,
 334 };
 335
 336 /* ECSR */
 337 enum ECSR_STATUS_BIT {
 338         ECSR_BRCRX = 0x20, ECSR_PSRTO = 0x10,
 339         ECSR_LCHNG = 0x04,
 340         ECSR_MPD = 0x02, ECSR_ICD = 0x01,
 341 };
 342
 343 #define DEFAULT_ECSR_INIT       (ECSR_BRCRX | ECSR_PSRTO | ECSR_LCHNG | \
 344                                  ECSR_ICD | ECSIPR_MPDIP)
 345
 346 /* ECSIPR */
 347 enum ECSIPR_STATUS_MASK_BIT {
 348         ECSIPR_BRCRXIP = 0x20, ECSIPR_PSRTOIP = 0x10,
 349         ECSIPR_LCHNGIP = 0x04,
 350         ECSIPR_MPDIP = 0x02, ECSIPR_ICDIP = 0x01,
 351 };
 352
 353 #define DEFAULT_ECSIPR_INIT     (ECSIPR_BRCRXIP | ECSIPR_PSRTOIP | \
 354                                  ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP)
 355
 356 /* APR */
 357 enum APR_BIT {
 358         APR_AP = 0x00000001,
 359 };
 360
 361 /* MPR */
 362 enum MPR_BIT {
 363         MPR_MP = 0x00000001,
 364 };
 365
 366 /* TRSCER */
 367 enum DESC_I_BIT {
 368         DESC_I_TINT4 = 0x0800, DESC_I_TINT3 = 0x0400, DESC_I_TINT2 = 0x0200,
 369         DESC_I_TINT1 = 0x0100, DESC_I_RINT8 = 0x0080, DESC_I_RINT5 = 0x0010,
 370         DESC_I_RINT4 = 0x0008, DESC_I_RINT3 = 0x0004, DESC_I_RINT2 = 0x0002,
 371         DESC_I_RINT1 = 0x0001,
 372 };
 373
 374 /* RPADIR */
 375 enum RPADIR_BIT {
 376         RPADIR_PADS1 = 0x20000, RPADIR_PADS0 = 0x10000,
 377         RPADIR_PADR = 0x0003f,
 378 };
 379
 380 /* FDR */
 381 #define DEFAULT_FDR_INIT        0x00000707
 382
 383 /* ARSTR */
 384 enum ARSTR_BIT { ARSTR_ARSTR = 0x00000001, };
 385
 386 /* TSU_FWEN0 */
 387 enum TSU_FWEN0_BIT {
 388         TSU_FWEN0_0 = 0x00000001,
 389 };
 390
 391 /* TSU_ADSBSY */
 392 enum TSU_ADSBSY_BIT {
 393         TSU_ADSBSY_0 = 0x00000001,
 394 };
 395
 396 /* TSU_TEN */
 397 enum TSU_TEN_BIT {
 398         TSU_TEN_0 = 0x80000000,
 399 };
 400
 401 /* TSU_FWSL0 */
 402 enum TSU_FWSL0_BIT {
 403         TSU_FWSL0_FW50 = 0x1000, TSU_FWSL0_FW40 = 0x0800,
 404         TSU_FWSL0_FW30 = 0x0400, TSU_FWSL0_FW20 = 0x0200,
 405         TSU_FWSL0_FW10 = 0x0100, TSU_FWSL0_RMSA0 = 0x0010,
 406 };
 407
 408 /* TSU_FWSLC */
 409 enum TSU_FWSLC_BIT {
 410         TSU_FWSLC_POSTENU = 0x2000, TSU_FWSLC_POSTENL = 0x1000,
 411         TSU_FWSLC_CAMSEL03 = 0x0080, TSU_FWSLC_CAMSEL02 = 0x0040,
 412         TSU_FWSLC_CAMSEL01 = 0x0020, TSU_FWSLC_CAMSEL00 = 0x0010,
 413         TSU_FWSLC_CAMSEL13 = 0x0008, TSU_FWSLC_CAMSEL12 = 0x0004,
 414         TSU_FWSLC_CAMSEL11 = 0x0002, TSU_FWSLC_CAMSEL10 = 0x0001,
 415 };
 416
 417 /* TSU_VTAGn */
 418 #define TSU_VTAG_ENABLE         0x80000000
 419 #define TSU_VTAG_VID_MASK       0x00000fff
 420
 421 /* The sh ether Tx buffer descriptors.
 422  * This structure should be 20 bytes.
 423  */
 424 struct sh_eth_txdesc {
 425         u32 status;             /* TD0 */
 426 #if defined(__LITTLE_ENDIAN)
 427         u16 pad0;               /* TD1 */
 428         u16 buffer_length;      /* TD1 */
 429 #else
 430         u16 buffer_length;      /* TD1 */
 431         u16 pad0;               /* TD1 */
 432 #endif
 433         u32 addr;               /* TD2 */
 434         u32 pad1;               /* padding data */
 435 } __aligned(2) __packed;
 436
 437 /* The sh ether Rx buffer descriptors.
 438  * This structure should be 20 bytes.
 439  */
 440 struct sh_eth_rxdesc {
 441         u32 status;             /* RD0 */
 442 #if defined(__LITTLE_ENDIAN)
 443         u16 frame_length;       /* RD1 */
 444         u16 buffer_length;      /* RD1 */
 445 #else
 446         u16 buffer_length;      /* RD1 */
 447         u16 frame_length;       /* RD1 */
 448 #endif
 449         u32 addr;               /* RD2 */
 450         u32 pad0;               /* padding data */
 451 } __aligned(2) __packed;
 452
 453 /* This structure is used by each CPU dependency handling. */
 454 struct sh_eth_cpu_data {
 455         /* optional functions */
 456         void (*chip_reset)(struct net_device *ndev);
 457         void (*set_duplex)(struct net_device *ndev);
 458         void (*set_rate)(struct net_device *ndev);
 459
 460         /* mandatory initialize value */
 461         int register_type;
 462         unsigned long eesipr_value;
 463
 464         /* optional initialize value */
 465         unsigned long ecsr_value;
 466         unsigned long ecsipr_value;
 467         unsigned long fdr_value;
 468         unsigned long fcftr_value;
 469         unsigned long rpadir_value;
 470         unsigned long rmcr_value;
 471
 472         /* interrupt checking mask */
 473         unsigned long tx_check;
 474         unsigned long eesr_err_check;
 475
 476         /* hardware features */
 477         unsigned long irq_flags; /* IRQ configuration flags */
 478         unsigned no_psr:1;      /* EtherC DO NOT have PSR */
 479         unsigned apr:1;         /* EtherC have APR */
 480         unsigned mpr:1;         /* EtherC have MPR */
 481         unsigned tpauser:1;     /* EtherC have TPAUSER */
 482         unsigned bculr:1;       /* EtherC have BCULR */
 483         unsigned tsu:1;         /* EtherC have TSU */
 484         unsigned hw_swap:1;     /* E-DMAC have DE bit in EDMR */
 485         unsigned rpadir:1;      /* E-DMAC have RPADIR */
 486         unsigned no_trimd:1;    /* E-DMAC DO NOT have TRIMD */
 487         unsigned no_ade:1;      /* E-DMAC DO NOT have ADE bit in EESR */
 488         unsigned hw_crc:1;      /* E-DMAC have CSMR */
 489         unsigned select_mii:1;  /* EtherC have RMII_MII (MII select register) */
 490         unsigned shift_rd0:1;   /* shift Rx descriptor word 0 right by 16 */
 491         unsigned rmiimode:1;    /* EtherC has RMIIMODE register */
 492 };
 493
 494 struct sh_eth_private {
 495         struct platform_device *pdev;
 496         struct sh_eth_cpu_data *cd;
 497         const u16 *reg_offset;
 498         void __iomem *addr;
 499         void __iomem *tsu_addr;
 500         u32 num_rx_ring;
 501         u32 num_tx_ring;
 502         dma_addr_t rx_desc_dma;
 503         dma_addr_t tx_desc_dma;
 504         struct sh_eth_rxdesc *rx_ring;
 505         struct sh_eth_txdesc *tx_ring;
 506         struct sk_buff **rx_skbuff;
 507         struct sk_buff **tx_skbuff;
 508         spinlock_t lock;                /* Register access lock */
 509         u32 cur_rx, dirty_rx;           /* Producer/consumer ring indices */
 510         u32 cur_tx, dirty_tx;
 511         u32 rx_buf_sz;                  /* Based on MTU+slack. */
 512         int edmac_endian;
 513         struct napi_struct napi;
 514         /* MII transceiver section. */
 515         u32 phy_id;                     /* PHY ID */
 516         struct mii_bus *mii_bus;        /* MDIO bus control */
 517         struct phy_device *phydev;      /* PHY device control */
 518         int link;
 519         phy_interface_t phy_interface;
 520         int msg_enable;
 521         int speed;
 522         int duplex;
 523         int port;                       /* for TSU */
 524         int vlan_num_ids;               /* for VLAN tag filter */
 525
 526         unsigned no_ether_link:1;
 527         unsigned ether_link_active_low:1;
 528 };
 529
 530 static inline void sh_eth_soft_swap(char *src, int len)
 531 {
 532 #ifdef __LITTLE_ENDIAN__
 533         u32 *p = (u32 *)src;
 534         u32 *maxp;
 535         maxp = p + ((len + sizeof(u32) - 1) / sizeof(u32));
 536
 537         for (; p < maxp; p++)
 538                 *p = swab32(*p);
 539 #endif
 540 }
 541
 542 static inline void sh_eth_write(struct net_device *ndev, unsigned long data,
 543                                 int enum_index)
 544 {
 545         struct sh_eth_private *mdp = netdev_priv(ndev);
 546
 547         iowrite32(data, mdp->addr + mdp->reg_offset[enum_index]);
 548 }
 549
 550 static inline unsigned long sh_eth_read(struct net_device *ndev,
 551                                         int enum_index)
 552 {
 553         struct sh_eth_private *mdp = netdev_priv(ndev);
 554
 555         return ioread32(mdp->addr + mdp->reg_offset[enum_index]);
 556 }
 557
 558 static inline void *sh_eth_tsu_get_offset(struct sh_eth_private *mdp,
 559                                           int enum_index)
 560 {
 561         return mdp->tsu_addr + mdp->reg_offset[enum_index];
 562 }
 563
 564 static inline void sh_eth_tsu_write(struct sh_eth_private *mdp,
 565                                 unsigned long data, int enum_index)
 566 {
 567         iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
 568 }
 569
 570 static inline unsigned long sh_eth_tsu_read(struct sh_eth_private *mdp,
 571                                         int enum_index)
 572 {
 573         return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
 574 }
 575
 576 #endif  /* #ifndef __SH_ETH_H__ */