1 /****************************************************************************
2 * Driver for Solarflare network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2013 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/random.h>
17 #include "net_driver.h"
21 #include "farch_regs.h"
24 #include "workarounds.h"
26 #include "mcdi_pcol.h"
29 /* Hardware control for SFC9000 family including SFL9021 (aka Siena). */
31 static void siena_init_wol(struct efx_nic
*efx
);
34 static void siena_push_irq_moderation(struct efx_channel
*channel
)
36 efx_dword_t timer_cmd
;
38 if (channel
->irq_moderation
)
39 EFX_POPULATE_DWORD_2(timer_cmd
,
41 FFE_CZ_TIMER_MODE_INT_HLDOFF
,
43 channel
->irq_moderation
- 1);
45 EFX_POPULATE_DWORD_2(timer_cmd
,
47 FFE_CZ_TIMER_MODE_DIS
,
48 FRF_CZ_TC_TIMER_VAL
, 0);
49 efx_writed_page_locked(channel
->efx
, &timer_cmd
, FR_BZ_TIMER_COMMAND_P0
,
53 void siena_prepare_flush(struct efx_nic
*efx
)
55 if (efx
->fc_disable
++ == 0)
56 efx_mcdi_set_mac(efx
);
59 void siena_finish_flush(struct efx_nic
*efx
)
61 if (--efx
->fc_disable
== 0)
62 efx_mcdi_set_mac(efx
);
65 static const struct efx_farch_register_test siena_register_tests
[] = {
67 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
69 EFX_OWORD32(0x000103FF, 0x00000000, 0x00000000, 0x00000000) },
71 EFX_OWORD32(0xFFFFFFFE, 0xFFFFFFFF, 0x0003FFFF, 0x00000000) },
73 EFX_OWORD32(0x7FFF0037, 0xFFFF8000, 0xFFFFFFFF, 0x03FFFFFF) },
75 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
76 { FR_AZ_SRM_TX_DC_CFG
,
77 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
79 EFX_OWORD32(0x00000003, 0x00000000, 0x00000000, 0x00000000) },
81 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
83 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
85 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
86 { FR_CZ_RX_RSS_IPV6_REG1
,
87 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
88 { FR_CZ_RX_RSS_IPV6_REG2
,
89 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF) },
90 { FR_CZ_RX_RSS_IPV6_REG3
,
91 EFX_OWORD32(0xFFFFFFFF, 0xFFFFFFFF, 0x00000007, 0x00000000) },
94 static int siena_test_chip(struct efx_nic
*efx
, struct efx_self_tests
*tests
)
96 enum reset_type reset_method
= RESET_TYPE_ALL
;
99 efx_reset_down(efx
, reset_method
);
101 /* Reset the chip immediately so that it is completely
102 * quiescent regardless of what any VF driver does.
104 rc
= efx_mcdi_reset(efx
, reset_method
);
109 efx_farch_test_registers(efx
, siena_register_tests
,
110 ARRAY_SIZE(siena_register_tests
))
113 rc
= efx_mcdi_reset(efx
, reset_method
);
115 rc2
= efx_reset_up(efx
, reset_method
, rc
== 0);
116 return rc
? rc
: rc2
;
119 /**************************************************************************
123 **************************************************************************
126 static void siena_ptp_write_host_time(struct efx_nic
*efx
, u32 host_time
)
128 _efx_writed(efx
, cpu_to_le32(host_time
),
129 FR_CZ_MC_TREG_SMEM
+ MC_SMEM_P0_PTP_TIME_OFST
);
132 static int siena_ptp_set_ts_config(struct efx_nic
*efx
,
133 struct hwtstamp_config
*init
)
137 switch (init
->rx_filter
) {
138 case HWTSTAMP_FILTER_NONE
:
139 /* if TX timestamping is still requested then leave PTP on */
140 return efx_ptp_change_mode(efx
,
141 init
->tx_type
!= HWTSTAMP_TX_OFF
,
142 efx_ptp_get_mode(efx
));
143 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT
:
144 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC
:
145 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
:
146 init
->rx_filter
= HWTSTAMP_FILTER_PTP_V1_L4_EVENT
;
147 return efx_ptp_change_mode(efx
, true, MC_CMD_PTP_MODE_V1
);
148 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT
:
149 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC
:
150 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
:
151 init
->rx_filter
= HWTSTAMP_FILTER_PTP_V2_L4_EVENT
;
152 rc
= efx_ptp_change_mode(efx
, true,
153 MC_CMD_PTP_MODE_V2_ENHANCED
);
154 /* bug 33070 - old versions of the firmware do not support the
155 * improved UUID filtering option. Similarly old versions of the
156 * application do not expect it to be enabled. If the firmware
157 * does not accept the enhanced mode, fall back to the standard
158 * PTP v2 UUID filtering. */
160 rc
= efx_ptp_change_mode(efx
, true, MC_CMD_PTP_MODE_V2
);
167 /**************************************************************************
171 **************************************************************************
174 static int siena_map_reset_flags(u32
*flags
)
177 SIENA_RESET_PORT
= (ETH_RESET_DMA
| ETH_RESET_FILTER
|
178 ETH_RESET_OFFLOAD
| ETH_RESET_MAC
|
180 SIENA_RESET_MC
= (SIENA_RESET_PORT
|
181 ETH_RESET_MGMT
<< ETH_RESET_SHARED_SHIFT
),
184 if ((*flags
& SIENA_RESET_MC
) == SIENA_RESET_MC
) {
185 *flags
&= ~SIENA_RESET_MC
;
186 return RESET_TYPE_WORLD
;
189 if ((*flags
& SIENA_RESET_PORT
) == SIENA_RESET_PORT
) {
190 *flags
&= ~SIENA_RESET_PORT
;
191 return RESET_TYPE_ALL
;
194 /* no invisible reset implemented */
200 /* When a PCI device is isolated from the bus, a subsequent MMIO read is
201 * required for the kernel EEH mechanisms to notice. As the Solarflare driver
202 * was written to minimise MMIO read (for latency) then a periodic call to check
203 * the EEH status of the device is required so that device recovery can happen
204 * in a timely fashion.
206 static void siena_monitor(struct efx_nic
*efx
)
208 struct eeh_dev
*eehdev
=
209 of_node_to_eeh_dev(pci_device_to_OF_node(efx
->pci_dev
));
211 eeh_dev_check_failure(eehdev
);
215 static int siena_probe_nvconfig(struct efx_nic
*efx
)
220 rc
= efx_mcdi_get_board_cfg(efx
, efx
->net_dev
->perm_addr
, NULL
, &caps
);
222 efx
->timer_quantum_ns
=
223 (caps
& (1 << MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN
)) ?
224 3072 : 6144; /* 768 cycles */
228 static int siena_dimension_resources(struct efx_nic
*efx
)
230 /* Each port has a small block of internal SRAM dedicated to
231 * the buffer table and descriptor caches. In theory we can
232 * map both blocks to one port, but we don't.
234 efx_farch_dimension_resources(efx
, FR_CZ_BUF_FULL_TBL_ROWS
/ 2);
238 static unsigned int siena_mem_map_size(struct efx_nic
*efx
)
240 return FR_CZ_MC_TREG_SMEM
+
241 FR_CZ_MC_TREG_SMEM_STEP
* FR_CZ_MC_TREG_SMEM_ROWS
;
244 static int siena_probe_nic(struct efx_nic
*efx
)
246 struct siena_nic_data
*nic_data
;
250 /* Allocate storage for hardware specific data */
251 nic_data
= kzalloc(sizeof(struct siena_nic_data
), GFP_KERNEL
);
254 efx
->nic_data
= nic_data
;
256 if (efx_farch_fpga_ver(efx
) != 0) {
257 netif_err(efx
, probe
, efx
->net_dev
,
258 "Siena FPGA not supported\n");
263 efx
->max_channels
= EFX_MAX_CHANNELS
;
265 efx_reado(efx
, ®
, FR_AZ_CS_DEBUG
);
266 efx
->port_num
= EFX_OWORD_FIELD(reg
, FRF_CZ_CS_PORT_NUM
) - 1;
268 rc
= efx_mcdi_init(efx
);
272 /* Now we can reset the NIC */
273 rc
= efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
275 netif_err(efx
, probe
, efx
->net_dev
, "failed to reset NIC\n");
281 /* Allocate memory for INT_KER */
282 rc
= efx_nic_alloc_buffer(efx
, &efx
->irq_status
, sizeof(efx_oword_t
),
286 BUG_ON(efx
->irq_status
.dma_addr
& 0x0f);
288 netif_dbg(efx
, probe
, efx
->net_dev
,
289 "INT_KER at %llx (virt %p phys %llx)\n",
290 (unsigned long long)efx
->irq_status
.dma_addr
,
291 efx
->irq_status
.addr
,
292 (unsigned long long)virt_to_phys(efx
->irq_status
.addr
));
294 /* Read in the non-volatile configuration */
295 rc
= siena_probe_nvconfig(efx
);
297 netif_err(efx
, probe
, efx
->net_dev
,
298 "NVRAM is invalid therefore using defaults\n");
299 efx
->phy_type
= PHY_TYPE_NONE
;
300 efx
->mdio
.prtad
= MDIO_PRTAD_NONE
;
305 rc
= efx_mcdi_mon_probe(efx
);
309 efx_sriov_probe(efx
);
310 efx_ptp_defer_probe_with_channel(efx
);
315 efx_nic_free_buffer(efx
, &efx
->irq_status
);
320 kfree(efx
->nic_data
);
324 static void siena_rx_push_rss_config(struct efx_nic
*efx
)
328 /* Set hash key for IPv4 */
329 memcpy(&temp
, efx
->rx_hash_key
, sizeof(temp
));
330 efx_writeo(efx
, &temp
, FR_BZ_RX_RSS_TKEY
);
332 /* Enable IPv6 RSS */
333 BUILD_BUG_ON(sizeof(efx
->rx_hash_key
) <
334 2 * sizeof(temp
) + FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH
/ 8 ||
335 FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN
!= 0);
336 memcpy(&temp
, efx
->rx_hash_key
, sizeof(temp
));
337 efx_writeo(efx
, &temp
, FR_CZ_RX_RSS_IPV6_REG1
);
338 memcpy(&temp
, efx
->rx_hash_key
+ sizeof(temp
), sizeof(temp
));
339 efx_writeo(efx
, &temp
, FR_CZ_RX_RSS_IPV6_REG2
);
340 EFX_POPULATE_OWORD_2(temp
, FRF_CZ_RX_RSS_IPV6_THASH_ENABLE
, 1,
341 FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE
, 1);
342 memcpy(&temp
, efx
->rx_hash_key
+ 2 * sizeof(temp
),
343 FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH
/ 8);
344 efx_writeo(efx
, &temp
, FR_CZ_RX_RSS_IPV6_REG3
);
346 efx_farch_rx_push_indir_table(efx
);
349 /* This call performs hardware-specific global initialisation, such as
350 * defining the descriptor cache sizes and number of RSS channels.
351 * It does not set up any buffers, descriptor rings or event queues.
353 static int siena_init_nic(struct efx_nic
*efx
)
358 /* Recover from a failed assertion post-reset */
359 rc
= efx_mcdi_handle_assertion(efx
);
363 /* Squash TX of packets of 16 bytes or less */
364 efx_reado(efx
, &temp
, FR_AZ_TX_RESERVED
);
365 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_TX_FLUSH_MIN_LEN_EN
, 1);
366 efx_writeo(efx
, &temp
, FR_AZ_TX_RESERVED
);
368 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
369 * descriptors (which is bad).
371 efx_reado(efx
, &temp
, FR_AZ_TX_CFG
);
372 EFX_SET_OWORD_FIELD(temp
, FRF_AZ_TX_NO_EOP_DISC_EN
, 0);
373 EFX_SET_OWORD_FIELD(temp
, FRF_CZ_TX_FILTER_EN_BIT
, 1);
374 efx_writeo(efx
, &temp
, FR_AZ_TX_CFG
);
376 efx_reado(efx
, &temp
, FR_AZ_RX_CFG
);
377 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_RX_DESC_PUSH_EN
, 0);
378 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_RX_INGR_EN
, 1);
379 /* Enable hash insertion. This is broken for the 'Falcon' hash
380 * if IPv6 hashing is also enabled, so also select Toeplitz
381 * TCP/IPv4 and IPv4 hashes. */
382 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_RX_HASH_INSRT_HDR
, 1);
383 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_RX_HASH_ALG
, 1);
384 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_RX_IP_HASH
, 1);
385 EFX_SET_OWORD_FIELD(temp
, FRF_BZ_RX_USR_BUF_SIZE
,
386 EFX_RX_USR_BUF_SIZE
>> 5);
387 efx_writeo(efx
, &temp
, FR_AZ_RX_CFG
);
389 siena_rx_push_rss_config(efx
);
391 /* Enable event logging */
392 rc
= efx_mcdi_log_ctrl(efx
, true, false, 0);
396 /* Set destination of both TX and RX Flush events */
397 EFX_POPULATE_OWORD_1(temp
, FRF_BZ_FLS_EVQ_ID
, 0);
398 efx_writeo(efx
, &temp
, FR_BZ_DP_CTRL
);
400 EFX_POPULATE_OWORD_1(temp
, FRF_CZ_USREV_DIS
, 1);
401 efx_writeo(efx
, &temp
, FR_CZ_USR_EV_CFG
);
403 efx_farch_init_common(efx
);
407 static void siena_remove_nic(struct efx_nic
*efx
)
409 efx_mcdi_mon_remove(efx
);
411 efx_nic_free_buffer(efx
, &efx
->irq_status
);
413 efx_mcdi_reset(efx
, RESET_TYPE_ALL
);
417 /* Tear down the private nic state */
418 kfree(efx
->nic_data
);
419 efx
->nic_data
= NULL
;
422 #define SIENA_DMA_STAT(ext_name, mcdi_name) \
423 [SIENA_STAT_ ## ext_name] = \
424 { #ext_name, 64, 8 * MC_CMD_MAC_ ## mcdi_name }
425 #define SIENA_OTHER_STAT(ext_name) \
426 [SIENA_STAT_ ## ext_name] = { #ext_name, 0, 0 }
428 static const struct efx_hw_stat_desc siena_stat_desc
[SIENA_STAT_COUNT
] = {
429 SIENA_DMA_STAT(tx_bytes
, TX_BYTES
),
430 SIENA_OTHER_STAT(tx_good_bytes
),
431 SIENA_DMA_STAT(tx_bad_bytes
, TX_BAD_BYTES
),
432 SIENA_DMA_STAT(tx_packets
, TX_PKTS
),
433 SIENA_DMA_STAT(tx_bad
, TX_BAD_FCS_PKTS
),
434 SIENA_DMA_STAT(tx_pause
, TX_PAUSE_PKTS
),
435 SIENA_DMA_STAT(tx_control
, TX_CONTROL_PKTS
),
436 SIENA_DMA_STAT(tx_unicast
, TX_UNICAST_PKTS
),
437 SIENA_DMA_STAT(tx_multicast
, TX_MULTICAST_PKTS
),
438 SIENA_DMA_STAT(tx_broadcast
, TX_BROADCAST_PKTS
),
439 SIENA_DMA_STAT(tx_lt64
, TX_LT64_PKTS
),
440 SIENA_DMA_STAT(tx_64
, TX_64_PKTS
),
441 SIENA_DMA_STAT(tx_65_to_127
, TX_65_TO_127_PKTS
),
442 SIENA_DMA_STAT(tx_128_to_255
, TX_128_TO_255_PKTS
),
443 SIENA_DMA_STAT(tx_256_to_511
, TX_256_TO_511_PKTS
),
444 SIENA_DMA_STAT(tx_512_to_1023
, TX_512_TO_1023_PKTS
),
445 SIENA_DMA_STAT(tx_1024_to_15xx
, TX_1024_TO_15XX_PKTS
),
446 SIENA_DMA_STAT(tx_15xx_to_jumbo
, TX_15XX_TO_JUMBO_PKTS
),
447 SIENA_DMA_STAT(tx_gtjumbo
, TX_GTJUMBO_PKTS
),
448 SIENA_OTHER_STAT(tx_collision
),
449 SIENA_DMA_STAT(tx_single_collision
, TX_SINGLE_COLLISION_PKTS
),
450 SIENA_DMA_STAT(tx_multiple_collision
, TX_MULTIPLE_COLLISION_PKTS
),
451 SIENA_DMA_STAT(tx_excessive_collision
, TX_EXCESSIVE_COLLISION_PKTS
),
452 SIENA_DMA_STAT(tx_deferred
, TX_DEFERRED_PKTS
),
453 SIENA_DMA_STAT(tx_late_collision
, TX_LATE_COLLISION_PKTS
),
454 SIENA_DMA_STAT(tx_excessive_deferred
, TX_EXCESSIVE_DEFERRED_PKTS
),
455 SIENA_DMA_STAT(tx_non_tcpudp
, TX_NON_TCPUDP_PKTS
),
456 SIENA_DMA_STAT(tx_mac_src_error
, TX_MAC_SRC_ERR_PKTS
),
457 SIENA_DMA_STAT(tx_ip_src_error
, TX_IP_SRC_ERR_PKTS
),
458 SIENA_DMA_STAT(rx_bytes
, RX_BYTES
),
459 SIENA_OTHER_STAT(rx_good_bytes
),
460 SIENA_DMA_STAT(rx_bad_bytes
, RX_BAD_BYTES
),
461 SIENA_DMA_STAT(rx_packets
, RX_PKTS
),
462 SIENA_DMA_STAT(rx_good
, RX_GOOD_PKTS
),
463 SIENA_DMA_STAT(rx_bad
, RX_BAD_FCS_PKTS
),
464 SIENA_DMA_STAT(rx_pause
, RX_PAUSE_PKTS
),
465 SIENA_DMA_STAT(rx_control
, RX_CONTROL_PKTS
),
466 SIENA_DMA_STAT(rx_unicast
, RX_UNICAST_PKTS
),
467 SIENA_DMA_STAT(rx_multicast
, RX_MULTICAST_PKTS
),
468 SIENA_DMA_STAT(rx_broadcast
, RX_BROADCAST_PKTS
),
469 SIENA_DMA_STAT(rx_lt64
, RX_UNDERSIZE_PKTS
),
470 SIENA_DMA_STAT(rx_64
, RX_64_PKTS
),
471 SIENA_DMA_STAT(rx_65_to_127
, RX_65_TO_127_PKTS
),
472 SIENA_DMA_STAT(rx_128_to_255
, RX_128_TO_255_PKTS
),
473 SIENA_DMA_STAT(rx_256_to_511
, RX_256_TO_511_PKTS
),
474 SIENA_DMA_STAT(rx_512_to_1023
, RX_512_TO_1023_PKTS
),
475 SIENA_DMA_STAT(rx_1024_to_15xx
, RX_1024_TO_15XX_PKTS
),
476 SIENA_DMA_STAT(rx_15xx_to_jumbo
, RX_15XX_TO_JUMBO_PKTS
),
477 SIENA_DMA_STAT(rx_gtjumbo
, RX_GTJUMBO_PKTS
),
478 SIENA_DMA_STAT(rx_bad_gtjumbo
, RX_JABBER_PKTS
),
479 SIENA_DMA_STAT(rx_overflow
, RX_OVERFLOW_PKTS
),
480 SIENA_DMA_STAT(rx_false_carrier
, RX_FALSE_CARRIER_PKTS
),
481 SIENA_DMA_STAT(rx_symbol_error
, RX_SYMBOL_ERROR_PKTS
),
482 SIENA_DMA_STAT(rx_align_error
, RX_ALIGN_ERROR_PKTS
),
483 SIENA_DMA_STAT(rx_length_error
, RX_LENGTH_ERROR_PKTS
),
484 SIENA_DMA_STAT(rx_internal_error
, RX_INTERNAL_ERROR_PKTS
),
485 SIENA_DMA_STAT(rx_nodesc_drop_cnt
, RX_NODESC_DROPS
),
487 static const unsigned long siena_stat_mask
[] = {
488 [0 ... BITS_TO_LONGS(SIENA_STAT_COUNT
) - 1] = ~0UL,
491 static size_t siena_describe_nic_stats(struct efx_nic
*efx
, u8
*names
)
493 return efx_nic_describe_stats(siena_stat_desc
, SIENA_STAT_COUNT
,
494 siena_stat_mask
, names
);
497 static int siena_try_update_nic_stats(struct efx_nic
*efx
)
499 struct siena_nic_data
*nic_data
= efx
->nic_data
;
500 u64
*stats
= nic_data
->stats
;
502 __le64 generation_start
, generation_end
;
504 dma_stats
= efx
->stats_buffer
.addr
;
506 generation_end
= dma_stats
[MC_CMD_MAC_GENERATION_END
];
507 if (generation_end
== EFX_MC_STATS_GENERATION_INVALID
)
510 efx_nic_update_stats(siena_stat_desc
, SIENA_STAT_COUNT
, siena_stat_mask
,
511 stats
, efx
->stats_buffer
.addr
, false);
513 generation_start
= dma_stats
[MC_CMD_MAC_GENERATION_START
];
514 if (generation_end
!= generation_start
)
517 /* Update derived statistics */
518 efx_nic_fix_nodesc_drop_stat(efx
,
519 &stats
[SIENA_STAT_rx_nodesc_drop_cnt
]);
520 efx_update_diff_stat(&stats
[SIENA_STAT_tx_good_bytes
],
521 stats
[SIENA_STAT_tx_bytes
] -
522 stats
[SIENA_STAT_tx_bad_bytes
]);
523 stats
[SIENA_STAT_tx_collision
] =
524 stats
[SIENA_STAT_tx_single_collision
] +
525 stats
[SIENA_STAT_tx_multiple_collision
] +
526 stats
[SIENA_STAT_tx_excessive_collision
] +
527 stats
[SIENA_STAT_tx_late_collision
];
528 efx_update_diff_stat(&stats
[SIENA_STAT_rx_good_bytes
],
529 stats
[SIENA_STAT_rx_bytes
] -
530 stats
[SIENA_STAT_rx_bad_bytes
]);
534 static size_t siena_update_nic_stats(struct efx_nic
*efx
, u64
*full_stats
,
535 struct rtnl_link_stats64
*core_stats
)
537 struct siena_nic_data
*nic_data
= efx
->nic_data
;
538 u64
*stats
= nic_data
->stats
;
541 /* If we're unlucky enough to read statistics wduring the DMA, wait
542 * up to 10ms for it to finish (typically takes <500us) */
543 for (retry
= 0; retry
< 100; ++retry
) {
544 if (siena_try_update_nic_stats(efx
) == 0)
550 memcpy(full_stats
, stats
, sizeof(u64
) * SIENA_STAT_COUNT
);
553 core_stats
->rx_packets
= stats
[SIENA_STAT_rx_packets
];
554 core_stats
->tx_packets
= stats
[SIENA_STAT_tx_packets
];
555 core_stats
->rx_bytes
= stats
[SIENA_STAT_rx_bytes
];
556 core_stats
->tx_bytes
= stats
[SIENA_STAT_tx_bytes
];
557 core_stats
->rx_dropped
= stats
[SIENA_STAT_rx_nodesc_drop_cnt
];
558 core_stats
->multicast
= stats
[SIENA_STAT_rx_multicast
];
559 core_stats
->collisions
= stats
[SIENA_STAT_tx_collision
];
560 core_stats
->rx_length_errors
=
561 stats
[SIENA_STAT_rx_gtjumbo
] +
562 stats
[SIENA_STAT_rx_length_error
];
563 core_stats
->rx_crc_errors
= stats
[SIENA_STAT_rx_bad
];
564 core_stats
->rx_frame_errors
= stats
[SIENA_STAT_rx_align_error
];
565 core_stats
->rx_fifo_errors
= stats
[SIENA_STAT_rx_overflow
];
566 core_stats
->tx_window_errors
=
567 stats
[SIENA_STAT_tx_late_collision
];
569 core_stats
->rx_errors
= (core_stats
->rx_length_errors
+
570 core_stats
->rx_crc_errors
+
571 core_stats
->rx_frame_errors
+
572 stats
[SIENA_STAT_rx_symbol_error
]);
573 core_stats
->tx_errors
= (core_stats
->tx_window_errors
+
574 stats
[SIENA_STAT_tx_bad
]);
577 return SIENA_STAT_COUNT
;
580 static int siena_mac_reconfigure(struct efx_nic
*efx
)
582 MCDI_DECLARE_BUF(inbuf
, MC_CMD_SET_MCAST_HASH_IN_LEN
);
585 BUILD_BUG_ON(MC_CMD_SET_MCAST_HASH_IN_LEN
!=
586 MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST
+
587 sizeof(efx
->multicast_hash
));
589 efx_farch_filter_sync_rx_mode(efx
);
591 WARN_ON(!mutex_is_locked(&efx
->mac_lock
));
593 rc
= efx_mcdi_set_mac(efx
);
597 memcpy(MCDI_PTR(inbuf
, SET_MCAST_HASH_IN_HASH0
),
598 efx
->multicast_hash
.byte
, sizeof(efx
->multicast_hash
));
599 return efx_mcdi_rpc(efx
, MC_CMD_SET_MCAST_HASH
,
600 inbuf
, sizeof(inbuf
), NULL
, 0, NULL
);
603 /**************************************************************************
607 **************************************************************************
610 static void siena_get_wol(struct efx_nic
*efx
, struct ethtool_wolinfo
*wol
)
612 struct siena_nic_data
*nic_data
= efx
->nic_data
;
614 wol
->supported
= WAKE_MAGIC
;
615 if (nic_data
->wol_filter_id
!= -1)
616 wol
->wolopts
= WAKE_MAGIC
;
619 memset(&wol
->sopass
, 0, sizeof(wol
->sopass
));
623 static int siena_set_wol(struct efx_nic
*efx
, u32 type
)
625 struct siena_nic_data
*nic_data
= efx
->nic_data
;
628 if (type
& ~WAKE_MAGIC
)
631 if (type
& WAKE_MAGIC
) {
632 if (nic_data
->wol_filter_id
!= -1)
633 efx_mcdi_wol_filter_remove(efx
,
634 nic_data
->wol_filter_id
);
635 rc
= efx_mcdi_wol_filter_set_magic(efx
, efx
->net_dev
->dev_addr
,
636 &nic_data
->wol_filter_id
);
640 pci_wake_from_d3(efx
->pci_dev
, true);
642 rc
= efx_mcdi_wol_filter_reset(efx
);
643 nic_data
->wol_filter_id
= -1;
644 pci_wake_from_d3(efx
->pci_dev
, false);
651 netif_err(efx
, hw
, efx
->net_dev
, "%s failed: type=%d rc=%d\n",
657 static void siena_init_wol(struct efx_nic
*efx
)
659 struct siena_nic_data
*nic_data
= efx
->nic_data
;
662 rc
= efx_mcdi_wol_filter_get_magic(efx
, &nic_data
->wol_filter_id
);
665 /* If it failed, attempt to get into a synchronised
666 * state with MC by resetting any set WoL filters */
667 efx_mcdi_wol_filter_reset(efx
);
668 nic_data
->wol_filter_id
= -1;
669 } else if (nic_data
->wol_filter_id
!= -1) {
670 pci_wake_from_d3(efx
->pci_dev
, true);
674 /**************************************************************************
678 **************************************************************************
681 #define MCDI_PDU(efx) \
682 (efx_port_num(efx) ? MC_SMEM_P1_PDU_OFST : MC_SMEM_P0_PDU_OFST)
683 #define MCDI_DOORBELL(efx) \
684 (efx_port_num(efx) ? MC_SMEM_P1_DOORBELL_OFST : MC_SMEM_P0_DOORBELL_OFST)
685 #define MCDI_STATUS(efx) \
686 (efx_port_num(efx) ? MC_SMEM_P1_STATUS_OFST : MC_SMEM_P0_STATUS_OFST)
688 static void siena_mcdi_request(struct efx_nic
*efx
,
689 const efx_dword_t
*hdr
, size_t hdr_len
,
690 const efx_dword_t
*sdu
, size_t sdu_len
)
692 unsigned pdu
= FR_CZ_MC_TREG_SMEM
+ MCDI_PDU(efx
);
693 unsigned doorbell
= FR_CZ_MC_TREG_SMEM
+ MCDI_DOORBELL(efx
);
695 unsigned int inlen_dw
= DIV_ROUND_UP(sdu_len
, 4);
697 EFX_BUG_ON_PARANOID(hdr_len
!= 4);
699 efx_writed(efx
, hdr
, pdu
);
701 for (i
= 0; i
< inlen_dw
; i
++)
702 efx_writed(efx
, &sdu
[i
], pdu
+ hdr_len
+ 4 * i
);
704 /* Ensure the request is written out before the doorbell */
707 /* ring the doorbell with a distinctive value */
708 _efx_writed(efx
, (__force __le32
) 0x45789abc, doorbell
);
711 static bool siena_mcdi_poll_response(struct efx_nic
*efx
)
713 unsigned int pdu
= FR_CZ_MC_TREG_SMEM
+ MCDI_PDU(efx
);
716 efx_readd(efx
, &hdr
, pdu
);
718 /* All 1's indicates that shared memory is in reset (and is
719 * not a valid hdr). Wait for it to come out reset before
720 * completing the command
722 return EFX_DWORD_FIELD(hdr
, EFX_DWORD_0
) != 0xffffffff &&
723 EFX_DWORD_FIELD(hdr
, MCDI_HEADER_RESPONSE
);
726 static void siena_mcdi_read_response(struct efx_nic
*efx
, efx_dword_t
*outbuf
,
727 size_t offset
, size_t outlen
)
729 unsigned int pdu
= FR_CZ_MC_TREG_SMEM
+ MCDI_PDU(efx
);
730 unsigned int outlen_dw
= DIV_ROUND_UP(outlen
, 4);
733 for (i
= 0; i
< outlen_dw
; i
++)
734 efx_readd(efx
, &outbuf
[i
], pdu
+ offset
+ 4 * i
);
737 static int siena_mcdi_poll_reboot(struct efx_nic
*efx
)
739 struct siena_nic_data
*nic_data
= efx
->nic_data
;
740 unsigned int addr
= FR_CZ_MC_TREG_SMEM
+ MCDI_STATUS(efx
);
744 efx_readd(efx
, ®
, addr
);
745 value
= EFX_DWORD_FIELD(reg
, EFX_DWORD_0
);
751 efx_writed(efx
, ®
, addr
);
753 /* MAC statistics have been cleared on the NIC; clear the local
754 * copies that we update with efx_update_diff_stat().
756 nic_data
->stats
[SIENA_STAT_tx_good_bytes
] = 0;
757 nic_data
->stats
[SIENA_STAT_rx_good_bytes
] = 0;
759 if (value
== MC_STATUS_DWORD_ASSERT
)
765 /**************************************************************************
769 **************************************************************************
772 #ifdef CONFIG_SFC_MTD
774 struct siena_nvram_type_info
{
779 static const struct siena_nvram_type_info siena_nvram_types
[] = {
780 [MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO
] = { 0, "sfc_dummy_phy" },
781 [MC_CMD_NVRAM_TYPE_MC_FW
] = { 0, "sfc_mcfw" },
782 [MC_CMD_NVRAM_TYPE_MC_FW_BACKUP
] = { 0, "sfc_mcfw_backup" },
783 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0
] = { 0, "sfc_static_cfg" },
784 [MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1
] = { 1, "sfc_static_cfg" },
785 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0
] = { 0, "sfc_dynamic_cfg" },
786 [MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1
] = { 1, "sfc_dynamic_cfg" },
787 [MC_CMD_NVRAM_TYPE_EXP_ROM
] = { 0, "sfc_exp_rom" },
788 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0
] = { 0, "sfc_exp_rom_cfg" },
789 [MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1
] = { 1, "sfc_exp_rom_cfg" },
790 [MC_CMD_NVRAM_TYPE_PHY_PORT0
] = { 0, "sfc_phy_fw" },
791 [MC_CMD_NVRAM_TYPE_PHY_PORT1
] = { 1, "sfc_phy_fw" },
792 [MC_CMD_NVRAM_TYPE_FPGA
] = { 0, "sfc_fpga" },
795 static int siena_mtd_probe_partition(struct efx_nic
*efx
,
796 struct efx_mcdi_mtd_partition
*part
,
799 const struct siena_nvram_type_info
*info
;
800 size_t size
, erase_size
;
804 if (type
>= ARRAY_SIZE(siena_nvram_types
) ||
805 siena_nvram_types
[type
].name
== NULL
)
808 info
= &siena_nvram_types
[type
];
810 if (info
->port
!= efx_port_num(efx
))
813 rc
= efx_mcdi_nvram_info(efx
, type
, &size
, &erase_size
, &protected);
817 return -ENODEV
; /* hide it */
819 part
->nvram_type
= type
;
820 part
->common
.dev_type_name
= "Siena NVRAM manager";
821 part
->common
.type_name
= info
->name
;
823 part
->common
.mtd
.type
= MTD_NORFLASH
;
824 part
->common
.mtd
.flags
= MTD_CAP_NORFLASH
;
825 part
->common
.mtd
.size
= size
;
826 part
->common
.mtd
.erasesize
= erase_size
;
831 static int siena_mtd_get_fw_subtypes(struct efx_nic
*efx
,
832 struct efx_mcdi_mtd_partition
*parts
,
835 uint16_t fw_subtype_list
[
836 MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM
];
840 rc
= efx_mcdi_get_board_cfg(efx
, NULL
, fw_subtype_list
, NULL
);
844 for (i
= 0; i
< n_parts
; i
++)
845 parts
[i
].fw_subtype
= fw_subtype_list
[parts
[i
].nvram_type
];
850 static int siena_mtd_probe(struct efx_nic
*efx
)
852 struct efx_mcdi_mtd_partition
*parts
;
860 rc
= efx_mcdi_nvram_types(efx
, &nvram_types
);
864 parts
= kcalloc(hweight32(nvram_types
), sizeof(*parts
), GFP_KERNEL
);
871 while (nvram_types
!= 0) {
872 if (nvram_types
& 1) {
873 rc
= siena_mtd_probe_partition(efx
, &parts
[n_parts
],
877 else if (rc
!= -ENODEV
)
884 rc
= siena_mtd_get_fw_subtypes(efx
, parts
, n_parts
);
888 rc
= efx_mtd_add(efx
, &parts
[0].common
, n_parts
, sizeof(*parts
));
895 #endif /* CONFIG_SFC_MTD */
897 /**************************************************************************
899 * Revision-dependent attributes used by efx.c and nic.c
901 **************************************************************************
904 const struct efx_nic_type siena_a0_nic_type
= {
905 .mem_map_size
= siena_mem_map_size
,
906 .probe
= siena_probe_nic
,
907 .remove
= siena_remove_nic
,
908 .init
= siena_init_nic
,
909 .dimension_resources
= siena_dimension_resources
,
910 .fini
= efx_port_dummy_op_void
,
912 .monitor
= siena_monitor
,
916 .map_reset_reason
= efx_mcdi_map_reset_reason
,
917 .map_reset_flags
= siena_map_reset_flags
,
918 .reset
= efx_mcdi_reset
,
919 .probe_port
= efx_mcdi_port_probe
,
920 .remove_port
= efx_mcdi_port_remove
,
921 .fini_dmaq
= efx_farch_fini_dmaq
,
922 .prepare_flush
= siena_prepare_flush
,
923 .finish_flush
= siena_finish_flush
,
924 .describe_stats
= siena_describe_nic_stats
,
925 .update_stats
= siena_update_nic_stats
,
926 .start_stats
= efx_mcdi_mac_start_stats
,
927 .pull_stats
= efx_mcdi_mac_pull_stats
,
928 .stop_stats
= efx_mcdi_mac_stop_stats
,
929 .set_id_led
= efx_mcdi_set_id_led
,
930 .push_irq_moderation
= siena_push_irq_moderation
,
931 .reconfigure_mac
= siena_mac_reconfigure
,
932 .check_mac_fault
= efx_mcdi_mac_check_fault
,
933 .reconfigure_port
= efx_mcdi_port_reconfigure
,
934 .get_wol
= siena_get_wol
,
935 .set_wol
= siena_set_wol
,
936 .resume_wol
= siena_init_wol
,
937 .test_chip
= siena_test_chip
,
938 .test_nvram
= efx_mcdi_nvram_test_all
,
939 .mcdi_request
= siena_mcdi_request
,
940 .mcdi_poll_response
= siena_mcdi_poll_response
,
941 .mcdi_read_response
= siena_mcdi_read_response
,
942 .mcdi_poll_reboot
= siena_mcdi_poll_reboot
,
943 .irq_enable_master
= efx_farch_irq_enable_master
,
944 .irq_test_generate
= efx_farch_irq_test_generate
,
945 .irq_disable_non_ev
= efx_farch_irq_disable_master
,
946 .irq_handle_msi
= efx_farch_msi_interrupt
,
947 .irq_handle_legacy
= efx_farch_legacy_interrupt
,
948 .tx_probe
= efx_farch_tx_probe
,
949 .tx_init
= efx_farch_tx_init
,
950 .tx_remove
= efx_farch_tx_remove
,
951 .tx_write
= efx_farch_tx_write
,
952 .rx_push_rss_config
= siena_rx_push_rss_config
,
953 .rx_probe
= efx_farch_rx_probe
,
954 .rx_init
= efx_farch_rx_init
,
955 .rx_remove
= efx_farch_rx_remove
,
956 .rx_write
= efx_farch_rx_write
,
957 .rx_defer_refill
= efx_farch_rx_defer_refill
,
958 .ev_probe
= efx_farch_ev_probe
,
959 .ev_init
= efx_farch_ev_init
,
960 .ev_fini
= efx_farch_ev_fini
,
961 .ev_remove
= efx_farch_ev_remove
,
962 .ev_process
= efx_farch_ev_process
,
963 .ev_read_ack
= efx_farch_ev_read_ack
,
964 .ev_test_generate
= efx_farch_ev_test_generate
,
965 .filter_table_probe
= efx_farch_filter_table_probe
,
966 .filter_table_restore
= efx_farch_filter_table_restore
,
967 .filter_table_remove
= efx_farch_filter_table_remove
,
968 .filter_update_rx_scatter
= efx_farch_filter_update_rx_scatter
,
969 .filter_insert
= efx_farch_filter_insert
,
970 .filter_remove_safe
= efx_farch_filter_remove_safe
,
971 .filter_get_safe
= efx_farch_filter_get_safe
,
972 .filter_clear_rx
= efx_farch_filter_clear_rx
,
973 .filter_count_rx_used
= efx_farch_filter_count_rx_used
,
974 .filter_get_rx_id_limit
= efx_farch_filter_get_rx_id_limit
,
975 .filter_get_rx_ids
= efx_farch_filter_get_rx_ids
,
976 #ifdef CONFIG_RFS_ACCEL
977 .filter_rfs_insert
= efx_farch_filter_rfs_insert
,
978 .filter_rfs_expire_one
= efx_farch_filter_rfs_expire_one
,
980 #ifdef CONFIG_SFC_MTD
981 .mtd_probe
= siena_mtd_probe
,
982 .mtd_rename
= efx_mcdi_mtd_rename
,
983 .mtd_read
= efx_mcdi_mtd_read
,
984 .mtd_erase
= efx_mcdi_mtd_erase
,
985 .mtd_write
= efx_mcdi_mtd_write
,
986 .mtd_sync
= efx_mcdi_mtd_sync
,
988 .ptp_write_host_time
= siena_ptp_write_host_time
,
989 .ptp_set_ts_config
= siena_ptp_set_ts_config
,
991 .revision
= EFX_REV_SIENA_A0
,
992 .txd_ptr_tbl_base
= FR_BZ_TX_DESC_PTR_TBL
,
993 .rxd_ptr_tbl_base
= FR_BZ_RX_DESC_PTR_TBL
,
994 .buf_tbl_base
= FR_BZ_BUF_FULL_TBL
,
995 .evq_ptr_tbl_base
= FR_BZ_EVQ_PTR_TBL
,
996 .evq_rptr_tbl_base
= FR_BZ_EVQ_RPTR
,
997 .max_dma_mask
= DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH
),
998 .rx_prefix_size
= FS_BZ_RX_PREFIX_SIZE
,
999 .rx_hash_offset
= FS_BZ_RX_PREFIX_HASH_OFST
,
1000 .rx_buffer_padding
= 0,
1001 .can_rx_scatter
= true,
1002 .max_interrupt_mode
= EFX_INT_MODE_MSIX
,
1003 .timer_period_max
= 1 << FRF_CZ_TC_TIMER_VAL_WIDTH
,
1004 .offload_features
= (NETIF_F_IP_CSUM
| NETIF_F_IPV6_CSUM
|
1005 NETIF_F_RXHASH
| NETIF_F_NTUPLE
),
1007 .max_rx_ip_filters
= FR_BZ_RX_FILTER_TBL0_ROWS
,
1008 .hwtstamp_filters
= (1 << HWTSTAMP_FILTER_NONE
|
1009 1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT
|
1010 1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC
|
1011 1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ
|
1012 1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT
|
1013 1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC
|
1014 1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ
),