drivers/net/ethernet/stmicro/stmmac/dwmac1000_dma.c

   1 /*******************************************************************************
   2   This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
   3   DWC Ether MAC 10/100/1000 Universal version 3.41a  has been used for
   4   developing this code.
   5
   6   This contains the functions to handle the dma.
   7
   8   Copyright (C) 2007-2009  STMicroelectronics Ltd
   9
  10   This program is free software; you can redistribute it and/or modify it
  11   under the terms and conditions of the GNU General Public License,
  12   version 2, as published by the Free Software Foundation.
  13
  14   This program is distributed in the hope it will be useful, but WITHOUT
  15   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17   more details.
  18
  19   You should have received a copy of the GNU General Public License along with
  20   this program; if not, write to the Free Software Foundation, Inc.,
  21   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  22
  23   The full GNU General Public License is included in this distribution in
  24   the file called "COPYING".
  25
  26   Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
  27 *******************************************************************************/
  28
  29 #include <asm/io.h>
  30 #include "dwmac1000.h"
  31 #include "dwmac_dma.h"
  32
  33 static int dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
  34                               int burst_len, u32 dma_tx, u32 dma_rx, int atds)
  35 {
  36         u32 value = readl(ioaddr + DMA_BUS_MODE);
  37         int limit;
  38
  39         /* DMA SW reset */
  40         value |= DMA_BUS_MODE_SFT_RESET;
  41         writel(value, ioaddr + DMA_BUS_MODE);
  42         limit = 10;
  43         while (limit--) {
  44                 if (!(readl(ioaddr + DMA_BUS_MODE) & DMA_BUS_MODE_SFT_RESET))
  45                         break;
  46                 mdelay(10);
  47         }
  48         if (limit < 0)
  49                 return -EBUSY;
  50
  51         /*
  52          * Set the DMA PBL (Programmable Burst Length) mode
  53          * Before stmmac core 3.50 this mode bit was 4xPBL, and
  54          * post 3.5 mode bit acts as 8*PBL.
  55          * For core rev < 3.5, when the core is set for 4xPBL mode, the
  56          * DMA transfers the data in 4, 8, 16, 32, 64 & 128 beats
  57          * depending on pbl value.
  58          * For core rev > 3.5, when the core is set for 8xPBL mode, the
  59          * DMA transfers the data in 8, 16, 32, 64, 128 & 256 beats
  60          * depending on pbl value.
  61          */
  62         value = DMA_BUS_MODE_PBL | ((pbl << DMA_BUS_MODE_PBL_SHIFT) |
  63                                     (pbl << DMA_BUS_MODE_RPBL_SHIFT));
  64
  65         /* Set the Fixed burst mode */
  66         if (fb)
  67                 value |= DMA_BUS_MODE_FB;
  68
  69         /* Mixed Burst has no effect when fb is set */
  70         if (mb)
  71                 value |= DMA_BUS_MODE_MB;
  72
  73 #ifdef CONFIG_STMMAC_DA
  74         value |= DMA_BUS_MODE_DA;       /* Rx has priority over tx */
  75 #endif
  76
  77         if (atds)
  78                 value |= DMA_BUS_MODE_ATDS;
  79
  80         writel(value, ioaddr + DMA_BUS_MODE);
  81
  82         /* In case of GMAC AXI configuration, program the DMA_AXI_BUS_MODE
  83          * for supported bursts.
  84          *
  85          * Note: This is applicable only for revision GMACv3.61a. For
  86          * older version this register is reserved and shall have no
  87          * effect.
  88          *
  89          * Note:
  90          *  For Fixed Burst Mode: if we directly write 0xFF to this
  91          *  register using the configurations pass from platform code,
  92          *  this would ensure that all bursts supported by core are set
  93          *  and those which are not supported would remain ineffective.
  94          *
  95          *  For Non Fixed Burst Mode: provide the maximum value of the
  96          *  burst length. Any burst equal or below the provided burst
  97          *  length would be allowed to perform.
  98          */
  99         writel(burst_len, ioaddr + DMA_AXI_BUS_MODE);
 100
 101         /* Mask interrupts by writing to CSR7 */
 102         writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
 103
 104         /* RX/TX descriptor base address lists must be written into
 105          * DMA CSR3 and CSR4, respectively
 106          */
 107         writel(dma_tx, ioaddr + DMA_TX_BASE_ADDR);
 108         writel(dma_rx, ioaddr + DMA_RCV_BASE_ADDR);
 109
 110         return 0;
 111 }
 112
 113 static void dwmac1000_dma_operation_mode(void __iomem *ioaddr, int txmode,
 114                                          int rxmode)
 115 {
 116         u32 csr6 = readl(ioaddr + DMA_CONTROL);
 117
 118         if (txmode == SF_DMA_MODE) {
 119                 pr_debug("GMAC: enable TX store and forward mode\n");
 120                 /* Transmit COE type 2 cannot be done in cut-through mode. */
 121                 csr6 |= DMA_CONTROL_TSF;
 122                 /* Operating on second frame increase the performance
 123                  * especially when transmit store-and-forward is used.
 124                  */
 125                 csr6 |= DMA_CONTROL_OSF;
 126         } else {
 127                 pr_debug("GMAC: disabling TX SF (threshold %d)\n", txmode);
 128                 csr6 &= ~DMA_CONTROL_TSF;
 129                 csr6 &= DMA_CONTROL_TC_TX_MASK;
 130                 /* Set the transmit threshold */
 131                 if (txmode <= 32)
 132                         csr6 |= DMA_CONTROL_TTC_32;
 133                 else if (txmode <= 64)
 134                         csr6 |= DMA_CONTROL_TTC_64;
 135                 else if (txmode <= 128)
 136                         csr6 |= DMA_CONTROL_TTC_128;
 137                 else if (txmode <= 192)
 138                         csr6 |= DMA_CONTROL_TTC_192;
 139                 else
 140                         csr6 |= DMA_CONTROL_TTC_256;
 141         }
 142
 143         if (rxmode == SF_DMA_MODE) {
 144                 pr_debug("GMAC: enable RX store and forward mode\n");
 145                 csr6 |= DMA_CONTROL_RSF;
 146         } else {
 147                 pr_debug("GMAC: disable RX SF mode (threshold %d)\n", rxmode);
 148                 csr6 &= ~DMA_CONTROL_RSF;
 149                 csr6 &= DMA_CONTROL_TC_RX_MASK;
 150                 if (rxmode <= 32)
 151                         csr6 |= DMA_CONTROL_RTC_32;
 152                 else if (rxmode <= 64)
 153                         csr6 |= DMA_CONTROL_RTC_64;
 154                 else if (rxmode <= 96)
 155                         csr6 |= DMA_CONTROL_RTC_96;
 156                 else
 157                         csr6 |= DMA_CONTROL_RTC_128;
 158         }
 159
 160         writel(csr6, ioaddr + DMA_CONTROL);
 161 }
 162
 163 static void dwmac1000_dump_dma_regs(void __iomem *ioaddr)
 164 {
 165         int i;
 166         pr_info(" DMA registers\n");
 167         for (i = 0; i < 22; i++) {
 168                 if ((i < 9) || (i > 17)) {
 169                         int offset = i * 4;
 170                         pr_err("\t Reg No. %d (offset 0x%x): 0x%08x\n", i,
 171                                (DMA_BUS_MODE + offset),
 172                                readl(ioaddr + DMA_BUS_MODE + offset));
 173                 }
 174         }
 175 }
 176
 177 static unsigned int dwmac1000_get_hw_feature(void __iomem *ioaddr)
 178 {
 179         return readl(ioaddr + DMA_HW_FEATURE);
 180 }
 181
 182 static void dwmac1000_rx_watchdog(void __iomem *ioaddr, u32 riwt)
 183 {
 184         writel(riwt, ioaddr + DMA_RX_WATCHDOG);
 185 }
 186
 187 const struct stmmac_dma_ops dwmac1000_dma_ops = {
 188         .init = dwmac1000_dma_init,
 189         .dump_regs = dwmac1000_dump_dma_regs,
 190         .dma_mode = dwmac1000_dma_operation_mode,
 191         .enable_dma_transmission = dwmac_enable_dma_transmission,
 192         .enable_dma_irq = dwmac_enable_dma_irq,
 193         .disable_dma_irq = dwmac_disable_dma_irq,
 194         .start_tx = dwmac_dma_start_tx,
 195         .stop_tx = dwmac_dma_stop_tx,
 196         .start_rx = dwmac_dma_start_rx,
 197         .stop_rx = dwmac_dma_stop_rx,
 198         .dma_interrupt = dwmac_dma_interrupt,
 199         .get_hw_feature = dwmac1000_get_hw_feature,
 200         .rx_watchdog = dwmac1000_rx_watchdog,
 201 };