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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / ar9002_calib.c
blobcdc74005650ce9848147ee0e051c64f9df989ffd
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include "ar9002_phy.h"
20
21 #define AR9285_CLCAL_REDO_THRESH 1
22
23 enum ar9002_cal_types {
24 ADC_GAIN_CAL = BIT(0),
25 ADC_DC_CAL = BIT(1),
26 IQ_MISMATCH_CAL = BIT(2),
27 };
28
29 static bool ar9002_hw_is_cal_supported(struct ath_hw *ah,
30 struct ath9k_channel *chan,
31 enum ar9002_cal_types cal_type)
32 {
33 bool supported = false;
34 switch (ah->supp_cals & cal_type) {
35 case IQ_MISMATCH_CAL:
36 supported = true;
37 break;
38 case ADC_GAIN_CAL:
39 case ADC_DC_CAL:
40 /* Run ADC Gain Cal for non-CCK & non 2GHz-HT20 only */
41 if (!((IS_CHAN_2GHZ(chan) || IS_CHAN_A_FAST_CLOCK(ah, chan)) &&
42 IS_CHAN_HT20(chan)))
43 supported = true;
44 break;
45 }
46 return supported;
47 }
48
49 static void ar9002_hw_setup_calibration(struct ath_hw *ah,
50 struct ath9k_cal_list *currCal)
51 {
52 struct ath_common *common = ath9k_hw_common(ah);
53
54 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
55 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
56 currCal->calData->calCountMax);
57
58 switch (currCal->calData->calType) {
59 case IQ_MISMATCH_CAL:
60 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
61 ath_dbg(common, CALIBRATE,
62 "starting IQ Mismatch Calibration\n");
63 break;
64 case ADC_GAIN_CAL:
65 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
66 ath_dbg(common, CALIBRATE, "starting ADC Gain Calibration\n");
67 break;
68 case ADC_DC_CAL:
69 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
70 ath_dbg(common, CALIBRATE, "starting ADC DC Calibration\n");
71 break;
72 }
73
74 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
75 AR_PHY_TIMING_CTRL4_DO_CAL);
76 }
77
78 static bool ar9002_hw_per_calibration(struct ath_hw *ah,
79 struct ath9k_channel *ichan,
80 u8 rxchainmask,
81 struct ath9k_cal_list *currCal)
82 {
83 struct ath9k_hw_cal_data *caldata = ah->caldata;
84 bool iscaldone = false;
85
86 if (currCal->calState == CAL_RUNNING) {
87 if (!(REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
88 AR_PHY_TIMING_CTRL4_DO_CAL)) {
89
90 currCal->calData->calCollect(ah);
91 ah->cal_samples++;
92
93 if (ah->cal_samples >=
94 currCal->calData->calNumSamples) {
95 int i, numChains = 0;
96 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
97 if (rxchainmask & (1 << i))
98 numChains++;
99 }
100
101 currCal->calData->calPostProc(ah, numChains);
102 caldata->CalValid |= currCal->calData->calType;
103 currCal->calState = CAL_DONE;
104 iscaldone = true;
105 } else {
106 ar9002_hw_setup_calibration(ah, currCal);
107 }
108 }
109 } else if (!(caldata->CalValid & currCal->calData->calType)) {
110 ath9k_hw_reset_calibration(ah, currCal);
111 }
112
113 return iscaldone;
114 }
115
116 static void ar9002_hw_iqcal_collect(struct ath_hw *ah)
117 {
118 int i;
119
120 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
121 ah->totalPowerMeasI[i] +=
122 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
123 ah->totalPowerMeasQ[i] +=
124 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
125 ah->totalIqCorrMeas[i] +=
126 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
127 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
128 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
129 ah->cal_samples, i, ah->totalPowerMeasI[i],
130 ah->totalPowerMeasQ[i],
131 ah->totalIqCorrMeas[i]);
132 }
133 }
134
135 static void ar9002_hw_adc_gaincal_collect(struct ath_hw *ah)
136 {
137 int i;
138
139 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
140 ah->totalAdcIOddPhase[i] +=
141 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
142 ah->totalAdcIEvenPhase[i] +=
143 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
144 ah->totalAdcQOddPhase[i] +=
145 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
146 ah->totalAdcQEvenPhase[i] +=
147 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
148
149 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
150 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
151 ah->cal_samples, i,
152 ah->totalAdcIOddPhase[i],
153 ah->totalAdcIEvenPhase[i],
154 ah->totalAdcQOddPhase[i],
155 ah->totalAdcQEvenPhase[i]);
156 }
157 }
158
159 static void ar9002_hw_adc_dccal_collect(struct ath_hw *ah)
160 {
161 int i;
162
163 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
164 ah->totalAdcDcOffsetIOddPhase[i] +=
165 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
166 ah->totalAdcDcOffsetIEvenPhase[i] +=
167 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
168 ah->totalAdcDcOffsetQOddPhase[i] +=
169 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
170 ah->totalAdcDcOffsetQEvenPhase[i] +=
171 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
172
173 ath_dbg(ath9k_hw_common(ah), CALIBRATE,
174 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; oddq=0x%08x; evenq=0x%08x;\n",
175 ah->cal_samples, i,
176 ah->totalAdcDcOffsetIOddPhase[i],
177 ah->totalAdcDcOffsetIEvenPhase[i],
178 ah->totalAdcDcOffsetQOddPhase[i],
179 ah->totalAdcDcOffsetQEvenPhase[i]);
180 }
181 }
182
183 static void ar9002_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
184 {
185 struct ath_common *common = ath9k_hw_common(ah);
186 u32 powerMeasQ, powerMeasI, iqCorrMeas;
187 u32 qCoffDenom, iCoffDenom;
188 int32_t qCoff, iCoff;
189 int iqCorrNeg, i;
190
191 for (i = 0; i < numChains; i++) {
192 powerMeasI = ah->totalPowerMeasI[i];
193 powerMeasQ = ah->totalPowerMeasQ[i];
194 iqCorrMeas = ah->totalIqCorrMeas[i];
195
196 ath_dbg(common, CALIBRATE,
197 "Starting IQ Cal and Correction for Chain %d\n",
198 i);
199
200 ath_dbg(common, CALIBRATE,
201 "Original: Chn %d iq_corr_meas = 0x%08x\n",
202 i, ah->totalIqCorrMeas[i]);
203
204 iqCorrNeg = 0;
205
206 if (iqCorrMeas > 0x80000000) {
207 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
208 iqCorrNeg = 1;
209 }
210
211 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_i = 0x%08x\n",
212 i, powerMeasI);
213 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_q = 0x%08x\n",
214 i, powerMeasQ);
215 ath_dbg(common, CALIBRATE, "iqCorrNeg is 0x%08x\n", iqCorrNeg);
216
217 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
218 qCoffDenom = powerMeasQ / 64;
219
220 if ((powerMeasQ != 0) && (iCoffDenom != 0) &&
221 (qCoffDenom != 0)) {
222 iCoff = iqCorrMeas / iCoffDenom;
223 qCoff = powerMeasI / qCoffDenom - 64;
224 ath_dbg(common, CALIBRATE, "Chn %d iCoff = 0x%08x\n",
225 i, iCoff);
226 ath_dbg(common, CALIBRATE, "Chn %d qCoff = 0x%08x\n",
227 i, qCoff);
228
229 iCoff = iCoff & 0x3f;
230 ath_dbg(common, CALIBRATE,
231 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
232 if (iqCorrNeg == 0x0)
233 iCoff = 0x40 - iCoff;
234
235 if (qCoff > 15)
236 qCoff = 15;
237 else if (qCoff <= -16)
238 qCoff = -16;
239
240 ath_dbg(common, CALIBRATE,
241 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
242 i, iCoff, qCoff);
243
244 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
245 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
246 iCoff);
247 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
248 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
249 qCoff);
250 ath_dbg(common, CALIBRATE,
251 "IQ Cal and Correction done for Chain %d\n",
252 i);
253 }
254 }
255
256 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
257 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
258 }
259
260 static void ar9002_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
261 {
262 struct ath_common *common = ath9k_hw_common(ah);
263 u32 iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset, qEvenMeasOffset;
264 u32 qGainMismatch, iGainMismatch, val, i;
265
266 for (i = 0; i < numChains; i++) {
267 iOddMeasOffset = ah->totalAdcIOddPhase[i];
268 iEvenMeasOffset = ah->totalAdcIEvenPhase[i];
269 qOddMeasOffset = ah->totalAdcQOddPhase[i];
270 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
271
272 ath_dbg(common, CALIBRATE,
273 "Starting ADC Gain Cal for Chain %d\n", i);
274
275 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_i = 0x%08x\n",
276 i, iOddMeasOffset);
277 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_i = 0x%08x\n",
278 i, iEvenMeasOffset);
279 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_q = 0x%08x\n",
280 i, qOddMeasOffset);
281 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_q = 0x%08x\n",
282 i, qEvenMeasOffset);
283
284 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
285 iGainMismatch =
286 ((iEvenMeasOffset * 32) /
287 iOddMeasOffset) & 0x3f;
288 qGainMismatch =
289 ((qOddMeasOffset * 32) /
290 qEvenMeasOffset) & 0x3f;
291
292 ath_dbg(common, CALIBRATE,
293 "Chn %d gain_mismatch_i = 0x%08x\n",
294 i, iGainMismatch);
295 ath_dbg(common, CALIBRATE,
296 "Chn %d gain_mismatch_q = 0x%08x\n",
297 i, qGainMismatch);
298
299 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
300 val &= 0xfffff000;
301 val |= (qGainMismatch) | (iGainMismatch << 6);
302 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
303
304 ath_dbg(common, CALIBRATE,
305 "ADC Gain Cal done for Chain %d\n", i);
306 }
307 }
308
309 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
310 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
311 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
312 }
313
314 static void ar9002_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
315 {
316 struct ath_common *common = ath9k_hw_common(ah);
317 u32 iOddMeasOffset, iEvenMeasOffset, val, i;
318 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
319 const struct ath9k_percal_data *calData =
320 ah->cal_list_curr->calData;
321 u32 numSamples =
322 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
323
324 for (i = 0; i < numChains; i++) {
325 iOddMeasOffset = ah->totalAdcDcOffsetIOddPhase[i];
326 iEvenMeasOffset = ah->totalAdcDcOffsetIEvenPhase[i];
327 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
328 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
329
330 ath_dbg(common, CALIBRATE,
331 "Starting ADC DC Offset Cal for Chain %d\n", i);
332
333 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_i = %d\n",
334 i, iOddMeasOffset);
335 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_i = %d\n",
336 i, iEvenMeasOffset);
337 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_odd_q = %d\n",
338 i, qOddMeasOffset);
339 ath_dbg(common, CALIBRATE, "Chn %d pwr_meas_even_q = %d\n",
340 i, qEvenMeasOffset);
341
342 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
343 numSamples) & 0x1ff;
344 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
345 numSamples) & 0x1ff;
346
347 ath_dbg(common, CALIBRATE,
348 "Chn %d dc_offset_mismatch_i = 0x%08x\n",
349 i, iDcMismatch);
350 ath_dbg(common, CALIBRATE,
351 "Chn %d dc_offset_mismatch_q = 0x%08x\n",
352 i, qDcMismatch);
353
354 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
355 val &= 0xc0000fff;
356 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
357 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
358
359 ath_dbg(common, CALIBRATE,
360 "ADC DC Offset Cal done for Chain %d\n", i);
361 }
362
363 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
364 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
365 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
366 }
367
368 static void ar9287_hw_olc_temp_compensation(struct ath_hw *ah)
369 {
370 u32 rddata;
371 int32_t delta, currPDADC, slope;
372
373 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
374 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
375
376 if (ah->initPDADC == 0 || currPDADC == 0) {
377 /*
378 * Zero value indicates that no frames have been transmitted
379 * yet, can't do temperature compensation until frames are
380 * transmitted.
381 */
382 return;
383 } else {
384 slope = ah->eep_ops->get_eeprom(ah, EEP_TEMPSENSE_SLOPE);
385
386 if (slope == 0) { /* to avoid divide by zero case */
387 delta = 0;
388 } else {
389 delta = ((currPDADC - ah->initPDADC)*4) / slope;
390 }
391 REG_RMW_FIELD(ah, AR_PHY_CH0_TX_PWRCTRL11,
392 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
393 REG_RMW_FIELD(ah, AR_PHY_CH1_TX_PWRCTRL11,
394 AR_PHY_TX_PWRCTRL_OLPC_TEMP_COMP, delta);
395 }
396 }
397
398 static void ar9280_hw_olc_temp_compensation(struct ath_hw *ah)
399 {
400 u32 rddata, i;
401 int delta, currPDADC, regval;
402
403 rddata = REG_READ(ah, AR_PHY_TX_PWRCTRL4);
404 currPDADC = MS(rddata, AR_PHY_TX_PWRCTRL_PD_AVG_OUT);
405
406 if (ah->initPDADC == 0 || currPDADC == 0)
407 return;
408
409 if (ah->eep_ops->get_eeprom(ah, EEP_DAC_HPWR_5G))
410 delta = (currPDADC - ah->initPDADC + 4) / 8;
411 else
412 delta = (currPDADC - ah->initPDADC + 5) / 10;
413
414 if (delta != ah->PDADCdelta) {
415 ah->PDADCdelta = delta;
416 for (i = 1; i < AR9280_TX_GAIN_TABLE_SIZE; i++) {
417 regval = ah->originalGain[i] - delta;
418 if (regval < 0)
419 regval = 0;
420
421 REG_RMW_FIELD(ah,
422 AR_PHY_TX_GAIN_TBL1 + i * 4,
423 AR_PHY_TX_GAIN, regval);
424 }
425 }
426 }
427
428 static void ar9271_hw_pa_cal(struct ath_hw *ah, bool is_reset)
429 {
430 u32 regVal;
431 unsigned int i;
432 u32 regList[][2] = {
433 { 0x786c, 0 },
434 { 0x7854, 0 },
435 { 0x7820, 0 },
436 { 0x7824, 0 },
437 { 0x7868, 0 },
438 { 0x783c, 0 },
439 { 0x7838, 0 } ,
440 { 0x7828, 0 } ,
441 };
442
443 for (i = 0; i < ARRAY_SIZE(regList); i++)
444 regList[i][1] = REG_READ(ah, regList[i][0]);
445
446 regVal = REG_READ(ah, 0x7834);
447 regVal &= (~(0x1));
448 REG_WRITE(ah, 0x7834, regVal);
449 regVal = REG_READ(ah, 0x9808);
450 regVal |= (0x1 << 27);
451 REG_WRITE(ah, 0x9808, regVal);
452
453 /* 786c,b23,1, pwddac=1 */
454 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
455 /* 7854, b5,1, pdrxtxbb=1 */
456 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
457 /* 7854, b7,1, pdv2i=1 */
458 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
459 /* 7854, b8,1, pddacinterface=1 */
460 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
461 /* 7824,b12,0, offcal=0 */
462 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
463 /* 7838, b1,0, pwddb=0 */
464 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
465 /* 7820,b11,0, enpacal=0 */
466 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
467 /* 7820,b25,1, pdpadrv1=0 */
468 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
469 /* 7820,b24,0, pdpadrv2=0 */
470 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
471 /* 7820,b23,0, pdpaout=0 */
472 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
473 /* 783c,b14-16,7, padrvgn2tab_0=7 */
474 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
475 /*
476 * 7838,b29-31,0, padrvgn1tab_0=0
477 * does not matter since we turn it off
478 */
479 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
480
481 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9271_AN_RF2G3_CCOMP, 0xfff);
482
483 /* Set:
484 * localmode=1,bmode=1,bmoderxtx=1,synthon=1,
485 * txon=1,paon=1,oscon=1,synthon_force=1
486 */
487 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
488 udelay(30);
489 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9271_AN_RF2G6_OFFS, 0);
490
491 /* find off_6_1; */
492 for (i = 6; i > 0; i--) {
493 regVal = REG_READ(ah, 0x7834);
494 regVal |= (1 << (20 + i));
495 REG_WRITE(ah, 0x7834, regVal);
496 udelay(1);
497 /* regVal = REG_READ(ah, 0x7834); */
498 regVal &= (~(0x1 << (20 + i)));
499 regVal |= (MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9)
500 << (20 + i));
501 REG_WRITE(ah, 0x7834, regVal);
502 }
503
504 regVal = (regVal >> 20) & 0x7f;
505
506 /* Update PA cal info */
507 if ((!is_reset) && (ah->pacal_info.prev_offset == regVal)) {
508 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
509 ah->pacal_info.max_skipcount =
510 2 * ah->pacal_info.max_skipcount;
511 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
512 } else {
513 ah->pacal_info.max_skipcount = 1;
514 ah->pacal_info.skipcount = 0;
515 ah->pacal_info.prev_offset = regVal;
516 }
517
518 ENABLE_REGWRITE_BUFFER(ah);
519
520 regVal = REG_READ(ah, 0x7834);
521 regVal |= 0x1;
522 REG_WRITE(ah, 0x7834, regVal);
523 regVal = REG_READ(ah, 0x9808);
524 regVal &= (~(0x1 << 27));
525 REG_WRITE(ah, 0x9808, regVal);
526
527 for (i = 0; i < ARRAY_SIZE(regList); i++)
528 REG_WRITE(ah, regList[i][0], regList[i][1]);
529
530 REGWRITE_BUFFER_FLUSH(ah);
531 }
532
533 static inline void ar9285_hw_pa_cal(struct ath_hw *ah, bool is_reset)
534 {
535 struct ath_common *common = ath9k_hw_common(ah);
536 u32 regVal;
537 int i, offset, offs_6_1, offs_0;
538 u32 ccomp_org, reg_field;
539 u32 regList[][2] = {
540 { 0x786c, 0 },
541 { 0x7854, 0 },
542 { 0x7820, 0 },
543 { 0x7824, 0 },
544 { 0x7868, 0 },
545 { 0x783c, 0 },
546 { 0x7838, 0 },
547 };
548
549 ath_dbg(common, CALIBRATE, "Running PA Calibration\n");
550
551 /* PA CAL is not needed for high power solution */
552 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
553 AR5416_EEP_TXGAIN_HIGH_POWER)
554 return;
555
556 for (i = 0; i < ARRAY_SIZE(regList); i++)
557 regList[i][1] = REG_READ(ah, regList[i][0]);
558
559 regVal = REG_READ(ah, 0x7834);
560 regVal &= (~(0x1));
561 REG_WRITE(ah, 0x7834, regVal);
562 regVal = REG_READ(ah, 0x9808);
563 regVal |= (0x1 << 27);
564 REG_WRITE(ah, 0x9808, regVal);
565
566 REG_RMW_FIELD(ah, AR9285_AN_TOP3, AR9285_AN_TOP3_PWDDAC, 1);
567 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDRXTXBB1, 1);
568 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDV2I, 1);
569 REG_RMW_FIELD(ah, AR9285_AN_RXTXBB1, AR9285_AN_RXTXBB1_PDDACIF, 1);
570 REG_RMW_FIELD(ah, AR9285_AN_RF2G2, AR9285_AN_RF2G2_OFFCAL, 0);
571 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PWDDB, 0);
572 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_ENPACAL, 0);
573 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV1, 0);
574 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPADRV2, 0);
575 REG_RMW_FIELD(ah, AR9285_AN_RF2G1, AR9285_AN_RF2G1_PDPAOUT, 0);
576 REG_RMW_FIELD(ah, AR9285_AN_RF2G8, AR9285_AN_RF2G8_PADRVGN2TAB0, 7);
577 REG_RMW_FIELD(ah, AR9285_AN_RF2G7, AR9285_AN_RF2G7_PADRVGN2TAB0, 0);
578 ccomp_org = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_CCOMP);
579 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, 0xf);
580
581 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0);
582 udelay(30);
583 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, 0);
584 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 0);
585
586 for (i = 6; i > 0; i--) {
587 regVal = REG_READ(ah, 0x7834);
588 regVal |= (1 << (19 + i));
589 REG_WRITE(ah, 0x7834, regVal);
590 udelay(1);
591 regVal = REG_READ(ah, 0x7834);
592 regVal &= (~(0x1 << (19 + i)));
593 reg_field = MS(REG_READ(ah, 0x7840), AR9285_AN_RXTXBB1_SPARE9);
594 regVal |= (reg_field << (19 + i));
595 REG_WRITE(ah, 0x7834, regVal);
596 }
597
598 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, 1);
599 udelay(1);
600 reg_field = MS(REG_READ(ah, AR9285_AN_RF2G9), AR9285_AN_RXTXBB1_SPARE9);
601 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, reg_field);
602 offs_6_1 = MS(REG_READ(ah, AR9285_AN_RF2G6), AR9285_AN_RF2G6_OFFS);
603 offs_0 = MS(REG_READ(ah, AR9285_AN_RF2G3), AR9285_AN_RF2G3_PDVCCOMP);
604
605 offset = (offs_6_1<<1) | offs_0;
606 offset = offset - 0;
607 offs_6_1 = offset>>1;
608 offs_0 = offset & 1;
609
610 if ((!is_reset) && (ah->pacal_info.prev_offset == offset)) {
611 if (ah->pacal_info.max_skipcount < MAX_PACAL_SKIPCOUNT)
612 ah->pacal_info.max_skipcount =
613 2 * ah->pacal_info.max_skipcount;
614 ah->pacal_info.skipcount = ah->pacal_info.max_skipcount;
615 } else {
616 ah->pacal_info.max_skipcount = 1;
617 ah->pacal_info.skipcount = 0;
618 ah->pacal_info.prev_offset = offset;
619 }
620
621 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_OFFS, offs_6_1);
622 REG_RMW_FIELD(ah, AR9285_AN_RF2G3, AR9285_AN_RF2G3_PDVCCOMP, offs_0);
623
624 regVal = REG_READ(ah, 0x7834);
625 regVal |= 0x1;
626 REG_WRITE(ah, 0x7834, regVal);
627 regVal = REG_READ(ah, 0x9808);
628 regVal &= (~(0x1 << 27));
629 REG_WRITE(ah, 0x9808, regVal);
630
631 for (i = 0; i < ARRAY_SIZE(regList); i++)
632 REG_WRITE(ah, regList[i][0], regList[i][1]);
633
634 REG_RMW_FIELD(ah, AR9285_AN_RF2G6, AR9285_AN_RF2G6_CCOMP, ccomp_org);
635 }
636
637 static void ar9002_hw_pa_cal(struct ath_hw *ah, bool is_reset)
638 {
639 if (AR_SREV_9271(ah)) {
640 if (is_reset || !ah->pacal_info.skipcount)
641 ar9271_hw_pa_cal(ah, is_reset);
642 else
643 ah->pacal_info.skipcount--;
644 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
645 if (is_reset || !ah->pacal_info.skipcount)
646 ar9285_hw_pa_cal(ah, is_reset);
647 else
648 ah->pacal_info.skipcount--;
649 }
650 }
651
652 static void ar9002_hw_olc_temp_compensation(struct ath_hw *ah)
653 {
654 if (OLC_FOR_AR9287_10_LATER)
655 ar9287_hw_olc_temp_compensation(ah);
656 else if (OLC_FOR_AR9280_20_LATER)
657 ar9280_hw_olc_temp_compensation(ah);
658 }
659
660 static bool ar9002_hw_calibrate(struct ath_hw *ah,
661 struct ath9k_channel *chan,
662 u8 rxchainmask,
663 bool longcal)
664 {
665 bool iscaldone = true;
666 struct ath9k_cal_list *currCal = ah->cal_list_curr;
667 bool nfcal, nfcal_pending = false;
668
669 nfcal = !!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF);
670 if (ah->caldata)
671 nfcal_pending = test_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
672
673 if (currCal && !nfcal &&
674 (currCal->calState == CAL_RUNNING ||
675 currCal->calState == CAL_WAITING)) {
676 iscaldone = ar9002_hw_per_calibration(ah, chan,
677 rxchainmask, currCal);
678 if (iscaldone) {
679 ah->cal_list_curr = currCal = currCal->calNext;
680
681 if (currCal->calState == CAL_WAITING) {
682 iscaldone = false;
683 ath9k_hw_reset_calibration(ah, currCal);
684 }
685 }
686 }
687
688 /* Do NF cal only at longer intervals */
689 if (longcal || nfcal_pending) {
690 /*
691 * Get the value from the previous NF cal and update
692 * history buffer.
693 */
694 if (ath9k_hw_getnf(ah, chan)) {
695 /*
696 * Load the NF from history buffer of the current
697 * channel.
698 * NF is slow time-variant, so it is OK to use a
699 * historical value.
700 */
701 ath9k_hw_loadnf(ah, ah->curchan);
702 }
703
704 if (longcal) {
705 ath9k_hw_start_nfcal(ah, false);
706 /* Do periodic PAOffset Cal */
707 ar9002_hw_pa_cal(ah, false);
708 ar9002_hw_olc_temp_compensation(ah);
709 }
710 }
711
712 return iscaldone;
713 }
714
715 /* Carrier leakage Calibration fix */
716 static bool ar9285_hw_cl_cal(struct ath_hw *ah, struct ath9k_channel *chan)
717 {
718 struct ath_common *common = ath9k_hw_common(ah);
719
720 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
721 if (IS_CHAN_HT20(chan)) {
722 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
723 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
724 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
725 AR_PHY_AGC_CONTROL_FLTR_CAL);
726 REG_CLR_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
727 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
728 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
729 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
730 ath_dbg(common, CALIBRATE,
731 "offset calibration failed to complete in %d ms; noisy environment?\n",
732 AH_WAIT_TIMEOUT / 1000);
733 return false;
734 }
735 REG_CLR_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN);
736 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE);
737 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
738 }
739 REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
740 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
741 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE);
742 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
743 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
744 0, AH_WAIT_TIMEOUT)) {
745 ath_dbg(common, CALIBRATE,
746 "offset calibration failed to complete in %d ms; noisy environment?\n",
747 AH_WAIT_TIMEOUT / 1000);
748 return false;
749 }
750
751 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC);
752 REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE);
753 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL);
754
755 return true;
756 }
757
758 static bool ar9285_hw_clc(struct ath_hw *ah, struct ath9k_channel *chan)
759 {
760 int i;
761 u_int32_t txgain_max;
762 u_int32_t clc_gain, gain_mask = 0, clc_num = 0;
763 u_int32_t reg_clc_I0, reg_clc_Q0;
764 u_int32_t i0_num = 0;
765 u_int32_t q0_num = 0;
766 u_int32_t total_num = 0;
767 u_int32_t reg_rf2g5_org;
768 bool retv = true;
769
770 if (!(ar9285_hw_cl_cal(ah, chan)))
771 return false;
772
773 txgain_max = MS(REG_READ(ah, AR_PHY_TX_PWRCTRL7),
774 AR_PHY_TX_PWRCTRL_TX_GAIN_TAB_MAX);
775
776 for (i = 0; i < (txgain_max+1); i++) {
777 clc_gain = (REG_READ(ah, (AR_PHY_TX_GAIN_TBL1+(i<<2))) &
778 AR_PHY_TX_GAIN_CLC) >> AR_PHY_TX_GAIN_CLC_S;
779 if (!(gain_mask & (1 << clc_gain))) {
780 gain_mask |= (1 << clc_gain);
781 clc_num++;
782 }
783 }
784
785 for (i = 0; i < clc_num; i++) {
786 reg_clc_I0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
787 & AR_PHY_CLC_I0) >> AR_PHY_CLC_I0_S;
788 reg_clc_Q0 = (REG_READ(ah, (AR_PHY_CLC_TBL1 + (i << 2)))
789 & AR_PHY_CLC_Q0) >> AR_PHY_CLC_Q0_S;
790 if (reg_clc_I0 == 0)
791 i0_num++;
792
793 if (reg_clc_Q0 == 0)
794 q0_num++;
795 }
796 total_num = i0_num + q0_num;
797 if (total_num > AR9285_CLCAL_REDO_THRESH) {
798 reg_rf2g5_org = REG_READ(ah, AR9285_RF2G5);
799 if (AR_SREV_9285E_20(ah)) {
800 REG_WRITE(ah, AR9285_RF2G5,
801 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
802 AR9285_RF2G5_IC50TX_XE_SET);
803 } else {
804 REG_WRITE(ah, AR9285_RF2G5,
805 (reg_rf2g5_org & AR9285_RF2G5_IC50TX) |
806 AR9285_RF2G5_IC50TX_SET);
807 }
808 retv = ar9285_hw_cl_cal(ah, chan);
809 REG_WRITE(ah, AR9285_RF2G5, reg_rf2g5_org);
810 }
811 return retv;
812 }
813
814 static bool ar9002_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
815 {
816 struct ath_common *common = ath9k_hw_common(ah);
817
818 if (AR_SREV_9271(ah)) {
819 if (!ar9285_hw_cl_cal(ah, chan))
820 return false;
821 } else if (AR_SREV_9285(ah) && AR_SREV_9285_12_OR_LATER(ah)) {
822 if (!ar9285_hw_clc(ah, chan))
823 return false;
824 } else {
825 if (AR_SREV_9280_20_OR_LATER(ah)) {
826 if (!AR_SREV_9287_11_OR_LATER(ah))
827 REG_CLR_BIT(ah, AR_PHY_ADC_CTL,
828 AR_PHY_ADC_CTL_OFF_PWDADC);
829 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
830 AR_PHY_AGC_CONTROL_FLTR_CAL);
831 }
832
833 /* Calibrate the AGC */
834 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
835 REG_READ(ah, AR_PHY_AGC_CONTROL) |
836 AR_PHY_AGC_CONTROL_CAL);
837
838 /* Poll for offset calibration complete */
839 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
840 AR_PHY_AGC_CONTROL_CAL,
841 0, AH_WAIT_TIMEOUT)) {
842 ath_dbg(common, CALIBRATE,
843 "offset calibration failed to complete in %d ms; noisy environment?\n",
844 AH_WAIT_TIMEOUT / 1000);
845 return false;
846 }
847
848 if (AR_SREV_9280_20_OR_LATER(ah)) {
849 if (!AR_SREV_9287_11_OR_LATER(ah))
850 REG_SET_BIT(ah, AR_PHY_ADC_CTL,
851 AR_PHY_ADC_CTL_OFF_PWDADC);
852 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
853 AR_PHY_AGC_CONTROL_FLTR_CAL);
854 }
855 }
856
857 /* Do PA Calibration */
858 ar9002_hw_pa_cal(ah, true);
859
860 if (ah->caldata)
861 set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
862
863 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL;
864
865 /* Enable IQ, ADC Gain and ADC DC offset CALs */
866 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
867 ah->supp_cals = IQ_MISMATCH_CAL;
868
869 if (AR_SREV_9160_10_OR_LATER(ah))
870 ah->supp_cals |= ADC_GAIN_CAL | ADC_DC_CAL;
871
872 if (AR_SREV_9287(ah))
873 ah->supp_cals &= ~ADC_GAIN_CAL;
874
875 if (ar9002_hw_is_cal_supported(ah, chan, ADC_GAIN_CAL)) {
876 INIT_CAL(&ah->adcgain_caldata);
877 INSERT_CAL(ah, &ah->adcgain_caldata);
878 ath_dbg(common, CALIBRATE,
879 "enabling ADC Gain Calibration\n");
880 }
881
882 if (ar9002_hw_is_cal_supported(ah, chan, ADC_DC_CAL)) {
883 INIT_CAL(&ah->adcdc_caldata);
884 INSERT_CAL(ah, &ah->adcdc_caldata);
885 ath_dbg(common, CALIBRATE,
886 "enabling ADC DC Calibration\n");
887 }
888
889 if (ar9002_hw_is_cal_supported(ah, chan, IQ_MISMATCH_CAL)) {
890 INIT_CAL(&ah->iq_caldata);
891 INSERT_CAL(ah, &ah->iq_caldata);
892 ath_dbg(common, CALIBRATE, "enabling IQ Calibration\n");
893 }
894
895 ah->cal_list_curr = ah->cal_list;
896
897 if (ah->cal_list_curr)
898 ath9k_hw_reset_calibration(ah, ah->cal_list_curr);
899 }
900
901 if (ah->caldata)
902 ah->caldata->CalValid = 0;
903
904 return true;
905 }
906
907 static const struct ath9k_percal_data iq_cal_multi_sample = {
908 IQ_MISMATCH_CAL,
909 MAX_CAL_SAMPLES,
910 PER_MIN_LOG_COUNT,
911 ar9002_hw_iqcal_collect,
912 ar9002_hw_iqcalibrate
913 };
914 static const struct ath9k_percal_data iq_cal_single_sample = {
915 IQ_MISMATCH_CAL,
916 MIN_CAL_SAMPLES,
917 PER_MAX_LOG_COUNT,
918 ar9002_hw_iqcal_collect,
919 ar9002_hw_iqcalibrate
920 };
921 static const struct ath9k_percal_data adc_gain_cal_multi_sample = {
922 ADC_GAIN_CAL,
923 MAX_CAL_SAMPLES,
924 PER_MIN_LOG_COUNT,
925 ar9002_hw_adc_gaincal_collect,
926 ar9002_hw_adc_gaincal_calibrate
927 };
928 static const struct ath9k_percal_data adc_gain_cal_single_sample = {
929 ADC_GAIN_CAL,
930 MIN_CAL_SAMPLES,
931 PER_MAX_LOG_COUNT,
932 ar9002_hw_adc_gaincal_collect,
933 ar9002_hw_adc_gaincal_calibrate
934 };
935 static const struct ath9k_percal_data adc_dc_cal_multi_sample = {
936 ADC_DC_CAL,
937 MAX_CAL_SAMPLES,
938 PER_MIN_LOG_COUNT,
939 ar9002_hw_adc_dccal_collect,
940 ar9002_hw_adc_dccal_calibrate
941 };
942 static const struct ath9k_percal_data adc_dc_cal_single_sample = {
943 ADC_DC_CAL,
944 MIN_CAL_SAMPLES,
945 PER_MAX_LOG_COUNT,
946 ar9002_hw_adc_dccal_collect,
947 ar9002_hw_adc_dccal_calibrate
948 };
949
950 static void ar9002_hw_init_cal_settings(struct ath_hw *ah)
951 {
952 if (AR_SREV_9100(ah)) {
953 ah->iq_caldata.calData = &iq_cal_multi_sample;
954 ah->supp_cals = IQ_MISMATCH_CAL;
955 return;
956 }
957
958 if (AR_SREV_9160_10_OR_LATER(ah)) {
959 if (AR_SREV_9280_20_OR_LATER(ah)) {
960 ah->iq_caldata.calData = &iq_cal_single_sample;
961 ah->adcgain_caldata.calData =
962 &adc_gain_cal_single_sample;
963 ah->adcdc_caldata.calData =
964 &adc_dc_cal_single_sample;
965 } else {
966 ah->iq_caldata.calData = &iq_cal_multi_sample;
967 ah->adcgain_caldata.calData =
968 &adc_gain_cal_multi_sample;
969 ah->adcdc_caldata.calData =
970 &adc_dc_cal_multi_sample;
971 }
972 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
973
974 if (AR_SREV_9287(ah))
975 ah->supp_cals &= ~ADC_GAIN_CAL;
976 }
977 }
978
979 void ar9002_hw_attach_calib_ops(struct ath_hw *ah)
980 {
981 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
982 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
983
984 priv_ops->init_cal_settings = ar9002_hw_init_cal_settings;
985 priv_ops->init_cal = ar9002_hw_init_cal;
986 priv_ops->setup_calibration = ar9002_hw_setup_calibration;
987
988 ops->calibrate = ar9002_hw_calibrate;
989 }
Linux with added FPC-III support