| blob | ec1da0cc25f53b14412414f2d3aebef7eb1224cc |
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
33 /* General hardware code for the AR9003 hadware family */
35 /*
36 * The AR9003 family uses a new INI format (pre, core, post
37 * arrays per subsystem). This provides support for the
38 * AR9003 2.2 chipsets.
39 */
41 {
43 /* mac */
45 ar9331_1p1_mac_core);
47 ar9331_1p1_mac_postamble);
49 /* bb */
51 ar9331_1p1_baseband_core);
53 ar9331_1p1_baseband_postamble);
55 /* radio */
57 ar9331_1p1_radio_core);
59 /* soc */
61 ar9331_1p1_soc_preamble);
63 ar9331_1p1_soc_postamble);
65 /* rx/tx gain */
67 ar9331_common_rx_gain_1p1);
69 ar9331_modes_lowest_ob_db_tx_gain_1p1);
71 /* Japan 2484 Mhz CCK */
73 ar9331_1p1_baseband_core_txfir_coeff_japan_2484);
75 /* additional clock settings */
78 ar9331_1p1_xtal_25M);
79 else
81 ar9331_1p1_xtal_40M);
83 /* mac */
85 ar9331_1p2_mac_core);
87 ar9331_1p2_mac_postamble);
89 /* bb */
91 ar9331_1p2_baseband_core);
93 ar9331_1p2_baseband_postamble);
95 /* radio */
97 ar9331_1p2_radio_core);
99 /* soc */
101 ar9331_1p2_soc_preamble);
103 ar9331_1p2_soc_postamble);
105 /* rx/tx gain */
107 ar9331_common_rx_gain_1p2);
109 ar9331_modes_lowest_ob_db_tx_gain_1p2);
111 /* Japan 2484 Mhz CCK */
113 ar9331_1p2_baseband_core_txfir_coeff_japan_2484);
115 /* additional clock settings */
118 ar9331_1p2_xtal_25M);
119 else
121 ar9331_1p2_xtal_40M);
123 /* mac */
125 ar9340_1p0_mac_core);
127 ar9340_1p0_mac_postamble);
129 /* bb */
131 ar9340_1p0_baseband_core);
133 ar9340_1p0_baseband_postamble);
135 /* radio */
137 ar9340_1p0_radio_core);
139 ar9340_1p0_radio_postamble);
141 /* soc */
143 ar9340_1p0_soc_preamble);
145 ar9340_1p0_soc_postamble);
147 /* rx/tx gain */
149 ar9340Common_wo_xlna_rx_gain_table_1p0);
151 ar9340Modes_high_ob_db_tx_gain_table_1p0);
154 ar9340Modes_fast_clock_1p0);
156 ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
158 ar9340_1p0_baseband_postamble_dfs_channel);
162 ar9340_1p0_radio_core_40M);
164 /* mac */
166 ar9485_1_1_mac_core);
168 ar9485_1_1_mac_postamble);
170 /* bb */
173 ar9485_1_1_baseband_core);
175 ar9485_1_1_baseband_postamble);
177 /* radio */
179 ar9485_1_1_radio_core);
181 ar9485_1_1_radio_postamble);
183 /* soc */
185 ar9485_1_1_soc_preamble);
187 /* rx/tx gain */
189 ar9485Common_wo_xlna_rx_gain_1_1);
191 ar9485_modes_lowest_ob_db_tx_gain_1_1);
193 /* Japan 2484 Mhz CCK */
195 ar9485_1_1_baseband_core_txfir_coeff_japan_2484);
199 ar9485_1_1_pcie_phy_clkreq_disable_L1);
201 ar9485_1_1_pcie_phy_clkreq_disable_L1);
204 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
206 ar9485_1_1_pll_on_cdr_on_clkreq_disable_L1);
207 }
210 ar9462_2p1_mac_core);
212 ar9462_2p1_mac_postamble);
214 ar9462_2p1_baseband_core);
216 ar9462_2p1_baseband_postamble);
218 ar9462_2p1_radio_core);
220 ar9462_2p1_radio_postamble);
222 ar9462_2p1_radio_postamble_sys2ant);
224 ar9462_2p1_soc_preamble);
226 ar9462_2p1_soc_postamble);
228 ar9462_2p1_common_rx_gain);
230 ar9462_2p1_modes_fast_clock);
232 ar9462_2p1_baseband_core_txfir_coeff_japan_2484);
234 ar9462_2p1_pciephy_clkreq_disable_L1);
236 ar9462_2p1_pciephy_clkreq_disable_L1);
241 ar9462_2p0_mac_postamble);
244 ar9462_2p0_baseband_core);
246 ar9462_2p0_baseband_postamble);
249 ar9462_2p0_radio_core);
251 ar9462_2p0_radio_postamble);
253 ar9462_2p0_radio_postamble_sys2ant);
256 ar9462_2p0_soc_preamble);
258 ar9462_2p0_soc_postamble);
261 ar9462_2p0_common_rx_gain);
263 /* Awake -> Sleep Setting */
265 ar9462_2p0_pciephy_clkreq_disable_L1);
266 /* Sleep -> Awake Setting */
268 ar9462_2p0_pciephy_clkreq_disable_L1);
270 /* Fast clock modal settings */
272 ar9462_2p0_modes_fast_clock);
275 ar9462_2p0_baseband_core_txfir_coeff_japan_2484);
277 /* mac */
279 ar955x_1p0_mac_core);
281 ar955x_1p0_mac_postamble);
283 /* bb */
285 ar955x_1p0_baseband_core);
287 ar955x_1p0_baseband_postamble);
289 /* radio */
291 ar955x_1p0_radio_core);
293 ar955x_1p0_radio_postamble);
295 /* soc */
297 ar955x_1p0_soc_preamble);
299 ar955x_1p0_soc_postamble);
301 /* rx/tx gain */
303 ar955x_1p0_common_wo_xlna_rx_gain_table);
305 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
307 ar955x_1p0_modes_xpa_tx_gain_table);
309 /* Fast clock modal settings */
311 ar955x_1p0_modes_fast_clock);
314 qca953x_1p0_mac_core);
316 qca953x_1p0_mac_postamble);
318 qca953x_1p0_baseband_core);
320 qca953x_1p0_baseband_postamble);
322 qca953x_1p0_radio_core);
324 qca953x_1p0_radio_postamble);
326 qca953x_1p0_soc_preamble);
328 qca953x_1p0_soc_postamble);
330 qca953x_1p0_common_wo_xlna_rx_gain_table);
332 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
334 qca953x_1p0_modes_no_xpa_tx_gain_table);
336 qca953x_1p0_modes_fast_clock);
338 /* mac */
340 ar9580_1p0_mac_core);
342 ar9580_1p0_mac_postamble);
344 /* bb */
346 ar9580_1p0_baseband_core);
348 ar9580_1p0_baseband_postamble);
350 /* radio */
352 ar9580_1p0_radio_core);
354 ar9580_1p0_radio_postamble);
356 /* soc */
358 ar9580_1p0_soc_preamble);
360 ar9580_1p0_soc_postamble);
362 /* rx/tx gain */
364 ar9580_1p0_rx_gain_table);
366 ar9580_1p0_low_ob_db_tx_gain_table);
369 ar9580_1p0_modes_fast_clock);
371 ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
373 ar9580_1p0_baseband_postamble_dfs_channel);
376 ar9565_1p1_mac_core);
378 ar9565_1p1_mac_postamble);
381 ar9565_1p1_baseband_core);
383 ar9565_1p1_baseband_postamble);
386 ar9565_1p1_radio_core);
388 ar9565_1p1_radio_postamble);
391 ar9565_1p1_soc_preamble);
393 ar9565_1p1_soc_postamble);
396 ar9565_1p1_Common_rx_gain_table);
398 ar9565_1p1_Modes_lowest_ob_db_tx_gain_table);
401 ar9565_1p1_pciephy_clkreq_disable_L1);
403 ar9565_1p1_pciephy_clkreq_disable_L1);
406 ar9565_1p1_modes_fast_clock);
408 ar9565_1p1_baseband_core_txfir_coeff_japan_2484);
411 ar9565_1p0_mac_core);
413 ar9565_1p0_mac_postamble);
416 ar9565_1p0_baseband_core);
418 ar9565_1p0_baseband_postamble);
421 ar9565_1p0_radio_core);
423 ar9565_1p0_radio_postamble);
426 ar9565_1p0_soc_preamble);
428 ar9565_1p0_soc_postamble);
431 ar9565_1p0_Common_rx_gain_table);
433 ar9565_1p0_Modes_lowest_ob_db_tx_gain_table);
436 ar9565_1p0_pciephy_clkreq_disable_L1);
438 ar9565_1p0_pciephy_clkreq_disable_L1);
441 ar9565_1p0_modes_fast_clock);
443 ar9565_1p0_baseband_core_txfir_coeff_japan_2484);
445 /* mac */
447 ar9300_2p2_mac_core);
449 ar9300_2p2_mac_postamble);
451 /* bb */
453 ar9300_2p2_baseband_core);
455 ar9300_2p2_baseband_postamble);
457 /* radio */
459 ar9300_2p2_radio_core);
461 ar9300_2p2_radio_postamble);
463 /* soc */
465 ar9300_2p2_soc_preamble);
467 ar9300_2p2_soc_postamble);
469 /* rx/tx gain */
471 ar9300Common_rx_gain_table_2p2);
473 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
475 /* Load PCIE SERDES settings from INI */
477 /* Awake Setting */
480 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
482 /* Sleep Setting */
485 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2);
487 /* Fast clock modal settings */
489 ar9300Modes_fast_clock_2p2);
491 ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
493 ar9300_2p2_baseband_postamble_dfs_channel);
494 }
495 }
498 {
501 ar9331_modes_lowest_ob_db_tx_gain_1p2);
504 ar9331_modes_lowest_ob_db_tx_gain_1p1);
507 ar9340Modes_lowest_ob_db_tx_gain_table_1p0);
510 ar9485_modes_lowest_ob_db_tx_gain_1_1);
513 ar955x_1p0_modes_xpa_tx_gain_table);
516 qca953x_1p0_modes_xpa_tx_gain_table);
519 ar9580_1p0_lowest_ob_db_tx_gain_table);
522 ar9462_2p1_modes_low_ob_db_tx_gain);
525 ar9462_2p0_modes_low_ob_db_tx_gain);
528 ar9565_1p1_modes_low_ob_db_tx_gain_table);
531 ar9565_1p0_modes_low_ob_db_tx_gain_table);
532 else
534 ar9300Modes_lowest_ob_db_tx_gain_table_2p2);
535 }
538 {
541 ar9331_modes_high_ob_db_tx_gain_1p2);
544 ar9331_modes_high_ob_db_tx_gain_1p1);
547 ar9340Modes_high_ob_db_tx_gain_table_1p0);
550 ar9485Modes_high_ob_db_tx_gain_1_1);
553 ar9580_1p0_high_ob_db_tx_gain_table);
556 ar955x_1p0_modes_no_xpa_tx_gain_table);
560 qca953x_1p1_modes_no_xpa_tx_gain_table);
561 else
563 qca953x_1p0_modes_no_xpa_tx_gain_table);
566 ar9462_2p1_modes_high_ob_db_tx_gain);
569 ar9462_2p0_modes_high_ob_db_tx_gain);
572 ar9565_1p1_modes_high_ob_db_tx_gain_table);
575 ar9565_1p0_modes_high_ob_db_tx_gain_table);
576 else
578 ar9300Modes_high_ob_db_tx_gain_table_2p2);
579 }
582 {
585 ar9331_modes_low_ob_db_tx_gain_1p2);
588 ar9331_modes_low_ob_db_tx_gain_1p1);
591 ar9340Modes_low_ob_db_tx_gain_table_1p0);
594 ar9485Modes_low_ob_db_tx_gain_1_1);
597 ar9580_1p0_low_ob_db_tx_gain_table);
600 ar9565_1p1_modes_low_ob_db_tx_gain_table);
603 ar9565_1p0_modes_low_ob_db_tx_gain_table);
604 else
606 ar9300Modes_low_ob_db_tx_gain_table_2p2);
607 }
610 {
613 ar9331_modes_high_power_tx_gain_1p2);
616 ar9331_modes_high_power_tx_gain_1p1);
619 ar9340Modes_high_power_tx_gain_table_1p0);
622 ar9485Modes_high_power_tx_gain_1_1);
625 ar9580_1p0_high_power_tx_gain_table);
628 ar9565_1p1_modes_high_power_tx_gain_table);
631 ar9565_1p0_modes_high_power_tx_gain_table);
635 ar9300Modes_high_power_tx_gain_table_buffalo);
636 else
638 ar9300Modes_high_power_tx_gain_table_2p2);
639 }
640 }
643 {
646 ar9340Modes_mixed_ob_db_tx_gain_table_1p0);
649 ar9580_1p0_mixed_ob_db_tx_gain_table);
652 ar9462_2p1_modes_mix_ob_db_tx_gain);
655 ar9462_2p0_modes_mix_ob_db_tx_gain);
656 else
658 ar9300Modes_mixed_ob_db_tx_gain_table_2p2);
659 }
662 {
665 ar9485Modes_green_ob_db_tx_gain_1_1);
668 ar9340Modes_ub124_tx_gain_table_1p0);
671 ar9580_1p0_type5_tx_gain_table);
674 ar9300Modes_type5_tx_gain_table_2p2);
675 }
678 {
681 ar9340Modes_low_ob_db_and_spur_tx_gain_table_1p0);
684 ar9485Modes_green_spur_ob_db_tx_gain_1_1);
687 ar9580_1p0_type6_tx_gain_table);
688 }
691 {
694 ar9340_cus227_tx_gain_table_1p0);
695 }
700 {
702 ar9003_tx_gain_table_mode0,
703 ar9003_tx_gain_table_mode1,
704 ar9003_tx_gain_table_mode2,
705 ar9003_tx_gain_table_mode3,
706 ar9003_tx_gain_table_mode4,
707 ar9003_tx_gain_table_mode5,
708 ar9003_tx_gain_table_mode6,
709 ar9003_tx_gain_table_mode7,
710 };
717 }
720 {
723 ar9331_common_rx_gain_1p2);
726 ar9331_common_rx_gain_1p1);
729 ar9340Common_rx_gain_table_1p0);
732 ar9485_common_rx_gain_1_1);
735 ar955x_1p0_common_rx_gain_table);
737 ar955x_1p0_common_rx_gain_bounds);
740 qca953x_1p0_common_rx_gain_table);
742 qca953x_1p0_common_rx_gain_bounds);
745 ar9580_1p0_rx_gain_table);
748 ar9462_2p1_common_rx_gain);
751 ar9462_2p0_common_rx_gain);
754 ar9565_1p1_Common_rx_gain_table);
757 ar9565_1p0_Common_rx_gain_table);
758 else
760 ar9300Common_rx_gain_table_2p2);
761 }
764 {
767 ar9331_common_wo_xlna_rx_gain_1p2);
770 ar9331_common_wo_xlna_rx_gain_1p1);
773 ar9340Common_wo_xlna_rx_gain_table_1p0);
776 ar9485Common_wo_xlna_rx_gain_1_1);
779 ar9462_2p1_common_wo_xlna_rx_gain);
782 ar9462_2p0_common_wo_xlna_rx_gain);
785 ar955x_1p0_common_wo_xlna_rx_gain_table);
787 ar955x_1p0_common_wo_xlna_rx_gain_bounds);
790 qca953x_1p0_common_wo_xlna_rx_gain_table);
792 qca953x_1p0_common_wo_xlna_rx_gain_bounds);
795 ar9580_1p0_wo_xlna_rx_gain_table);
798 ar9565_1p1_common_wo_xlna_rx_gain_table);
801 ar9565_1p0_common_wo_xlna_rx_gain_table);
802 else
804 ar9300Common_wo_xlna_rx_gain_table_2p2);
805 }
808 {
811 ar9462_2p1_common_mixed_rx_gain);
813 ar9462_2p1_baseband_core_mix_rxgain);
815 ar9462_2p1_baseband_postamble_mix_rxgain);
817 ar9462_2p1_baseband_postamble_5g_xlna);
820 ar9462_2p0_common_mixed_rx_gain);
822 ar9462_2p0_baseband_core_mix_rxgain);
824 ar9462_2p0_baseband_postamble_mix_rxgain);
826 ar9462_2p0_baseband_postamble_5g_xlna);
827 }
828 }
831 {
834 ar9462_2p1_common_5g_xlna_only_rxgain);
836 ar9462_2p1_baseband_postamble_5g_xlna);
839 ar9462_2p0_common_5g_xlna_only_rxgain);
841 ar9462_2p0_baseband_postamble_5g_xlna);
842 }
843 }
846 {
861 }
862 }
864 /* set gain table pointers according to values read from the eeprom */
866 {
869 }
871 /*
872 * Helper for ASPM support.
873 *
874 * Disable PLL when in L0s as well as receiver clock when in L1.
875 * This power saving option must be enabled through the SerDes.
876 *
877 * Programming the SerDes must go through the same 288 bit serial shift
878 * register as the other analog registers. Hence the 9 writes.
879 */
882 {
886 /*
887 * Increase L1 Entry Latency. Some WB222 boards don't have
888 * this change in eeprom/OTP.
889 *
890 */
897 }
898 }
900 /* Nothing to do on restore for 11N */
902 /* set bit 19 to allow forcing of pcie core into L1 state */
905 }
907 /*
908 * Configire PCIE after Ini init. SERDES values now come from ini file
909 * This enables PCIe low power mode.
910 */
918 }
919 }
922 {
923 /*
924 * All chips support detection of BB/MAC hangs.
925 */
929 /*
930 * This is not required for AR9580 1.0
931 */
937 else
939 }
941 /*
942 * MAC HW hang check
943 * =================
944 *
945 * Signature: dcu_chain_state is 0x6 and dcu_complete_state is 0x1.
946 *
947 * The state of each DCU chain (mapped to TX queues) is available from these
948 * DMA debug registers:
949 *
950 * Chain 0 state : Bits 4:0 of AR_DMADBG_4
951 * Chain 1 state : Bits 9:5 of AR_DMADBG_4
952 * Chain 2 state : Bits 14:10 of AR_DMADBG_4
953 * Chain 3 state : Bits 19:15 of AR_DMADBG_4
954 * Chain 4 state : Bits 24:20 of AR_DMADBG_4
955 * Chain 5 state : Bits 29:25 of AR_DMADBG_4
956 * Chain 6 state : Bits 4:0 of AR_DMADBG_5
957 * Chain 7 state : Bits 9:5 of AR_DMADBG_5
958 * Chain 8 state : Bits 14:10 of AR_DMADBG_5
959 * Chain 9 state : Bits 19:15 of AR_DMADBG_5
960 *
961 * The DCU chain state "0x6" means "WAIT_FRDONE" - wait for TX frame to be done.
962 */
964 #define NUM_STATUS_READS 50
967 {
975 else
985 }
991 }
994 {
1012 else
1019 }
1020 }
1026 }
1027 }
1028 exit:
1030 }
1032 /* Sets up the AR9003 hardware familiy callbacks */
1034 {
1048 }