PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / calib.c
blob278365b8a8955dda362292b99949e63155be354c
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include "hw.h"
18 #include "hw-ops.h"
19 #include <linux/export.h>
21 /* Common calibration code */
24 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
26 int16_t nfval;
27 int16_t sort[ATH9K_NF_CAL_HIST_MAX];
28 int i, j;
30 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX; i++)
31 sort[i] = nfCalBuffer[i];
33 for (i = 0; i < ATH9K_NF_CAL_HIST_MAX - 1; i++) {
34 for (j = 1; j < ATH9K_NF_CAL_HIST_MAX - i; j++) {
35 if (sort[j] > sort[j - 1]) {
36 nfval = sort[j];
37 sort[j] = sort[j - 1];
38 sort[j - 1] = nfval;
42 nfval = sort[(ATH9K_NF_CAL_HIST_MAX - 1) >> 1];
44 return nfval;
47 static struct ath_nf_limits *ath9k_hw_get_nf_limits(struct ath_hw *ah,
48 struct ath9k_channel *chan)
50 struct ath_nf_limits *limit;
52 if (!chan || IS_CHAN_2GHZ(chan))
53 limit = &ah->nf_2g;
54 else
55 limit = &ah->nf_5g;
57 return limit;
60 static s16 ath9k_hw_get_default_nf(struct ath_hw *ah,
61 struct ath9k_channel *chan)
63 return ath9k_hw_get_nf_limits(ah, chan)->nominal;
66 s16 ath9k_hw_getchan_noise(struct ath_hw *ah, struct ath9k_channel *chan,
67 s16 nf)
69 s8 noise = ATH_DEFAULT_NOISE_FLOOR;
71 if (nf) {
72 s8 delta = nf - ATH9K_NF_CAL_NOISE_THRESH -
73 ath9k_hw_get_default_nf(ah, chan);
74 if (delta > 0)
75 noise += delta;
77 return noise;
79 EXPORT_SYMBOL(ath9k_hw_getchan_noise);
81 static void ath9k_hw_update_nfcal_hist_buffer(struct ath_hw *ah,
82 struct ath9k_hw_cal_data *cal,
83 int16_t *nfarray)
85 struct ath_common *common = ath9k_hw_common(ah);
86 struct ath_nf_limits *limit;
87 struct ath9k_nfcal_hist *h;
88 bool high_nf_mid = false;
89 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
90 int i;
92 h = cal->nfCalHist;
93 limit = ath9k_hw_get_nf_limits(ah, ah->curchan);
95 for (i = 0; i < NUM_NF_READINGS; i++) {
96 if (!(chainmask & (1 << i)) ||
97 ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(ah->curchan)))
98 continue;
100 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
102 if (++h[i].currIndex >= ATH9K_NF_CAL_HIST_MAX)
103 h[i].currIndex = 0;
105 if (h[i].invalidNFcount > 0) {
106 h[i].invalidNFcount--;
107 h[i].privNF = nfarray[i];
108 } else {
109 h[i].privNF =
110 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
113 if (!h[i].privNF)
114 continue;
116 if (h[i].privNF > limit->max) {
117 high_nf_mid = true;
119 ath_dbg(common, CALIBRATE,
120 "NFmid[%d] (%d) > MAX (%d), %s\n",
121 i, h[i].privNF, limit->max,
122 (test_bit(NFCAL_INTF, &cal->cal_flags) ?
123 "not corrected (due to interference)" :
124 "correcting to MAX"));
127 * Normally we limit the average noise floor by the
128 * hardware specific maximum here. However if we have
129 * encountered stuck beacons because of interference,
130 * we bypass this limit here in order to better deal
131 * with our environment.
133 if (!test_bit(NFCAL_INTF, &cal->cal_flags))
134 h[i].privNF = limit->max;
139 * If the noise floor seems normal for all chains, assume that
140 * there is no significant interference in the environment anymore.
141 * Re-enable the enforcement of the NF maximum again.
143 if (!high_nf_mid)
144 clear_bit(NFCAL_INTF, &cal->cal_flags);
147 static bool ath9k_hw_get_nf_thresh(struct ath_hw *ah,
148 enum ieee80211_band band,
149 int16_t *nft)
151 switch (band) {
152 case IEEE80211_BAND_5GHZ:
153 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_5);
154 break;
155 case IEEE80211_BAND_2GHZ:
156 *nft = (int8_t)ah->eep_ops->get_eeprom(ah, EEP_NFTHRESH_2);
157 break;
158 default:
159 BUG_ON(1);
160 return false;
163 return true;
166 void ath9k_hw_reset_calibration(struct ath_hw *ah,
167 struct ath9k_cal_list *currCal)
169 int i;
171 ath9k_hw_setup_calibration(ah, currCal);
173 currCal->calState = CAL_RUNNING;
175 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
176 ah->meas0.sign[i] = 0;
177 ah->meas1.sign[i] = 0;
178 ah->meas2.sign[i] = 0;
179 ah->meas3.sign[i] = 0;
182 ah->cal_samples = 0;
185 /* This is done for the currently configured channel */
186 bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
188 struct ath_common *common = ath9k_hw_common(ah);
189 struct ath9k_cal_list *currCal = ah->cal_list_curr;
191 if (!ah->caldata)
192 return true;
194 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
195 return true;
197 if (currCal == NULL)
198 return true;
200 if (currCal->calState != CAL_DONE) {
201 ath_dbg(common, CALIBRATE, "Calibration state incorrect, %d\n",
202 currCal->calState);
203 return true;
206 if (!(ah->supp_cals & currCal->calData->calType))
207 return true;
209 ath_dbg(common, CALIBRATE, "Resetting Cal %d state for channel %u\n",
210 currCal->calData->calType, ah->curchan->chan->center_freq);
212 ah->caldata->CalValid &= ~currCal->calData->calType;
213 currCal->calState = CAL_WAITING;
215 return false;
217 EXPORT_SYMBOL(ath9k_hw_reset_calvalid);
219 void ath9k_hw_start_nfcal(struct ath_hw *ah, bool update)
221 if (ah->caldata)
222 set_bit(NFCAL_PENDING, &ah->caldata->cal_flags);
224 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
225 AR_PHY_AGC_CONTROL_ENABLE_NF);
227 if (update)
228 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
229 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
230 else
231 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
232 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
234 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
237 void ath9k_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
239 struct ath9k_nfcal_hist *h = NULL;
240 unsigned i, j;
241 int32_t val;
242 u8 chainmask = (ah->rxchainmask << 3) | ah->rxchainmask;
243 struct ath_common *common = ath9k_hw_common(ah);
244 s16 default_nf = ath9k_hw_get_default_nf(ah, chan);
246 if (ah->caldata)
247 h = ah->caldata->nfCalHist;
249 for (i = 0; i < NUM_NF_READINGS; i++) {
250 if (chainmask & (1 << i)) {
251 s16 nfval;
253 if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
254 continue;
256 if (h)
257 nfval = h[i].privNF;
258 else
259 nfval = default_nf;
261 val = REG_READ(ah, ah->nf_regs[i]);
262 val &= 0xFFFFFE00;
263 val |= (((u32) nfval << 1) & 0x1ff);
264 REG_WRITE(ah, ah->nf_regs[i], val);
269 * Load software filtered NF value into baseband internal minCCApwr
270 * variable.
272 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
273 AR_PHY_AGC_CONTROL_ENABLE_NF);
274 REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
275 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
276 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
279 * Wait for load to complete, should be fast, a few 10s of us.
280 * The max delay was changed from an original 250us to 10000us
281 * since 250us often results in NF load timeout and causes deaf
282 * condition during stress testing 12/12/2009
284 for (j = 0; j < 10000; j++) {
285 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
286 AR_PHY_AGC_CONTROL_NF) == 0)
287 break;
288 udelay(10);
292 * We timed out waiting for the noisefloor to load, probably due to an
293 * in-progress rx. Simply return here and allow the load plenty of time
294 * to complete before the next calibration interval. We need to avoid
295 * trying to load -50 (which happens below) while the previous load is
296 * still in progress as this can cause rx deafness. Instead by returning
297 * here, the baseband nf cal will just be capped by our present
298 * noisefloor until the next calibration timer.
300 if (j == 10000) {
301 ath_dbg(common, ANY,
302 "Timeout while waiting for nf to load: AR_PHY_AGC_CONTROL=0x%x\n",
303 REG_READ(ah, AR_PHY_AGC_CONTROL));
304 return;
308 * Restore maxCCAPower register parameter again so that we're not capped
309 * by the median we just loaded. This will be initial (and max) value
310 * of next noise floor calibration the baseband does.
312 ENABLE_REGWRITE_BUFFER(ah);
313 for (i = 0; i < NUM_NF_READINGS; i++) {
314 if (chainmask & (1 << i)) {
315 if ((i >= AR5416_MAX_CHAINS) && !IS_CHAN_HT40(chan))
316 continue;
318 val = REG_READ(ah, ah->nf_regs[i]);
319 val &= 0xFFFFFE00;
320 val |= (((u32) (-50) << 1) & 0x1ff);
321 REG_WRITE(ah, ah->nf_regs[i], val);
324 REGWRITE_BUFFER_FLUSH(ah);
328 static void ath9k_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
330 struct ath_common *common = ath9k_hw_common(ah);
331 struct ath_nf_limits *limit;
332 int i;
334 if (IS_CHAN_2GHZ(ah->curchan))
335 limit = &ah->nf_2g;
336 else
337 limit = &ah->nf_5g;
339 for (i = 0; i < NUM_NF_READINGS; i++) {
340 if (!nf[i])
341 continue;
343 ath_dbg(common, CALIBRATE,
344 "NF calibrated [%s] [chain %d] is %d\n",
345 (i >= 3 ? "ext" : "ctl"), i % 3, nf[i]);
347 if (nf[i] > limit->max) {
348 ath_dbg(common, CALIBRATE,
349 "NF[%d] (%d) > MAX (%d), correcting to MAX\n",
350 i, nf[i], limit->max);
351 nf[i] = limit->max;
352 } else if (nf[i] < limit->min) {
353 ath_dbg(common, CALIBRATE,
354 "NF[%d] (%d) < MIN (%d), correcting to NOM\n",
355 i, nf[i], limit->min);
356 nf[i] = limit->nominal;
361 bool ath9k_hw_getnf(struct ath_hw *ah, struct ath9k_channel *chan)
363 struct ath_common *common = ath9k_hw_common(ah);
364 int16_t nf, nfThresh;
365 int16_t nfarray[NUM_NF_READINGS] = { 0 };
366 struct ath9k_nfcal_hist *h;
367 struct ieee80211_channel *c = chan->chan;
368 struct ath9k_hw_cal_data *caldata = ah->caldata;
370 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
371 ath_dbg(common, CALIBRATE,
372 "NF did not complete in calibration window\n");
373 return false;
376 ath9k_hw_do_getnf(ah, nfarray);
377 ath9k_hw_nf_sanitize(ah, nfarray);
378 nf = nfarray[0];
379 if (ath9k_hw_get_nf_thresh(ah, c->band, &nfThresh)
380 && nf > nfThresh) {
381 ath_dbg(common, CALIBRATE,
382 "noise floor failed detected; detected %d, threshold %d\n",
383 nf, nfThresh);
386 if (!caldata) {
387 chan->noisefloor = nf;
388 return false;
391 h = caldata->nfCalHist;
392 clear_bit(NFCAL_PENDING, &caldata->cal_flags);
393 ath9k_hw_update_nfcal_hist_buffer(ah, caldata, nfarray);
394 chan->noisefloor = h[0].privNF;
395 ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
396 return true;
398 EXPORT_SYMBOL(ath9k_hw_getnf);
400 void ath9k_init_nfcal_hist_buffer(struct ath_hw *ah,
401 struct ath9k_channel *chan)
403 struct ath9k_nfcal_hist *h;
404 s16 default_nf;
405 int i, j;
407 ah->caldata->channel = chan->channel;
408 ah->caldata->channelFlags = chan->channelFlags;
409 h = ah->caldata->nfCalHist;
410 default_nf = ath9k_hw_get_default_nf(ah, chan);
411 for (i = 0; i < NUM_NF_READINGS; i++) {
412 h[i].currIndex = 0;
413 h[i].privNF = default_nf;
414 h[i].invalidNFcount = AR_PHY_CCA_FILTERWINDOW_LENGTH;
415 for (j = 0; j < ATH9K_NF_CAL_HIST_MAX; j++) {
416 h[i].nfCalBuffer[j] = default_nf;
422 void ath9k_hw_bstuck_nfcal(struct ath_hw *ah)
424 struct ath9k_hw_cal_data *caldata = ah->caldata;
426 if (unlikely(!caldata))
427 return;
430 * If beacons are stuck, the most likely cause is interference.
431 * Triggering a noise floor calibration at this point helps the
432 * hardware adapt to a noisy environment much faster.
433 * To ensure that we recover from stuck beacons quickly, let
434 * the baseband update the internal NF value itself, similar to
435 * what is being done after a full reset.
437 if (!test_bit(NFCAL_PENDING, &caldata->cal_flags))
438 ath9k_hw_start_nfcal(ah, true);
439 else if (!(REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF))
440 ath9k_hw_getnf(ah, ah->curchan);
442 set_bit(NFCAL_INTF, &caldata->cal_flags);
444 EXPORT_SYMBOL(ath9k_hw_bstuck_nfcal);