drivers/net/wireless/ath/ath9k/debug.h

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #ifndef DEBUG_H
  18 #define DEBUG_H
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "dfs_debug.h"
  23
  24 struct ath_txq;
  25 struct ath_buf;
  26 struct fft_sample_tlv;
  27
  28 #ifdef CONFIG_ATH9K_DEBUGFS
  29 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
  30 #define RX_STAT_INC(c) (sc->debug.stats.rxstats.c++)
  31 #define RESET_STAT_INC(sc, type) sc->debug.stats.reset[type]++
  32 #define ANT_STAT_INC(i, c) sc->debug.stats.ant_stats[i].c++
  33 #define ANT_LNA_INC(i, c) sc->debug.stats.ant_stats[i].lna_recv_cnt[c]++;
  34 #else
  35 #define TX_STAT_INC(q, c) do { } while (0)
  36 #define RX_STAT_INC(c)
  37 #define RESET_STAT_INC(sc, type) do { } while (0)
  38 #define ANT_STAT_INC(i, c) do { } while (0)
  39 #define ANT_LNA_INC(i, c) do { } while (0)
  40 #endif
  41
  42 enum ath_reset_type {
  43         RESET_TYPE_BB_HANG,
  44         RESET_TYPE_BB_WATCHDOG,
  45         RESET_TYPE_FATAL_INT,
  46         RESET_TYPE_TX_ERROR,
  47         RESET_TYPE_TX_GTT,
  48         RESET_TYPE_TX_HANG,
  49         RESET_TYPE_PLL_HANG,
  50         RESET_TYPE_MAC_HANG,
  51         RESET_TYPE_BEACON_STUCK,
  52         RESET_TYPE_MCI,
  53         __RESET_TYPE_MAX
  54 };
  55
  56 #ifdef CONFIG_ATH9K_DEBUGFS
  57
  58 /**
  59  * struct ath_interrupt_stats - Contains statistics about interrupts
  60  * @total: Total no. of interrupts generated so far
  61  * @rxok: RX with no errors
  62  * @rxlp: RX with low priority RX
  63  * @rxhp: RX with high priority, uapsd only
  64  * @rxeol: RX with no more RXDESC available
  65  * @rxorn: RX FIFO overrun
  66  * @txok: TX completed at the requested rate
  67  * @txurn: TX FIFO underrun
  68  * @mib: MIB regs reaching its threshold
  69  * @rxphyerr: RX with phy errors
  70  * @rx_keycache_miss: RX with key cache misses
  71  * @swba: Software Beacon Alert
  72  * @bmiss: Beacon Miss
  73  * @bnr: Beacon Not Ready
  74  * @cst: Carrier Sense TImeout
  75  * @gtt: Global TX Timeout
  76  * @tim: RX beacon TIM occurrence
  77  * @cabend: RX End of CAB traffic
  78  * @dtimsync: DTIM sync lossage
  79  * @dtim: RX Beacon with DTIM
  80  * @bb_watchdog: Baseband watchdog
  81  * @tsfoor: TSF out of range, indicates that the corrected TSF received
  82  * from a beacon differs from the PCU's internal TSF by more than a
  83  * (programmable) threshold
  84  * @local_timeout: Internal bus timeout.
  85  * @mci: MCI interrupt, specific to MCI based BTCOEX chipsets
  86  * @gen_timer: Generic hardware timer interrupt
  87  */
  88 struct ath_interrupt_stats {
  89         u32 total;
  90         u32 rxok;
  91         u32 rxlp;
  92         u32 rxhp;
  93         u32 rxeol;
  94         u32 rxorn;
  95         u32 txok;
  96         u32 txeol;
  97         u32 txurn;
  98         u32 mib;
  99         u32 rxphyerr;
 100         u32 rx_keycache_miss;
 101         u32 swba;
 102         u32 bmiss;
 103         u32 bnr;
 104         u32 cst;
 105         u32 gtt;
 106         u32 tim;
 107         u32 cabend;
 108         u32 dtimsync;
 109         u32 dtim;
 110         u32 bb_watchdog;
 111         u32 tsfoor;
 112         u32 mci;
 113         u32 gen_timer;
 114
 115         /* Sync-cause stats */
 116         u32 sync_cause_all;
 117         u32 sync_rtc_irq;
 118         u32 sync_mac_irq;
 119         u32 eeprom_illegal_access;
 120         u32 apb_timeout;
 121         u32 pci_mode_conflict;
 122         u32 host1_fatal;
 123         u32 host1_perr;
 124         u32 trcv_fifo_perr;
 125         u32 radm_cpl_ep;
 126         u32 radm_cpl_dllp_abort;
 127         u32 radm_cpl_tlp_abort;
 128         u32 radm_cpl_ecrc_err;
 129         u32 radm_cpl_timeout;
 130         u32 local_timeout;
 131         u32 pm_access;
 132         u32 mac_awake;
 133         u32 mac_asleep;
 134         u32 mac_sleep_access;
 135 };
 136
 137
 138 /**
 139  * struct ath_tx_stats - Statistics about TX
 140  * @tx_pkts_all:  No. of total frames transmitted, including ones that
 141         may have had errors.
 142  * @tx_bytes_all:  No. of total bytes transmitted, including ones that
 143         may have had errors.
 144  * @queued: Total MPDUs (non-aggr) queued
 145  * @completed: Total MPDUs (non-aggr) completed
 146  * @a_aggr: Total no. of aggregates queued
 147  * @a_queued_hw: Total AMPDUs queued to hardware
 148  * @a_queued_sw: Total AMPDUs queued to software queues
 149  * @a_completed: Total AMPDUs completed
 150  * @a_retries: No. of AMPDUs retried (SW)
 151  * @a_xretries: No. of AMPDUs dropped due to xretries
 152  * @txerr_filtered: No. of frames with TXERR_FILT flag set.
 153  * @fifo_underrun: FIFO underrun occurrences
 154         Valid only for:
 155                 - non-aggregate condition.
 156                 - first packet of aggregate.
 157  * @xtxop: No. of frames filtered because of TXOP limit
 158  * @timer_exp: Transmit timer expiry
 159  * @desc_cfg_err: Descriptor configuration errors
 160  * @data_urn: TX data underrun errors
 161  * @delim_urn: TX delimiter underrun errors
 162  * @puttxbuf: Number of times hardware was given txbuf to write.
 163  * @txstart:  Number of times hardware was told to start tx.
 164  * @txprocdesc:  Number of times tx descriptor was processed
 165  * @txfailed:  Out-of-memory or other errors in xmit path.
 166  */
 167 struct ath_tx_stats {
 168         u32 tx_pkts_all;
 169         u32 tx_bytes_all;
 170         u32 queued;
 171         u32 completed;
 172         u32 xretries;
 173         u32 a_aggr;
 174         u32 a_queued_hw;
 175         u32 a_queued_sw;
 176         u32 a_completed;
 177         u32 a_retries;
 178         u32 a_xretries;
 179         u32 txerr_filtered;
 180         u32 fifo_underrun;
 181         u32 xtxop;
 182         u32 timer_exp;
 183         u32 desc_cfg_err;
 184         u32 data_underrun;
 185         u32 delim_underrun;
 186         u32 puttxbuf;
 187         u32 txstart;
 188         u32 txprocdesc;
 189         u32 txfailed;
 190 };
 191
 192 /*
 193  * Various utility macros to print TX/Queue counters.
 194  */
 195 #define PR_QNUM(_n) sc->tx.txq_map[_n]->axq_qnum
 196 #define TXSTATS sc->debug.stats.txstats
 197 #define PR(str, elem)                                                   \
 198         do {                                                            \
 199                 len += scnprintf(buf + len, size - len,                 \
 200                                  "%s%13u%11u%10u%10u\n", str,           \
 201                                  TXSTATS[PR_QNUM(IEEE80211_AC_BE)].elem,\
 202                                  TXSTATS[PR_QNUM(IEEE80211_AC_BK)].elem,\
 203                                  TXSTATS[PR_QNUM(IEEE80211_AC_VI)].elem,\
 204                                  TXSTATS[PR_QNUM(IEEE80211_AC_VO)].elem); \
 205         } while(0)
 206
 207 struct ath_rx_rate_stats {
 208         struct {
 209                 u32 ht20_cnt;
 210                 u32 ht40_cnt;
 211                 u32 sgi_cnt;
 212                 u32 lgi_cnt;
 213         } ht_stats[24];
 214
 215         struct {
 216                 u32 ofdm_cnt;
 217         } ofdm_stats[8];
 218
 219         struct {
 220                 u32 cck_lp_cnt;
 221                 u32 cck_sp_cnt;
 222         } cck_stats[4];
 223 };
 224
 225 /**
 226  * struct ath_rx_stats - RX Statistics
 227  * @rx_pkts_all:  No. of total frames received, including ones that
 228         may have had errors.
 229  * @rx_bytes_all:  No. of total bytes received, including ones that
 230         may have had errors.
 231  * @crc_err: No. of frames with incorrect CRC value
 232  * @decrypt_crc_err: No. of frames whose CRC check failed after
 233         decryption process completed
 234  * @phy_err: No. of frames whose reception failed because the PHY
 235         encountered an error
 236  * @mic_err: No. of frames with incorrect TKIP MIC verification failure
 237  * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
 238  * @post_delim_crc_err: Post-Frame delimiter CRC error detections
 239  * @decrypt_busy_err: Decryption interruptions counter
 240  * @phy_err_stats: Individual PHY error statistics
 241  * @rx_len_err:  No. of frames discarded due to bad length.
 242  * @rx_oom_err:  No. of frames dropped due to OOM issues.
 243  * @rx_rate_err:  No. of frames dropped due to rate errors.
 244  * @rx_too_many_frags_err:  Frames dropped due to too-many-frags received.
 245  * @rx_beacons:  No. of beacons received.
 246  * @rx_frags:  No. of rx-fragements received.
 247  * @rx_spectral: No of spectral packets received.
 248  */
 249 struct ath_rx_stats {
 250         u32 rx_pkts_all;
 251         u32 rx_bytes_all;
 252         u32 crc_err;
 253         u32 decrypt_crc_err;
 254         u32 phy_err;
 255         u32 mic_err;
 256         u32 pre_delim_crc_err;
 257         u32 post_delim_crc_err;
 258         u32 decrypt_busy_err;
 259         u32 phy_err_stats[ATH9K_PHYERR_MAX];
 260         u32 rx_len_err;
 261         u32 rx_oom_err;
 262         u32 rx_rate_err;
 263         u32 rx_too_many_frags_err;
 264         u32 rx_beacons;
 265         u32 rx_frags;
 266         u32 rx_spectral;
 267 };
 268
 269 #define ANT_MAIN 0
 270 #define ANT_ALT  1
 271
 272 struct ath_antenna_stats {
 273         u32 recv_cnt;
 274         u32 rssi_avg;
 275         u32 lna_recv_cnt[4];
 276         u32 lna_attempt_cnt[4];
 277 };
 278
 279 struct ath_stats {
 280         struct ath_interrupt_stats istats;
 281         struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
 282         struct ath_rx_stats rxstats;
 283         struct ath_dfs_stats dfs_stats;
 284         struct ath_antenna_stats ant_stats[2];
 285         u32 reset[__RESET_TYPE_MAX];
 286 };
 287
 288 struct ath9k_debug {
 289         struct dentry *debugfs_phy;
 290         u32 regidx;
 291         struct ath_stats stats;
 292 };
 293
 294 int ath9k_init_debug(struct ath_hw *ah);
 295 void ath9k_deinit_debug(struct ath_softc *sc);
 296
 297 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
 298 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
 299                        struct ath_tx_status *ts, struct ath_txq *txq,
 300                        unsigned int flags);
 301 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
 302 int ath9k_get_et_sset_count(struct ieee80211_hw *hw,
 303                             struct ieee80211_vif *vif, int sset);
 304 void ath9k_get_et_stats(struct ieee80211_hw *hw,
 305                         struct ieee80211_vif *vif,
 306                         struct ethtool_stats *stats, u64 *data);
 307 void ath9k_get_et_strings(struct ieee80211_hw *hw,
 308                           struct ieee80211_vif *vif,
 309                           u32 sset, u8 *data);
 310 void ath9k_sta_add_debugfs(struct ieee80211_hw *hw,
 311                            struct ieee80211_vif *vif,
 312                            struct ieee80211_sta *sta,
 313                            struct dentry *dir);
 314 void ath9k_debug_stat_ant(struct ath_softc *sc,
 315                           struct ath_hw_antcomb_conf *div_ant_conf,
 316                           int main_rssi_avg, int alt_rssi_avg);
 317 void ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause);
 318
 319 #else
 320
 321 static inline int ath9k_init_debug(struct ath_hw *ah)
 322 {
 323         return 0;
 324 }
 325
 326 static inline void ath9k_deinit_debug(struct ath_softc *sc)
 327 {
 328 }
 329 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
 330                                             enum ath9k_int status)
 331 {
 332 }
 333 static inline void ath_debug_stat_tx(struct ath_softc *sc,
 334                                      struct ath_buf *bf,
 335                                      struct ath_tx_status *ts,
 336                                      struct ath_txq *txq,
 337                                      unsigned int flags)
 338 {
 339 }
 340 static inline void ath_debug_stat_rx(struct ath_softc *sc,
 341                                      struct ath_rx_status *rs)
 342 {
 343 }
 344 static inline void ath9k_debug_stat_ant(struct ath_softc *sc,
 345                                         struct ath_hw_antcomb_conf *div_ant_conf,
 346                                         int main_rssi_avg, int alt_rssi_avg)
 347 {
 348
 349 }
 350
 351 static inline void
 352 ath9k_debug_sync_cause(struct ath_softc *sc, u32 sync_cause)
 353 {
 354 }
 355
 356 #endif /* CONFIG_ATH9K_DEBUGFS */
 357
 358 #ifdef CONFIG_ATH9K_STATION_STATISTICS
 359 void ath_debug_rate_stats(struct ath_softc *sc,
 360                           struct ath_rx_status *rs,
 361                           struct sk_buff *skb);
 362 #else
 363 static inline void ath_debug_rate_stats(struct ath_softc *sc,
 364                                         struct ath_rx_status *rs,
 365                                         struct sk_buff *skb)
 366 {
 367 }
 368 #endif /* CONFIG_ATH9K_STATION_STATISTICS */
 369
 370 #endif /* DEBUG_H */