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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / wireless / ath / ath9k / main.c
blob5924f72dd4932c4be474f87f246643c6e49ccabb
1 /*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/nl80211.h>
18 #include <linux/delay.h>
19 #include "ath9k.h"
20 #include "btcoex.h"
21
22 static void ath9k_set_assoc_state(struct ath_softc *sc,
23 struct ieee80211_vif *vif);
24
25 u8 ath9k_parse_mpdudensity(u8 mpdudensity)
26 {
27 /*
28 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
29 * 0 for no restriction
30 * 1 for 1/4 us
31 * 2 for 1/2 us
32 * 3 for 1 us
33 * 4 for 2 us
34 * 5 for 4 us
35 * 6 for 8 us
36 * 7 for 16 us
37 */
38 switch (mpdudensity) {
39 case 0:
40 return 0;
41 case 1:
42 case 2:
43 case 3:
44 /* Our lower layer calculations limit our precision to
45 1 microsecond */
46 return 1;
47 case 4:
48 return 2;
49 case 5:
50 return 4;
51 case 6:
52 return 8;
53 case 7:
54 return 16;
55 default:
56 return 0;
57 }
58 }
59
60 static bool ath9k_has_pending_frames(struct ath_softc *sc, struct ath_txq *txq)
61 {
62 bool pending = false;
63
64 spin_lock_bh(&txq->axq_lock);
65
66 if (txq->axq_depth || !list_empty(&txq->axq_acq))
67 pending = true;
68
69 spin_unlock_bh(&txq->axq_lock);
70 return pending;
71 }
72
73 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
74 {
75 unsigned long flags;
76 bool ret;
77
78 spin_lock_irqsave(&sc->sc_pm_lock, flags);
79 ret = ath9k_hw_setpower(sc->sc_ah, mode);
80 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
81
82 return ret;
83 }
84
85 void ath_ps_full_sleep(unsigned long data)
86 {
87 struct ath_softc *sc = (struct ath_softc *) data;
88 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
89 bool reset;
90
91 spin_lock(&common->cc_lock);
92 ath_hw_cycle_counters_update(common);
93 spin_unlock(&common->cc_lock);
94
95 ath9k_hw_setrxabort(sc->sc_ah, 1);
96 ath9k_hw_stopdmarecv(sc->sc_ah, &reset);
97
98 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
99 }
100
101 void ath9k_ps_wakeup(struct ath_softc *sc)
102 {
103 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
104 unsigned long flags;
105 enum ath9k_power_mode power_mode;
106
107 spin_lock_irqsave(&sc->sc_pm_lock, flags);
108 if (++sc->ps_usecount != 1)
109 goto unlock;
110
111 del_timer_sync(&sc->sleep_timer);
112 power_mode = sc->sc_ah->power_mode;
113 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
114
115 /*
116 * While the hardware is asleep, the cycle counters contain no
117 * useful data. Better clear them now so that they don't mess up
118 * survey data results.
119 */
120 if (power_mode != ATH9K_PM_AWAKE) {
121 spin_lock(&common->cc_lock);
122 ath_hw_cycle_counters_update(common);
123 memset(&common->cc_survey, 0, sizeof(common->cc_survey));
124 memset(&common->cc_ani, 0, sizeof(common->cc_ani));
125 spin_unlock(&common->cc_lock);
126 }
127
128 unlock:
129 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
130 }
131
132 void ath9k_ps_restore(struct ath_softc *sc)
133 {
134 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
135 enum ath9k_power_mode mode;
136 unsigned long flags;
137
138 spin_lock_irqsave(&sc->sc_pm_lock, flags);
139 if (--sc->ps_usecount != 0)
140 goto unlock;
141
142 if (sc->ps_idle) {
143 mod_timer(&sc->sleep_timer, jiffies + HZ / 10);
144 goto unlock;
145 }
146
147 if (sc->ps_enabled &&
148 !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
149 PS_WAIT_FOR_CAB |
150 PS_WAIT_FOR_PSPOLL_DATA |
151 PS_WAIT_FOR_TX_ACK |
152 PS_WAIT_FOR_ANI))) {
153 mode = ATH9K_PM_NETWORK_SLEEP;
154 if (ath9k_hw_btcoex_is_enabled(sc->sc_ah))
155 ath9k_btcoex_stop_gen_timer(sc);
156 } else {
157 goto unlock;
158 }
159
160 spin_lock(&common->cc_lock);
161 ath_hw_cycle_counters_update(common);
162 spin_unlock(&common->cc_lock);
163
164 ath9k_hw_setpower(sc->sc_ah, mode);
165
166 unlock:
167 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
168 }
169
170 static void __ath_cancel_work(struct ath_softc *sc)
171 {
172 cancel_work_sync(&sc->paprd_work);
173 cancel_delayed_work_sync(&sc->tx_complete_work);
174 cancel_delayed_work_sync(&sc->hw_pll_work);
175
176 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
177 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
178 cancel_work_sync(&sc->mci_work);
179 #endif
180 }
181
182 void ath_cancel_work(struct ath_softc *sc)
183 {
184 __ath_cancel_work(sc);
185 cancel_work_sync(&sc->hw_reset_work);
186 }
187
188 void ath_restart_work(struct ath_softc *sc)
189 {
190 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
191
192 if (AR_SREV_9340(sc->sc_ah) || AR_SREV_9330(sc->sc_ah))
193 ieee80211_queue_delayed_work(sc->hw, &sc->hw_pll_work,
194 msecs_to_jiffies(ATH_PLL_WORK_INTERVAL));
195
196 ath_start_ani(sc);
197 }
198
199 static bool ath_prepare_reset(struct ath_softc *sc)
200 {
201 struct ath_hw *ah = sc->sc_ah;
202 bool ret = true;
203
204 ieee80211_stop_queues(sc->hw);
205 ath_stop_ani(sc);
206 ath9k_hw_disable_interrupts(ah);
207
208 if (!ath_drain_all_txq(sc))
209 ret = false;
210
211 if (!ath_stoprecv(sc))
212 ret = false;
213
214 return ret;
215 }
216
217 static bool ath_complete_reset(struct ath_softc *sc, bool start)
218 {
219 struct ath_hw *ah = sc->sc_ah;
220 struct ath_common *common = ath9k_hw_common(ah);
221 unsigned long flags;
222 int i;
223
224 if (ath_startrecv(sc) != 0) {
225 ath_err(common, "Unable to restart recv logic\n");
226 return false;
227 }
228
229 ath9k_cmn_update_txpow(ah, sc->curtxpow,
230 sc->config.txpowlimit, &sc->curtxpow);
231
232 clear_bit(SC_OP_HW_RESET, &sc->sc_flags);
233 ath9k_hw_set_interrupts(ah);
234 ath9k_hw_enable_interrupts(ah);
235
236 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL) && start) {
237 if (!test_bit(SC_OP_BEACONS, &sc->sc_flags))
238 goto work;
239
240 if (ah->opmode == NL80211_IFTYPE_STATION &&
241 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
242 spin_lock_irqsave(&sc->sc_pm_lock, flags);
243 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
244 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
245 } else {
246 ath9k_set_beacon(sc);
247 }
248 work:
249 ath_restart_work(sc);
250
251 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
252 if (!ATH_TXQ_SETUP(sc, i))
253 continue;
254
255 spin_lock_bh(&sc->tx.txq[i].axq_lock);
256 ath_txq_schedule(sc, &sc->tx.txq[i]);
257 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
258 }
259 }
260
261 sc->gtt_cnt = 0;
262 ieee80211_wake_queues(sc->hw);
263
264 return true;
265 }
266
267 static int ath_reset_internal(struct ath_softc *sc, struct ath9k_channel *hchan)
268 {
269 struct ath_hw *ah = sc->sc_ah;
270 struct ath_common *common = ath9k_hw_common(ah);
271 struct ath9k_hw_cal_data *caldata = NULL;
272 bool fastcc = true;
273 int r;
274
275 __ath_cancel_work(sc);
276
277 tasklet_disable(&sc->intr_tq);
278 spin_lock_bh(&sc->sc_pcu_lock);
279
280 if (!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)) {
281 fastcc = false;
282 caldata = &sc->caldata;
283 }
284
285 if (!hchan) {
286 fastcc = false;
287 hchan = ah->curchan;
288 }
289
290 if (!ath_prepare_reset(sc))
291 fastcc = false;
292
293 ath_dbg(common, CONFIG, "Reset to %u MHz, HT40: %d fastcc: %d\n",
294 hchan->channel, IS_CHAN_HT40(hchan), fastcc);
295
296 r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
297 if (r) {
298 ath_err(common,
299 "Unable to reset channel, reset status %d\n", r);
300
301 ath9k_hw_enable_interrupts(ah);
302 ath9k_queue_reset(sc, RESET_TYPE_BB_HANG);
303
304 goto out;
305 }
306
307 if (ath9k_hw_mci_is_enabled(sc->sc_ah) &&
308 (sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
309 ath9k_mci_set_txpower(sc, true, false);
310
311 if (!ath_complete_reset(sc, true))
312 r = -EIO;
313
314 out:
315 spin_unlock_bh(&sc->sc_pcu_lock);
316 tasklet_enable(&sc->intr_tq);
317
318 return r;
319 }
320
321
322 /*
323 * Set/change channels. If the channel is really being changed, it's done
324 * by reseting the chip. To accomplish this we must first cleanup any pending
325 * DMA, then restart stuff.
326 */
327 static int ath_set_channel(struct ath_softc *sc, struct cfg80211_chan_def *chandef)
328 {
329 struct ath_hw *ah = sc->sc_ah;
330 struct ath_common *common = ath9k_hw_common(ah);
331 struct ieee80211_hw *hw = sc->hw;
332 struct ath9k_channel *hchan;
333 struct ieee80211_channel *chan = chandef->chan;
334 bool offchannel;
335 int pos = chan->hw_value;
336 int old_pos = -1;
337 int r;
338
339 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
340 return -EIO;
341
342 offchannel = !!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL);
343
344 if (ah->curchan)
345 old_pos = ah->curchan - &ah->channels[0];
346
347 ath_dbg(common, CONFIG, "Set channel: %d MHz width: %d\n",
348 chan->center_freq, chandef->width);
349
350 /* update survey stats for the old channel before switching */
351 spin_lock_bh(&common->cc_lock);
352 ath_update_survey_stats(sc);
353 spin_unlock_bh(&common->cc_lock);
354
355 ath9k_cmn_get_channel(hw, ah, chandef);
356
357 /*
358 * If the operating channel changes, change the survey in-use flags
359 * along with it.
360 * Reset the survey data for the new channel, unless we're switching
361 * back to the operating channel from an off-channel operation.
362 */
363 if (!offchannel && sc->cur_survey != &sc->survey[pos]) {
364 if (sc->cur_survey)
365 sc->cur_survey->filled &= ~SURVEY_INFO_IN_USE;
366
367 sc->cur_survey = &sc->survey[pos];
368
369 memset(sc->cur_survey, 0, sizeof(struct survey_info));
370 sc->cur_survey->filled |= SURVEY_INFO_IN_USE;
371 } else if (!(sc->survey[pos].filled & SURVEY_INFO_IN_USE)) {
372 memset(&sc->survey[pos], 0, sizeof(struct survey_info));
373 }
374
375 hchan = &sc->sc_ah->channels[pos];
376 r = ath_reset_internal(sc, hchan);
377 if (r)
378 return r;
379
380 /*
381 * The most recent snapshot of channel->noisefloor for the old
382 * channel is only available after the hardware reset. Copy it to
383 * the survey stats now.
384 */
385 if (old_pos >= 0)
386 ath_update_survey_nf(sc, old_pos);
387
388 /*
389 * Enable radar pulse detection if on a DFS channel. Spectral
390 * scanning and radar detection can not be used concurrently.
391 */
392 if (hw->conf.radar_enabled) {
393 u32 rxfilter;
394
395 /* set HW specific DFS configuration */
396 ath9k_hw_set_radar_params(ah);
397 rxfilter = ath9k_hw_getrxfilter(ah);
398 rxfilter |= ATH9K_RX_FILTER_PHYRADAR |
399 ATH9K_RX_FILTER_PHYERR;
400 ath9k_hw_setrxfilter(ah, rxfilter);
401 ath_dbg(common, DFS, "DFS enabled at freq %d\n",
402 chan->center_freq);
403 } else {
404 /* perform spectral scan if requested. */
405 if (test_bit(SC_OP_SCANNING, &sc->sc_flags) &&
406 sc->spectral_mode == SPECTRAL_CHANSCAN)
407 ath9k_spectral_scan_trigger(hw);
408 }
409
410 return 0;
411 }
412
413 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta,
414 struct ieee80211_vif *vif)
415 {
416 struct ath_node *an;
417 an = (struct ath_node *)sta->drv_priv;
418
419 an->sc = sc;
420 an->sta = sta;
421 an->vif = vif;
422
423 ath_tx_node_init(sc, an);
424 }
425
426 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
427 {
428 struct ath_node *an = (struct ath_node *)sta->drv_priv;
429 ath_tx_node_cleanup(sc, an);
430 }
431
432 void ath9k_tasklet(unsigned long data)
433 {
434 struct ath_softc *sc = (struct ath_softc *)data;
435 struct ath_hw *ah = sc->sc_ah;
436 struct ath_common *common = ath9k_hw_common(ah);
437 enum ath_reset_type type;
438 unsigned long flags;
439 u32 status = sc->intrstatus;
440 u32 rxmask;
441
442 ath9k_ps_wakeup(sc);
443 spin_lock(&sc->sc_pcu_lock);
444
445 if (status & ATH9K_INT_FATAL) {
446 type = RESET_TYPE_FATAL_INT;
447 ath9k_queue_reset(sc, type);
448
449 /*
450 * Increment the ref. counter here so that
451 * interrupts are enabled in the reset routine.
452 */
453 atomic_inc(&ah->intr_ref_cnt);
454 ath_dbg(common, ANY, "FATAL: Skipping interrupts\n");
455 goto out;
456 }
457
458 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
459 (status & ATH9K_INT_BB_WATCHDOG)) {
460 spin_lock(&common->cc_lock);
461 ath_hw_cycle_counters_update(common);
462 ar9003_hw_bb_watchdog_dbg_info(ah);
463 spin_unlock(&common->cc_lock);
464
465 if (ar9003_hw_bb_watchdog_check(ah)) {
466 type = RESET_TYPE_BB_WATCHDOG;
467 ath9k_queue_reset(sc, type);
468
469 /*
470 * Increment the ref. counter here so that
471 * interrupts are enabled in the reset routine.
472 */
473 atomic_inc(&ah->intr_ref_cnt);
474 ath_dbg(common, ANY,
475 "BB_WATCHDOG: Skipping interrupts\n");
476 goto out;
477 }
478 }
479
480 if (status & ATH9K_INT_GTT) {
481 sc->gtt_cnt++;
482
483 if ((sc->gtt_cnt >= MAX_GTT_CNT) && !ath9k_hw_check_alive(ah)) {
484 type = RESET_TYPE_TX_GTT;
485 ath9k_queue_reset(sc, type);
486 atomic_inc(&ah->intr_ref_cnt);
487 ath_dbg(common, ANY,
488 "GTT: Skipping interrupts\n");
489 goto out;
490 }
491 }
492
493 spin_lock_irqsave(&sc->sc_pm_lock, flags);
494 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
495 /*
496 * TSF sync does not look correct; remain awake to sync with
497 * the next Beacon.
498 */
499 ath_dbg(common, PS, "TSFOOR - Sync with next Beacon\n");
500 sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
501 }
502 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
503
504 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
505 rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
506 ATH9K_INT_RXORN);
507 else
508 rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
509
510 if (status & rxmask) {
511 /* Check for high priority Rx first */
512 if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
513 (status & ATH9K_INT_RXHP))
514 ath_rx_tasklet(sc, 0, true);
515
516 ath_rx_tasklet(sc, 0, false);
517 }
518
519 if (status & ATH9K_INT_TX) {
520 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
521 /*
522 * For EDMA chips, TX completion is enabled for the
523 * beacon queue, so if a beacon has been transmitted
524 * successfully after a GTT interrupt, the GTT counter
525 * gets reset to zero here.
526 */
527 sc->gtt_cnt = 0;
528
529 ath_tx_edma_tasklet(sc);
530 } else {
531 ath_tx_tasklet(sc);
532 }
533
534 wake_up(&sc->tx_wait);
535 }
536
537 if (status & ATH9K_INT_GENTIMER)
538 ath_gen_timer_isr(sc->sc_ah);
539
540 ath9k_btcoex_handle_interrupt(sc, status);
541
542 /* re-enable hardware interrupt */
543 ath9k_hw_enable_interrupts(ah);
544 out:
545 spin_unlock(&sc->sc_pcu_lock);
546 ath9k_ps_restore(sc);
547 }
548
549 irqreturn_t ath_isr(int irq, void *dev)
550 {
551 #define SCHED_INTR ( \
552 ATH9K_INT_FATAL | \
553 ATH9K_INT_BB_WATCHDOG | \
554 ATH9K_INT_RXORN | \
555 ATH9K_INT_RXEOL | \
556 ATH9K_INT_RX | \
557 ATH9K_INT_RXLP | \
558 ATH9K_INT_RXHP | \
559 ATH9K_INT_TX | \
560 ATH9K_INT_BMISS | \
561 ATH9K_INT_CST | \
562 ATH9K_INT_GTT | \
563 ATH9K_INT_TSFOOR | \
564 ATH9K_INT_GENTIMER | \
565 ATH9K_INT_MCI)
566
567 struct ath_softc *sc = dev;
568 struct ath_hw *ah = sc->sc_ah;
569 enum ath9k_int status;
570 u32 sync_cause = 0;
571 bool sched = false;
572
573 /*
574 * The hardware is not ready/present, don't
575 * touch anything. Note this can happen early
576 * on if the IRQ is shared.
577 */
578 if (test_bit(SC_OP_INVALID, &sc->sc_flags))
579 return IRQ_NONE;
580
581 /* shared irq, not for us */
582
583 if (!ath9k_hw_intrpend(ah))
584 return IRQ_NONE;
585
586 if (test_bit(SC_OP_HW_RESET, &sc->sc_flags)) {
587 ath9k_hw_kill_interrupts(ah);
588 return IRQ_HANDLED;
589 }
590
591 /*
592 * Figure out the reason(s) for the interrupt. Note
593 * that the hal returns a pseudo-ISR that may include
594 * bits we haven't explicitly enabled so we mask the
595 * value to insure we only process bits we requested.
596 */
597 ath9k_hw_getisr(ah, &status, &sync_cause); /* NB: clears ISR too */
598 ath9k_debug_sync_cause(sc, sync_cause);
599 status &= ah->imask; /* discard unasked-for bits */
600
601 /*
602 * If there are no status bits set, then this interrupt was not
603 * for me (should have been caught above).
604 */
605 if (!status)
606 return IRQ_NONE;
607
608 /* Cache the status */
609 sc->intrstatus = status;
610
611 if (status & SCHED_INTR)
612 sched = true;
613
614 /*
615 * If a FATAL or RXORN interrupt is received, we have to reset the
616 * chip immediately.
617 */
618 if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
619 !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
620 goto chip_reset;
621
622 if ((ah->config.hw_hang_checks & HW_BB_WATCHDOG) &&
623 (status & ATH9K_INT_BB_WATCHDOG))
624 goto chip_reset;
625
626 #ifdef CONFIG_ATH9K_WOW
627 if (status & ATH9K_INT_BMISS) {
628 if (atomic_read(&sc->wow_sleep_proc_intr) == 0) {
629 atomic_inc(&sc->wow_got_bmiss_intr);
630 atomic_dec(&sc->wow_sleep_proc_intr);
631 }
632 }
633 #endif
634
635 if (status & ATH9K_INT_SWBA)
636 tasklet_schedule(&sc->bcon_tasklet);
637
638 if (status & ATH9K_INT_TXURN)
639 ath9k_hw_updatetxtriglevel(ah, true);
640
641 if (status & ATH9K_INT_RXEOL) {
642 ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
643 ath9k_hw_set_interrupts(ah);
644 }
645
646 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
647 if (status & ATH9K_INT_TIM_TIMER) {
648 if (ATH_DBG_WARN_ON_ONCE(sc->ps_idle))
649 goto chip_reset;
650 /* Clear RxAbort bit so that we can
651 * receive frames */
652 ath9k_setpower(sc, ATH9K_PM_AWAKE);
653 spin_lock(&sc->sc_pm_lock);
654 ath9k_hw_setrxabort(sc->sc_ah, 0);
655 sc->ps_flags |= PS_WAIT_FOR_BEACON;
656 spin_unlock(&sc->sc_pm_lock);
657 }
658
659 chip_reset:
660
661 ath_debug_stat_interrupt(sc, status);
662
663 if (sched) {
664 /* turn off every interrupt */
665 ath9k_hw_disable_interrupts(ah);
666 tasklet_schedule(&sc->intr_tq);
667 }
668
669 return IRQ_HANDLED;
670
671 #undef SCHED_INTR
672 }
673
674 int ath_reset(struct ath_softc *sc)
675 {
676 int r;
677
678 ath9k_ps_wakeup(sc);
679 r = ath_reset_internal(sc, NULL);
680 ath9k_ps_restore(sc);
681
682 return r;
683 }
684
685 void ath9k_queue_reset(struct ath_softc *sc, enum ath_reset_type type)
686 {
687 #ifdef CONFIG_ATH9K_DEBUGFS
688 RESET_STAT_INC(sc, type);
689 #endif
690 set_bit(SC_OP_HW_RESET, &sc->sc_flags);
691 ieee80211_queue_work(sc->hw, &sc->hw_reset_work);
692 }
693
694 void ath_reset_work(struct work_struct *work)
695 {
696 struct ath_softc *sc = container_of(work, struct ath_softc, hw_reset_work);
697
698 ath_reset(sc);
699 }
700
701 /**********************/
702 /* mac80211 callbacks */
703 /**********************/
704
705 static int ath9k_start(struct ieee80211_hw *hw)
706 {
707 struct ath_softc *sc = hw->priv;
708 struct ath_hw *ah = sc->sc_ah;
709 struct ath_common *common = ath9k_hw_common(ah);
710 struct ieee80211_channel *curchan = hw->conf.chandef.chan;
711 struct ath9k_channel *init_channel;
712 int r;
713
714 ath_dbg(common, CONFIG,
715 "Starting driver with initial channel: %d MHz\n",
716 curchan->center_freq);
717
718 ath9k_ps_wakeup(sc);
719 mutex_lock(&sc->mutex);
720
721 init_channel = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef);
722
723 /* Reset SERDES registers */
724 ath9k_hw_configpcipowersave(ah, false);
725
726 /*
727 * The basic interface to setting the hardware in a good
728 * state is ``reset''. On return the hardware is known to
729 * be powered up and with interrupts disabled. This must
730 * be followed by initialization of the appropriate bits
731 * and then setup of the interrupt mask.
732 */
733 spin_lock_bh(&sc->sc_pcu_lock);
734
735 atomic_set(&ah->intr_ref_cnt, -1);
736
737 r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
738 if (r) {
739 ath_err(common,
740 "Unable to reset hardware; reset status %d (freq %u MHz)\n",
741 r, curchan->center_freq);
742 ah->reset_power_on = false;
743 }
744
745 /* Setup our intr mask. */
746 ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
747 ATH9K_INT_RXORN | ATH9K_INT_FATAL |
748 ATH9K_INT_GLOBAL;
749
750 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
751 ah->imask |= ATH9K_INT_RXHP |
752 ATH9K_INT_RXLP;
753 else
754 ah->imask |= ATH9K_INT_RX;
755
756 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG)
757 ah->imask |= ATH9K_INT_BB_WATCHDOG;
758
759 /*
760 * Enable GTT interrupts only for AR9003/AR9004 chips
761 * for now.
762 */
763 if (AR_SREV_9300_20_OR_LATER(ah))
764 ah->imask |= ATH9K_INT_GTT;
765
766 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
767 ah->imask |= ATH9K_INT_CST;
768
769 ath_mci_enable(sc);
770
771 clear_bit(SC_OP_INVALID, &sc->sc_flags);
772 sc->sc_ah->is_monitoring = false;
773
774 if (!ath_complete_reset(sc, false))
775 ah->reset_power_on = false;
776
777 if (ah->led_pin >= 0) {
778 ath9k_hw_cfg_output(ah, ah->led_pin,
779 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
780 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
781 }
782
783 /*
784 * Reset key cache to sane defaults (all entries cleared) instead of
785 * semi-random values after suspend/resume.
786 */
787 ath9k_cmn_init_crypto(sc->sc_ah);
788
789 ath9k_hw_reset_tsf(ah);
790
791 spin_unlock_bh(&sc->sc_pcu_lock);
792
793 mutex_unlock(&sc->mutex);
794
795 ath9k_ps_restore(sc);
796
797 return 0;
798 }
799
800 static void ath9k_tx(struct ieee80211_hw *hw,
801 struct ieee80211_tx_control *control,
802 struct sk_buff *skb)
803 {
804 struct ath_softc *sc = hw->priv;
805 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
806 struct ath_tx_control txctl;
807 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
808 unsigned long flags;
809
810 if (sc->ps_enabled) {
811 /*
812 * mac80211 does not set PM field for normal data frames, so we
813 * need to update that based on the current PS mode.
814 */
815 if (ieee80211_is_data(hdr->frame_control) &&
816 !ieee80211_is_nullfunc(hdr->frame_control) &&
817 !ieee80211_has_pm(hdr->frame_control)) {
818 ath_dbg(common, PS,
819 "Add PM=1 for a TX frame while in PS mode\n");
820 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
821 }
822 }
823
824 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_NETWORK_SLEEP)) {
825 /*
826 * We are using PS-Poll and mac80211 can request TX while in
827 * power save mode. Need to wake up hardware for the TX to be
828 * completed and if needed, also for RX of buffered frames.
829 */
830 ath9k_ps_wakeup(sc);
831 spin_lock_irqsave(&sc->sc_pm_lock, flags);
832 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
833 ath9k_hw_setrxabort(sc->sc_ah, 0);
834 if (ieee80211_is_pspoll(hdr->frame_control)) {
835 ath_dbg(common, PS,
836 "Sending PS-Poll to pick a buffered frame\n");
837 sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
838 } else {
839 ath_dbg(common, PS, "Wake up to complete TX\n");
840 sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
841 }
842 /*
843 * The actual restore operation will happen only after
844 * the ps_flags bit is cleared. We are just dropping
845 * the ps_usecount here.
846 */
847 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
848 ath9k_ps_restore(sc);
849 }
850
851 /*
852 * Cannot tx while the hardware is in full sleep, it first needs a full
853 * chip reset to recover from that
854 */
855 if (unlikely(sc->sc_ah->power_mode == ATH9K_PM_FULL_SLEEP)) {
856 ath_err(common, "TX while HW is in FULL_SLEEP mode\n");
857 goto exit;
858 }
859
860 memset(&txctl, 0, sizeof(struct ath_tx_control));
861 txctl.txq = sc->tx.txq_map[skb_get_queue_mapping(skb)];
862 txctl.sta = control->sta;
863
864 ath_dbg(common, XMIT, "transmitting packet, skb: %p\n", skb);
865
866 if (ath_tx_start(hw, skb, &txctl) != 0) {
867 ath_dbg(common, XMIT, "TX failed\n");
868 TX_STAT_INC(txctl.txq->axq_qnum, txfailed);
869 goto exit;
870 }
871
872 return;
873 exit:
874 ieee80211_free_txskb(hw, skb);
875 }
876
877 static void ath9k_stop(struct ieee80211_hw *hw)
878 {
879 struct ath_softc *sc = hw->priv;
880 struct ath_hw *ah = sc->sc_ah;
881 struct ath_common *common = ath9k_hw_common(ah);
882 bool prev_idle;
883
884 mutex_lock(&sc->mutex);
885
886 ath_cancel_work(sc);
887
888 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
889 ath_dbg(common, ANY, "Device not present\n");
890 mutex_unlock(&sc->mutex);
891 return;
892 }
893
894 /* Ensure HW is awake when we try to shut it down. */
895 ath9k_ps_wakeup(sc);
896
897 spin_lock_bh(&sc->sc_pcu_lock);
898
899 /* prevent tasklets to enable interrupts once we disable them */
900 ah->imask &= ~ATH9K_INT_GLOBAL;
901
902 /* make sure h/w will not generate any interrupt
903 * before setting the invalid flag. */
904 ath9k_hw_disable_interrupts(ah);
905
906 spin_unlock_bh(&sc->sc_pcu_lock);
907
908 /* we can now sync irq and kill any running tasklets, since we already
909 * disabled interrupts and not holding a spin lock */
910 synchronize_irq(sc->irq);
911 tasklet_kill(&sc->intr_tq);
912 tasklet_kill(&sc->bcon_tasklet);
913
914 prev_idle = sc->ps_idle;
915 sc->ps_idle = true;
916
917 spin_lock_bh(&sc->sc_pcu_lock);
918
919 if (ah->led_pin >= 0) {
920 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
921 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
922 }
923
924 ath_prepare_reset(sc);
925
926 if (sc->rx.frag) {
927 dev_kfree_skb_any(sc->rx.frag);
928 sc->rx.frag = NULL;
929 }
930
931 if (!ah->curchan)
932 ah->curchan = ath9k_cmn_get_channel(hw, ah, &hw->conf.chandef);
933
934 ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
935 ath9k_hw_phy_disable(ah);
936
937 ath9k_hw_configpcipowersave(ah, true);
938
939 spin_unlock_bh(&sc->sc_pcu_lock);
940
941 ath9k_ps_restore(sc);
942
943 set_bit(SC_OP_INVALID, &sc->sc_flags);
944 sc->ps_idle = prev_idle;
945
946 mutex_unlock(&sc->mutex);
947
948 ath_dbg(common, CONFIG, "Driver halt\n");
949 }
950
951 static bool ath9k_uses_beacons(int type)
952 {
953 switch (type) {
954 case NL80211_IFTYPE_AP:
955 case NL80211_IFTYPE_ADHOC:
956 case NL80211_IFTYPE_MESH_POINT:
957 return true;
958 default:
959 return false;
960 }
961 }
962
963 static void ath9k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
964 {
965 struct ath9k_vif_iter_data *iter_data = data;
966 int i;
967
968 if (iter_data->has_hw_macaddr) {
969 for (i = 0; i < ETH_ALEN; i++)
970 iter_data->mask[i] &=
971 ~(iter_data->hw_macaddr[i] ^ mac[i]);
972 } else {
973 memcpy(iter_data->hw_macaddr, mac, ETH_ALEN);
974 iter_data->has_hw_macaddr = true;
975 }
976
977 switch (vif->type) {
978 case NL80211_IFTYPE_AP:
979 iter_data->naps++;
980 break;
981 case NL80211_IFTYPE_STATION:
982 iter_data->nstations++;
983 break;
984 case NL80211_IFTYPE_ADHOC:
985 iter_data->nadhocs++;
986 break;
987 case NL80211_IFTYPE_MESH_POINT:
988 iter_data->nmeshes++;
989 break;
990 case NL80211_IFTYPE_WDS:
991 iter_data->nwds++;
992 break;
993 default:
994 break;
995 }
996 }
997
998 static void ath9k_sta_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
999 {
1000 struct ath_softc *sc = data;
1001 struct ath_vif *avp = (void *)vif->drv_priv;
1002
1003 if (vif->type != NL80211_IFTYPE_STATION)
1004 return;
1005
1006 if (avp->primary_sta_vif)
1007 ath9k_set_assoc_state(sc, vif);
1008 }
1009
1010 /* Called with sc->mutex held. */
1011 void ath9k_calculate_iter_data(struct ieee80211_hw *hw,
1012 struct ieee80211_vif *vif,
1013 struct ath9k_vif_iter_data *iter_data)
1014 {
1015 struct ath_softc *sc = hw->priv;
1016 struct ath_hw *ah = sc->sc_ah;
1017 struct ath_common *common = ath9k_hw_common(ah);
1018
1019 /*
1020 * Pick the MAC address of the first interface as the new hardware
1021 * MAC address. The hardware will use it together with the BSSID mask
1022 * when matching addresses.
1023 */
1024 memset(iter_data, 0, sizeof(*iter_data));
1025 memset(&iter_data->mask, 0xff, ETH_ALEN);
1026
1027 if (vif)
1028 ath9k_vif_iter(iter_data, vif->addr, vif);
1029
1030 /* Get list of all active MAC addresses */
1031 ieee80211_iterate_active_interfaces_atomic(
1032 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1033 ath9k_vif_iter, iter_data);
1034
1035 memcpy(common->macaddr, iter_data->hw_macaddr, ETH_ALEN);
1036 }
1037
1038 /* Called with sc->mutex held. */
1039 static void ath9k_calculate_summary_state(struct ieee80211_hw *hw,
1040 struct ieee80211_vif *vif)
1041 {
1042 struct ath_softc *sc = hw->priv;
1043 struct ath_hw *ah = sc->sc_ah;
1044 struct ath_common *common = ath9k_hw_common(ah);
1045 struct ath9k_vif_iter_data iter_data;
1046 enum nl80211_iftype old_opmode = ah->opmode;
1047
1048 ath9k_calculate_iter_data(hw, vif, &iter_data);
1049
1050 memcpy(common->bssidmask, iter_data.mask, ETH_ALEN);
1051 ath_hw_setbssidmask(common);
1052
1053 if (iter_data.naps > 0) {
1054 ath9k_hw_set_tsfadjust(ah, true);
1055 ah->opmode = NL80211_IFTYPE_AP;
1056 } else {
1057 ath9k_hw_set_tsfadjust(ah, false);
1058
1059 if (iter_data.nmeshes)
1060 ah->opmode = NL80211_IFTYPE_MESH_POINT;
1061 else if (iter_data.nwds)
1062 ah->opmode = NL80211_IFTYPE_AP;
1063 else if (iter_data.nadhocs)
1064 ah->opmode = NL80211_IFTYPE_ADHOC;
1065 else
1066 ah->opmode = NL80211_IFTYPE_STATION;
1067 }
1068
1069 ath9k_hw_setopmode(ah);
1070
1071 if ((iter_data.nstations + iter_data.nadhocs + iter_data.nmeshes) > 0)
1072 ah->imask |= ATH9K_INT_TSFOOR;
1073 else
1074 ah->imask &= ~ATH9K_INT_TSFOOR;
1075
1076 ath9k_hw_set_interrupts(ah);
1077
1078 /*
1079 * If we are changing the opmode to STATION,
1080 * a beacon sync needs to be done.
1081 */
1082 if (ah->opmode == NL80211_IFTYPE_STATION &&
1083 old_opmode == NL80211_IFTYPE_AP &&
1084 test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags)) {
1085 ieee80211_iterate_active_interfaces_atomic(
1086 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1087 ath9k_sta_vif_iter, sc);
1088 }
1089 }
1090
1091 static int ath9k_add_interface(struct ieee80211_hw *hw,
1092 struct ieee80211_vif *vif)
1093 {
1094 struct ath_softc *sc = hw->priv;
1095 struct ath_hw *ah = sc->sc_ah;
1096 struct ath_common *common = ath9k_hw_common(ah);
1097 struct ath_vif *avp = (void *)vif->drv_priv;
1098 struct ath_node *an = &avp->mcast_node;
1099
1100 mutex_lock(&sc->mutex);
1101
1102 if (config_enabled(CONFIG_ATH9K_TX99)) {
1103 if (sc->nvifs >= 1) {
1104 mutex_unlock(&sc->mutex);
1105 return -EOPNOTSUPP;
1106 }
1107 sc->tx99_vif = vif;
1108 }
1109
1110 ath_dbg(common, CONFIG, "Attach a VIF of type: %d\n", vif->type);
1111 sc->nvifs++;
1112
1113 ath9k_ps_wakeup(sc);
1114 ath9k_calculate_summary_state(hw, vif);
1115 ath9k_ps_restore(sc);
1116
1117 if (ath9k_uses_beacons(vif->type))
1118 ath9k_beacon_assign_slot(sc, vif);
1119
1120 an->sc = sc;
1121 an->sta = NULL;
1122 an->vif = vif;
1123 an->no_ps_filter = true;
1124 ath_tx_node_init(sc, an);
1125
1126 mutex_unlock(&sc->mutex);
1127 return 0;
1128 }
1129
1130 static int ath9k_change_interface(struct ieee80211_hw *hw,
1131 struct ieee80211_vif *vif,
1132 enum nl80211_iftype new_type,
1133 bool p2p)
1134 {
1135 struct ath_softc *sc = hw->priv;
1136 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1137
1138 mutex_lock(&sc->mutex);
1139
1140 if (config_enabled(CONFIG_ATH9K_TX99)) {
1141 mutex_unlock(&sc->mutex);
1142 return -EOPNOTSUPP;
1143 }
1144
1145 ath_dbg(common, CONFIG, "Change Interface\n");
1146
1147 if (ath9k_uses_beacons(vif->type))
1148 ath9k_beacon_remove_slot(sc, vif);
1149
1150 vif->type = new_type;
1151 vif->p2p = p2p;
1152
1153 ath9k_ps_wakeup(sc);
1154 ath9k_calculate_summary_state(hw, vif);
1155 ath9k_ps_restore(sc);
1156
1157 if (ath9k_uses_beacons(vif->type))
1158 ath9k_beacon_assign_slot(sc, vif);
1159
1160 mutex_unlock(&sc->mutex);
1161 return 0;
1162 }
1163
1164 static void ath9k_remove_interface(struct ieee80211_hw *hw,
1165 struct ieee80211_vif *vif)
1166 {
1167 struct ath_softc *sc = hw->priv;
1168 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1169 struct ath_vif *avp = (void *)vif->drv_priv;
1170
1171 ath_dbg(common, CONFIG, "Detach Interface\n");
1172
1173 mutex_lock(&sc->mutex);
1174
1175 sc->nvifs--;
1176 sc->tx99_vif = NULL;
1177
1178 if (ath9k_uses_beacons(vif->type))
1179 ath9k_beacon_remove_slot(sc, vif);
1180
1181 if (sc->csa_vif == vif)
1182 sc->csa_vif = NULL;
1183
1184 ath9k_ps_wakeup(sc);
1185 ath9k_calculate_summary_state(hw, NULL);
1186 ath9k_ps_restore(sc);
1187
1188 ath_tx_node_cleanup(sc, &avp->mcast_node);
1189
1190 mutex_unlock(&sc->mutex);
1191 }
1192
1193 static void ath9k_enable_ps(struct ath_softc *sc)
1194 {
1195 struct ath_hw *ah = sc->sc_ah;
1196 struct ath_common *common = ath9k_hw_common(ah);
1197
1198 if (config_enabled(CONFIG_ATH9K_TX99))
1199 return;
1200
1201 sc->ps_enabled = true;
1202 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1203 if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
1204 ah->imask |= ATH9K_INT_TIM_TIMER;
1205 ath9k_hw_set_interrupts(ah);
1206 }
1207 ath9k_hw_setrxabort(ah, 1);
1208 }
1209 ath_dbg(common, PS, "PowerSave enabled\n");
1210 }
1211
1212 static void ath9k_disable_ps(struct ath_softc *sc)
1213 {
1214 struct ath_hw *ah = sc->sc_ah;
1215 struct ath_common *common = ath9k_hw_common(ah);
1216
1217 if (config_enabled(CONFIG_ATH9K_TX99))
1218 return;
1219
1220 sc->ps_enabled = false;
1221 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1222 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1223 ath9k_hw_setrxabort(ah, 0);
1224 sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
1225 PS_WAIT_FOR_CAB |
1226 PS_WAIT_FOR_PSPOLL_DATA |
1227 PS_WAIT_FOR_TX_ACK);
1228 if (ah->imask & ATH9K_INT_TIM_TIMER) {
1229 ah->imask &= ~ATH9K_INT_TIM_TIMER;
1230 ath9k_hw_set_interrupts(ah);
1231 }
1232 }
1233 ath_dbg(common, PS, "PowerSave disabled\n");
1234 }
1235
1236 void ath9k_spectral_scan_trigger(struct ieee80211_hw *hw)
1237 {
1238 struct ath_softc *sc = hw->priv;
1239 struct ath_hw *ah = sc->sc_ah;
1240 struct ath_common *common = ath9k_hw_common(ah);
1241 u32 rxfilter;
1242
1243 if (config_enabled(CONFIG_ATH9K_TX99))
1244 return;
1245
1246 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1247 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1248 return;
1249 }
1250
1251 ath9k_ps_wakeup(sc);
1252 rxfilter = ath9k_hw_getrxfilter(ah);
1253 ath9k_hw_setrxfilter(ah, rxfilter |
1254 ATH9K_RX_FILTER_PHYRADAR |
1255 ATH9K_RX_FILTER_PHYERR);
1256
1257 /* TODO: usually this should not be neccesary, but for some reason
1258 * (or in some mode?) the trigger must be called after the
1259 * configuration, otherwise the register will have its values reset
1260 * (on my ar9220 to value 0x01002310)
1261 */
1262 ath9k_spectral_scan_config(hw, sc->spectral_mode);
1263 ath9k_hw_ops(ah)->spectral_scan_trigger(ah);
1264 ath9k_ps_restore(sc);
1265 }
1266
1267 int ath9k_spectral_scan_config(struct ieee80211_hw *hw,
1268 enum spectral_mode spectral_mode)
1269 {
1270 struct ath_softc *sc = hw->priv;
1271 struct ath_hw *ah = sc->sc_ah;
1272 struct ath_common *common = ath9k_hw_common(ah);
1273
1274 if (!ath9k_hw_ops(ah)->spectral_scan_trigger) {
1275 ath_err(common, "spectrum analyzer not implemented on this hardware\n");
1276 return -1;
1277 }
1278
1279 switch (spectral_mode) {
1280 case SPECTRAL_DISABLED:
1281 sc->spec_config.enabled = 0;
1282 break;
1283 case SPECTRAL_BACKGROUND:
1284 /* send endless samples.
1285 * TODO: is this really useful for "background"?
1286 */
1287 sc->spec_config.endless = 1;
1288 sc->spec_config.enabled = 1;
1289 break;
1290 case SPECTRAL_CHANSCAN:
1291 case SPECTRAL_MANUAL:
1292 sc->spec_config.endless = 0;
1293 sc->spec_config.enabled = 1;
1294 break;
1295 default:
1296 return -1;
1297 }
1298
1299 ath9k_ps_wakeup(sc);
1300 ath9k_hw_ops(ah)->spectral_scan_config(ah, &sc->spec_config);
1301 ath9k_ps_restore(sc);
1302
1303 sc->spectral_mode = spectral_mode;
1304
1305 return 0;
1306 }
1307
1308 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
1309 {
1310 struct ath_softc *sc = hw->priv;
1311 struct ath_hw *ah = sc->sc_ah;
1312 struct ath_common *common = ath9k_hw_common(ah);
1313 struct ieee80211_conf *conf = &hw->conf;
1314 bool reset_channel = false;
1315
1316 ath9k_ps_wakeup(sc);
1317 mutex_lock(&sc->mutex);
1318
1319 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
1320 sc->ps_idle = !!(conf->flags & IEEE80211_CONF_IDLE);
1321 if (sc->ps_idle) {
1322 ath_cancel_work(sc);
1323 ath9k_stop_btcoex(sc);
1324 } else {
1325 ath9k_start_btcoex(sc);
1326 /*
1327 * The chip needs a reset to properly wake up from
1328 * full sleep
1329 */
1330 reset_channel = ah->chip_fullsleep;
1331 }
1332 }
1333
1334 /*
1335 * We just prepare to enable PS. We have to wait until our AP has
1336 * ACK'd our null data frame to disable RX otherwise we'll ignore
1337 * those ACKs and end up retransmitting the same null data frames.
1338 * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
1339 */
1340 if (changed & IEEE80211_CONF_CHANGE_PS) {
1341 unsigned long flags;
1342 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1343 if (conf->flags & IEEE80211_CONF_PS)
1344 ath9k_enable_ps(sc);
1345 else
1346 ath9k_disable_ps(sc);
1347 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1348 }
1349
1350 if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
1351 if (conf->flags & IEEE80211_CONF_MONITOR) {
1352 ath_dbg(common, CONFIG, "Monitor mode is enabled\n");
1353 sc->sc_ah->is_monitoring = true;
1354 } else {
1355 ath_dbg(common, CONFIG, "Monitor mode is disabled\n");
1356 sc->sc_ah->is_monitoring = false;
1357 }
1358 }
1359
1360 if ((changed & IEEE80211_CONF_CHANGE_CHANNEL) || reset_channel) {
1361 if (ath_set_channel(sc, &hw->conf.chandef) < 0) {
1362 ath_err(common, "Unable to set channel\n");
1363 mutex_unlock(&sc->mutex);
1364 ath9k_ps_restore(sc);
1365 return -EINVAL;
1366 }
1367 }
1368
1369 if (changed & IEEE80211_CONF_CHANGE_POWER) {
1370 ath_dbg(common, CONFIG, "Set power: %d\n", conf->power_level);
1371 sc->config.txpowlimit = 2 * conf->power_level;
1372 ath9k_cmn_update_txpow(ah, sc->curtxpow,
1373 sc->config.txpowlimit, &sc->curtxpow);
1374 }
1375
1376 mutex_unlock(&sc->mutex);
1377 ath9k_ps_restore(sc);
1378
1379 return 0;
1380 }
1381
1382 #define SUPPORTED_FILTERS \
1383 (FIF_PROMISC_IN_BSS | \
1384 FIF_ALLMULTI | \
1385 FIF_CONTROL | \
1386 FIF_PSPOLL | \
1387 FIF_OTHER_BSS | \
1388 FIF_BCN_PRBRESP_PROMISC | \
1389 FIF_PROBE_REQ | \
1390 FIF_FCSFAIL)
1391
1392 /* FIXME: sc->sc_full_reset ? */
1393 static void ath9k_configure_filter(struct ieee80211_hw *hw,
1394 unsigned int changed_flags,
1395 unsigned int *total_flags,
1396 u64 multicast)
1397 {
1398 struct ath_softc *sc = hw->priv;
1399 u32 rfilt;
1400
1401 changed_flags &= SUPPORTED_FILTERS;
1402 *total_flags &= SUPPORTED_FILTERS;
1403
1404 sc->rx.rxfilter = *total_flags;
1405 ath9k_ps_wakeup(sc);
1406 rfilt = ath_calcrxfilter(sc);
1407 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
1408 ath9k_ps_restore(sc);
1409
1410 ath_dbg(ath9k_hw_common(sc->sc_ah), CONFIG, "Set HW RX filter: 0x%x\n",
1411 rfilt);
1412 }
1413
1414 static int ath9k_sta_add(struct ieee80211_hw *hw,
1415 struct ieee80211_vif *vif,
1416 struct ieee80211_sta *sta)
1417 {
1418 struct ath_softc *sc = hw->priv;
1419 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1420 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1421 struct ieee80211_key_conf ps_key = { };
1422 int key;
1423
1424 ath_node_attach(sc, sta, vif);
1425
1426 if (vif->type != NL80211_IFTYPE_AP &&
1427 vif->type != NL80211_IFTYPE_AP_VLAN)
1428 return 0;
1429
1430 key = ath_key_config(common, vif, sta, &ps_key);
1431 if (key > 0)
1432 an->ps_key = key;
1433
1434 return 0;
1435 }
1436
1437 static void ath9k_del_ps_key(struct ath_softc *sc,
1438 struct ieee80211_vif *vif,
1439 struct ieee80211_sta *sta)
1440 {
1441 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1442 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1443 struct ieee80211_key_conf ps_key = { .hw_key_idx = an->ps_key };
1444
1445 if (!an->ps_key)
1446 return;
1447
1448 ath_key_delete(common, &ps_key);
1449 an->ps_key = 0;
1450 }
1451
1452 static int ath9k_sta_remove(struct ieee80211_hw *hw,
1453 struct ieee80211_vif *vif,
1454 struct ieee80211_sta *sta)
1455 {
1456 struct ath_softc *sc = hw->priv;
1457
1458 ath9k_del_ps_key(sc, vif, sta);
1459 ath_node_detach(sc, sta);
1460
1461 return 0;
1462 }
1463
1464 static void ath9k_sta_notify(struct ieee80211_hw *hw,
1465 struct ieee80211_vif *vif,
1466 enum sta_notify_cmd cmd,
1467 struct ieee80211_sta *sta)
1468 {
1469 struct ath_softc *sc = hw->priv;
1470 struct ath_node *an = (struct ath_node *) sta->drv_priv;
1471
1472 switch (cmd) {
1473 case STA_NOTIFY_SLEEP:
1474 an->sleeping = true;
1475 ath_tx_aggr_sleep(sta, sc, an);
1476 break;
1477 case STA_NOTIFY_AWAKE:
1478 an->sleeping = false;
1479 ath_tx_aggr_wakeup(sc, an);
1480 break;
1481 }
1482 }
1483
1484 static int ath9k_conf_tx(struct ieee80211_hw *hw,
1485 struct ieee80211_vif *vif, u16 queue,
1486 const struct ieee80211_tx_queue_params *params)
1487 {
1488 struct ath_softc *sc = hw->priv;
1489 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1490 struct ath_txq *txq;
1491 struct ath9k_tx_queue_info qi;
1492 int ret = 0;
1493
1494 if (queue >= IEEE80211_NUM_ACS)
1495 return 0;
1496
1497 txq = sc->tx.txq_map[queue];
1498
1499 ath9k_ps_wakeup(sc);
1500 mutex_lock(&sc->mutex);
1501
1502 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
1503
1504 qi.tqi_aifs = params->aifs;
1505 qi.tqi_cwmin = params->cw_min;
1506 qi.tqi_cwmax = params->cw_max;
1507 qi.tqi_burstTime = params->txop * 32;
1508
1509 ath_dbg(common, CONFIG,
1510 "Configure tx [queue/halq] [%d/%d], aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
1511 queue, txq->axq_qnum, params->aifs, params->cw_min,
1512 params->cw_max, params->txop);
1513
1514 ath_update_max_aggr_framelen(sc, queue, qi.tqi_burstTime);
1515 ret = ath_txq_update(sc, txq->axq_qnum, &qi);
1516 if (ret)
1517 ath_err(common, "TXQ Update failed\n");
1518
1519 mutex_unlock(&sc->mutex);
1520 ath9k_ps_restore(sc);
1521
1522 return ret;
1523 }
1524
1525 static int ath9k_set_key(struct ieee80211_hw *hw,
1526 enum set_key_cmd cmd,
1527 struct ieee80211_vif *vif,
1528 struct ieee80211_sta *sta,
1529 struct ieee80211_key_conf *key)
1530 {
1531 struct ath_softc *sc = hw->priv;
1532 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1533 int ret = 0;
1534
1535 if (ath9k_modparam_nohwcrypt)
1536 return -ENOSPC;
1537
1538 if ((vif->type == NL80211_IFTYPE_ADHOC ||
1539 vif->type == NL80211_IFTYPE_MESH_POINT) &&
1540 (key->cipher == WLAN_CIPHER_SUITE_TKIP ||
1541 key->cipher == WLAN_CIPHER_SUITE_CCMP) &&
1542 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
1543 /*
1544 * For now, disable hw crypto for the RSN IBSS group keys. This
1545 * could be optimized in the future to use a modified key cache
1546 * design to support per-STA RX GTK, but until that gets
1547 * implemented, use of software crypto for group addressed
1548 * frames is a acceptable to allow RSN IBSS to be used.
1549 */
1550 return -EOPNOTSUPP;
1551 }
1552
1553 mutex_lock(&sc->mutex);
1554 ath9k_ps_wakeup(sc);
1555 ath_dbg(common, CONFIG, "Set HW Key\n");
1556
1557 switch (cmd) {
1558 case SET_KEY:
1559 if (sta)
1560 ath9k_del_ps_key(sc, vif, sta);
1561
1562 ret = ath_key_config(common, vif, sta, key);
1563 if (ret >= 0) {
1564 key->hw_key_idx = ret;
1565 /* push IV and Michael MIC generation to stack */
1566 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
1567 if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
1568 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
1569 if (sc->sc_ah->sw_mgmt_crypto &&
1570 key->cipher == WLAN_CIPHER_SUITE_CCMP)
1571 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
1572 ret = 0;
1573 }
1574 break;
1575 case DISABLE_KEY:
1576 ath_key_delete(common, key);
1577 break;
1578 default:
1579 ret = -EINVAL;
1580 }
1581
1582 ath9k_ps_restore(sc);
1583 mutex_unlock(&sc->mutex);
1584
1585 return ret;
1586 }
1587
1588 static void ath9k_set_assoc_state(struct ath_softc *sc,
1589 struct ieee80211_vif *vif)
1590 {
1591 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1592 struct ath_vif *avp = (void *)vif->drv_priv;
1593 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1594 unsigned long flags;
1595
1596 set_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1597 avp->primary_sta_vif = true;
1598
1599 /*
1600 * Set the AID, BSSID and do beacon-sync only when
1601 * the HW opmode is STATION.
1602 *
1603 * But the primary bit is set above in any case.
1604 */
1605 if (sc->sc_ah->opmode != NL80211_IFTYPE_STATION)
1606 return;
1607
1608 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1609 common->curaid = bss_conf->aid;
1610 ath9k_hw_write_associd(sc->sc_ah);
1611
1612 sc->last_rssi = ATH_RSSI_DUMMY_MARKER;
1613 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1614
1615 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1616 sc->ps_flags |= PS_BEACON_SYNC | PS_WAIT_FOR_BEACON;
1617 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1618
1619 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1620 ath9k_mci_update_wlan_channels(sc, false);
1621
1622 ath_dbg(common, CONFIG,
1623 "Primary Station interface: %pM, BSSID: %pM\n",
1624 vif->addr, common->curbssid);
1625 }
1626
1627 static void ath9k_bss_assoc_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
1628 {
1629 struct ath_softc *sc = data;
1630 struct ieee80211_bss_conf *bss_conf = &vif->bss_conf;
1631
1632 if (test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags))
1633 return;
1634
1635 if (bss_conf->assoc)
1636 ath9k_set_assoc_state(sc, vif);
1637 }
1638
1639 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
1640 struct ieee80211_vif *vif,
1641 struct ieee80211_bss_conf *bss_conf,
1642 u32 changed)
1643 {
1644 #define CHECK_ANI \
1645 (BSS_CHANGED_ASSOC | \
1646 BSS_CHANGED_IBSS | \
1647 BSS_CHANGED_BEACON_ENABLED)
1648
1649 struct ath_softc *sc = hw->priv;
1650 struct ath_hw *ah = sc->sc_ah;
1651 struct ath_common *common = ath9k_hw_common(ah);
1652 struct ath_vif *avp = (void *)vif->drv_priv;
1653 int slottime;
1654
1655 ath9k_ps_wakeup(sc);
1656 mutex_lock(&sc->mutex);
1657
1658 if (changed & BSS_CHANGED_ASSOC) {
1659 ath_dbg(common, CONFIG, "BSSID %pM Changed ASSOC %d\n",
1660 bss_conf->bssid, bss_conf->assoc);
1661
1662 if (avp->primary_sta_vif && !bss_conf->assoc) {
1663 clear_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags);
1664 avp->primary_sta_vif = false;
1665
1666 if (ah->opmode == NL80211_IFTYPE_STATION)
1667 clear_bit(SC_OP_BEACONS, &sc->sc_flags);
1668 }
1669
1670 ieee80211_iterate_active_interfaces_atomic(
1671 sc->hw, IEEE80211_IFACE_ITER_RESUME_ALL,
1672 ath9k_bss_assoc_iter, sc);
1673
1674 if (!test_bit(SC_OP_PRIM_STA_VIF, &sc->sc_flags) &&
1675 ah->opmode == NL80211_IFTYPE_STATION) {
1676 memset(common->curbssid, 0, ETH_ALEN);
1677 common->curaid = 0;
1678 ath9k_hw_write_associd(sc->sc_ah);
1679 if (ath9k_hw_mci_is_enabled(sc->sc_ah))
1680 ath9k_mci_update_wlan_channels(sc, true);
1681 }
1682 }
1683
1684 if (changed & BSS_CHANGED_IBSS) {
1685 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
1686 common->curaid = bss_conf->aid;
1687 ath9k_hw_write_associd(sc->sc_ah);
1688 }
1689
1690 if ((changed & BSS_CHANGED_BEACON_ENABLED) ||
1691 (changed & BSS_CHANGED_BEACON_INT))
1692 ath9k_beacon_config(sc, vif, changed);
1693
1694 if (changed & BSS_CHANGED_ERP_SLOT) {
1695 if (bss_conf->use_short_slot)
1696 slottime = 9;
1697 else
1698 slottime = 20;
1699 if (vif->type == NL80211_IFTYPE_AP) {
1700 /*
1701 * Defer update, so that connected stations can adjust
1702 * their settings at the same time.
1703 * See beacon.c for more details
1704 */
1705 sc->beacon.slottime = slottime;
1706 sc->beacon.updateslot = UPDATE;
1707 } else {
1708 ah->slottime = slottime;
1709 ath9k_hw_init_global_settings(ah);
1710 }
1711 }
1712
1713 if (changed & CHECK_ANI)
1714 ath_check_ani(sc);
1715
1716 mutex_unlock(&sc->mutex);
1717 ath9k_ps_restore(sc);
1718
1719 #undef CHECK_ANI
1720 }
1721
1722 static u64 ath9k_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1723 {
1724 struct ath_softc *sc = hw->priv;
1725 u64 tsf;
1726
1727 mutex_lock(&sc->mutex);
1728 ath9k_ps_wakeup(sc);
1729 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1730 ath9k_ps_restore(sc);
1731 mutex_unlock(&sc->mutex);
1732
1733 return tsf;
1734 }
1735
1736 static void ath9k_set_tsf(struct ieee80211_hw *hw,
1737 struct ieee80211_vif *vif,
1738 u64 tsf)
1739 {
1740 struct ath_softc *sc = hw->priv;
1741
1742 mutex_lock(&sc->mutex);
1743 ath9k_ps_wakeup(sc);
1744 ath9k_hw_settsf64(sc->sc_ah, tsf);
1745 ath9k_ps_restore(sc);
1746 mutex_unlock(&sc->mutex);
1747 }
1748
1749 static void ath9k_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
1750 {
1751 struct ath_softc *sc = hw->priv;
1752
1753 mutex_lock(&sc->mutex);
1754
1755 ath9k_ps_wakeup(sc);
1756 ath9k_hw_reset_tsf(sc->sc_ah);
1757 ath9k_ps_restore(sc);
1758
1759 mutex_unlock(&sc->mutex);
1760 }
1761
1762 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
1763 struct ieee80211_vif *vif,
1764 enum ieee80211_ampdu_mlme_action action,
1765 struct ieee80211_sta *sta,
1766 u16 tid, u16 *ssn, u8 buf_size)
1767 {
1768 struct ath_softc *sc = hw->priv;
1769 bool flush = false;
1770 int ret = 0;
1771
1772 mutex_lock(&sc->mutex);
1773
1774 switch (action) {
1775 case IEEE80211_AMPDU_RX_START:
1776 break;
1777 case IEEE80211_AMPDU_RX_STOP:
1778 break;
1779 case IEEE80211_AMPDU_TX_START:
1780 ath9k_ps_wakeup(sc);
1781 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
1782 if (!ret)
1783 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1784 ath9k_ps_restore(sc);
1785 break;
1786 case IEEE80211_AMPDU_TX_STOP_FLUSH:
1787 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
1788 flush = true;
1789 case IEEE80211_AMPDU_TX_STOP_CONT:
1790 ath9k_ps_wakeup(sc);
1791 ath_tx_aggr_stop(sc, sta, tid);
1792 if (!flush)
1793 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
1794 ath9k_ps_restore(sc);
1795 break;
1796 case IEEE80211_AMPDU_TX_OPERATIONAL:
1797 ath9k_ps_wakeup(sc);
1798 ath_tx_aggr_resume(sc, sta, tid);
1799 ath9k_ps_restore(sc);
1800 break;
1801 default:
1802 ath_err(ath9k_hw_common(sc->sc_ah), "Unknown AMPDU action\n");
1803 }
1804
1805 mutex_unlock(&sc->mutex);
1806
1807 return ret;
1808 }
1809
1810 static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
1811 struct survey_info *survey)
1812 {
1813 struct ath_softc *sc = hw->priv;
1814 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1815 struct ieee80211_supported_band *sband;
1816 struct ieee80211_channel *chan;
1817 int pos;
1818
1819 if (config_enabled(CONFIG_ATH9K_TX99))
1820 return -EOPNOTSUPP;
1821
1822 spin_lock_bh(&common->cc_lock);
1823 if (idx == 0)
1824 ath_update_survey_stats(sc);
1825
1826 sband = hw->wiphy->bands[IEEE80211_BAND_2GHZ];
1827 if (sband && idx >= sband->n_channels) {
1828 idx -= sband->n_channels;
1829 sband = NULL;
1830 }
1831
1832 if (!sband)
1833 sband = hw->wiphy->bands[IEEE80211_BAND_5GHZ];
1834
1835 if (!sband || idx >= sband->n_channels) {
1836 spin_unlock_bh(&common->cc_lock);
1837 return -ENOENT;
1838 }
1839
1840 chan = &sband->channels[idx];
1841 pos = chan->hw_value;
1842 memcpy(survey, &sc->survey[pos], sizeof(*survey));
1843 survey->channel = chan;
1844 spin_unlock_bh(&common->cc_lock);
1845
1846 return 0;
1847 }
1848
1849 static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
1850 {
1851 struct ath_softc *sc = hw->priv;
1852 struct ath_hw *ah = sc->sc_ah;
1853
1854 if (config_enabled(CONFIG_ATH9K_TX99))
1855 return;
1856
1857 mutex_lock(&sc->mutex);
1858 ah->coverage_class = coverage_class;
1859
1860 ath9k_ps_wakeup(sc);
1861 ath9k_hw_init_global_settings(ah);
1862 ath9k_ps_restore(sc);
1863
1864 mutex_unlock(&sc->mutex);
1865 }
1866
1867 static bool ath9k_has_tx_pending(struct ath_softc *sc)
1868 {
1869 int i, npend;
1870
1871 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1872 if (!ATH_TXQ_SETUP(sc, i))
1873 continue;
1874
1875 if (!sc->tx.txq[i].axq_depth)
1876 continue;
1877
1878 npend = ath9k_has_pending_frames(sc, &sc->tx.txq[i]);
1879 if (npend)
1880 break;
1881 }
1882
1883 return !!npend;
1884 }
1885
1886 static void ath9k_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1887 {
1888 struct ath_softc *sc = hw->priv;
1889 struct ath_hw *ah = sc->sc_ah;
1890 struct ath_common *common = ath9k_hw_common(ah);
1891 int timeout = HZ / 5; /* 200 ms */
1892 bool drain_txq;
1893
1894 mutex_lock(&sc->mutex);
1895 cancel_delayed_work_sync(&sc->tx_complete_work);
1896
1897 if (ah->ah_flags & AH_UNPLUGGED) {
1898 ath_dbg(common, ANY, "Device has been unplugged!\n");
1899 mutex_unlock(&sc->mutex);
1900 return;
1901 }
1902
1903 if (test_bit(SC_OP_INVALID, &sc->sc_flags)) {
1904 ath_dbg(common, ANY, "Device not present\n");
1905 mutex_unlock(&sc->mutex);
1906 return;
1907 }
1908
1909 if (wait_event_timeout(sc->tx_wait, !ath9k_has_tx_pending(sc),
1910 timeout) > 0)
1911 drop = false;
1912
1913 if (drop) {
1914 ath9k_ps_wakeup(sc);
1915 spin_lock_bh(&sc->sc_pcu_lock);
1916 drain_txq = ath_drain_all_txq(sc);
1917 spin_unlock_bh(&sc->sc_pcu_lock);
1918
1919 if (!drain_txq)
1920 ath_reset(sc);
1921
1922 ath9k_ps_restore(sc);
1923 ieee80211_wake_queues(hw);
1924 }
1925
1926 ieee80211_queue_delayed_work(hw, &sc->tx_complete_work, 0);
1927 mutex_unlock(&sc->mutex);
1928 }
1929
1930 static bool ath9k_tx_frames_pending(struct ieee80211_hw *hw)
1931 {
1932 struct ath_softc *sc = hw->priv;
1933 int i;
1934
1935 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1936 if (!ATH_TXQ_SETUP(sc, i))
1937 continue;
1938
1939 if (ath9k_has_pending_frames(sc, &sc->tx.txq[i]))
1940 return true;
1941 }
1942 return false;
1943 }
1944
1945 static int ath9k_tx_last_beacon(struct ieee80211_hw *hw)
1946 {
1947 struct ath_softc *sc = hw->priv;
1948 struct ath_hw *ah = sc->sc_ah;
1949 struct ieee80211_vif *vif;
1950 struct ath_vif *avp;
1951 struct ath_buf *bf;
1952 struct ath_tx_status ts;
1953 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1954 int status;
1955
1956 vif = sc->beacon.bslot[0];
1957 if (!vif)
1958 return 0;
1959
1960 if (!vif->bss_conf.enable_beacon)
1961 return 0;
1962
1963 avp = (void *)vif->drv_priv;
1964
1965 if (!sc->beacon.tx_processed && !edma) {
1966 tasklet_disable(&sc->bcon_tasklet);
1967
1968 bf = avp->av_bcbuf;
1969 if (!bf || !bf->bf_mpdu)
1970 goto skip;
1971
1972 status = ath9k_hw_txprocdesc(ah, bf->bf_desc, &ts);
1973 if (status == -EINPROGRESS)
1974 goto skip;
1975
1976 sc->beacon.tx_processed = true;
1977 sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
1978
1979 skip:
1980 tasklet_enable(&sc->bcon_tasklet);
1981 }
1982
1983 return sc->beacon.tx_last;
1984 }
1985
1986 static int ath9k_get_stats(struct ieee80211_hw *hw,
1987 struct ieee80211_low_level_stats *stats)
1988 {
1989 struct ath_softc *sc = hw->priv;
1990 struct ath_hw *ah = sc->sc_ah;
1991 struct ath9k_mib_stats *mib_stats = &ah->ah_mibStats;
1992
1993 stats->dot11ACKFailureCount = mib_stats->ackrcv_bad;
1994 stats->dot11RTSFailureCount = mib_stats->rts_bad;
1995 stats->dot11FCSErrorCount = mib_stats->fcs_bad;
1996 stats->dot11RTSSuccessCount = mib_stats->rts_good;
1997 return 0;
1998 }
1999
2000 static u32 fill_chainmask(u32 cap, u32 new)
2001 {
2002 u32 filled = 0;
2003 int i;
2004
2005 for (i = 0; cap && new; i++, cap >>= 1) {
2006 if (!(cap & BIT(0)))
2007 continue;
2008
2009 if (new & BIT(0))
2010 filled |= BIT(i);
2011
2012 new >>= 1;
2013 }
2014
2015 return filled;
2016 }
2017
2018 static bool validate_antenna_mask(struct ath_hw *ah, u32 val)
2019 {
2020 if (AR_SREV_9300_20_OR_LATER(ah))
2021 return true;
2022
2023 switch (val & 0x7) {
2024 case 0x1:
2025 case 0x3:
2026 case 0x7:
2027 return true;
2028 case 0x2:
2029 return (ah->caps.rx_chainmask == 1);
2030 default:
2031 return false;
2032 }
2033 }
2034
2035 static int ath9k_set_antenna(struct ieee80211_hw *hw, u32 tx_ant, u32 rx_ant)
2036 {
2037 struct ath_softc *sc = hw->priv;
2038 struct ath_hw *ah = sc->sc_ah;
2039
2040 if (ah->caps.rx_chainmask != 1)
2041 rx_ant |= tx_ant;
2042
2043 if (!validate_antenna_mask(ah, rx_ant) || !tx_ant)
2044 return -EINVAL;
2045
2046 sc->ant_rx = rx_ant;
2047 sc->ant_tx = tx_ant;
2048
2049 if (ah->caps.rx_chainmask == 1)
2050 return 0;
2051
2052 /* AR9100 runs into calibration issues if not all rx chains are enabled */
2053 if (AR_SREV_9100(ah))
2054 ah->rxchainmask = 0x7;
2055 else
2056 ah->rxchainmask = fill_chainmask(ah->caps.rx_chainmask, rx_ant);
2057
2058 ah->txchainmask = fill_chainmask(ah->caps.tx_chainmask, tx_ant);
2059 ath9k_reload_chainmask_settings(sc);
2060
2061 return 0;
2062 }
2063
2064 static int ath9k_get_antenna(struct ieee80211_hw *hw, u32 *tx_ant, u32 *rx_ant)
2065 {
2066 struct ath_softc *sc = hw->priv;
2067
2068 *tx_ant = sc->ant_tx;
2069 *rx_ant = sc->ant_rx;
2070 return 0;
2071 }
2072
2073 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2074 {
2075 struct ath_softc *sc = hw->priv;
2076 set_bit(SC_OP_SCANNING, &sc->sc_flags);
2077 }
2078
2079 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2080 {
2081 struct ath_softc *sc = hw->priv;
2082 clear_bit(SC_OP_SCANNING, &sc->sc_flags);
2083 }
2084
2085 static void ath9k_channel_switch_beacon(struct ieee80211_hw *hw,
2086 struct ieee80211_vif *vif,
2087 struct cfg80211_chan_def *chandef)
2088 {
2089 struct ath_softc *sc = hw->priv;
2090
2091 /* mac80211 does not support CSA in multi-if cases (yet) */
2092 if (WARN_ON(sc->csa_vif))
2093 return;
2094
2095 sc->csa_vif = vif;
2096 }
2097
2098 struct ieee80211_ops ath9k_ops = {
2099 .tx = ath9k_tx,
2100 .start = ath9k_start,
2101 .stop = ath9k_stop,
2102 .add_interface = ath9k_add_interface,
2103 .change_interface = ath9k_change_interface,
2104 .remove_interface = ath9k_remove_interface,
2105 .config = ath9k_config,
2106 .configure_filter = ath9k_configure_filter,
2107 .sta_add = ath9k_sta_add,
2108 .sta_remove = ath9k_sta_remove,
2109 .sta_notify = ath9k_sta_notify,
2110 .conf_tx = ath9k_conf_tx,
2111 .bss_info_changed = ath9k_bss_info_changed,
2112 .set_key = ath9k_set_key,
2113 .get_tsf = ath9k_get_tsf,
2114 .set_tsf = ath9k_set_tsf,
2115 .reset_tsf = ath9k_reset_tsf,
2116 .ampdu_action = ath9k_ampdu_action,
2117 .get_survey = ath9k_get_survey,
2118 .rfkill_poll = ath9k_rfkill_poll_state,
2119 .set_coverage_class = ath9k_set_coverage_class,
2120 .flush = ath9k_flush,
2121 .tx_frames_pending = ath9k_tx_frames_pending,
2122 .tx_last_beacon = ath9k_tx_last_beacon,
2123 .release_buffered_frames = ath9k_release_buffered_frames,
2124 .get_stats = ath9k_get_stats,
2125 .set_antenna = ath9k_set_antenna,
2126 .get_antenna = ath9k_get_antenna,
2127
2128 #ifdef CONFIG_ATH9K_WOW
2129 .suspend = ath9k_suspend,
2130 .resume = ath9k_resume,
2131 .set_wakeup = ath9k_set_wakeup,
2132 #endif
2133
2134 #ifdef CONFIG_ATH9K_DEBUGFS
2135 .get_et_sset_count = ath9k_get_et_sset_count,
2136 .get_et_stats = ath9k_get_et_stats,
2137 .get_et_strings = ath9k_get_et_strings,
2138 #endif
2139
2140 #if defined(CONFIG_MAC80211_DEBUGFS) && defined(CONFIG_ATH9K_STATION_STATISTICS)
2141 .sta_add_debugfs = ath9k_sta_add_debugfs,
2142 #endif
2143 .sw_scan_start = ath9k_sw_scan_start,
2144 .sw_scan_complete = ath9k_sw_scan_complete,
2145 .channel_switch_beacon = ath9k_channel_switch_beacon,
2146 };
Linux with added FPC-III support