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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / wireless / rtl818x / rtl8180 / dev.c
blob3867d1470b36aef5664bcab74e85f38702c8315d
1
2 /*
3 * Linux device driver for RTL8180 / RTL8185
4 *
5 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
6 * Copyright 2007 Andrea Merello <andrea.merello@gmail.com>
7 *
8 * Based on the r8180 driver, which is:
9 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 *
11 * Thanks to Realtek for their support!
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18 #include <linux/interrupt.h>
19 #include <linux/pci.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/etherdevice.h>
23 #include <linux/eeprom_93cx6.h>
24 #include <linux/module.h>
25 #include <net/mac80211.h>
26
27 #include "rtl8180.h"
28 #include "rtl8225.h"
29 #include "sa2400.h"
30 #include "max2820.h"
31 #include "grf5101.h"
32
33 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
34 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
35 MODULE_DESCRIPTION("RTL8180 / RTL8185 PCI wireless driver");
36 MODULE_LICENSE("GPL");
37
38 static DEFINE_PCI_DEVICE_TABLE(rtl8180_table) = {
39 /* rtl8185 */
40 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
41 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
42 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
43
44 /* rtl8180 */
45 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
46 { PCI_DEVICE(0x1799, 0x6001) },
47 { PCI_DEVICE(0x1799, 0x6020) },
48 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
49 { PCI_DEVICE(0x1186, 0x3301) },
50 { PCI_DEVICE(0x1432, 0x7106) },
51 { }
52 };
53
54 MODULE_DEVICE_TABLE(pci, rtl8180_table);
55
56 static const struct ieee80211_rate rtl818x_rates[] = {
57 { .bitrate = 10, .hw_value = 0, },
58 { .bitrate = 20, .hw_value = 1, },
59 { .bitrate = 55, .hw_value = 2, },
60 { .bitrate = 110, .hw_value = 3, },
61 { .bitrate = 60, .hw_value = 4, },
62 { .bitrate = 90, .hw_value = 5, },
63 { .bitrate = 120, .hw_value = 6, },
64 { .bitrate = 180, .hw_value = 7, },
65 { .bitrate = 240, .hw_value = 8, },
66 { .bitrate = 360, .hw_value = 9, },
67 { .bitrate = 480, .hw_value = 10, },
68 { .bitrate = 540, .hw_value = 11, },
69 };
70
71 static const struct ieee80211_channel rtl818x_channels[] = {
72 { .center_freq = 2412 },
73 { .center_freq = 2417 },
74 { .center_freq = 2422 },
75 { .center_freq = 2427 },
76 { .center_freq = 2432 },
77 { .center_freq = 2437 },
78 { .center_freq = 2442 },
79 { .center_freq = 2447 },
80 { .center_freq = 2452 },
81 { .center_freq = 2457 },
82 { .center_freq = 2462 },
83 { .center_freq = 2467 },
84 { .center_freq = 2472 },
85 { .center_freq = 2484 },
86 };
87
88
89 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
90 {
91 struct rtl8180_priv *priv = dev->priv;
92 int i = 10;
93 u32 buf;
94
95 buf = (data << 8) | addr;
96
97 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
98 while (i--) {
99 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
100 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
101 return;
102 }
103 }
104
105 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
106 {
107 struct rtl8180_priv *priv = dev->priv;
108 unsigned int count = 32;
109 u8 signal, agc, sq;
110 dma_addr_t mapping;
111
112 while (count--) {
113 struct rtl8180_rx_desc *entry = &priv->rx_ring[priv->rx_idx];
114 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
115 u32 flags = le32_to_cpu(entry->flags);
116
117 if (flags & RTL818X_RX_DESC_FLAG_OWN)
118 return;
119
120 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
121 RTL818X_RX_DESC_FLAG_FOF |
122 RTL818X_RX_DESC_FLAG_RX_ERR)))
123 goto done;
124 else {
125 u32 flags2 = le32_to_cpu(entry->flags2);
126 struct ieee80211_rx_status rx_status = {0};
127 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
128
129 if (unlikely(!new_skb))
130 goto done;
131
132 mapping = pci_map_single(priv->pdev,
133 skb_tail_pointer(new_skb),
134 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
135
136 if (pci_dma_mapping_error(priv->pdev, mapping)) {
137 kfree_skb(new_skb);
138 dev_err(&priv->pdev->dev, "RX DMA map error\n");
139
140 goto done;
141 }
142
143 pci_unmap_single(priv->pdev,
144 *((dma_addr_t *)skb->cb),
145 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
146 skb_put(skb, flags & 0xFFF);
147
148 rx_status.antenna = (flags2 >> 15) & 1;
149 rx_status.rate_idx = (flags >> 20) & 0xF;
150 agc = (flags2 >> 17) & 0x7F;
151 if (priv->r8185) {
152 if (rx_status.rate_idx > 3)
153 signal = 90 - clamp_t(u8, agc, 25, 90);
154 else
155 signal = 95 - clamp_t(u8, agc, 30, 95);
156 } else {
157 sq = flags2 & 0xff;
158 signal = priv->rf->calc_rssi(agc, sq);
159 }
160 rx_status.signal = signal;
161 rx_status.freq = dev->conf.chandef.chan->center_freq;
162 rx_status.band = dev->conf.chandef.chan->band;
163 rx_status.mactime = le64_to_cpu(entry->tsft);
164 rx_status.flag |= RX_FLAG_MACTIME_START;
165 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
166 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
167
168 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
169 ieee80211_rx_irqsafe(dev, skb);
170
171 skb = new_skb;
172 priv->rx_buf[priv->rx_idx] = skb;
173 *((dma_addr_t *) skb->cb) = mapping;
174 }
175
176 done:
177 entry->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
178 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
179 MAX_RX_SIZE);
180 if (priv->rx_idx == 31)
181 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
182 priv->rx_idx = (priv->rx_idx + 1) % 32;
183 }
184 }
185
186 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
187 {
188 struct rtl8180_priv *priv = dev->priv;
189 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
190
191 while (skb_queue_len(&ring->queue)) {
192 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
193 struct sk_buff *skb;
194 struct ieee80211_tx_info *info;
195 u32 flags = le32_to_cpu(entry->flags);
196
197 if (flags & RTL818X_TX_DESC_FLAG_OWN)
198 return;
199
200 ring->idx = (ring->idx + 1) % ring->entries;
201 skb = __skb_dequeue(&ring->queue);
202 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
203 skb->len, PCI_DMA_TODEVICE);
204
205 info = IEEE80211_SKB_CB(skb);
206 ieee80211_tx_info_clear_status(info);
207
208 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
209 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
210 info->flags |= IEEE80211_TX_STAT_ACK;
211
212 info->status.rates[0].count = (flags & 0xFF) + 1;
213 info->status.rates[1].idx = -1;
214
215 ieee80211_tx_status_irqsafe(dev, skb);
216 if (ring->entries - skb_queue_len(&ring->queue) == 2)
217 ieee80211_wake_queue(dev, prio);
218 }
219 }
220
221 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
222 {
223 struct ieee80211_hw *dev = dev_id;
224 struct rtl8180_priv *priv = dev->priv;
225 u16 reg;
226
227 spin_lock(&priv->lock);
228 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
229 if (unlikely(reg == 0xFFFF)) {
230 spin_unlock(&priv->lock);
231 return IRQ_HANDLED;
232 }
233
234 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
235
236 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
237 rtl8180_handle_tx(dev, 3);
238
239 if (reg & (RTL818X_INT_TXH_OK | RTL818X_INT_TXH_ERR))
240 rtl8180_handle_tx(dev, 2);
241
242 if (reg & (RTL818X_INT_TXN_OK | RTL818X_INT_TXN_ERR))
243 rtl8180_handle_tx(dev, 1);
244
245 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
246 rtl8180_handle_tx(dev, 0);
247
248 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
249 rtl8180_handle_rx(dev);
250
251 spin_unlock(&priv->lock);
252
253 return IRQ_HANDLED;
254 }
255
256 static void rtl8180_tx(struct ieee80211_hw *dev,
257 struct ieee80211_tx_control *control,
258 struct sk_buff *skb)
259 {
260 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
261 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
262 struct rtl8180_priv *priv = dev->priv;
263 struct rtl8180_tx_ring *ring;
264 struct rtl8180_tx_desc *entry;
265 unsigned long flags;
266 unsigned int idx, prio;
267 dma_addr_t mapping;
268 u32 tx_flags;
269 u8 rc_flags;
270 u16 plcp_len = 0;
271 __le16 rts_duration = 0;
272
273 prio = skb_get_queue_mapping(skb);
274 ring = &priv->tx_ring[prio];
275
276 mapping = pci_map_single(priv->pdev, skb->data,
277 skb->len, PCI_DMA_TODEVICE);
278
279 if (pci_dma_mapping_error(priv->pdev, mapping)) {
280 kfree_skb(skb);
281 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
282 return;
283
284 }
285
286 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
287 RTL818X_TX_DESC_FLAG_LS |
288 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
289 skb->len;
290
291 if (priv->r8185)
292 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
293 RTL818X_TX_DESC_FLAG_NO_ENC;
294
295 rc_flags = info->control.rates[0].flags;
296 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
297 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
298 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
299 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
300 tx_flags |= RTL818X_TX_DESC_FLAG_CTS;
301 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
302 }
303
304 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS)
305 rts_duration = ieee80211_rts_duration(dev, priv->vif, skb->len,
306 info);
307
308 if (!priv->r8185) {
309 unsigned int remainder;
310
311 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
312 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
313 remainder = (16 * (skb->len + 4)) %
314 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
315 if (remainder <= 6)
316 plcp_len |= 1 << 15;
317 }
318
319 spin_lock_irqsave(&priv->lock, flags);
320
321 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
322 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
323 priv->seqno += 0x10;
324 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
325 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
326 }
327
328 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
329 entry = &ring->desc[idx];
330
331 entry->rts_duration = rts_duration;
332 entry->plcp_len = cpu_to_le16(plcp_len);
333 entry->tx_buf = cpu_to_le32(mapping);
334 entry->frame_len = cpu_to_le32(skb->len);
335 entry->flags2 = info->control.rates[1].idx >= 0 ?
336 ieee80211_get_alt_retry_rate(dev, info, 0)->bitrate << 4 : 0;
337 entry->retry_limit = info->control.rates[0].count;
338 entry->flags = cpu_to_le32(tx_flags);
339 __skb_queue_tail(&ring->queue, skb);
340 if (ring->entries - skb_queue_len(&ring->queue) < 2)
341 ieee80211_stop_queue(dev, prio);
342
343 spin_unlock_irqrestore(&priv->lock, flags);
344
345 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING, (1 << (prio + 4)));
346 }
347
348 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
349 {
350 u8 reg;
351
352 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
353 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
354 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
355 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
356 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
357 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
358 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
359 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
360 }
361
362 static int rtl8180_init_hw(struct ieee80211_hw *dev)
363 {
364 struct rtl8180_priv *priv = dev->priv;
365 u16 reg;
366
367 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
368 rtl818x_ioread8(priv, &priv->map->CMD);
369 msleep(10);
370
371 /* reset */
372 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
373 rtl818x_ioread8(priv, &priv->map->CMD);
374
375 reg = rtl818x_ioread8(priv, &priv->map->CMD);
376 reg &= (1 << 1);
377 reg |= RTL818X_CMD_RESET;
378 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
379 rtl818x_ioread8(priv, &priv->map->CMD);
380 msleep(200);
381
382 /* check success of reset */
383 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
384 wiphy_err(dev->wiphy, "reset timeout!\n");
385 return -ETIMEDOUT;
386 }
387
388 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
389 rtl818x_ioread8(priv, &priv->map->CMD);
390 msleep(200);
391
392 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
393 /* For cardbus */
394 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
395 reg |= 1 << 1;
396 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg);
397 reg = rtl818x_ioread16(priv, &priv->map->FEMR);
398 reg |= (1 << 15) | (1 << 14) | (1 << 4);
399 rtl818x_iowrite16(priv, &priv->map->FEMR, reg);
400 }
401
402 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
403
404 if (!priv->r8185)
405 rtl8180_set_anaparam(priv, priv->anaparam);
406
407 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
408 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
409 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
410 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
411 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
412
413 /* TODO: necessary? specs indicate not */
414 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
415 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
416 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
417 if (priv->r8185) {
418 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
419 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
420 }
421 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
422
423 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
424
425 /* TODO: turn off hw wep on rtl8180 */
426
427 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
428
429 if (priv->r8185) {
430 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
431 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0x81);
432 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (8 << 4) | 0);
433
434 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
435
436 /* TODO: set ClkRun enable? necessary? */
437 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
438 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
439 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
440 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
441 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
442 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
443 } else {
444 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x1);
445 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
446
447 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
448 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
449 }
450
451 priv->rf->init(dev);
452 if (priv->r8185)
453 rtl818x_iowrite16(priv, &priv->map->BRSR, 0x01F3);
454 return 0;
455 }
456
457 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
458 {
459 struct rtl8180_priv *priv = dev->priv;
460 struct rtl8180_rx_desc *entry;
461 int i;
462
463 priv->rx_ring = pci_alloc_consistent(priv->pdev,
464 sizeof(*priv->rx_ring) * 32,
465 &priv->rx_ring_dma);
466
467 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
468 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
469 return -ENOMEM;
470 }
471
472 memset(priv->rx_ring, 0, sizeof(*priv->rx_ring) * 32);
473 priv->rx_idx = 0;
474
475 for (i = 0; i < 32; i++) {
476 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
477 dma_addr_t *mapping;
478 entry = &priv->rx_ring[i];
479 if (!skb)
480 return 0;
481
482 priv->rx_buf[i] = skb;
483 mapping = (dma_addr_t *)skb->cb;
484 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
485 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
486 entry->rx_buf = cpu_to_le32(*mapping);
487 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
488 MAX_RX_SIZE);
489 }
490 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
491 return 0;
492 }
493
494 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
495 {
496 struct rtl8180_priv *priv = dev->priv;
497 int i;
498
499 for (i = 0; i < 32; i++) {
500 struct sk_buff *skb = priv->rx_buf[i];
501 if (!skb)
502 continue;
503
504 pci_unmap_single(priv->pdev,
505 *((dma_addr_t *)skb->cb),
506 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
507 kfree_skb(skb);
508 }
509
510 pci_free_consistent(priv->pdev, sizeof(*priv->rx_ring) * 32,
511 priv->rx_ring, priv->rx_ring_dma);
512 priv->rx_ring = NULL;
513 }
514
515 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
516 unsigned int prio, unsigned int entries)
517 {
518 struct rtl8180_priv *priv = dev->priv;
519 struct rtl8180_tx_desc *ring;
520 dma_addr_t dma;
521 int i;
522
523 ring = pci_alloc_consistent(priv->pdev, sizeof(*ring) * entries, &dma);
524 if (!ring || (unsigned long)ring & 0xFF) {
525 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
526 prio);
527 return -ENOMEM;
528 }
529
530 memset(ring, 0, sizeof(*ring)*entries);
531 priv->tx_ring[prio].desc = ring;
532 priv->tx_ring[prio].dma = dma;
533 priv->tx_ring[prio].idx = 0;
534 priv->tx_ring[prio].entries = entries;
535 skb_queue_head_init(&priv->tx_ring[prio].queue);
536
537 for (i = 0; i < entries; i++)
538 ring[i].next_tx_desc =
539 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
540
541 return 0;
542 }
543
544 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
545 {
546 struct rtl8180_priv *priv = dev->priv;
547 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
548
549 while (skb_queue_len(&ring->queue)) {
550 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
551 struct sk_buff *skb = __skb_dequeue(&ring->queue);
552
553 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
554 skb->len, PCI_DMA_TODEVICE);
555 kfree_skb(skb);
556 ring->idx = (ring->idx + 1) % ring->entries;
557 }
558
559 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
560 ring->desc, ring->dma);
561 ring->desc = NULL;
562 }
563
564 static int rtl8180_start(struct ieee80211_hw *dev)
565 {
566 struct rtl8180_priv *priv = dev->priv;
567 int ret, i;
568 u32 reg;
569
570 ret = rtl8180_init_rx_ring(dev);
571 if (ret)
572 return ret;
573
574 for (i = 0; i < 4; i++)
575 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
576 goto err_free_rings;
577
578 ret = rtl8180_init_hw(dev);
579 if (ret)
580 goto err_free_rings;
581
582 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
583 rtl818x_iowrite32(priv, &priv->map->TBDA, priv->tx_ring[3].dma);
584 rtl818x_iowrite32(priv, &priv->map->THPDA, priv->tx_ring[2].dma);
585 rtl818x_iowrite32(priv, &priv->map->TNPDA, priv->tx_ring[1].dma);
586 rtl818x_iowrite32(priv, &priv->map->TLPDA, priv->tx_ring[0].dma);
587
588 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
589 IRQF_SHARED, KBUILD_MODNAME, dev);
590 if (ret) {
591 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
592 goto err_free_rings;
593 }
594
595 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
596
597 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
598 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
599
600 reg = RTL818X_RX_CONF_ONLYERLPKT |
601 RTL818X_RX_CONF_RX_AUTORESETPHY |
602 RTL818X_RX_CONF_MGMT |
603 RTL818X_RX_CONF_DATA |
604 (7 << 8 /* MAX RX DMA */) |
605 RTL818X_RX_CONF_BROADCAST |
606 RTL818X_RX_CONF_NICMAC;
607
608 if (priv->r8185)
609 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
610 else {
611 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
612 ? RTL818X_RX_CONF_CSDM1 : 0;
613 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
614 ? RTL818X_RX_CONF_CSDM2 : 0;
615 }
616
617 priv->rx_conf = reg;
618 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
619
620 if (priv->r8185) {
621 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
622 reg &= ~RTL818X_CW_CONF_PERPACKET_CW_SHIFT;
623 reg |= RTL818X_CW_CONF_PERPACKET_RETRY_SHIFT;
624 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
625
626 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
627 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN_SHIFT;
628 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL_SHIFT;
629 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
630 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
631
632 /* disable early TX */
633 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
634 }
635
636 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
637 reg |= (6 << 21 /* MAX TX DMA */) |
638 RTL818X_TX_CONF_NO_ICV;
639
640 if (priv->r8185)
641 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
642 else
643 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
644
645 /* different meaning, same value on both rtl8185 and rtl8180 */
646 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
647
648 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
649
650 reg = rtl818x_ioread8(priv, &priv->map->CMD);
651 reg |= RTL818X_CMD_RX_ENABLE;
652 reg |= RTL818X_CMD_TX_ENABLE;
653 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
654
655 return 0;
656
657 err_free_rings:
658 rtl8180_free_rx_ring(dev);
659 for (i = 0; i < 4; i++)
660 if (priv->tx_ring[i].desc)
661 rtl8180_free_tx_ring(dev, i);
662
663 return ret;
664 }
665
666 static void rtl8180_stop(struct ieee80211_hw *dev)
667 {
668 struct rtl8180_priv *priv = dev->priv;
669 u8 reg;
670 int i;
671
672 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
673
674 reg = rtl818x_ioread8(priv, &priv->map->CMD);
675 reg &= ~RTL818X_CMD_TX_ENABLE;
676 reg &= ~RTL818X_CMD_RX_ENABLE;
677 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
678
679 priv->rf->stop(dev);
680
681 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
682 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
683 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
684 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
685
686 free_irq(priv->pdev->irq, dev);
687
688 rtl8180_free_rx_ring(dev);
689 for (i = 0; i < 4; i++)
690 rtl8180_free_tx_ring(dev, i);
691 }
692
693 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
694 struct ieee80211_vif *vif)
695 {
696 struct rtl8180_priv *priv = dev->priv;
697
698 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
699 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
700 }
701
702 static void rtl8180_beacon_work(struct work_struct *work)
703 {
704 struct rtl8180_vif *vif_priv =
705 container_of(work, struct rtl8180_vif, beacon_work.work);
706 struct ieee80211_vif *vif =
707 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
708 struct ieee80211_hw *dev = vif_priv->dev;
709 struct ieee80211_mgmt *mgmt;
710 struct sk_buff *skb;
711
712 /* don't overflow the tx ring */
713 if (ieee80211_queue_stopped(dev, 0))
714 goto resched;
715
716 /* grab a fresh beacon */
717 skb = ieee80211_beacon_get(dev, vif);
718 if (!skb)
719 goto resched;
720
721 /*
722 * update beacon timestamp w/ TSF value
723 * TODO: make hardware update beacon timestamp
724 */
725 mgmt = (struct ieee80211_mgmt *)skb->data;
726 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
727
728 /* TODO: use actual beacon queue */
729 skb_set_queue_mapping(skb, 0);
730
731 rtl8180_tx(dev, NULL, skb);
732
733 resched:
734 /*
735 * schedule next beacon
736 * TODO: use hardware support for beacon timing
737 */
738 schedule_delayed_work(&vif_priv->beacon_work,
739 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
740 }
741
742 static int rtl8180_add_interface(struct ieee80211_hw *dev,
743 struct ieee80211_vif *vif)
744 {
745 struct rtl8180_priv *priv = dev->priv;
746 struct rtl8180_vif *vif_priv;
747
748 /*
749 * We only support one active interface at a time.
750 */
751 if (priv->vif)
752 return -EBUSY;
753
754 switch (vif->type) {
755 case NL80211_IFTYPE_STATION:
756 case NL80211_IFTYPE_ADHOC:
757 break;
758 default:
759 return -EOPNOTSUPP;
760 }
761
762 priv->vif = vif;
763
764 /* Initialize driver private area */
765 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
766 vif_priv->dev = dev;
767 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
768 vif_priv->enable_beacon = false;
769
770 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
771 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
772 le32_to_cpu(*(__le32 *)vif->addr));
773 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
774 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
775 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
776
777 return 0;
778 }
779
780 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
781 struct ieee80211_vif *vif)
782 {
783 struct rtl8180_priv *priv = dev->priv;
784 priv->vif = NULL;
785 }
786
787 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
788 {
789 struct rtl8180_priv *priv = dev->priv;
790 struct ieee80211_conf *conf = &dev->conf;
791
792 priv->rf->set_chan(dev, conf);
793
794 return 0;
795 }
796
797 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
798 struct ieee80211_vif *vif,
799 struct ieee80211_bss_conf *info,
800 u32 changed)
801 {
802 struct rtl8180_priv *priv = dev->priv;
803 struct rtl8180_vif *vif_priv;
804 int i;
805 u8 reg;
806
807 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
808
809 if (changed & BSS_CHANGED_BSSID) {
810 for (i = 0; i < ETH_ALEN; i++)
811 rtl818x_iowrite8(priv, &priv->map->BSSID[i],
812 info->bssid[i]);
813
814 if (is_valid_ether_addr(info->bssid)) {
815 if (vif->type == NL80211_IFTYPE_ADHOC)
816 reg = RTL818X_MSR_ADHOC;
817 else
818 reg = RTL818X_MSR_INFRA;
819 } else
820 reg = RTL818X_MSR_NO_LINK;
821 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
822 }
823
824 if (changed & BSS_CHANGED_ERP_SLOT && priv->rf->conf_erp)
825 priv->rf->conf_erp(dev, info);
826
827 if (changed & BSS_CHANGED_BEACON_ENABLED)
828 vif_priv->enable_beacon = info->enable_beacon;
829
830 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
831 cancel_delayed_work_sync(&vif_priv->beacon_work);
832 if (vif_priv->enable_beacon)
833 schedule_work(&vif_priv->beacon_work.work);
834 }
835 }
836
837 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
838 struct netdev_hw_addr_list *mc_list)
839 {
840 return netdev_hw_addr_list_count(mc_list);
841 }
842
843 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
844 unsigned int changed_flags,
845 unsigned int *total_flags,
846 u64 multicast)
847 {
848 struct rtl8180_priv *priv = dev->priv;
849
850 if (changed_flags & FIF_FCSFAIL)
851 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
852 if (changed_flags & FIF_CONTROL)
853 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
854 if (changed_flags & FIF_OTHER_BSS)
855 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
856 if (*total_flags & FIF_ALLMULTI || multicast > 0)
857 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
858 else
859 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
860
861 *total_flags = 0;
862
863 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
864 *total_flags |= FIF_FCSFAIL;
865 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
866 *total_flags |= FIF_CONTROL;
867 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
868 *total_flags |= FIF_OTHER_BSS;
869 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
870 *total_flags |= FIF_ALLMULTI;
871
872 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
873 }
874
875 static const struct ieee80211_ops rtl8180_ops = {
876 .tx = rtl8180_tx,
877 .start = rtl8180_start,
878 .stop = rtl8180_stop,
879 .add_interface = rtl8180_add_interface,
880 .remove_interface = rtl8180_remove_interface,
881 .config = rtl8180_config,
882 .bss_info_changed = rtl8180_bss_info_changed,
883 .prepare_multicast = rtl8180_prepare_multicast,
884 .configure_filter = rtl8180_configure_filter,
885 .get_tsf = rtl8180_get_tsf,
886 };
887
888 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
889 {
890 struct ieee80211_hw *dev = eeprom->data;
891 struct rtl8180_priv *priv = dev->priv;
892 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
893
894 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
895 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
896 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
897 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
898 }
899
900 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
901 {
902 struct ieee80211_hw *dev = eeprom->data;
903 struct rtl8180_priv *priv = dev->priv;
904 u8 reg = 2 << 6;
905
906 if (eeprom->reg_data_in)
907 reg |= RTL818X_EEPROM_CMD_WRITE;
908 if (eeprom->reg_data_out)
909 reg |= RTL818X_EEPROM_CMD_READ;
910 if (eeprom->reg_data_clock)
911 reg |= RTL818X_EEPROM_CMD_CK;
912 if (eeprom->reg_chip_select)
913 reg |= RTL818X_EEPROM_CMD_CS;
914
915 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
916 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
917 udelay(10);
918 }
919
920 static int rtl8180_probe(struct pci_dev *pdev,
921 const struct pci_device_id *id)
922 {
923 struct ieee80211_hw *dev;
924 struct rtl8180_priv *priv;
925 unsigned long mem_addr, mem_len;
926 unsigned int io_addr, io_len;
927 int err, i;
928 struct eeprom_93cx6 eeprom;
929 const char *chip_name, *rf_name = NULL;
930 u32 reg;
931 u16 eeprom_val;
932 u8 mac_addr[ETH_ALEN];
933
934 err = pci_enable_device(pdev);
935 if (err) {
936 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
937 pci_name(pdev));
938 return err;
939 }
940
941 err = pci_request_regions(pdev, KBUILD_MODNAME);
942 if (err) {
943 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
944 pci_name(pdev));
945 return err;
946 }
947
948 io_addr = pci_resource_start(pdev, 0);
949 io_len = pci_resource_len(pdev, 0);
950 mem_addr = pci_resource_start(pdev, 1);
951 mem_len = pci_resource_len(pdev, 1);
952
953 if (mem_len < sizeof(struct rtl818x_csr) ||
954 io_len < sizeof(struct rtl818x_csr)) {
955 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
956 pci_name(pdev));
957 err = -ENOMEM;
958 goto err_free_reg;
959 }
960
961 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
962 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
963 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
964 pci_name(pdev));
965 goto err_free_reg;
966 }
967
968 pci_set_master(pdev);
969
970 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
971 if (!dev) {
972 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
973 pci_name(pdev));
974 err = -ENOMEM;
975 goto err_free_reg;
976 }
977
978 priv = dev->priv;
979 priv->pdev = pdev;
980
981 dev->max_rates = 2;
982 SET_IEEE80211_DEV(dev, &pdev->dev);
983 pci_set_drvdata(pdev, dev);
984
985 priv->map = pci_iomap(pdev, 1, mem_len);
986 if (!priv->map)
987 priv->map = pci_iomap(pdev, 0, io_len);
988
989 if (!priv->map) {
990 printk(KERN_ERR "%s (rtl8180): Cannot map device memory\n",
991 pci_name(pdev));
992 goto err_free_dev;
993 }
994
995 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
996 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
997
998 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
999 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1000
1001 priv->band.band = IEEE80211_BAND_2GHZ;
1002 priv->band.channels = priv->channels;
1003 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1004 priv->band.bitrates = priv->rates;
1005 priv->band.n_bitrates = 4;
1006 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1007
1008 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1009 IEEE80211_HW_RX_INCLUDES_FCS |
1010 IEEE80211_HW_SIGNAL_UNSPEC;
1011 dev->vif_data_size = sizeof(struct rtl8180_vif);
1012 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1013 BIT(NL80211_IFTYPE_ADHOC);
1014 dev->queues = 1;
1015 dev->max_signal = 65;
1016
1017 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1018 reg &= RTL818X_TX_CONF_HWVER_MASK;
1019 switch (reg) {
1020 case RTL818X_TX_CONF_R8180_ABCD:
1021 chip_name = "RTL8180";
1022 break;
1023 case RTL818X_TX_CONF_R8180_F:
1024 chip_name = "RTL8180vF";
1025 break;
1026 case RTL818X_TX_CONF_R8185_ABC:
1027 chip_name = "RTL8185";
1028 break;
1029 case RTL818X_TX_CONF_R8185_D:
1030 chip_name = "RTL8185vD";
1031 break;
1032 default:
1033 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1034 pci_name(pdev), reg >> 25);
1035 goto err_iounmap;
1036 }
1037
1038 priv->r8185 = reg & RTL818X_TX_CONF_R8185_ABC;
1039 if (priv->r8185) {
1040 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1041 pci_try_set_mwi(pdev);
1042 }
1043
1044 eeprom.data = dev;
1045 eeprom.register_read = rtl8180_eeprom_register_read;
1046 eeprom.register_write = rtl8180_eeprom_register_write;
1047 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1048 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1049 else
1050 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1051
1052 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_PROGRAM);
1053 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1054 udelay(10);
1055
1056 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1057 eeprom_val &= 0xFF;
1058 switch (eeprom_val) {
1059 case 1: rf_name = "Intersil";
1060 break;
1061 case 2: rf_name = "RFMD";
1062 break;
1063 case 3: priv->rf = &sa2400_rf_ops;
1064 break;
1065 case 4: priv->rf = &max2820_rf_ops;
1066 break;
1067 case 5: priv->rf = &grf5101_rf_ops;
1068 break;
1069 case 9: priv->rf = rtl8180_detect_rf(dev);
1070 break;
1071 case 10:
1072 rf_name = "RTL8255";
1073 break;
1074 default:
1075 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1076 pci_name(pdev), eeprom_val);
1077 goto err_iounmap;
1078 }
1079
1080 if (!priv->rf) {
1081 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1082 pci_name(pdev), rf_name);
1083 goto err_iounmap;
1084 }
1085
1086 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1087 priv->csthreshold = eeprom_val >> 8;
1088 if (!priv->r8185) {
1089 __le32 anaparam;
1090 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1091 priv->anaparam = le32_to_cpu(anaparam);
1092 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1093 }
1094
1095 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)mac_addr, 3);
1096 if (!is_valid_ether_addr(mac_addr)) {
1097 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1098 " randomly generated MAC addr\n", pci_name(pdev));
1099 eth_random_addr(mac_addr);
1100 }
1101 SET_IEEE80211_PERM_ADDR(dev, mac_addr);
1102
1103 /* CCK TX power */
1104 for (i = 0; i < 14; i += 2) {
1105 u16 txpwr;
1106 eeprom_93cx6_read(&eeprom, 0x10 + (i >> 1), &txpwr);
1107 priv->channels[i].hw_value = txpwr & 0xFF;
1108 priv->channels[i + 1].hw_value = txpwr >> 8;
1109 }
1110
1111 /* OFDM TX power */
1112 if (priv->r8185) {
1113 for (i = 0; i < 14; i += 2) {
1114 u16 txpwr;
1115 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1116 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1117 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1118 }
1119 }
1120
1121 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1122
1123 spin_lock_init(&priv->lock);
1124
1125 err = ieee80211_register_hw(dev);
1126 if (err) {
1127 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1128 pci_name(pdev));
1129 goto err_iounmap;
1130 }
1131
1132 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1133 mac_addr, chip_name, priv->rf->name);
1134
1135 return 0;
1136
1137 err_iounmap:
1138 iounmap(priv->map);
1139
1140 err_free_dev:
1141 ieee80211_free_hw(dev);
1142
1143 err_free_reg:
1144 pci_release_regions(pdev);
1145 pci_disable_device(pdev);
1146 return err;
1147 }
1148
1149 static void rtl8180_remove(struct pci_dev *pdev)
1150 {
1151 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1152 struct rtl8180_priv *priv;
1153
1154 if (!dev)
1155 return;
1156
1157 ieee80211_unregister_hw(dev);
1158
1159 priv = dev->priv;
1160
1161 pci_iounmap(pdev, priv->map);
1162 pci_release_regions(pdev);
1163 pci_disable_device(pdev);
1164 ieee80211_free_hw(dev);
1165 }
1166
1167 #ifdef CONFIG_PM
1168 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1169 {
1170 pci_save_state(pdev);
1171 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1172 return 0;
1173 }
1174
1175 static int rtl8180_resume(struct pci_dev *pdev)
1176 {
1177 pci_set_power_state(pdev, PCI_D0);
1178 pci_restore_state(pdev);
1179 return 0;
1180 }
1181
1182 #endif /* CONFIG_PM */
1183
1184 static struct pci_driver rtl8180_driver = {
1185 .name = KBUILD_MODNAME,
1186 .id_table = rtl8180_table,
1187 .probe = rtl8180_probe,
1188 .remove = rtl8180_remove,
1189 #ifdef CONFIG_PM
1190 .suspend = rtl8180_suspend,
1191 .resume = rtl8180_resume,
1192 #endif /* CONFIG_PM */
1193 };
1194
1195 module_pci_driver(rtl8180_driver);
Linux with added FPC-III support