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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / rtl8192ce / hw.c
bloba82b30a1996ca97cc5041ac47899171fef15e25e
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #include "../wifi.h"
31 #include "../efuse.h"
32 #include "../base.h"
33 #include "../regd.h"
34 #include "../cam.h"
35 #include "../ps.h"
36 #include "../pci.h"
37 #include "reg.h"
38 #include "def.h"
39 #include "phy.h"
40 #include "../rtl8192c/fw_common.h"
41 #include "dm.h"
42 #include "led.h"
43 #include "hw.h"
44
45 #define LLT_CONFIG 5
46
47 static void _rtl92ce_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
48 u8 set_bits, u8 clear_bits)
49 {
50 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
51 struct rtl_priv *rtlpriv = rtl_priv(hw);
52
53 rtlpci->reg_bcn_ctrl_val |= set_bits;
54 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
55
56 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
57 }
58
59 static void _rtl92ce_stop_tx_beacon(struct ieee80211_hw *hw)
60 {
61 struct rtl_priv *rtlpriv = rtl_priv(hw);
62 u8 tmp1byte;
63
64 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
65 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
66 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
67 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
68 tmp1byte &= ~(BIT(0));
69 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
70 }
71
72 static void _rtl92ce_resume_tx_beacon(struct ieee80211_hw *hw)
73 {
74 struct rtl_priv *rtlpriv = rtl_priv(hw);
75 u8 tmp1byte;
76
77 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
78 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
79 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
80 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
81 tmp1byte |= BIT(0);
82 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
83 }
84
85 static void _rtl92ce_enable_bcn_sub_func(struct ieee80211_hw *hw)
86 {
87 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(1));
88 }
89
90 static void _rtl92ce_disable_bcn_sub_func(struct ieee80211_hw *hw)
91 {
92 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(1), 0);
93 }
94
95 void rtl92ce_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
96 {
97 struct rtl_priv *rtlpriv = rtl_priv(hw);
98 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
99 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
100
101 switch (variable) {
102 case HW_VAR_RCR:
103 *((u32 *) (val)) = rtlpci->receive_config;
104 break;
105 case HW_VAR_RF_STATE:
106 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
107 break;
108 case HW_VAR_FWLPS_RF_ON:{
109 enum rf_pwrstate rfState;
110 u32 val_rcr;
111
112 rtlpriv->cfg->ops->get_hw_reg(hw,
113 HW_VAR_RF_STATE,
114 (u8 *) (&rfState));
115 if (rfState == ERFOFF) {
116 *((bool *) (val)) = true;
117 } else {
118 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
119 val_rcr &= 0x00070000;
120 if (val_rcr)
121 *((bool *) (val)) = false;
122 else
123 *((bool *) (val)) = true;
124 }
125 break;
126 }
127 case HW_VAR_FW_PSMODE_STATUS:
128 *((bool *) (val)) = ppsc->fw_current_inpsmode;
129 break;
130 case HW_VAR_CORRECT_TSF:{
131 u64 tsf;
132 u32 *ptsf_low = (u32 *)&tsf;
133 u32 *ptsf_high = ((u32 *)&tsf) + 1;
134
135 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
136 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
137
138 *((u64 *) (val)) = tsf;
139
140 break;
141 }
142 default:
143 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
144 "switch case not processed\n");
145 break;
146 }
147 }
148
149 void rtl92ce_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
150 {
151 struct rtl_priv *rtlpriv = rtl_priv(hw);
152 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
153 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
154 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
155 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
156 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
157 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
158 u8 idx;
159
160 switch (variable) {
161 case HW_VAR_ETHER_ADDR:{
162 for (idx = 0; idx < ETH_ALEN; idx++) {
163 rtl_write_byte(rtlpriv, (REG_MACID + idx),
164 val[idx]);
165 }
166 break;
167 }
168 case HW_VAR_BASIC_RATE:{
169 u16 rate_cfg = ((u16 *) val)[0];
170 u8 rate_index = 0;
171 rate_cfg &= 0x15f;
172 rate_cfg |= 0x01;
173 rtl_write_byte(rtlpriv, REG_RRSR, rate_cfg & 0xff);
174 rtl_write_byte(rtlpriv, REG_RRSR + 1,
175 (rate_cfg >> 8) & 0xff);
176 while (rate_cfg > 0x1) {
177 rate_cfg = (rate_cfg >> 1);
178 rate_index++;
179 }
180 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
181 rate_index);
182 break;
183 }
184 case HW_VAR_BSSID:{
185 for (idx = 0; idx < ETH_ALEN; idx++) {
186 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
187 val[idx]);
188 }
189 break;
190 }
191 case HW_VAR_SIFS:{
192 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
193 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
194
195 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
196 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
197
198 if (!mac->ht_enable)
199 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
200 0x0e0e);
201 else
202 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
203 *((u16 *) val));
204 break;
205 }
206 case HW_VAR_SLOT_TIME:{
207 u8 e_aci;
208
209 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
210 "HW_VAR_SLOT_TIME %x\n", val[0]);
211
212 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
213
214 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
215 rtlpriv->cfg->ops->set_hw_reg(hw,
216 HW_VAR_AC_PARAM,
217 &e_aci);
218 }
219 break;
220 }
221 case HW_VAR_ACK_PREAMBLE:{
222 u8 reg_tmp;
223 u8 short_preamble = (bool)*val;
224 reg_tmp = (mac->cur_40_prime_sc) << 5;
225 if (short_preamble)
226 reg_tmp |= 0x80;
227
228 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
229 break;
230 }
231 case HW_VAR_AMPDU_MIN_SPACE:{
232 u8 min_spacing_to_set;
233 u8 sec_min_space;
234
235 min_spacing_to_set = *val;
236 if (min_spacing_to_set <= 7) {
237 sec_min_space = 0;
238
239 if (min_spacing_to_set < sec_min_space)
240 min_spacing_to_set = sec_min_space;
241
242 mac->min_space_cfg = ((mac->min_space_cfg &
243 0xf8) |
244 min_spacing_to_set);
245
246 *val = min_spacing_to_set;
247
248 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
249 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
250 mac->min_space_cfg);
251
252 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
253 mac->min_space_cfg);
254 }
255 break;
256 }
257 case HW_VAR_SHORTGI_DENSITY:{
258 u8 density_to_set;
259
260 density_to_set = *val;
261 mac->min_space_cfg |= (density_to_set << 3);
262
263 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
264 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
265 mac->min_space_cfg);
266
267 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
268 mac->min_space_cfg);
269
270 break;
271 }
272 case HW_VAR_AMPDU_FACTOR:{
273 u8 regtoset_normal[4] = {0x41, 0xa8, 0x72, 0xb9};
274 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
275
276 u8 factor_toset;
277 u8 *p_regtoset = NULL;
278 u8 index = 0;
279
280 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
281 (rtlpcipriv->bt_coexist.bt_coexist_type ==
282 BT_CSR_BC4))
283 p_regtoset = regtoset_bt;
284 else
285 p_regtoset = regtoset_normal;
286
287 factor_toset = *(val);
288 if (factor_toset <= 3) {
289 factor_toset = (1 << (factor_toset + 2));
290 if (factor_toset > 0xf)
291 factor_toset = 0xf;
292
293 for (index = 0; index < 4; index++) {
294 if ((p_regtoset[index] & 0xf0) >
295 (factor_toset << 4))
296 p_regtoset[index] =
297 (p_regtoset[index] & 0x0f) |
298 (factor_toset << 4);
299
300 if ((p_regtoset[index] & 0x0f) >
301 factor_toset)
302 p_regtoset[index] =
303 (p_regtoset[index] & 0xf0) |
304 (factor_toset);
305
306 rtl_write_byte(rtlpriv,
307 (REG_AGGLEN_LMT + index),
308 p_regtoset[index]);
309
310 }
311
312 RT_TRACE(rtlpriv, COMP_MLME, DBG_LOUD,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
314 factor_toset);
315 }
316 break;
317 }
318 case HW_VAR_AC_PARAM:{
319 u8 e_aci = *(val);
320 rtl92c_dm_init_edca_turbo(hw);
321
322 if (rtlpci->acm_method != eAcmWay2_SW)
323 rtlpriv->cfg->ops->set_hw_reg(hw,
324 HW_VAR_ACM_CTRL,
325 (&e_aci));
326 break;
327 }
328 case HW_VAR_ACM_CTRL:{
329 u8 e_aci = *(val);
330 union aci_aifsn *p_aci_aifsn =
331 (union aci_aifsn *)(&(mac->ac[0].aifs));
332 u8 acm = p_aci_aifsn->f.acm;
333 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
334
335 acm_ctrl =
336 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
337
338 if (acm) {
339 switch (e_aci) {
340 case AC0_BE:
341 acm_ctrl |= AcmHw_BeqEn;
342 break;
343 case AC2_VI:
344 acm_ctrl |= AcmHw_ViqEn;
345 break;
346 case AC3_VO:
347 acm_ctrl |= AcmHw_VoqEn;
348 break;
349 default:
350 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
351 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
352 acm);
353 break;
354 }
355 } else {
356 switch (e_aci) {
357 case AC0_BE:
358 acm_ctrl &= (~AcmHw_BeqEn);
359 break;
360 case AC2_VI:
361 acm_ctrl &= (~AcmHw_ViqEn);
362 break;
363 case AC3_VO:
364 acm_ctrl &= (~AcmHw_BeqEn);
365 break;
366 default:
367 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
368 "switch case not processed\n");
369 break;
370 }
371 }
372
373 RT_TRACE(rtlpriv, COMP_QOS, DBG_TRACE,
374 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
375 acm_ctrl);
376 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
377 break;
378 }
379 case HW_VAR_RCR:{
380 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *) (val))[0]);
381 rtlpci->receive_config = ((u32 *) (val))[0];
382 break;
383 }
384 case HW_VAR_RETRY_LIMIT:{
385 u8 retry_limit = val[0];
386
387 rtl_write_word(rtlpriv, REG_RL,
388 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
389 retry_limit << RETRY_LIMIT_LONG_SHIFT);
390 break;
391 }
392 case HW_VAR_DUAL_TSF_RST:
393 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
394 break;
395 case HW_VAR_EFUSE_BYTES:
396 rtlefuse->efuse_usedbytes = *((u16 *) val);
397 break;
398 case HW_VAR_EFUSE_USAGE:
399 rtlefuse->efuse_usedpercentage = *val;
400 break;
401 case HW_VAR_IO_CMD:
402 rtl92c_phy_set_io_cmd(hw, (*(enum io_type *)val));
403 break;
404 case HW_VAR_WPA_CONFIG:
405 rtl_write_byte(rtlpriv, REG_SECCFG, *val);
406 break;
407 case HW_VAR_SET_RPWM:{
408 u8 rpwm_val;
409
410 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
411 udelay(1);
412
413 if (rpwm_val & BIT(7)) {
414 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM, *val);
415 } else {
416 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
417 *val | BIT(7));
418 }
419
420 break;
421 }
422 case HW_VAR_H2C_FW_PWRMODE:{
423 u8 psmode = *val;
424
425 if ((psmode != FW_PS_ACTIVE_MODE) &&
426 (!IS_92C_SERIAL(rtlhal->version))) {
427 rtl92c_dm_rf_saving(hw, true);
428 }
429
430 rtl92c_set_fw_pwrmode_cmd(hw, *val);
431 break;
432 }
433 case HW_VAR_FW_PSMODE_STATUS:
434 ppsc->fw_current_inpsmode = *((bool *) val);
435 break;
436 case HW_VAR_H2C_FW_JOINBSSRPT:{
437 u8 mstatus = *val;
438 u8 tmp_regcr, tmp_reg422;
439 bool recover = false;
440
441 if (mstatus == RT_MEDIA_CONNECT) {
442 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
443 NULL);
444
445 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
446 rtl_write_byte(rtlpriv, REG_CR + 1,
447 (tmp_regcr | BIT(0)));
448
449 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
450 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
451
452 tmp_reg422 =
453 rtl_read_byte(rtlpriv,
454 REG_FWHW_TXQ_CTRL + 2);
455 if (tmp_reg422 & BIT(6))
456 recover = true;
457 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
458 tmp_reg422 & (~BIT(6)));
459
460 rtl92c_set_fw_rsvdpagepkt(hw, 0);
461
462 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
463 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
464
465 if (recover) {
466 rtl_write_byte(rtlpriv,
467 REG_FWHW_TXQ_CTRL + 2,
468 tmp_reg422);
469 }
470
471 rtl_write_byte(rtlpriv, REG_CR + 1,
472 (tmp_regcr & ~(BIT(0))));
473 }
474 rtl92c_set_fw_joinbss_report_cmd(hw, *val);
475
476 break;
477 }
478 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:
479 rtl92c_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
480 break;
481 case HW_VAR_AID:{
482 u16 u2btmp;
483 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
484 u2btmp &= 0xC000;
485 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT, (u2btmp |
486 mac->assoc_id));
487
488 break;
489 }
490 case HW_VAR_CORRECT_TSF:{
491 u8 btype_ibss = val[0];
492
493 if (btype_ibss)
494 _rtl92ce_stop_tx_beacon(hw);
495
496 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(3));
497
498 rtl_write_dword(rtlpriv, REG_TSFTR,
499 (u32) (mac->tsf & 0xffffffff));
500 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
501 (u32) ((mac->tsf >> 32) & 0xffffffff));
502
503 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(3), 0);
504
505 if (btype_ibss)
506 _rtl92ce_resume_tx_beacon(hw);
507
508 break;
509
510 }
511 case HW_VAR_FW_LPS_ACTION: {
512 bool enter_fwlps = *((bool *)val);
513 u8 rpwm_val, fw_pwrmode;
514 bool fw_current_inps;
515
516 if (enter_fwlps) {
517 rpwm_val = 0x02; /* RF off */
518 fw_current_inps = true;
519 rtlpriv->cfg->ops->set_hw_reg(hw,
520 HW_VAR_FW_PSMODE_STATUS,
521 (u8 *)(&fw_current_inps));
522 rtlpriv->cfg->ops->set_hw_reg(hw,
523 HW_VAR_H2C_FW_PWRMODE,
524 (u8 *)(&ppsc->fwctrl_psmode));
525
526 rtlpriv->cfg->ops->set_hw_reg(hw,
527 HW_VAR_SET_RPWM,
528 (u8 *)(&rpwm_val));
529 } else {
530 rpwm_val = 0x0C; /* RF on */
531 fw_pwrmode = FW_PS_ACTIVE_MODE;
532 fw_current_inps = false;
533 rtlpriv->cfg->ops->set_hw_reg(hw,
534 HW_VAR_SET_RPWM,
535 (u8 *)(&rpwm_val));
536 rtlpriv->cfg->ops->set_hw_reg(hw,
537 HW_VAR_H2C_FW_PWRMODE,
538 (u8 *)(&fw_pwrmode));
539
540 rtlpriv->cfg->ops->set_hw_reg(hw,
541 HW_VAR_FW_PSMODE_STATUS,
542 (u8 *)(&fw_current_inps));
543 }
544 break; }
545 default:
546 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
547 "switch case not processed\n");
548 break;
549 }
550 }
551
552 static bool _rtl92ce_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
553 {
554 struct rtl_priv *rtlpriv = rtl_priv(hw);
555 bool status = true;
556 long count = 0;
557 u32 value = _LLT_INIT_ADDR(address) |
558 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
559
560 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
561
562 do {
563 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
564 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
565 break;
566
567 if (count > POLLING_LLT_THRESHOLD) {
568 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
569 "Failed to polling write LLT done at address %d!\n",
570 address);
571 status = false;
572 break;
573 }
574 } while (++count);
575
576 return status;
577 }
578
579 static bool _rtl92ce_llt_table_init(struct ieee80211_hw *hw)
580 {
581 struct rtl_priv *rtlpriv = rtl_priv(hw);
582 unsigned short i;
583 u8 txpktbuf_bndy;
584 u8 maxPage;
585 bool status;
586
587 #if LLT_CONFIG == 1
588 maxPage = 255;
589 txpktbuf_bndy = 252;
590 #elif LLT_CONFIG == 2
591 maxPage = 127;
592 txpktbuf_bndy = 124;
593 #elif LLT_CONFIG == 3
594 maxPage = 255;
595 txpktbuf_bndy = 174;
596 #elif LLT_CONFIG == 4
597 maxPage = 255;
598 txpktbuf_bndy = 246;
599 #elif LLT_CONFIG == 5
600 maxPage = 255;
601 txpktbuf_bndy = 246;
602 #endif
603
604 #if LLT_CONFIG == 1
605 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
606 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
607 #elif LLT_CONFIG == 2
608 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
609 #elif LLT_CONFIG == 3
610 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
611 #elif LLT_CONFIG == 4
612 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
613 #elif LLT_CONFIG == 5
614 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
615
616 rtl_write_dword(rtlpriv, REG_RQPN, 0x80b01c29);
617 #endif
618
619 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
620 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
621
622 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
623 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
624
625 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
626 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
627 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
628
629 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
630 status = _rtl92ce_llt_write(hw, i, i + 1);
631 if (true != status)
632 return status;
633 }
634
635 status = _rtl92ce_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
636 if (true != status)
637 return status;
638
639 for (i = txpktbuf_bndy; i < maxPage; i++) {
640 status = _rtl92ce_llt_write(hw, i, (i + 1));
641 if (true != status)
642 return status;
643 }
644
645 status = _rtl92ce_llt_write(hw, maxPage, txpktbuf_bndy);
646 if (true != status)
647 return status;
648
649 return true;
650 }
651
652 static void _rtl92ce_gen_refresh_led_state(struct ieee80211_hw *hw)
653 {
654 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
655 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
656 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
657 struct rtl_led *pLed0 = &(pcipriv->ledctl.sw_led0);
658
659 if (rtlpci->up_first_time)
660 return;
661
662 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
663 rtl92ce_sw_led_on(hw, pLed0);
664 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
665 rtl92ce_sw_led_on(hw, pLed0);
666 else
667 rtl92ce_sw_led_off(hw, pLed0);
668 }
669
670 static bool _rtl92ce_init_mac(struct ieee80211_hw *hw)
671 {
672 struct rtl_priv *rtlpriv = rtl_priv(hw);
673 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
674 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
675 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
676
677 unsigned char bytetmp;
678 unsigned short wordtmp;
679 u16 retry;
680
681 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
682 if (rtlpcipriv->bt_coexist.bt_coexistence) {
683 u32 value32;
684 value32 = rtl_read_dword(rtlpriv, REG_APS_FSMCO);
685 value32 |= (SOP_ABG | SOP_AMB | XOP_BTCK);
686 rtl_write_dword(rtlpriv, REG_APS_FSMCO, value32);
687 }
688 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x2b);
689 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL, 0x0F);
690
691 if (rtlpcipriv->bt_coexist.bt_coexistence) {
692 u32 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
693
694 u4b_tmp &= (~0x00024800);
695 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
696 }
697
698 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1) | BIT(0);
699 udelay(2);
700
701 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, bytetmp);
702 udelay(2);
703
704 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
705 udelay(2);
706
707 retry = 0;
708 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
709 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
710
711 while ((bytetmp & BIT(0)) && retry < 1000) {
712 retry++;
713 udelay(50);
714 bytetmp = rtl_read_byte(rtlpriv, REG_APS_FSMCO + 1);
715 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "reg0xec:%x:%x\n",
716 rtl_read_dword(rtlpriv, 0xEC), bytetmp);
717 udelay(50);
718 }
719
720 rtl_write_word(rtlpriv, REG_APS_FSMCO, 0x1012);
721
722 rtl_write_byte(rtlpriv, REG_SYS_ISO_CTRL + 1, 0x82);
723 udelay(2);
724
725 if (rtlpcipriv->bt_coexist.bt_coexistence) {
726 bytetmp = rtl_read_byte(rtlpriv, REG_AFE_XTAL_CTRL+2) & 0xfd;
727 rtl_write_byte(rtlpriv, REG_AFE_XTAL_CTRL+2, bytetmp);
728 }
729
730 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
731
732 if (!_rtl92ce_llt_table_init(hw))
733 return false;
734
735 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
736 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
737
738 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
739
740 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
741 wordtmp &= 0xf;
742 wordtmp |= 0xF771;
743 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
744
745 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
746 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
747 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
748
749 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
750
751 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
752 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
753 DMA_BIT_MASK(32));
754 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
755 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
756 DMA_BIT_MASK(32));
757 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
758 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
759 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
760 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
761 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
762 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
763 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
764 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
765 rtl_write_dword(rtlpriv, REG_HQ_DESA,
766 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
767 DMA_BIT_MASK(32));
768 rtl_write_dword(rtlpriv, REG_RX_DESA,
769 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
770 DMA_BIT_MASK(32));
771
772 if (IS_92C_SERIAL(rtlhal->version))
773 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x77);
774 else
775 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x22);
776
777 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
778
779 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
780 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
781 do {
782 retry++;
783 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
784 } while ((retry < 200) && (bytetmp & BIT(7)));
785
786 _rtl92ce_gen_refresh_led_state(hw);
787
788 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
789
790 return true;
791 }
792
793 static void _rtl92ce_hw_configure(struct ieee80211_hw *hw)
794 {
795 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
796 struct rtl_priv *rtlpriv = rtl_priv(hw);
797 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
798 u8 reg_bw_opmode;
799 u32 reg_prsr;
800
801 reg_bw_opmode = BW_OPMODE_20MHZ;
802 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
803
804 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
805
806 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
807
808 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
809
810 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
811
812 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
813
814 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
815
816 rtl_write_word(rtlpriv, REG_RL, 0x0707);
817
818 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
819
820 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
821
822 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
823 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
824 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
825 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
826
827 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
828 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
829 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
830 else
831 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
832
833 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
834
835 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
836
837 rtlpci->reg_bcn_ctrl_val = 0x1f;
838 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
839
840 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
841
842 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
843
844 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
845 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
846
847 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
848 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
849 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
850 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
851 } else {
852 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
853 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
854 }
855
856 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
857 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4))
858 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
859 else
860 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
861
862 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
863
864 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
865 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
866
867 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
868
869 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
870
871 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
872 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
873
874 }
875
876 static void _rtl92ce_enable_aspm_back_door(struct ieee80211_hw *hw)
877 {
878 struct rtl_priv *rtlpriv = rtl_priv(hw);
879 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
880
881 rtl_write_byte(rtlpriv, 0x34b, 0x93);
882 rtl_write_word(rtlpriv, 0x350, 0x870c);
883 rtl_write_byte(rtlpriv, 0x352, 0x1);
884
885 if (ppsc->support_backdoor)
886 rtl_write_byte(rtlpriv, 0x349, 0x1b);
887 else
888 rtl_write_byte(rtlpriv, 0x349, 0x03);
889
890 rtl_write_word(rtlpriv, 0x350, 0x2718);
891 rtl_write_byte(rtlpriv, 0x352, 0x1);
892 }
893
894 void rtl92ce_enable_hw_security_config(struct ieee80211_hw *hw)
895 {
896 struct rtl_priv *rtlpriv = rtl_priv(hw);
897 u8 sec_reg_value;
898
899 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
900 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
901 rtlpriv->sec.pairwise_enc_algorithm,
902 rtlpriv->sec.group_enc_algorithm);
903
904 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
905 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
906 "not open hw encryption\n");
907 return;
908 }
909
910 sec_reg_value = SCR_TxEncEnable | SCR_RxDecEnable;
911
912 if (rtlpriv->sec.use_defaultkey) {
913 sec_reg_value |= SCR_TxUseDK;
914 sec_reg_value |= SCR_RxUseDK;
915 }
916
917 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
918
919 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
920
921 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
922 "The SECR-value %x\n", sec_reg_value);
923
924 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
925
926 }
927
928 int rtl92ce_hw_init(struct ieee80211_hw *hw)
929 {
930 struct rtl_priv *rtlpriv = rtl_priv(hw);
931 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
932 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
933 struct rtl_phy *rtlphy = &(rtlpriv->phy);
934 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
935 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
936 bool rtstatus = true;
937 bool is92c;
938 int err;
939 u8 tmp_u1b;
940
941 rtlpci->being_init_adapter = true;
942 rtlpriv->intf_ops->disable_aspm(hw);
943 rtstatus = _rtl92ce_init_mac(hw);
944 if (!rtstatus) {
945 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Init MAC failed\n");
946 err = 1;
947 return err;
948 }
949
950 err = rtl92c_download_fw(hw);
951 if (err) {
952 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
953 "Failed to download FW. Init HW without FW now..\n");
954 err = 1;
955 return err;
956 }
957
958 rtlhal->last_hmeboxnum = 0;
959 rtl92c_phy_mac_config(hw);
960 /* because last function modify RCR, so we update
961 * rcr var here, or TP will unstable for receive_config
962 * is wrong, RX RCR_ACRC32 will cause TP unstabel & Rx
963 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252*/
964 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
965 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
966 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
967 rtl92c_phy_bb_config(hw);
968 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
969 rtl92c_phy_rf_config(hw);
970 if (IS_VENDOR_UMC_A_CUT(rtlhal->version) &&
971 !IS_92C_SERIAL(rtlhal->version)) {
972 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
973 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
974 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version)) {
975 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
976 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
977 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
978 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
979 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
980 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
981 }
982 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
983 RF_CHNLBW, RFREG_OFFSET_MASK);
984 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
985 RF_CHNLBW, RFREG_OFFSET_MASK);
986 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
987 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
988 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
989 _rtl92ce_hw_configure(hw);
990 rtl_cam_reset_all_entry(hw);
991 rtl92ce_enable_hw_security_config(hw);
992
993 ppsc->rfpwr_state = ERFON;
994
995 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
996 _rtl92ce_enable_aspm_back_door(hw);
997 rtlpriv->intf_ops->enable_aspm(hw);
998
999 rtl8192ce_bt_hw_init(hw);
1000
1001 if (ppsc->rfpwr_state == ERFON) {
1002 rtl92c_phy_set_rfpath_switch(hw, 1);
1003 if (rtlphy->iqk_initialized) {
1004 rtl92c_phy_iq_calibrate(hw, true);
1005 } else {
1006 rtl92c_phy_iq_calibrate(hw, false);
1007 rtlphy->iqk_initialized = true;
1008 }
1009
1010 rtl92c_dm_check_txpower_tracking(hw);
1011 rtl92c_phy_lc_calibrate(hw);
1012 }
1013
1014 is92c = IS_92C_SERIAL(rtlhal->version);
1015 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1016 if (!(tmp_u1b & BIT(0))) {
1017 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1018 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1019 }
1020
1021 if (!(tmp_u1b & BIT(1)) && is92c) {
1022 rtl_set_rfreg(hw, RF90_PATH_B, 0x15, 0x0F, 0x05);
1023 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path B\n");
1024 }
1025
1026 if (!(tmp_u1b & BIT(4))) {
1027 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1028 tmp_u1b &= 0x0F;
1029 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1030 udelay(10);
1031 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1032 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1033 }
1034 rtl92c_dm_init(hw);
1035 rtlpci->being_init_adapter = false;
1036 return err;
1037 }
1038
1039 static enum version_8192c _rtl92ce_read_chip_version(struct ieee80211_hw *hw)
1040 {
1041 struct rtl_priv *rtlpriv = rtl_priv(hw);
1042 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1043 enum version_8192c version = VERSION_UNKNOWN;
1044 u32 value32;
1045 const char *versionid;
1046
1047 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1048 if (value32 & TRP_VAUX_EN) {
1049 version = (value32 & TYPE_ID) ? VERSION_A_CHIP_92C :
1050 VERSION_A_CHIP_88C;
1051 } else {
1052 version = (enum version_8192c) (CHIP_VER_B |
1053 ((value32 & TYPE_ID) ? CHIP_92C_BITMASK : 0) |
1054 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1055 if ((!IS_CHIP_VENDOR_UMC(version)) && (value32 &
1056 CHIP_VER_RTL_MASK)) {
1057 version = (enum version_8192c)(version |
1058 ((((value32 & CHIP_VER_RTL_MASK) == BIT(12))
1059 ? CHIP_VENDOR_UMC_B_CUT : CHIP_UNKNOWN) |
1060 CHIP_VENDOR_UMC));
1061 }
1062 if (IS_92C_SERIAL(version)) {
1063 value32 = rtl_read_dword(rtlpriv, REG_HPON_FSM);
1064 version = (enum version_8192c)(version |
1065 ((CHIP_BONDING_IDENTIFIER(value32)
1066 == CHIP_BONDING_92C_1T2R) ?
1067 RF_TYPE_1T2R : 0));
1068 }
1069 }
1070
1071 switch (version) {
1072 case VERSION_B_CHIP_92C:
1073 versionid = "B_CHIP_92C";
1074 break;
1075 case VERSION_B_CHIP_88C:
1076 versionid = "B_CHIP_88C";
1077 break;
1078 case VERSION_A_CHIP_92C:
1079 versionid = "A_CHIP_92C";
1080 break;
1081 case VERSION_A_CHIP_88C:
1082 versionid = "A_CHIP_88C";
1083 break;
1084 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_A_CUT:
1085 versionid = "A_CUT_92C_1T2R";
1086 break;
1087 case VERSION_NORMAL_UMC_CHIP_92C_A_CUT:
1088 versionid = "A_CUT_92C";
1089 break;
1090 case VERSION_NORMAL_UMC_CHIP_88C_A_CUT:
1091 versionid = "A_CUT_88C";
1092 break;
1093 case VERSION_NORMAL_UMC_CHIP_92C_1T2R_B_CUT:
1094 versionid = "B_CUT_92C_1T2R";
1095 break;
1096 case VERSION_NORMAL_UMC_CHIP_92C_B_CUT:
1097 versionid = "B_CUT_92C";
1098 break;
1099 case VERSION_NORMAL_UMC_CHIP_88C_B_CUT:
1100 versionid = "B_CUT_88C";
1101 break;
1102 default:
1103 versionid = "Unknown. Bug?";
1104 break;
1105 }
1106
1107 RT_TRACE(rtlpriv, COMP_INIT, DBG_EMERG,
1108 "Chip Version ID: %s\n", versionid);
1109
1110 switch (version & 0x3) {
1111 case CHIP_88C:
1112 rtlphy->rf_type = RF_1T1R;
1113 break;
1114 case CHIP_92C:
1115 rtlphy->rf_type = RF_2T2R;
1116 break;
1117 case CHIP_92C_1T2R:
1118 rtlphy->rf_type = RF_1T2R;
1119 break;
1120 default:
1121 rtlphy->rf_type = RF_1T1R;
1122 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1123 "ERROR RF_Type is set!!\n");
1124 break;
1125 }
1126
1127 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1128 rtlphy->rf_type == RF_2T2R ? "RF_2T2R" : "RF_1T1R");
1129
1130 return version;
1131 }
1132
1133 static int _rtl92ce_set_media_status(struct ieee80211_hw *hw,
1134 enum nl80211_iftype type)
1135 {
1136 struct rtl_priv *rtlpriv = rtl_priv(hw);
1137 u8 bt_msr = rtl_read_byte(rtlpriv, MSR);
1138 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1139 bt_msr &= 0xfc;
1140
1141 if (type == NL80211_IFTYPE_UNSPECIFIED ||
1142 type == NL80211_IFTYPE_STATION) {
1143 _rtl92ce_stop_tx_beacon(hw);
1144 _rtl92ce_enable_bcn_sub_func(hw);
1145 } else if (type == NL80211_IFTYPE_ADHOC || type == NL80211_IFTYPE_AP ||
1146 type == NL80211_IFTYPE_MESH_POINT) {
1147 _rtl92ce_resume_tx_beacon(hw);
1148 _rtl92ce_disable_bcn_sub_func(hw);
1149 } else {
1150 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1151 "Set HW_VAR_MEDIA_STATUS: No such media status(%x)\n",
1152 type);
1153 }
1154
1155 switch (type) {
1156 case NL80211_IFTYPE_UNSPECIFIED:
1157 bt_msr |= MSR_NOLINK;
1158 ledaction = LED_CTL_LINK;
1159 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1160 "Set Network type to NO LINK!\n");
1161 break;
1162 case NL80211_IFTYPE_ADHOC:
1163 bt_msr |= MSR_ADHOC;
1164 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1165 "Set Network type to Ad Hoc!\n");
1166 break;
1167 case NL80211_IFTYPE_STATION:
1168 bt_msr |= MSR_INFRA;
1169 ledaction = LED_CTL_LINK;
1170 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1171 "Set Network type to STA!\n");
1172 break;
1173 case NL80211_IFTYPE_AP:
1174 bt_msr |= MSR_AP;
1175 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1176 "Set Network type to AP!\n");
1177 break;
1178 case NL80211_IFTYPE_MESH_POINT:
1179 bt_msr |= MSR_ADHOC;
1180 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE,
1181 "Set Network type to Mesh Point!\n");
1182 break;
1183 default:
1184 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1185 "Network type %d not supported!\n", type);
1186 return 1;
1187 break;
1188
1189 }
1190
1191 rtl_write_byte(rtlpriv, (MSR), bt_msr);
1192 rtlpriv->cfg->ops->led_control(hw, ledaction);
1193 if ((bt_msr & 0xfc) == MSR_AP)
1194 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1195 else
1196 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1197 return 0;
1198 }
1199
1200 void rtl92ce_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1201 {
1202 struct rtl_priv *rtlpriv = rtl_priv(hw);
1203 u32 reg_rcr = rtl_read_dword(rtlpriv, REG_RCR);
1204
1205 if (rtlpriv->psc.rfpwr_state != ERFON)
1206 return;
1207
1208 if (check_bssid) {
1209 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1210 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1211 (u8 *) (&reg_rcr));
1212 _rtl92ce_set_bcn_ctrl_reg(hw, 0, BIT(4));
1213 } else if (!check_bssid) {
1214 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1215 _rtl92ce_set_bcn_ctrl_reg(hw, BIT(4), 0);
1216 rtlpriv->cfg->ops->set_hw_reg(hw,
1217 HW_VAR_RCR, (u8 *) (&reg_rcr));
1218 }
1219
1220 }
1221
1222 int rtl92ce_set_network_type(struct ieee80211_hw *hw, enum nl80211_iftype type)
1223 {
1224 struct rtl_priv *rtlpriv = rtl_priv(hw);
1225
1226 if (_rtl92ce_set_media_status(hw, type))
1227 return -EOPNOTSUPP;
1228
1229 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1230 if (type != NL80211_IFTYPE_AP &&
1231 type != NL80211_IFTYPE_MESH_POINT)
1232 rtl92ce_set_check_bssid(hw, true);
1233 } else {
1234 rtl92ce_set_check_bssid(hw, false);
1235 }
1236
1237 return 0;
1238 }
1239
1240 /* don't set REG_EDCA_BE_PARAM here because mac80211 will send pkt when scan */
1241 void rtl92ce_set_qos(struct ieee80211_hw *hw, int aci)
1242 {
1243 struct rtl_priv *rtlpriv = rtl_priv(hw);
1244 rtl92c_dm_init_edca_turbo(hw);
1245 switch (aci) {
1246 case AC1_BK:
1247 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1248 break;
1249 case AC0_BE:
1250 /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
1251 break;
1252 case AC2_VI:
1253 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1254 break;
1255 case AC3_VO:
1256 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1257 break;
1258 default:
1259 RT_ASSERT(false, "invalid aci: %d !\n", aci);
1260 break;
1261 }
1262 }
1263
1264 void rtl92ce_enable_interrupt(struct ieee80211_hw *hw)
1265 {
1266 struct rtl_priv *rtlpriv = rtl_priv(hw);
1267 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1268
1269 rtl_write_dword(rtlpriv, REG_HIMR, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1270 rtl_write_dword(rtlpriv, REG_HIMRE, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1271 }
1272
1273 void rtl92ce_disable_interrupt(struct ieee80211_hw *hw)
1274 {
1275 struct rtl_priv *rtlpriv = rtl_priv(hw);
1276 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1277
1278 rtl_write_dword(rtlpriv, REG_HIMR, IMR8190_DISABLED);
1279 rtl_write_dword(rtlpriv, REG_HIMRE, IMR8190_DISABLED);
1280 synchronize_irq(rtlpci->pdev->irq);
1281 }
1282
1283 static void _rtl92ce_poweroff_adapter(struct ieee80211_hw *hw)
1284 {
1285 struct rtl_priv *rtlpriv = rtl_priv(hw);
1286 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1287 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1288 u8 u1b_tmp;
1289 u32 u4b_tmp;
1290
1291 rtlpriv->intf_ops->enable_aspm(hw);
1292 rtl_write_byte(rtlpriv, REG_TXPAUSE, 0xFF);
1293 rtl_set_rfreg(hw, RF90_PATH_A, 0x00, RFREG_OFFSET_MASK, 0x00);
1294 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1295 rtl_write_byte(rtlpriv, REG_APSD_CTRL, 0x40);
1296 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE2);
1297 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN, 0xE0);
1298 if (rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7))
1299 rtl92c_firmware_selfreset(hw);
1300 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN + 1, 0x51);
1301 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1302 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00000000);
1303 u1b_tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL);
1304 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1305 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
1306 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8))) {
1307 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00F30000 |
1308 (u1b_tmp << 8));
1309 } else {
1310 rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x00FF0000 |
1311 (u1b_tmp << 8));
1312 }
1313 rtl_write_word(rtlpriv, REG_GPIO_IO_SEL, 0x0790);
1314 rtl_write_word(rtlpriv, REG_LEDCFG0, 0x8080);
1315 rtl_write_byte(rtlpriv, REG_AFE_PLL_CTRL, 0x80);
1316 if (!IS_81xxC_VENDOR_UMC_B_CUT(rtlhal->version))
1317 rtl_write_byte(rtlpriv, REG_SPS0_CTRL, 0x23);
1318 if (rtlpcipriv->bt_coexist.bt_coexistence) {
1319 u4b_tmp = rtl_read_dword(rtlpriv, REG_AFE_XTAL_CTRL);
1320 u4b_tmp |= 0x03824800;
1321 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, u4b_tmp);
1322 } else {
1323 rtl_write_dword(rtlpriv, REG_AFE_XTAL_CTRL, 0x0e);
1324 }
1325
1326 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1327 rtl_write_byte(rtlpriv, REG_APS_FSMCO + 1, 0x10);
1328 }
1329
1330 void rtl92ce_card_disable(struct ieee80211_hw *hw)
1331 {
1332 struct rtl_priv *rtlpriv = rtl_priv(hw);
1333 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1334 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1335 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1336 enum nl80211_iftype opmode;
1337
1338 mac->link_state = MAC80211_NOLINK;
1339 opmode = NL80211_IFTYPE_UNSPECIFIED;
1340 _rtl92ce_set_media_status(hw, opmode);
1341 if (rtlpci->driver_is_goingto_unload ||
1342 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1343 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1344 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1345 _rtl92ce_poweroff_adapter(hw);
1346
1347 /* after power off we should do iqk again */
1348 rtlpriv->phy.iqk_initialized = false;
1349 }
1350
1351 void rtl92ce_interrupt_recognized(struct ieee80211_hw *hw,
1352 u32 *p_inta, u32 *p_intb)
1353 {
1354 struct rtl_priv *rtlpriv = rtl_priv(hw);
1355 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1356
1357 *p_inta = rtl_read_dword(rtlpriv, ISR) & rtlpci->irq_mask[0];
1358 rtl_write_dword(rtlpriv, ISR, *p_inta);
1359
1360 /*
1361 * *p_intb = rtl_read_dword(rtlpriv, REG_HISRE) & rtlpci->irq_mask[1];
1362 * rtl_write_dword(rtlpriv, ISR + 4, *p_intb);
1363 */
1364 }
1365
1366 void rtl92ce_set_beacon_related_registers(struct ieee80211_hw *hw)
1367 {
1368
1369 struct rtl_priv *rtlpriv = rtl_priv(hw);
1370 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1371 u16 bcn_interval, atim_window;
1372
1373 bcn_interval = mac->beacon_interval;
1374 atim_window = 2; /*FIX MERGE */
1375 rtl92ce_disable_interrupt(hw);
1376 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1377 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1378 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1379 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1380 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1381 rtl_write_byte(rtlpriv, 0x606, 0x30);
1382 rtl92ce_enable_interrupt(hw);
1383 }
1384
1385 void rtl92ce_set_beacon_interval(struct ieee80211_hw *hw)
1386 {
1387 struct rtl_priv *rtlpriv = rtl_priv(hw);
1388 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1389 u16 bcn_interval = mac->beacon_interval;
1390
1391 RT_TRACE(rtlpriv, COMP_BEACON, DBG_DMESG,
1392 "beacon_interval:%d\n", bcn_interval);
1393 rtl92ce_disable_interrupt(hw);
1394 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1395 rtl92ce_enable_interrupt(hw);
1396 }
1397
1398 void rtl92ce_update_interrupt_mask(struct ieee80211_hw *hw,
1399 u32 add_msr, u32 rm_msr)
1400 {
1401 struct rtl_priv *rtlpriv = rtl_priv(hw);
1402 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1403
1404 RT_TRACE(rtlpriv, COMP_INTR, DBG_LOUD, "add_msr:%x, rm_msr:%x\n",
1405 add_msr, rm_msr);
1406
1407 if (add_msr)
1408 rtlpci->irq_mask[0] |= add_msr;
1409 if (rm_msr)
1410 rtlpci->irq_mask[0] &= (~rm_msr);
1411 rtl92ce_disable_interrupt(hw);
1412 rtl92ce_enable_interrupt(hw);
1413 }
1414
1415 static void _rtl92ce_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1416 bool autoload_fail,
1417 u8 *hwinfo)
1418 {
1419 struct rtl_priv *rtlpriv = rtl_priv(hw);
1420 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1421 u8 rf_path, index, tempval;
1422 u16 i;
1423
1424 for (rf_path = 0; rf_path < 2; rf_path++) {
1425 for (i = 0; i < 3; i++) {
1426 if (!autoload_fail) {
1427 rtlefuse->
1428 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1429 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1430 rtlefuse->
1431 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1432 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 +
1433 i];
1434 } else {
1435 rtlefuse->
1436 eeprom_chnlarea_txpwr_cck[rf_path][i] =
1437 EEPROM_DEFAULT_TXPOWERLEVEL;
1438 rtlefuse->
1439 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1440 EEPROM_DEFAULT_TXPOWERLEVEL;
1441 }
1442 }
1443 }
1444
1445 for (i = 0; i < 3; i++) {
1446 if (!autoload_fail)
1447 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1448 else
1449 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1450 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1451 (tempval & 0xf);
1452 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1453 ((tempval & 0xf0) >> 4);
1454 }
1455
1456 for (rf_path = 0; rf_path < 2; rf_path++)
1457 for (i = 0; i < 3; i++)
1458 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1459 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n",
1460 rf_path, i,
1461 rtlefuse->
1462 eeprom_chnlarea_txpwr_cck[rf_path][i]);
1463 for (rf_path = 0; rf_path < 2; rf_path++)
1464 for (i = 0; i < 3; i++)
1465 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1466 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1467 rf_path, i,
1468 rtlefuse->
1469 eeprom_chnlarea_txpwr_ht40_1s[rf_path][i]);
1470 for (rf_path = 0; rf_path < 2; rf_path++)
1471 for (i = 0; i < 3; i++)
1472 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1473 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1474 rf_path, i,
1475 rtlefuse->
1476 eprom_chnl_txpwr_ht40_2sdf[rf_path][i]);
1477
1478 for (rf_path = 0; rf_path < 2; rf_path++) {
1479 for (i = 0; i < 14; i++) {
1480 index = _rtl92c_get_chnl_group((u8) i);
1481
1482 rtlefuse->txpwrlevel_cck[rf_path][i] =
1483 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][index];
1484 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1485 rtlefuse->
1486 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index];
1487
1488 if ((rtlefuse->
1489 eeprom_chnlarea_txpwr_ht40_1s[rf_path][index] -
1490 rtlefuse->
1491 eprom_chnl_txpwr_ht40_2sdf[rf_path][index])
1492 > 0) {
1493 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1494 rtlefuse->
1495 eeprom_chnlarea_txpwr_ht40_1s[rf_path]
1496 [index] -
1497 rtlefuse->
1498 eprom_chnl_txpwr_ht40_2sdf[rf_path]
1499 [index];
1500 } else {
1501 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1502 }
1503 }
1504
1505 for (i = 0; i < 14; i++) {
1506 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1507 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1508 rf_path, i,
1509 rtlefuse->txpwrlevel_cck[rf_path][i],
1510 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1511 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1512 }
1513 }
1514
1515 for (i = 0; i < 3; i++) {
1516 if (!autoload_fail) {
1517 rtlefuse->eeprom_pwrlimit_ht40[i] =
1518 hwinfo[EEPROM_TXPWR_GROUP + i];
1519 rtlefuse->eeprom_pwrlimit_ht20[i] =
1520 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1521 } else {
1522 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1523 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1524 }
1525 }
1526
1527 for (rf_path = 0; rf_path < 2; rf_path++) {
1528 for (i = 0; i < 14; i++) {
1529 index = _rtl92c_get_chnl_group((u8) i);
1530
1531 if (rf_path == RF90_PATH_A) {
1532 rtlefuse->pwrgroup_ht20[rf_path][i] =
1533 (rtlefuse->eeprom_pwrlimit_ht20[index]
1534 & 0xf);
1535 rtlefuse->pwrgroup_ht40[rf_path][i] =
1536 (rtlefuse->eeprom_pwrlimit_ht40[index]
1537 & 0xf);
1538 } else if (rf_path == RF90_PATH_B) {
1539 rtlefuse->pwrgroup_ht20[rf_path][i] =
1540 ((rtlefuse->eeprom_pwrlimit_ht20[index]
1541 & 0xf0) >> 4);
1542 rtlefuse->pwrgroup_ht40[rf_path][i] =
1543 ((rtlefuse->eeprom_pwrlimit_ht40[index]
1544 & 0xf0) >> 4);
1545 }
1546
1547 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1548 "RF-%d pwrgroup_ht20[%d] = 0x%x\n",
1549 rf_path, i,
1550 rtlefuse->pwrgroup_ht20[rf_path][i]);
1551 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1552 "RF-%d pwrgroup_ht40[%d] = 0x%x\n",
1553 rf_path, i,
1554 rtlefuse->pwrgroup_ht40[rf_path][i]);
1555 }
1556 }
1557
1558 for (i = 0; i < 14; i++) {
1559 index = _rtl92c_get_chnl_group((u8) i);
1560
1561 if (!autoload_fail)
1562 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1563 else
1564 tempval = EEPROM_DEFAULT_HT20_DIFF;
1565
1566 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1567 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1568 ((tempval >> 4) & 0xF);
1569
1570 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1571 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1572
1573 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1574 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1575
1576 index = _rtl92c_get_chnl_group((u8) i);
1577
1578 if (!autoload_fail)
1579 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1580 else
1581 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1582
1583 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1584 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1585 ((tempval >> 4) & 0xF);
1586 }
1587
1588 rtlefuse->legacy_ht_txpowerdiff =
1589 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1590
1591 for (i = 0; i < 14; i++)
1592 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1593 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n",
1594 i, rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1595 for (i = 0; i < 14; i++)
1596 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1597 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n",
1598 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1599 for (i = 0; i < 14; i++)
1600 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1601 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n",
1602 i, rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1603 for (i = 0; i < 14; i++)
1604 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1605 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n",
1606 i, rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1607
1608 if (!autoload_fail)
1609 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1610 else
1611 rtlefuse->eeprom_regulatory = 0;
1612 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1613 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1614
1615 if (!autoload_fail) {
1616 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1617 rtlefuse->eeprom_tssi[RF90_PATH_B] = hwinfo[EEPROM_TSSI_B];
1618 } else {
1619 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1620 rtlefuse->eeprom_tssi[RF90_PATH_B] = EEPROM_DEFAULT_TSSI;
1621 }
1622 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER, "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1623 rtlefuse->eeprom_tssi[RF90_PATH_A],
1624 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1625
1626 if (!autoload_fail)
1627 tempval = hwinfo[EEPROM_THERMAL_METER];
1628 else
1629 tempval = EEPROM_DEFAULT_THERMALMETER;
1630 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1631
1632 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1633 rtlefuse->apk_thermalmeterignore = true;
1634
1635 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1636 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1637 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1638 }
1639
1640 static void _rtl92ce_read_adapter_info(struct ieee80211_hw *hw)
1641 {
1642 struct rtl_priv *rtlpriv = rtl_priv(hw);
1643 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1644 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1645 u16 i, usvalue;
1646 u8 hwinfo[HWSET_MAX_SIZE];
1647 u16 eeprom_id;
1648
1649 if (rtlefuse->epromtype == EEPROM_BOOT_EFUSE) {
1650 rtl_efuse_shadow_map_update(hw);
1651
1652 memcpy((void *)hwinfo,
1653 (void *)&rtlefuse->efuse_map[EFUSE_INIT_MAP][0],
1654 HWSET_MAX_SIZE);
1655 } else if (rtlefuse->epromtype == EEPROM_93C46) {
1656 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1657 "RTL819X Not boot from eeprom, check it !!");
1658 }
1659
1660 RT_PRINT_DATA(rtlpriv, COMP_INIT, DBG_DMESG, "MAP",
1661 hwinfo, HWSET_MAX_SIZE);
1662
1663 eeprom_id = *((u16 *)&hwinfo[0]);
1664 if (eeprom_id != RTL8190_EEPROM_ID) {
1665 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1666 "EEPROM ID(%#x) is invalid!!\n", eeprom_id);
1667 rtlefuse->autoload_failflag = true;
1668 } else {
1669 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1670 rtlefuse->autoload_failflag = false;
1671 }
1672
1673 if (rtlefuse->autoload_failflag)
1674 return;
1675
1676 rtlefuse->eeprom_vid = *(u16 *)&hwinfo[EEPROM_VID];
1677 rtlefuse->eeprom_did = *(u16 *)&hwinfo[EEPROM_DID];
1678 rtlefuse->eeprom_svid = *(u16 *)&hwinfo[EEPROM_SVID];
1679 rtlefuse->eeprom_smid = *(u16 *)&hwinfo[EEPROM_SMID];
1680 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1681 "EEPROMId = 0x%4x\n", eeprom_id);
1682 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1683 "EEPROM VID = 0x%4x\n", rtlefuse->eeprom_vid);
1684 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1685 "EEPROM DID = 0x%4x\n", rtlefuse->eeprom_did);
1686 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1687 "EEPROM SVID = 0x%4x\n", rtlefuse->eeprom_svid);
1688 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1689 "EEPROM SMID = 0x%4x\n", rtlefuse->eeprom_smid);
1690
1691 for (i = 0; i < 6; i += 2) {
1692 usvalue = *(u16 *)&hwinfo[EEPROM_MAC_ADDR + i];
1693 *((u16 *) (&rtlefuse->dev_addr[i])) = usvalue;
1694 }
1695
1696 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%pM\n", rtlefuse->dev_addr);
1697
1698 _rtl92ce_read_txpower_info_from_hwpg(hw,
1699 rtlefuse->autoload_failflag,
1700 hwinfo);
1701
1702 rtl8192ce_read_bt_coexist_info_from_hwpg(hw,
1703 rtlefuse->autoload_failflag,
1704 hwinfo);
1705
1706 rtlefuse->eeprom_channelplan = *&hwinfo[EEPROM_CHANNELPLAN];
1707 rtlefuse->eeprom_version = *(u16 *)&hwinfo[EEPROM_VERSION];
1708 rtlefuse->txpwr_fromeprom = true;
1709 rtlefuse->eeprom_oemid = *&hwinfo[EEPROM_CUSTOMER_ID];
1710
1711 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1712 "EEPROM Customer ID: 0x%2x\n", rtlefuse->eeprom_oemid);
1713
1714 /* set channel paln to world wide 13 */
1715 rtlefuse->channel_plan = COUNTRY_CODE_WORLD_WIDE_13;
1716
1717 if (rtlhal->oem_id == RT_CID_DEFAULT) {
1718 switch (rtlefuse->eeprom_oemid) {
1719 case EEPROM_CID_DEFAULT:
1720 if (rtlefuse->eeprom_did == 0x8176) {
1721 if ((rtlefuse->eeprom_svid == 0x103C &&
1722 rtlefuse->eeprom_smid == 0x1629))
1723 rtlhal->oem_id = RT_CID_819x_HP;
1724 else
1725 rtlhal->oem_id = RT_CID_DEFAULT;
1726 } else {
1727 rtlhal->oem_id = RT_CID_DEFAULT;
1728 }
1729 break;
1730 case EEPROM_CID_TOSHIBA:
1731 rtlhal->oem_id = RT_CID_TOSHIBA;
1732 break;
1733 case EEPROM_CID_QMI:
1734 rtlhal->oem_id = RT_CID_819x_QMI;
1735 break;
1736 case EEPROM_CID_WHQL:
1737 default:
1738 rtlhal->oem_id = RT_CID_DEFAULT;
1739 break;
1740
1741 }
1742 }
1743
1744 }
1745
1746 static void _rtl92ce_hal_customized_behavior(struct ieee80211_hw *hw)
1747 {
1748 struct rtl_priv *rtlpriv = rtl_priv(hw);
1749 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1750 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1751
1752 switch (rtlhal->oem_id) {
1753 case RT_CID_819x_HP:
1754 pcipriv->ledctl.led_opendrain = true;
1755 break;
1756 case RT_CID_819x_Lenovo:
1757 case RT_CID_DEFAULT:
1758 case RT_CID_TOSHIBA:
1759 case RT_CID_CCX:
1760 case RT_CID_819x_Acer:
1761 case RT_CID_WHQL:
1762 default:
1763 break;
1764 }
1765 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1766 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1767 }
1768
1769 void rtl92ce_read_eeprom_info(struct ieee80211_hw *hw)
1770 {
1771 struct rtl_priv *rtlpriv = rtl_priv(hw);
1772 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1773 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1774 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1775 u8 tmp_u1b;
1776
1777 rtlhal->version = _rtl92ce_read_chip_version(hw);
1778 if (get_rf_type(rtlphy) == RF_1T1R)
1779 rtlpriv->dm.rfpath_rxenable[0] = true;
1780 else
1781 rtlpriv->dm.rfpath_rxenable[0] =
1782 rtlpriv->dm.rfpath_rxenable[1] = true;
1783 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1784 rtlhal->version);
1785 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1786 if (tmp_u1b & BIT(4)) {
1787 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1788 rtlefuse->epromtype = EEPROM_93C46;
1789 } else {
1790 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1791 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1792 }
1793 if (tmp_u1b & BIT(5)) {
1794 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1795 rtlefuse->autoload_failflag = false;
1796 _rtl92ce_read_adapter_info(hw);
1797 } else {
1798 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Autoload ERR!!\n");
1799 }
1800 _rtl92ce_hal_customized_behavior(hw);
1801 }
1802
1803 static void rtl92ce_update_hal_rate_table(struct ieee80211_hw *hw,
1804 struct ieee80211_sta *sta)
1805 {
1806 struct rtl_priv *rtlpriv = rtl_priv(hw);
1807 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
1808 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1809 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1810 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1811 u32 ratr_value;
1812 u8 ratr_index = 0;
1813 u8 nmode = mac->ht_enable;
1814 u8 mimo_ps = IEEE80211_SMPS_OFF;
1815 u16 shortgi_rate;
1816 u32 tmp_ratr_value;
1817 u8 curtxbw_40mhz = mac->bw_40;
1818 u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1819 1 : 0;
1820 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1821 1 : 0;
1822 enum wireless_mode wirelessmode = mac->mode;
1823
1824 if (rtlhal->current_bandtype == BAND_ON_5G)
1825 ratr_value = sta->supp_rates[1] << 4;
1826 else
1827 ratr_value = sta->supp_rates[0];
1828 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1829 ratr_value = 0xfff;
1830
1831 ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1832 sta->ht_cap.mcs.rx_mask[0] << 12);
1833 switch (wirelessmode) {
1834 case WIRELESS_MODE_B:
1835 if (ratr_value & 0x0000000c)
1836 ratr_value &= 0x0000000d;
1837 else
1838 ratr_value &= 0x0000000f;
1839 break;
1840 case WIRELESS_MODE_G:
1841 ratr_value &= 0x00000FF5;
1842 break;
1843 case WIRELESS_MODE_N_24G:
1844 case WIRELESS_MODE_N_5G:
1845 nmode = 1;
1846 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1847 ratr_value &= 0x0007F005;
1848 } else {
1849 u32 ratr_mask;
1850
1851 if (get_rf_type(rtlphy) == RF_1T2R ||
1852 get_rf_type(rtlphy) == RF_1T1R)
1853 ratr_mask = 0x000ff005;
1854 else
1855 ratr_mask = 0x0f0ff005;
1856
1857 ratr_value &= ratr_mask;
1858 }
1859 break;
1860 default:
1861 if (rtlphy->rf_type == RF_1T2R)
1862 ratr_value &= 0x000ff0ff;
1863 else
1864 ratr_value &= 0x0f0ff0ff;
1865
1866 break;
1867 }
1868
1869 if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
1870 (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) &&
1871 (rtlpcipriv->bt_coexist.bt_cur_state) &&
1872 (rtlpcipriv->bt_coexist.bt_ant_isolation) &&
1873 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ||
1874 (rtlpcipriv->bt_coexist.bt_service == BT_BUSY)))
1875 ratr_value &= 0x0fffcfc0;
1876 else
1877 ratr_value &= 0x0FFFFFFF;
1878
1879 if (nmode && ((curtxbw_40mhz &&
1880 curshortgi_40mhz) || (!curtxbw_40mhz &&
1881 curshortgi_20mhz))) {
1882
1883 ratr_value |= 0x10000000;
1884 tmp_ratr_value = (ratr_value >> 12);
1885
1886 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1887 if ((1 << shortgi_rate) & tmp_ratr_value)
1888 break;
1889 }
1890
1891 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1892 (shortgi_rate << 4) | (shortgi_rate);
1893 }
1894
1895 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1896
1897 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
1898 rtl_read_dword(rtlpriv, REG_ARFR0));
1899 }
1900
1901 static void rtl92ce_update_hal_rate_mask(struct ieee80211_hw *hw,
1902 struct ieee80211_sta *sta, u8 rssi_level)
1903 {
1904 struct rtl_priv *rtlpriv = rtl_priv(hw);
1905 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1906 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1907 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1908 struct rtl_sta_info *sta_entry = NULL;
1909 u32 ratr_bitmap;
1910 u8 ratr_index;
1911 u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
1912 u8 curshortgi_40mhz = curtxbw_40mhz &&
1913 (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1914 1 : 0;
1915 u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1916 1 : 0;
1917 enum wireless_mode wirelessmode = 0;
1918 bool shortgi = false;
1919 u8 rate_mask[5];
1920 u8 macid = 0;
1921 u8 mimo_ps = IEEE80211_SMPS_OFF;
1922
1923 sta_entry = (struct rtl_sta_info *) sta->drv_priv;
1924 wirelessmode = sta_entry->wireless_mode;
1925 if (mac->opmode == NL80211_IFTYPE_STATION ||
1926 mac->opmode == NL80211_IFTYPE_MESH_POINT)
1927 curtxbw_40mhz = mac->bw_40;
1928 else if (mac->opmode == NL80211_IFTYPE_AP ||
1929 mac->opmode == NL80211_IFTYPE_ADHOC)
1930 macid = sta->aid + 1;
1931
1932 if (rtlhal->current_bandtype == BAND_ON_5G)
1933 ratr_bitmap = sta->supp_rates[1] << 4;
1934 else
1935 ratr_bitmap = sta->supp_rates[0];
1936 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1937 ratr_bitmap = 0xfff;
1938 ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
1939 sta->ht_cap.mcs.rx_mask[0] << 12);
1940 switch (wirelessmode) {
1941 case WIRELESS_MODE_B:
1942 ratr_index = RATR_INX_WIRELESS_B;
1943 if (ratr_bitmap & 0x0000000c)
1944 ratr_bitmap &= 0x0000000d;
1945 else
1946 ratr_bitmap &= 0x0000000f;
1947 break;
1948 case WIRELESS_MODE_G:
1949 ratr_index = RATR_INX_WIRELESS_GB;
1950
1951 if (rssi_level == 1)
1952 ratr_bitmap &= 0x00000f00;
1953 else if (rssi_level == 2)
1954 ratr_bitmap &= 0x00000ff0;
1955 else
1956 ratr_bitmap &= 0x00000ff5;
1957 break;
1958 case WIRELESS_MODE_A:
1959 ratr_index = RATR_INX_WIRELESS_A;
1960 ratr_bitmap &= 0x00000ff0;
1961 break;
1962 case WIRELESS_MODE_N_24G:
1963 case WIRELESS_MODE_N_5G:
1964 ratr_index = RATR_INX_WIRELESS_NGB;
1965
1966 if (mimo_ps == IEEE80211_SMPS_STATIC) {
1967 if (rssi_level == 1)
1968 ratr_bitmap &= 0x00070000;
1969 else if (rssi_level == 2)
1970 ratr_bitmap &= 0x0007f000;
1971 else
1972 ratr_bitmap &= 0x0007f005;
1973 } else {
1974 if (rtlphy->rf_type == RF_1T2R ||
1975 rtlphy->rf_type == RF_1T1R) {
1976 if (curtxbw_40mhz) {
1977 if (rssi_level == 1)
1978 ratr_bitmap &= 0x000f0000;
1979 else if (rssi_level == 2)
1980 ratr_bitmap &= 0x000ff000;
1981 else
1982 ratr_bitmap &= 0x000ff015;
1983 } else {
1984 if (rssi_level == 1)
1985 ratr_bitmap &= 0x000f0000;
1986 else if (rssi_level == 2)
1987 ratr_bitmap &= 0x000ff000;
1988 else
1989 ratr_bitmap &= 0x000ff005;
1990 }
1991 } else {
1992 if (curtxbw_40mhz) {
1993 if (rssi_level == 1)
1994 ratr_bitmap &= 0x0f0f0000;
1995 else if (rssi_level == 2)
1996 ratr_bitmap &= 0x0f0ff000;
1997 else
1998 ratr_bitmap &= 0x0f0ff015;
1999 } else {
2000 if (rssi_level == 1)
2001 ratr_bitmap &= 0x0f0f0000;
2002 else if (rssi_level == 2)
2003 ratr_bitmap &= 0x0f0ff000;
2004 else
2005 ratr_bitmap &= 0x0f0ff005;
2006 }
2007 }
2008 }
2009
2010 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2011 (!curtxbw_40mhz && curshortgi_20mhz)) {
2012
2013 if (macid == 0)
2014 shortgi = true;
2015 else if (macid == 1)
2016 shortgi = false;
2017 }
2018 break;
2019 default:
2020 ratr_index = RATR_INX_WIRELESS_NGB;
2021
2022 if (rtlphy->rf_type == RF_1T2R)
2023 ratr_bitmap &= 0x000ff0ff;
2024 else
2025 ratr_bitmap &= 0x0f0ff0ff;
2026 break;
2027 }
2028 sta_entry->ratr_index = ratr_index;
2029
2030 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2031 "ratr_bitmap :%x\n", ratr_bitmap);
2032 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2033 (ratr_index << 28);
2034 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2035 RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
2036 "Rate_index:%x, ratr_val:%x, %5phC\n",
2037 ratr_index, ratr_bitmap, rate_mask);
2038 rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2039
2040 if (macid != 0)
2041 sta_entry->ratr_index = ratr_index;
2042 }
2043
2044 void rtl92ce_update_hal_rate_tbl(struct ieee80211_hw *hw,
2045 struct ieee80211_sta *sta, u8 rssi_level)
2046 {
2047 struct rtl_priv *rtlpriv = rtl_priv(hw);
2048
2049 if (rtlpriv->dm.useramask)
2050 rtl92ce_update_hal_rate_mask(hw, sta, rssi_level);
2051 else
2052 rtl92ce_update_hal_rate_table(hw, sta);
2053 }
2054
2055 void rtl92ce_update_channel_access_setting(struct ieee80211_hw *hw)
2056 {
2057 struct rtl_priv *rtlpriv = rtl_priv(hw);
2058 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2059 u16 sifs_timer;
2060
2061 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME,
2062 &mac->slot_time);
2063 if (!mac->ht_enable)
2064 sifs_timer = 0x0a0a;
2065 else
2066 sifs_timer = 0x1010;
2067 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2068 }
2069
2070 bool rtl92ce_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2071 {
2072 struct rtl_priv *rtlpriv = rtl_priv(hw);
2073 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2074 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2075 enum rf_pwrstate e_rfpowerstate_toset;
2076 u8 u1tmp;
2077 bool actuallyset = false;
2078 unsigned long flag;
2079
2080 if (rtlpci->being_init_adapter)
2081 return false;
2082
2083 if (ppsc->swrf_processing)
2084 return false;
2085
2086 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2087 if (ppsc->rfchange_inprogress) {
2088 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2089 return false;
2090 } else {
2091 ppsc->rfchange_inprogress = true;
2092 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2093 }
2094
2095 rtl_write_byte(rtlpriv, REG_MAC_PINMUX_CFG, rtl_read_byte(rtlpriv,
2096 REG_MAC_PINMUX_CFG)&~(BIT(3)));
2097
2098 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL);
2099 e_rfpowerstate_toset = (u1tmp & BIT(3)) ? ERFON : ERFOFF;
2100
2101 if ((ppsc->hwradiooff) && (e_rfpowerstate_toset == ERFON)) {
2102 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2103 "GPIOChangeRF - HW Radio ON, RF ON\n");
2104
2105 e_rfpowerstate_toset = ERFON;
2106 ppsc->hwradiooff = false;
2107 actuallyset = true;
2108 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2109 RT_TRACE(rtlpriv, COMP_RF, DBG_DMESG,
2110 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2111
2112 e_rfpowerstate_toset = ERFOFF;
2113 ppsc->hwradiooff = true;
2114 actuallyset = true;
2115 }
2116
2117 if (actuallyset) {
2118 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2119 ppsc->rfchange_inprogress = false;
2120 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2121 } else {
2122 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2123 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2124
2125 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flag);
2126 ppsc->rfchange_inprogress = false;
2127 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flag);
2128 }
2129
2130 *valid = 1;
2131 return !ppsc->hwradiooff;
2132
2133 }
2134
2135 void rtl92ce_set_key(struct ieee80211_hw *hw, u32 key_index,
2136 u8 *p_macaddr, bool is_group, u8 enc_algo,
2137 bool is_wepkey, bool clear_all)
2138 {
2139 struct rtl_priv *rtlpriv = rtl_priv(hw);
2140 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2141 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2142 u8 *macaddr = p_macaddr;
2143 u32 entry_id = 0;
2144 bool is_pairwise = false;
2145
2146 static u8 cam_const_addr[4][6] = {
2147 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2148 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2149 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2150 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2151 };
2152 static u8 cam_const_broad[] = {
2153 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2154 };
2155
2156 if (clear_all) {
2157 u8 idx = 0;
2158 u8 cam_offset = 0;
2159 u8 clear_number = 5;
2160
2161 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2162
2163 for (idx = 0; idx < clear_number; idx++) {
2164 rtl_cam_mark_invalid(hw, cam_offset + idx);
2165 rtl_cam_empty_entry(hw, cam_offset + idx);
2166
2167 if (idx < 5) {
2168 memset(rtlpriv->sec.key_buf[idx], 0,
2169 MAX_KEY_LEN);
2170 rtlpriv->sec.key_len[idx] = 0;
2171 }
2172 }
2173
2174 } else {
2175 switch (enc_algo) {
2176 case WEP40_ENCRYPTION:
2177 enc_algo = CAM_WEP40;
2178 break;
2179 case WEP104_ENCRYPTION:
2180 enc_algo = CAM_WEP104;
2181 break;
2182 case TKIP_ENCRYPTION:
2183 enc_algo = CAM_TKIP;
2184 break;
2185 case AESCCMP_ENCRYPTION:
2186 enc_algo = CAM_AES;
2187 break;
2188 default:
2189 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
2190 "switch case not processed\n");
2191 enc_algo = CAM_TKIP;
2192 break;
2193 }
2194
2195 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2196 macaddr = cam_const_addr[key_index];
2197 entry_id = key_index;
2198 } else {
2199 if (is_group) {
2200 macaddr = cam_const_broad;
2201 entry_id = key_index;
2202 } else {
2203 if (mac->opmode == NL80211_IFTYPE_AP ||
2204 mac->opmode == NL80211_IFTYPE_MESH_POINT) {
2205 entry_id = rtl_cam_get_free_entry(hw,
2206 p_macaddr);
2207 if (entry_id >= TOTAL_CAM_ENTRY) {
2208 RT_TRACE(rtlpriv, COMP_SEC,
2209 DBG_EMERG,
2210 "Can not find free hw security cam entry\n");
2211 return;
2212 }
2213 } else {
2214 entry_id = CAM_PAIRWISE_KEY_POSITION;
2215 }
2216
2217 key_index = PAIRWISE_KEYIDX;
2218 is_pairwise = true;
2219 }
2220 }
2221
2222 if (rtlpriv->sec.key_len[key_index] == 0) {
2223 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2224 "delete one entry, entry_id is %d\n",
2225 entry_id);
2226 if (mac->opmode == NL80211_IFTYPE_AP ||
2227 mac->opmode == NL80211_IFTYPE_MESH_POINT)
2228 rtl_cam_del_entry(hw, p_macaddr);
2229 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2230 } else {
2231 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2232 "The insert KEY length is %d\n",
2233 rtlpriv->sec.key_len[PAIRWISE_KEYIDX]);
2234 RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
2235 "The insert KEY is %x %x\n",
2236 rtlpriv->sec.key_buf[0][0],
2237 rtlpriv->sec.key_buf[0][1]);
2238
2239 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2240 "add one entry\n");
2241 if (is_pairwise) {
2242 RT_PRINT_DATA(rtlpriv, COMP_SEC, DBG_LOUD,
2243 "Pairwise Key content",
2244 rtlpriv->sec.pairwise_key,
2245 rtlpriv->sec.
2246 key_len[PAIRWISE_KEYIDX]);
2247
2248 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2249 "set Pairwise key\n");
2250
2251 rtl_cam_add_one_entry(hw, macaddr, key_index,
2252 entry_id, enc_algo,
2253 CAM_CONFIG_NO_USEDK,
2254 rtlpriv->sec.
2255 key_buf[key_index]);
2256 } else {
2257 RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
2258 "set group key\n");
2259
2260 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2261 rtl_cam_add_one_entry(hw,
2262 rtlefuse->dev_addr,
2263 PAIRWISE_KEYIDX,
2264 CAM_PAIRWISE_KEY_POSITION,
2265 enc_algo,
2266 CAM_CONFIG_NO_USEDK,
2267 rtlpriv->sec.key_buf
2268 [entry_id]);
2269 }
2270
2271 rtl_cam_add_one_entry(hw, macaddr, key_index,
2272 entry_id, enc_algo,
2273 CAM_CONFIG_NO_USEDK,
2274 rtlpriv->sec.key_buf[entry_id]);
2275 }
2276
2277 }
2278 }
2279 }
2280
2281 static void rtl8192ce_bt_var_init(struct ieee80211_hw *hw)
2282 {
2283 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2284
2285 rtlpcipriv->bt_coexist.bt_coexistence =
2286 rtlpcipriv->bt_coexist.eeprom_bt_coexist;
2287 rtlpcipriv->bt_coexist.bt_ant_num =
2288 rtlpcipriv->bt_coexist.eeprom_bt_ant_num;
2289 rtlpcipriv->bt_coexist.bt_coexist_type =
2290 rtlpcipriv->bt_coexist.eeprom_bt_type;
2291
2292 if (rtlpcipriv->bt_coexist.reg_bt_iso == 2)
2293 rtlpcipriv->bt_coexist.bt_ant_isolation =
2294 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol;
2295 else
2296 rtlpcipriv->bt_coexist.bt_ant_isolation =
2297 rtlpcipriv->bt_coexist.reg_bt_iso;
2298
2299 rtlpcipriv->bt_coexist.bt_radio_shared_type =
2300 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared;
2301
2302 if (rtlpcipriv->bt_coexist.bt_coexistence) {
2303
2304 if (rtlpcipriv->bt_coexist.reg_bt_sco == 1)
2305 rtlpcipriv->bt_coexist.bt_service = BT_OTHER_ACTION;
2306 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 2)
2307 rtlpcipriv->bt_coexist.bt_service = BT_SCO;
2308 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 4)
2309 rtlpcipriv->bt_coexist.bt_service = BT_BUSY;
2310 else if (rtlpcipriv->bt_coexist.reg_bt_sco == 5)
2311 rtlpcipriv->bt_coexist.bt_service = BT_OTHERBUSY;
2312 else
2313 rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
2314
2315 rtlpcipriv->bt_coexist.bt_edca_ul = 0;
2316 rtlpcipriv->bt_coexist.bt_edca_dl = 0;
2317 rtlpcipriv->bt_coexist.bt_rssi_state = 0xff;
2318 }
2319 }
2320
2321 void rtl8192ce_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2322 bool auto_load_fail, u8 *hwinfo)
2323 {
2324 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2325 u8 val;
2326
2327 if (!auto_load_fail) {
2328 rtlpcipriv->bt_coexist.eeprom_bt_coexist =
2329 ((hwinfo[RF_OPTION1] & 0xe0) >> 5);
2330 val = hwinfo[RF_OPTION4];
2331 rtlpcipriv->bt_coexist.eeprom_bt_type = ((val & 0xe) >> 1);
2332 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = (val & 0x1);
2333 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = ((val & 0x10) >> 4);
2334 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared =
2335 ((val & 0x20) >> 5);
2336 } else {
2337 rtlpcipriv->bt_coexist.eeprom_bt_coexist = 0;
2338 rtlpcipriv->bt_coexist.eeprom_bt_type = BT_2WIRE;
2339 rtlpcipriv->bt_coexist.eeprom_bt_ant_num = ANT_X2;
2340 rtlpcipriv->bt_coexist.eeprom_bt_ant_isol = 0;
2341 rtlpcipriv->bt_coexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2342 }
2343
2344 rtl8192ce_bt_var_init(hw);
2345 }
2346
2347 void rtl8192ce_bt_reg_init(struct ieee80211_hw *hw)
2348 {
2349 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2350
2351 /* 0:Low, 1:High, 2:From Efuse. */
2352 rtlpcipriv->bt_coexist.reg_bt_iso = 2;
2353 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2354 rtlpcipriv->bt_coexist.reg_bt_sco = 3;
2355 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2356 rtlpcipriv->bt_coexist.reg_bt_sco = 0;
2357 }
2358
2359
2360 void rtl8192ce_bt_hw_init(struct ieee80211_hw *hw)
2361 {
2362 struct rtl_priv *rtlpriv = rtl_priv(hw);
2363 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2364 struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
2365
2366 u8 u1_tmp;
2367
2368 if (rtlpcipriv->bt_coexist.bt_coexistence &&
2369 ((rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4) ||
2370 rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC8)) {
2371
2372 if (rtlpcipriv->bt_coexist.bt_ant_isolation)
2373 rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
2374
2375 u1_tmp = rtl_read_byte(rtlpriv, 0x4fd) &
2376 BIT_OFFSET_LEN_MASK_32(0, 1);
2377 u1_tmp = u1_tmp |
2378 ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
2379 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
2380 ((rtlpcipriv->bt_coexist.bt_service == BT_SCO) ?
2381 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
2382 rtl_write_byte(rtlpriv, 0x4fd, u1_tmp);
2383
2384 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+4, 0xaaaa9aaa);
2385 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+8, 0xffbd0040);
2386 rtl_write_dword(rtlpriv, REG_BT_COEX_TABLE+0xc, 0x40000010);
2387
2388 /* Config to 1T1R. */
2389 if (rtlphy->rf_type == RF_1T1R) {
2390 u1_tmp = rtl_read_byte(rtlpriv, ROFDM0_TRXPATHENABLE);
2391 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2392 rtl_write_byte(rtlpriv, ROFDM0_TRXPATHENABLE, u1_tmp);
2393
2394 u1_tmp = rtl_read_byte(rtlpriv, ROFDM1_TRXPATHENABLE);
2395 u1_tmp &= ~(BIT_OFFSET_LEN_MASK_32(1, 1));
2396 rtl_write_byte(rtlpriv, ROFDM1_TRXPATHENABLE, u1_tmp);
2397 }
2398 }
2399 }
2400
2401 void rtl92ce_suspend(struct ieee80211_hw *hw)
2402 {
2403 }
2404
2405 void rtl92ce_resume(struct ieee80211_hw *hw)
2406 {
2407 }
2408
2409 /* Turn on AAP (RCR:bit 0) for promicuous mode. */
2410 void rtl92ce_allow_all_destaddr(struct ieee80211_hw *hw,
2411 bool allow_all_da, bool write_into_reg)
2412 {
2413 struct rtl_priv *rtlpriv = rtl_priv(hw);
2414 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
2415
2416 if (allow_all_da) {/* Set BIT0 */
2417 rtlpci->receive_config |= RCR_AAP;
2418 } else {/* Clear BIT0 */
2419 rtlpci->receive_config &= ~RCR_AAP;
2420 }
2421
2422 if (write_into_reg)
2423 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
2424
2425 RT_TRACE(rtlpriv, COMP_TURBO | COMP_INIT, DBG_LOUD,
2426 "receive_config=0x%08X, write_into_reg=%d\n",
2427 rtlpci->receive_config, write_into_reg);
2428 }
Linux with added FPC-III support