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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / net / wireless / rtlwifi / wifi.h
blob8c647391bedf0f4bc5ef4fca39b7ca39a05e1483
1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
17 *
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
20 *
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
25 *
26 * Larry Finger <Larry.Finger@lwfinger.net>
27 *
28 *****************************************************************************/
29
30 #ifndef __RTL_WIFI_H__
31 #define __RTL_WIFI_H__
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #include <linux/sched.h>
36 #include <linux/firmware.h>
37 #include <linux/etherdevice.h>
38 #include <linux/vmalloc.h>
39 #include <linux/usb.h>
40 #include <net/mac80211.h>
41 #include <linux/completion.h>
42 #include "debug.h"
43
44 #define RF_CHANGE_BY_INIT 0
45 #define RF_CHANGE_BY_IPS BIT(28)
46 #define RF_CHANGE_BY_PS BIT(29)
47 #define RF_CHANGE_BY_HW BIT(30)
48 #define RF_CHANGE_BY_SW BIT(31)
49
50 #define IQK_ADDA_REG_NUM 16
51 #define IQK_MAC_REG_NUM 4
52
53 #define MAX_KEY_LEN 61
54 #define KEY_BUF_SIZE 5
55
56 /* QoS related. */
57 /*aci: 0x00 Best Effort*/
58 /*aci: 0x01 Background*/
59 /*aci: 0x10 Video*/
60 /*aci: 0x11 Voice*/
61 /*Max: define total number.*/
62 #define AC0_BE 0
63 #define AC1_BK 1
64 #define AC2_VI 2
65 #define AC3_VO 3
66 #define AC_MAX 4
67 #define QOS_QUEUE_NUM 4
68 #define RTL_MAC80211_NUM_QUEUE 5
69 #define REALTEK_USB_VENQT_MAX_BUF_SIZE 254
70 #define RTL_USB_MAX_RX_COUNT 100
71 #define QBSS_LOAD_SIZE 5
72 #define MAX_WMMELE_LENGTH 64
73
74 #define TOTAL_CAM_ENTRY 32
75
76 /*slot time for 11g. */
77 #define RTL_SLOT_TIME_9 9
78 #define RTL_SLOT_TIME_20 20
79
80 /*related to tcp/ip. */
81 #define SNAP_SIZE 6
82 #define PROTOC_TYPE_SIZE 2
83
84 /*related with 802.11 frame*/
85 #define MAC80211_3ADDR_LEN 24
86 #define MAC80211_4ADDR_LEN 30
87
88 #define CHANNEL_MAX_NUMBER (14 + 24 + 21) /* 14 is the max channel no */
89 #define CHANNEL_GROUP_MAX (3 + 9) /* ch1~3, 4~9, 10~14 = three groups */
90 #define MAX_PG_GROUP 13
91 #define CHANNEL_GROUP_MAX_2G 3
92 #define CHANNEL_GROUP_IDX_5GL 3
93 #define CHANNEL_GROUP_IDX_5GM 6
94 #define CHANNEL_GROUP_IDX_5GH 9
95 #define CHANNEL_GROUP_MAX_5G 9
96 #define CHANNEL_MAX_NUMBER_2G 14
97 #define AVG_THERMAL_NUM 8
98 #define AVG_THERMAL_NUM_88E 4
99 #define MAX_TID_COUNT 9
100
101 /* for early mode */
102 #define FCS_LEN 4
103 #define EM_HDR_LEN 8
104
105 #define MAX_TX_COUNT 4
106 #define MAX_RF_PATH 4
107 #define MAX_CHNL_GROUP_24G 6
108 #define MAX_CHNL_GROUP_5G 14
109
110 struct txpower_info_2g {
111 u8 index_cck_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
112 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
113 /*If only one tx, only BW20 and OFDM are used.*/
114 u8 cck_diff[MAX_RF_PATH][MAX_TX_COUNT];
115 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
116 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
117 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
118 };
119
120 struct txpower_info_5g {
121 u8 index_bw40_base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
122 /*If only one tx, only BW20, OFDM, BW80 and BW160 are used.*/
123 u8 ofdm_diff[MAX_RF_PATH][MAX_TX_COUNT];
124 u8 bw20_diff[MAX_RF_PATH][MAX_TX_COUNT];
125 u8 bw40_diff[MAX_RF_PATH][MAX_TX_COUNT];
126 };
127
128 enum intf_type {
129 INTF_PCI = 0,
130 INTF_USB = 1,
131 };
132
133 enum radio_path {
134 RF90_PATH_A = 0,
135 RF90_PATH_B = 1,
136 RF90_PATH_C = 2,
137 RF90_PATH_D = 3,
138 };
139
140 enum rt_eeprom_type {
141 EEPROM_93C46,
142 EEPROM_93C56,
143 EEPROM_BOOT_EFUSE,
144 };
145
146 enum ttl_status {
147 RTL_STATUS_INTERFACE_START = 0,
148 };
149
150 enum hardware_type {
151 HARDWARE_TYPE_RTL8192E,
152 HARDWARE_TYPE_RTL8192U,
153 HARDWARE_TYPE_RTL8192SE,
154 HARDWARE_TYPE_RTL8192SU,
155 HARDWARE_TYPE_RTL8192CE,
156 HARDWARE_TYPE_RTL8192CU,
157 HARDWARE_TYPE_RTL8192DE,
158 HARDWARE_TYPE_RTL8192DU,
159 HARDWARE_TYPE_RTL8723AE,
160 HARDWARE_TYPE_RTL8723U,
161 HARDWARE_TYPE_RTL8188EE,
162
163 /* keep it last */
164 HARDWARE_TYPE_NUM
165 };
166
167 #define IS_HARDWARE_TYPE_8192SU(rtlhal) \
168 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SU)
169 #define IS_HARDWARE_TYPE_8192SE(rtlhal) \
170 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
171 #define IS_HARDWARE_TYPE_8192CE(rtlhal) \
172 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CE)
173 #define IS_HARDWARE_TYPE_8192CU(rtlhal) \
174 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192CU)
175 #define IS_HARDWARE_TYPE_8192DE(rtlhal) \
176 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE)
177 #define IS_HARDWARE_TYPE_8192DU(rtlhal) \
178 (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DU)
179 #define IS_HARDWARE_TYPE_8723E(rtlhal) \
180 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723E)
181 #define IS_HARDWARE_TYPE_8723U(rtlhal) \
182 (rtlhal->hw_type == HARDWARE_TYPE_RTL8723U)
183 #define IS_HARDWARE_TYPE_8192S(rtlhal) \
184 (IS_HARDWARE_TYPE_8192SE(rtlhal) || IS_HARDWARE_TYPE_8192SU(rtlhal))
185 #define IS_HARDWARE_TYPE_8192C(rtlhal) \
186 (IS_HARDWARE_TYPE_8192CE(rtlhal) || IS_HARDWARE_TYPE_8192CU(rtlhal))
187 #define IS_HARDWARE_TYPE_8192D(rtlhal) \
188 (IS_HARDWARE_TYPE_8192DE(rtlhal) || IS_HARDWARE_TYPE_8192DU(rtlhal))
189 #define IS_HARDWARE_TYPE_8723(rtlhal) \
190 (IS_HARDWARE_TYPE_8723E(rtlhal) || IS_HARDWARE_TYPE_8723U(rtlhal))
191
192 #define RX_HAL_IS_CCK_RATE(_pdesc)\
193 (_pdesc->rxmcs == DESC92_RATE1M || \
194 _pdesc->rxmcs == DESC92_RATE2M || \
195 _pdesc->rxmcs == DESC92_RATE5_5M || \
196 _pdesc->rxmcs == DESC92_RATE11M)
197
198 enum scan_operation_backup_opt {
199 SCAN_OPT_BACKUP = 0,
200 SCAN_OPT_RESTORE,
201 SCAN_OPT_MAX
202 };
203
204 /*RF state.*/
205 enum rf_pwrstate {
206 ERFON,
207 ERFSLEEP,
208 ERFOFF
209 };
210
211 struct bb_reg_def {
212 u32 rfintfs;
213 u32 rfintfi;
214 u32 rfintfo;
215 u32 rfintfe;
216 u32 rf3wire_offset;
217 u32 rflssi_select;
218 u32 rftxgain_stage;
219 u32 rfhssi_para1;
220 u32 rfhssi_para2;
221 u32 rfsw_ctrl;
222 u32 rfagc_control1;
223 u32 rfagc_control2;
224 u32 rfrxiq_imbal;
225 u32 rfrx_afe;
226 u32 rftxiq_imbal;
227 u32 rftx_afe;
228 u32 rf_rb; /* rflssi_readback */
229 u32 rf_rbpi; /* rflssi_readbackpi */
230 };
231
232 enum io_type {
233 IO_CMD_PAUSE_DM_BY_SCAN = 0,
234 IO_CMD_RESUME_DM_BY_SCAN = 1,
235 };
236
237 enum hw_variables {
238 HW_VAR_ETHER_ADDR,
239 HW_VAR_MULTICAST_REG,
240 HW_VAR_BASIC_RATE,
241 HW_VAR_BSSID,
242 HW_VAR_MEDIA_STATUS,
243 HW_VAR_SECURITY_CONF,
244 HW_VAR_BEACON_INTERVAL,
245 HW_VAR_ATIM_WINDOW,
246 HW_VAR_LISTEN_INTERVAL,
247 HW_VAR_CS_COUNTER,
248 HW_VAR_DEFAULTKEY0,
249 HW_VAR_DEFAULTKEY1,
250 HW_VAR_DEFAULTKEY2,
251 HW_VAR_DEFAULTKEY3,
252 HW_VAR_SIFS,
253 HW_VAR_DIFS,
254 HW_VAR_EIFS,
255 HW_VAR_SLOT_TIME,
256 HW_VAR_ACK_PREAMBLE,
257 HW_VAR_CW_CONFIG,
258 HW_VAR_CW_VALUES,
259 HW_VAR_RATE_FALLBACK_CONTROL,
260 HW_VAR_CONTENTION_WINDOW,
261 HW_VAR_RETRY_COUNT,
262 HW_VAR_TR_SWITCH,
263 HW_VAR_COMMAND,
264 HW_VAR_WPA_CONFIG,
265 HW_VAR_AMPDU_MIN_SPACE,
266 HW_VAR_SHORTGI_DENSITY,
267 HW_VAR_AMPDU_FACTOR,
268 HW_VAR_MCS_RATE_AVAILABLE,
269 HW_VAR_AC_PARAM,
270 HW_VAR_ACM_CTRL,
271 HW_VAR_DIS_Req_Qsize,
272 HW_VAR_CCX_CHNL_LOAD,
273 HW_VAR_CCX_NOISE_HISTOGRAM,
274 HW_VAR_CCX_CLM_NHM,
275 HW_VAR_TxOPLimit,
276 HW_VAR_TURBO_MODE,
277 HW_VAR_RF_STATE,
278 HW_VAR_RF_OFF_BY_HW,
279 HW_VAR_BUS_SPEED,
280 HW_VAR_SET_DEV_POWER,
281
282 HW_VAR_RCR,
283 HW_VAR_RATR_0,
284 HW_VAR_RRSR,
285 HW_VAR_CPU_RST,
286 HW_VAR_CHECK_BSSID,
287 HW_VAR_LBK_MODE,
288 HW_VAR_AES_11N_FIX,
289 HW_VAR_USB_RX_AGGR,
290 HW_VAR_USER_CONTROL_TURBO_MODE,
291 HW_VAR_RETRY_LIMIT,
292 HW_VAR_INIT_TX_RATE,
293 HW_VAR_TX_RATE_REG,
294 HW_VAR_EFUSE_USAGE,
295 HW_VAR_EFUSE_BYTES,
296 HW_VAR_AUTOLOAD_STATUS,
297 HW_VAR_RF_2R_DISABLE,
298 HW_VAR_SET_RPWM,
299 HW_VAR_H2C_FW_PWRMODE,
300 HW_VAR_H2C_FW_JOINBSSRPT,
301 HW_VAR_H2C_FW_P2P_PS_OFFLOAD,
302 HW_VAR_FW_PSMODE_STATUS,
303 HW_VAR_RESUME_CLK_ON,
304 HW_VAR_FW_LPS_ACTION,
305 HW_VAR_1X1_RECV_COMBINE,
306 HW_VAR_STOP_SEND_BEACON,
307 HW_VAR_TSF_TIMER,
308 HW_VAR_IO_CMD,
309
310 HW_VAR_RF_RECOVERY,
311 HW_VAR_H2C_FW_UPDATE_GTK,
312 HW_VAR_WF_MASK,
313 HW_VAR_WF_CRC,
314 HW_VAR_WF_IS_MAC_ADDR,
315 HW_VAR_H2C_FW_OFFLOAD,
316 HW_VAR_RESET_WFCRC,
317
318 HW_VAR_HANDLE_FW_C2H,
319 HW_VAR_DL_FW_RSVD_PAGE,
320 HW_VAR_AID,
321 HW_VAR_HW_SEQ_ENABLE,
322 HW_VAR_CORRECT_TSF,
323 HW_VAR_BCN_VALID,
324 HW_VAR_FWLPS_RF_ON,
325 HW_VAR_DUAL_TSF_RST,
326 HW_VAR_SWITCH_EPHY_WoWLAN,
327 HW_VAR_INT_MIGRATION,
328 HW_VAR_INT_AC,
329 HW_VAR_RF_TIMING,
330
331 HAL_DEF_WOWLAN,
332 HW_VAR_MRC,
333
334 HW_VAR_MGT_FILTER,
335 HW_VAR_CTRL_FILTER,
336 HW_VAR_DATA_FILTER,
337 };
338
339 enum _RT_MEDIA_STATUS {
340 RT_MEDIA_DISCONNECT = 0,
341 RT_MEDIA_CONNECT = 1
342 };
343
344 enum rt_oem_id {
345 RT_CID_DEFAULT = 0,
346 RT_CID_8187_ALPHA0 = 1,
347 RT_CID_8187_SERCOMM_PS = 2,
348 RT_CID_8187_HW_LED = 3,
349 RT_CID_8187_NETGEAR = 4,
350 RT_CID_WHQL = 5,
351 RT_CID_819x_CAMEO = 6,
352 RT_CID_819x_RUNTOP = 7,
353 RT_CID_819x_Senao = 8,
354 RT_CID_TOSHIBA = 9,
355 RT_CID_819x_Netcore = 10,
356 RT_CID_Nettronix = 11,
357 RT_CID_DLINK = 12,
358 RT_CID_PRONET = 13,
359 RT_CID_COREGA = 14,
360 RT_CID_819x_ALPHA = 15,
361 RT_CID_819x_Sitecom = 16,
362 RT_CID_CCX = 17,
363 RT_CID_819x_Lenovo = 18,
364 RT_CID_819x_QMI = 19,
365 RT_CID_819x_Edimax_Belkin = 20,
366 RT_CID_819x_Sercomm_Belkin = 21,
367 RT_CID_819x_CAMEO1 = 22,
368 RT_CID_819x_MSI = 23,
369 RT_CID_819x_Acer = 24,
370 RT_CID_819x_HP = 27,
371 RT_CID_819x_CLEVO = 28,
372 RT_CID_819x_Arcadyan_Belkin = 29,
373 RT_CID_819x_SAMSUNG = 30,
374 RT_CID_819x_WNC_COREGA = 31,
375 RT_CID_819x_Foxcoon = 32,
376 RT_CID_819x_DELL = 33,
377 RT_CID_819x_PRONETS = 34,
378 RT_CID_819x_Edimax_ASUS = 35,
379 RT_CID_NETGEAR = 36,
380 RT_CID_PLANEX = 37,
381 RT_CID_CC_C = 38,
382 };
383
384 enum hw_descs {
385 HW_DESC_OWN,
386 HW_DESC_RXOWN,
387 HW_DESC_TX_NEXTDESC_ADDR,
388 HW_DESC_TXBUFF_ADDR,
389 HW_DESC_RXBUFF_ADDR,
390 HW_DESC_RXPKT_LEN,
391 HW_DESC_RXERO,
392 };
393
394 enum prime_sc {
395 PRIME_CHNL_OFFSET_DONT_CARE = 0,
396 PRIME_CHNL_OFFSET_LOWER = 1,
397 PRIME_CHNL_OFFSET_UPPER = 2,
398 };
399
400 enum rf_type {
401 RF_1T1R = 0,
402 RF_1T2R = 1,
403 RF_2T2R = 2,
404 RF_2T2R_GREEN = 3,
405 };
406
407 enum ht_channel_width {
408 HT_CHANNEL_WIDTH_20 = 0,
409 HT_CHANNEL_WIDTH_20_40 = 1,
410 };
411
412 /* Ref: 802.11i sepc D10.0 7.3.2.25.1
413 Cipher Suites Encryption Algorithms */
414 enum rt_enc_alg {
415 NO_ENCRYPTION = 0,
416 WEP40_ENCRYPTION = 1,
417 TKIP_ENCRYPTION = 2,
418 RSERVED_ENCRYPTION = 3,
419 AESCCMP_ENCRYPTION = 4,
420 WEP104_ENCRYPTION = 5,
421 AESCMAC_ENCRYPTION = 6, /*IEEE802.11w */
422 };
423
424 enum rtl_hal_state {
425 _HAL_STATE_STOP = 0,
426 _HAL_STATE_START = 1,
427 };
428
429 enum rtl_desc92_rate {
430 DESC92_RATE1M = 0x00,
431 DESC92_RATE2M = 0x01,
432 DESC92_RATE5_5M = 0x02,
433 DESC92_RATE11M = 0x03,
434
435 DESC92_RATE6M = 0x04,
436 DESC92_RATE9M = 0x05,
437 DESC92_RATE12M = 0x06,
438 DESC92_RATE18M = 0x07,
439 DESC92_RATE24M = 0x08,
440 DESC92_RATE36M = 0x09,
441 DESC92_RATE48M = 0x0a,
442 DESC92_RATE54M = 0x0b,
443
444 DESC92_RATEMCS0 = 0x0c,
445 DESC92_RATEMCS1 = 0x0d,
446 DESC92_RATEMCS2 = 0x0e,
447 DESC92_RATEMCS3 = 0x0f,
448 DESC92_RATEMCS4 = 0x10,
449 DESC92_RATEMCS5 = 0x11,
450 DESC92_RATEMCS6 = 0x12,
451 DESC92_RATEMCS7 = 0x13,
452 DESC92_RATEMCS8 = 0x14,
453 DESC92_RATEMCS9 = 0x15,
454 DESC92_RATEMCS10 = 0x16,
455 DESC92_RATEMCS11 = 0x17,
456 DESC92_RATEMCS12 = 0x18,
457 DESC92_RATEMCS13 = 0x19,
458 DESC92_RATEMCS14 = 0x1a,
459 DESC92_RATEMCS15 = 0x1b,
460 DESC92_RATEMCS15_SG = 0x1c,
461 DESC92_RATEMCS32 = 0x20,
462 };
463
464 enum rtl_var_map {
465 /*reg map */
466 SYS_ISO_CTRL = 0,
467 SYS_FUNC_EN,
468 SYS_CLK,
469 MAC_RCR_AM,
470 MAC_RCR_AB,
471 MAC_RCR_ACRC32,
472 MAC_RCR_ACF,
473 MAC_RCR_AAP,
474
475 /*efuse map */
476 EFUSE_TEST,
477 EFUSE_CTRL,
478 EFUSE_CLK,
479 EFUSE_CLK_CTRL,
480 EFUSE_PWC_EV12V,
481 EFUSE_FEN_ELDR,
482 EFUSE_LOADER_CLK_EN,
483 EFUSE_ANA8M,
484 EFUSE_HWSET_MAX_SIZE,
485 EFUSE_MAX_SECTION_MAP,
486 EFUSE_REAL_CONTENT_SIZE,
487 EFUSE_OOB_PROTECT_BYTES_LEN,
488 EFUSE_ACCESS,
489
490 /*CAM map */
491 RWCAM,
492 WCAMI,
493 RCAMO,
494 CAMDBG,
495 SECR,
496 SEC_CAM_NONE,
497 SEC_CAM_WEP40,
498 SEC_CAM_TKIP,
499 SEC_CAM_AES,
500 SEC_CAM_WEP104,
501
502 /*IMR map */
503 RTL_IMR_BCNDMAINT6, /*Beacon DMA Interrupt 6 */
504 RTL_IMR_BCNDMAINT5, /*Beacon DMA Interrupt 5 */
505 RTL_IMR_BCNDMAINT4, /*Beacon DMA Interrupt 4 */
506 RTL_IMR_BCNDMAINT3, /*Beacon DMA Interrupt 3 */
507 RTL_IMR_BCNDMAINT2, /*Beacon DMA Interrupt 2 */
508 RTL_IMR_BCNDMAINT1, /*Beacon DMA Interrupt 1 */
509 RTL_IMR_BCNDOK8, /*Beacon Queue DMA OK Interrup 8 */
510 RTL_IMR_BCNDOK7, /*Beacon Queue DMA OK Interrup 7 */
511 RTL_IMR_BCNDOK6, /*Beacon Queue DMA OK Interrup 6 */
512 RTL_IMR_BCNDOK5, /*Beacon Queue DMA OK Interrup 5 */
513 RTL_IMR_BCNDOK4, /*Beacon Queue DMA OK Interrup 4 */
514 RTL_IMR_BCNDOK3, /*Beacon Queue DMA OK Interrup 3 */
515 RTL_IMR_BCNDOK2, /*Beacon Queue DMA OK Interrup 2 */
516 RTL_IMR_BCNDOK1, /*Beacon Queue DMA OK Interrup 1 */
517 RTL_IMR_TIMEOUT2, /*Timeout interrupt 2 */
518 RTL_IMR_TIMEOUT1, /*Timeout interrupt 1 */
519 RTL_IMR_TXFOVW, /*Transmit FIFO Overflow */
520 RTL_IMR_PSTIMEOUT, /*Power save time out interrupt */
521 RTL_IMR_BCNINT, /*Beacon DMA Interrupt 0 */
522 RTL_IMR_RXFOVW, /*Receive FIFO Overflow */
523 RTL_IMR_RDU, /*Receive Descriptor Unavailable */
524 RTL_IMR_ATIMEND, /*For 92C,ATIM Window End Interrupt */
525 RTL_IMR_BDOK, /*Beacon Queue DMA OK Interrup */
526 RTL_IMR_HIGHDOK, /*High Queue DMA OK Interrupt */
527 RTL_IMR_COMDOK, /*Command Queue DMA OK Interrupt*/
528 RTL_IMR_TBDOK, /*Transmit Beacon OK interrup */
529 RTL_IMR_MGNTDOK, /*Management Queue DMA OK Interrupt */
530 RTL_IMR_TBDER, /*For 92C,Transmit Beacon Error Interrupt */
531 RTL_IMR_BKDOK, /*AC_BK DMA OK Interrupt */
532 RTL_IMR_BEDOK, /*AC_BE DMA OK Interrupt */
533 RTL_IMR_VIDOK, /*AC_VI DMA OK Interrupt */
534 RTL_IMR_VODOK, /*AC_VO DMA Interrupt */
535 RTL_IMR_ROK, /*Receive DMA OK Interrupt */
536 RTL_IBSS_INT_MASKS, /*(RTL_IMR_BCNINT | RTL_IMR_TBDOK |
537 * RTL_IMR_TBDER) */
538 RTL_IMR_C2HCMD, /*fw interrupt*/
539
540 /*CCK Rates, TxHT = 0 */
541 RTL_RC_CCK_RATE1M,
542 RTL_RC_CCK_RATE2M,
543 RTL_RC_CCK_RATE5_5M,
544 RTL_RC_CCK_RATE11M,
545
546 /*OFDM Rates, TxHT = 0 */
547 RTL_RC_OFDM_RATE6M,
548 RTL_RC_OFDM_RATE9M,
549 RTL_RC_OFDM_RATE12M,
550 RTL_RC_OFDM_RATE18M,
551 RTL_RC_OFDM_RATE24M,
552 RTL_RC_OFDM_RATE36M,
553 RTL_RC_OFDM_RATE48M,
554 RTL_RC_OFDM_RATE54M,
555
556 RTL_RC_HT_RATEMCS7,
557 RTL_RC_HT_RATEMCS15,
558
559 /*keep it last */
560 RTL_VAR_MAP_MAX,
561 };
562
563 /*Firmware PS mode for control LPS.*/
564 enum _fw_ps_mode {
565 FW_PS_ACTIVE_MODE = 0,
566 FW_PS_MIN_MODE = 1,
567 FW_PS_MAX_MODE = 2,
568 FW_PS_DTIM_MODE = 3,
569 FW_PS_VOIP_MODE = 4,
570 FW_PS_UAPSD_WMM_MODE = 5,
571 FW_PS_UAPSD_MODE = 6,
572 FW_PS_IBSS_MODE = 7,
573 FW_PS_WWLAN_MODE = 8,
574 FW_PS_PM_Radio_Off = 9,
575 FW_PS_PM_Card_Disable = 10,
576 };
577
578 enum rt_psmode {
579 EACTIVE, /*Active/Continuous access. */
580 EMAXPS, /*Max power save mode. */
581 EFASTPS, /*Fast power save mode. */
582 EAUTOPS, /*Auto power save mode. */
583 };
584
585 /*LED related.*/
586 enum led_ctl_mode {
587 LED_CTL_POWER_ON = 1,
588 LED_CTL_LINK = 2,
589 LED_CTL_NO_LINK = 3,
590 LED_CTL_TX = 4,
591 LED_CTL_RX = 5,
592 LED_CTL_SITE_SURVEY = 6,
593 LED_CTL_POWER_OFF = 7,
594 LED_CTL_START_TO_LINK = 8,
595 LED_CTL_START_WPS = 9,
596 LED_CTL_STOP_WPS = 10,
597 };
598
599 enum rtl_led_pin {
600 LED_PIN_GPIO0,
601 LED_PIN_LED0,
602 LED_PIN_LED1,
603 LED_PIN_LED2
604 };
605
606 /*QoS related.*/
607 /*acm implementation method.*/
608 enum acm_method {
609 eAcmWay0_SwAndHw = 0,
610 eAcmWay1_HW = 1,
611 eAcmWay2_SW = 2,
612 };
613
614 enum macphy_mode {
615 SINGLEMAC_SINGLEPHY = 0,
616 DUALMAC_DUALPHY,
617 DUALMAC_SINGLEPHY,
618 };
619
620 enum band_type {
621 BAND_ON_2_4G = 0,
622 BAND_ON_5G,
623 BAND_ON_BOTH,
624 BANDMAX
625 };
626
627 /*aci/aifsn Field.
628 Ref: WMM spec 2.2.2: WME Parameter Element, p.12.*/
629 union aci_aifsn {
630 u8 char_data;
631
632 struct {
633 u8 aifsn:4;
634 u8 acm:1;
635 u8 aci:2;
636 u8 reserved:1;
637 } f; /* Field */
638 };
639
640 /*mlme related.*/
641 enum wireless_mode {
642 WIRELESS_MODE_UNKNOWN = 0x00,
643 WIRELESS_MODE_A = 0x01,
644 WIRELESS_MODE_B = 0x02,
645 WIRELESS_MODE_G = 0x04,
646 WIRELESS_MODE_AUTO = 0x08,
647 WIRELESS_MODE_N_24G = 0x10,
648 WIRELESS_MODE_N_5G = 0x20
649 };
650
651 #define IS_WIRELESS_MODE_A(wirelessmode) \
652 (wirelessmode == WIRELESS_MODE_A)
653 #define IS_WIRELESS_MODE_B(wirelessmode) \
654 (wirelessmode == WIRELESS_MODE_B)
655 #define IS_WIRELESS_MODE_G(wirelessmode) \
656 (wirelessmode == WIRELESS_MODE_G)
657 #define IS_WIRELESS_MODE_N_24G(wirelessmode) \
658 (wirelessmode == WIRELESS_MODE_N_24G)
659 #define IS_WIRELESS_MODE_N_5G(wirelessmode) \
660 (wirelessmode == WIRELESS_MODE_N_5G)
661
662 enum ratr_table_mode {
663 RATR_INX_WIRELESS_NGB = 0,
664 RATR_INX_WIRELESS_NG = 1,
665 RATR_INX_WIRELESS_NB = 2,
666 RATR_INX_WIRELESS_N = 3,
667 RATR_INX_WIRELESS_GB = 4,
668 RATR_INX_WIRELESS_G = 5,
669 RATR_INX_WIRELESS_B = 6,
670 RATR_INX_WIRELESS_MC = 7,
671 RATR_INX_WIRELESS_A = 8,
672 };
673
674 enum rtl_link_state {
675 MAC80211_NOLINK = 0,
676 MAC80211_LINKING = 1,
677 MAC80211_LINKED = 2,
678 MAC80211_LINKED_SCANNING = 3,
679 };
680
681 enum act_category {
682 ACT_CAT_QOS = 1,
683 ACT_CAT_DLS = 2,
684 ACT_CAT_BA = 3,
685 ACT_CAT_HT = 7,
686 ACT_CAT_WMM = 17,
687 };
688
689 enum ba_action {
690 ACT_ADDBAREQ = 0,
691 ACT_ADDBARSP = 1,
692 ACT_DELBA = 2,
693 };
694
695 enum rt_polarity_ctl {
696 RT_POLARITY_LOW_ACT = 0,
697 RT_POLARITY_HIGH_ACT = 1,
698 };
699
700 struct octet_string {
701 u8 *octet;
702 u16 length;
703 };
704
705 struct rtl_hdr_3addr {
706 __le16 frame_ctl;
707 __le16 duration_id;
708 u8 addr1[ETH_ALEN];
709 u8 addr2[ETH_ALEN];
710 u8 addr3[ETH_ALEN];
711 __le16 seq_ctl;
712 u8 payload[0];
713 } __packed;
714
715 struct rtl_info_element {
716 u8 id;
717 u8 len;
718 u8 data[0];
719 } __packed;
720
721 struct rtl_probe_rsp {
722 struct rtl_hdr_3addr header;
723 u32 time_stamp[2];
724 __le16 beacon_interval;
725 __le16 capability;
726 /*SSID, supported rates, FH params, DS params,
727 CF params, IBSS params, TIM (if beacon), RSN */
728 struct rtl_info_element info_element[0];
729 } __packed;
730
731 /*LED related.*/
732 /*ledpin Identify how to implement this SW led.*/
733 struct rtl_led {
734 void *hw;
735 enum rtl_led_pin ledpin;
736 bool ledon;
737 };
738
739 struct rtl_led_ctl {
740 bool led_opendrain;
741 struct rtl_led sw_led0;
742 struct rtl_led sw_led1;
743 };
744
745 struct rtl_qos_parameters {
746 __le16 cw_min;
747 __le16 cw_max;
748 u8 aifs;
749 u8 flag;
750 __le16 tx_op;
751 } __packed;
752
753 struct rt_smooth_data {
754 u32 elements[100]; /*array to store values */
755 u32 index; /*index to current array to store */
756 u32 total_num; /*num of valid elements */
757 u32 total_val; /*sum of valid elements */
758 };
759
760 struct false_alarm_statistics {
761 u32 cnt_parity_fail;
762 u32 cnt_rate_illegal;
763 u32 cnt_crc8_fail;
764 u32 cnt_mcs_fail;
765 u32 cnt_fast_fsync_fail;
766 u32 cnt_sb_search_fail;
767 u32 cnt_ofdm_fail;
768 u32 cnt_cck_fail;
769 u32 cnt_all;
770 u32 cnt_ofdm_cca;
771 u32 cnt_cck_cca;
772 u32 cnt_cca_all;
773 u32 cnt_bw_usc;
774 u32 cnt_bw_lsc;
775 };
776
777 struct init_gain {
778 u8 xaagccore1;
779 u8 xbagccore1;
780 u8 xcagccore1;
781 u8 xdagccore1;
782 u8 cca;
783
784 };
785
786 struct wireless_stats {
787 unsigned long txbytesunicast;
788 unsigned long txbytesmulticast;
789 unsigned long txbytesbroadcast;
790 unsigned long rxbytesunicast;
791
792 long rx_snr_db[4];
793 /*Correct smoothed ss in Dbm, only used
794 in driver to report real power now. */
795 long recv_signal_power;
796 long signal_quality;
797 long last_sigstrength_inpercent;
798
799 u32 rssi_calculate_cnt;
800
801 /*Transformed, in dbm. Beautified signal
802 strength for UI, not correct. */
803 long signal_strength;
804
805 u8 rx_rssi_percentage[4];
806 u8 rx_evm_percentage[2];
807
808 struct rt_smooth_data ui_rssi;
809 struct rt_smooth_data ui_link_quality;
810 };
811
812 struct rate_adaptive {
813 u8 rate_adaptive_disabled;
814 u8 ratr_state;
815 u16 reserve;
816
817 u32 high_rssi_thresh_for_ra;
818 u32 high2low_rssi_thresh_for_ra;
819 u8 low2high_rssi_thresh_for_ra40m;
820 u32 low_rssi_thresh_for_ra40M;
821 u8 low2high_rssi_thresh_for_ra20m;
822 u32 low_rssi_thresh_for_ra20M;
823 u32 upper_rssi_threshold_ratr;
824 u32 middleupper_rssi_threshold_ratr;
825 u32 middle_rssi_threshold_ratr;
826 u32 middlelow_rssi_threshold_ratr;
827 u32 low_rssi_threshold_ratr;
828 u32 ultralow_rssi_threshold_ratr;
829 u32 low_rssi_threshold_ratr_40m;
830 u32 low_rssi_threshold_ratr_20m;
831 u8 ping_rssi_enable;
832 u32 ping_rssi_ratr;
833 u32 ping_rssi_thresh_for_ra;
834 u32 last_ratr;
835 u8 pre_ratr_state;
836 };
837
838 struct regd_pair_mapping {
839 u16 reg_dmnenum;
840 u16 reg_5ghz_ctl;
841 u16 reg_2ghz_ctl;
842 };
843
844 struct rtl_regulatory {
845 char alpha2[2];
846 u16 country_code;
847 u16 max_power_level;
848 u32 tp_scale;
849 u16 current_rd;
850 u16 current_rd_ext;
851 int16_t power_limit;
852 struct regd_pair_mapping *regpair;
853 };
854
855 struct rtl_rfkill {
856 bool rfkill_state; /*0 is off, 1 is on */
857 };
858
859 /*for P2P PS**/
860 #define P2P_MAX_NOA_NUM 2
861
862 enum p2p_role {
863 P2P_ROLE_DISABLE = 0,
864 P2P_ROLE_DEVICE = 1,
865 P2P_ROLE_CLIENT = 2,
866 P2P_ROLE_GO = 3
867 };
868
869 enum p2p_ps_state {
870 P2P_PS_DISABLE = 0,
871 P2P_PS_ENABLE = 1,
872 P2P_PS_SCAN = 2,
873 P2P_PS_SCAN_DONE = 3,
874 P2P_PS_ALLSTASLEEP = 4, /* for P2P GO */
875 };
876
877 enum p2p_ps_mode {
878 P2P_PS_NONE = 0,
879 P2P_PS_CTWINDOW = 1,
880 P2P_PS_NOA = 2,
881 P2P_PS_MIX = 3, /* CTWindow and NoA */
882 };
883
884 struct rtl_p2p_ps_info {
885 enum p2p_ps_mode p2p_ps_mode; /* indicate p2p ps mode */
886 enum p2p_ps_state p2p_ps_state; /* indicate p2p ps state */
887 u8 noa_index; /* Identifies instance of Notice of Absence timing. */
888 /* Client traffic window. A period of time in TU after TBTT. */
889 u8 ctwindow;
890 u8 opp_ps; /* opportunistic power save. */
891 u8 noa_num; /* number of NoA descriptor in P2P IE. */
892 /* Count for owner, Type of client. */
893 u8 noa_count_type[P2P_MAX_NOA_NUM];
894 /* Max duration for owner, preferred or min acceptable duration
895 * for client.
896 */
897 u32 noa_duration[P2P_MAX_NOA_NUM];
898 /* Length of interval for owner, preferred or max acceptable intervali
899 * of client.
900 */
901 u32 noa_interval[P2P_MAX_NOA_NUM];
902 /* schedule in terms of the lower 4 bytes of the TSF timer. */
903 u32 noa_start_time[P2P_MAX_NOA_NUM];
904 };
905
906 struct p2p_ps_offload_t {
907 u8 offload_en:1;
908 u8 role:1; /* 1: Owner, 0: Client */
909 u8 ctwindow_en:1;
910 u8 noa0_en:1;
911 u8 noa1_en:1;
912 u8 allstasleep:1;
913 u8 discovery:1;
914 u8 reserved:1;
915 };
916
917 #define IQK_MATRIX_REG_NUM 8
918 #define IQK_MATRIX_SETTINGS_NUM (1 + 24 + 21)
919
920 struct iqk_matrix_regs {
921 bool iqk_done;
922 long value[1][IQK_MATRIX_REG_NUM];
923 };
924
925 struct phy_parameters {
926 u16 length;
927 u32 *pdata;
928 };
929
930 enum hw_param_tab_index {
931 PHY_REG_2T,
932 PHY_REG_1T,
933 PHY_REG_PG,
934 RADIOA_2T,
935 RADIOB_2T,
936 RADIOA_1T,
937 RADIOB_1T,
938 MAC_REG,
939 AGCTAB_2T,
940 AGCTAB_1T,
941 MAX_TAB
942 };
943
944 struct rtl_phy {
945 struct bb_reg_def phyreg_def[4]; /*Radio A/B/C/D */
946 struct init_gain initgain_backup;
947 enum io_type current_io_type;
948
949 u8 rf_mode;
950 u8 rf_type;
951 u8 current_chan_bw;
952 u8 set_bwmode_inprogress;
953 u8 sw_chnl_inprogress;
954 u8 sw_chnl_stage;
955 u8 sw_chnl_step;
956 u8 current_channel;
957 u8 h2c_box_num;
958 u8 set_io_inprogress;
959 u8 lck_inprogress;
960
961 /* record for power tracking */
962 s32 reg_e94;
963 s32 reg_e9c;
964 s32 reg_ea4;
965 s32 reg_eac;
966 s32 reg_eb4;
967 s32 reg_ebc;
968 s32 reg_ec4;
969 s32 reg_ecc;
970 u8 rfpienable;
971 u8 reserve_0;
972 u16 reserve_1;
973 u32 reg_c04, reg_c08, reg_874;
974 u32 adda_backup[16];
975 u32 iqk_mac_backup[IQK_MAC_REG_NUM];
976 u32 iqk_bb_backup[10];
977 bool iqk_initialized;
978
979 /* Dual mac */
980 bool need_iqk;
981 struct iqk_matrix_regs iqk_matrix[IQK_MATRIX_SETTINGS_NUM];
982
983 bool rfpi_enable;
984
985 u8 pwrgroup_cnt;
986 u8 cck_high_power;
987 /* MAX_PG_GROUP groups of pwr diff by rates */
988 u32 mcs_offset[MAX_PG_GROUP][16];
989 u8 default_initialgain[4];
990
991 /* the current Tx power level */
992 u8 cur_cck_txpwridx;
993 u8 cur_ofdm24g_txpwridx;
994 u8 cur_bw20_txpwridx;
995 u8 cur_bw40_txpwridx;
996
997 u32 rfreg_chnlval[2];
998 bool apk_done;
999 u32 reg_rf3c[2]; /* pathA / pathB */
1000
1001 /* bfsync */
1002 u8 framesync;
1003 u32 framesync_c34;
1004
1005 u8 num_total_rfpath;
1006 struct phy_parameters hwparam_tables[MAX_TAB];
1007 u16 rf_pathmap;
1008
1009 enum rt_polarity_ctl polarity_ctl;
1010 };
1011
1012 #define MAX_TID_COUNT 9
1013 #define RTL_AGG_STOP 0
1014 #define RTL_AGG_PROGRESS 1
1015 #define RTL_AGG_START 2
1016 #define RTL_AGG_OPERATIONAL 3
1017 #define RTL_AGG_OFF 0
1018 #define RTL_AGG_ON 1
1019 #define RTL_RX_AGG_START 1
1020 #define RTL_RX_AGG_STOP 0
1021 #define RTL_AGG_EMPTYING_HW_QUEUE_ADDBA 2
1022 #define RTL_AGG_EMPTYING_HW_QUEUE_DELBA 3
1023
1024 struct rtl_ht_agg {
1025 u16 txq_id;
1026 u16 wait_for_ba;
1027 u16 start_idx;
1028 u64 bitmap;
1029 u32 rate_n_flags;
1030 u8 agg_state;
1031 u8 rx_agg_state;
1032 };
1033
1034 struct rssi_sta {
1035 long undec_sm_pwdb;
1036 long undec_sm_cck;
1037 };
1038
1039 struct rtl_tid_data {
1040 u16 seq_number;
1041 struct rtl_ht_agg agg;
1042 };
1043
1044 struct rtl_sta_info {
1045 struct list_head list;
1046 u8 ratr_index;
1047 u8 wireless_mode;
1048 u8 mimo_ps;
1049 u8 mac_addr[ETH_ALEN];
1050 struct rtl_tid_data tids[MAX_TID_COUNT];
1051
1052 /* just used for ap adhoc or mesh*/
1053 struct rssi_sta rssi_stat;
1054 } __packed;
1055
1056 struct rtl_priv;
1057 struct rtl_io {
1058 struct device *dev;
1059 struct mutex bb_mutex;
1060
1061 /*PCI MEM map */
1062 unsigned long pci_mem_end; /*shared mem end */
1063 unsigned long pci_mem_start; /*shared mem start */
1064
1065 /*PCI IO map */
1066 unsigned long pci_base_addr; /*device I/O address */
1067
1068 void (*write8_async) (struct rtl_priv *rtlpriv, u32 addr, u8 val);
1069 void (*write16_async) (struct rtl_priv *rtlpriv, u32 addr, u16 val);
1070 void (*write32_async) (struct rtl_priv *rtlpriv, u32 addr, u32 val);
1071 void (*writeN_sync) (struct rtl_priv *rtlpriv, u32 addr, void *buf,
1072 u16 len);
1073
1074 u8(*read8_sync) (struct rtl_priv *rtlpriv, u32 addr);
1075 u16(*read16_sync) (struct rtl_priv *rtlpriv, u32 addr);
1076 u32(*read32_sync) (struct rtl_priv *rtlpriv, u32 addr);
1077
1078 };
1079
1080 struct rtl_mac {
1081 u8 mac_addr[ETH_ALEN];
1082 u8 mac80211_registered;
1083 u8 beacon_enabled;
1084
1085 u32 tx_ss_num;
1086 u32 rx_ss_num;
1087
1088 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
1089 struct ieee80211_hw *hw;
1090 struct ieee80211_vif *vif;
1091 enum nl80211_iftype opmode;
1092
1093 /*Probe Beacon management */
1094 struct rtl_tid_data tids[MAX_TID_COUNT];
1095 enum rtl_link_state link_state;
1096
1097 int n_channels;
1098 int n_bitrates;
1099
1100 bool offchan_delay;
1101 u8 p2p; /*using p2p role*/
1102 bool p2p_in_use;
1103
1104 /*filters */
1105 u32 rx_conf;
1106 u16 rx_mgt_filter;
1107 u16 rx_ctrl_filter;
1108 u16 rx_data_filter;
1109
1110 bool act_scanning;
1111 u8 cnt_after_linked;
1112 bool skip_scan;
1113
1114 /* early mode */
1115 /* skb wait queue */
1116 struct sk_buff_head skb_waitq[MAX_TID_COUNT];
1117
1118 /*RDG*/
1119 bool rdg_en;
1120
1121 /*AP*/
1122 u8 bssid[6];
1123 u32 vendor;
1124 u8 mcs[16]; /* 16 bytes mcs for HT rates. */
1125 u32 basic_rates; /* b/g rates */
1126 u8 ht_enable;
1127 u8 sgi_40;
1128 u8 sgi_20;
1129 u8 bw_40;
1130 u8 mode; /* wireless mode */
1131 u8 slot_time;
1132 u8 short_preamble;
1133 u8 use_cts_protect;
1134 u8 cur_40_prime_sc;
1135 u8 cur_40_prime_sc_bk;
1136 u64 tsf;
1137 u8 retry_short;
1138 u8 retry_long;
1139 u16 assoc_id;
1140 bool hiddenssid;
1141
1142 /*IBSS*/
1143 int beacon_interval;
1144
1145 /*AMPDU*/
1146 u8 min_space_cfg; /*For Min spacing configurations */
1147 u8 max_mss_density;
1148 u8 current_ampdu_factor;
1149 u8 current_ampdu_density;
1150
1151 /*QOS & EDCA */
1152 struct ieee80211_tx_queue_params edca_param[RTL_MAC80211_NUM_QUEUE];
1153 struct rtl_qos_parameters ac[AC_MAX];
1154
1155 /* counters */
1156 u64 last_txok_cnt;
1157 u64 last_rxok_cnt;
1158 u32 last_bt_edca_ul;
1159 u32 last_bt_edca_dl;
1160 };
1161
1162 struct btdm_8723 {
1163 bool all_off;
1164 bool agc_table_en;
1165 bool adc_back_off_on;
1166 bool b2_ant_hid_en;
1167 bool low_penalty_rate_adaptive;
1168 bool rf_rx_lpf_shrink;
1169 bool reject_aggre_pkt;
1170 bool tra_tdma_on;
1171 u8 tra_tdma_nav;
1172 u8 tra_tdma_ant;
1173 bool tdma_on;
1174 u8 tdma_ant;
1175 u8 tdma_nav;
1176 u8 tdma_dac_swing;
1177 u8 fw_dac_swing_lvl;
1178 bool ps_tdma_on;
1179 u8 ps_tdma_byte[5];
1180 bool pta_on;
1181 u32 val_0x6c0;
1182 u32 val_0x6c8;
1183 u32 val_0x6cc;
1184 bool sw_dac_swing_on;
1185 u32 sw_dac_swing_lvl;
1186 u32 wlan_act_hi;
1187 u32 wlan_act_lo;
1188 u32 bt_retry_index;
1189 bool dec_bt_pwr;
1190 bool ignore_wlan_act;
1191 };
1192
1193 struct bt_coexist_8723 {
1194 u32 high_priority_tx;
1195 u32 high_priority_rx;
1196 u32 low_priority_tx;
1197 u32 low_priority_rx;
1198 u8 c2h_bt_info;
1199 bool c2h_bt_info_req_sent;
1200 bool c2h_bt_inquiry_page;
1201 u32 bt_inq_page_start_time;
1202 u8 bt_retry_cnt;
1203 u8 c2h_bt_info_original;
1204 u8 bt_inquiry_page_cnt;
1205 struct btdm_8723 btdm;
1206 };
1207
1208 struct rtl_hal {
1209 struct ieee80211_hw *hw;
1210 bool driver_is_goingto_unload;
1211 bool up_first_time;
1212 bool first_init;
1213 bool being_init_adapter;
1214 bool bbrf_ready;
1215 bool mac_func_enable;
1216 struct bt_coexist_8723 hal_coex_8723;
1217
1218 enum intf_type interface;
1219 u16 hw_type; /*92c or 92d or 92s and so on */
1220 u8 ic_class;
1221 u8 oem_id;
1222 u32 version; /*version of chip */
1223 u8 state; /*stop 0, start 1 */
1224 u8 board_type;
1225
1226 /*firmware */
1227 u32 fwsize;
1228 u8 *pfirmware;
1229 u16 fw_version;
1230 u16 fw_subversion;
1231 bool h2c_setinprogress;
1232 u8 last_hmeboxnum;
1233 bool fw_ready;
1234 /*Reserve page start offset except beacon in TxQ. */
1235 u8 fw_rsvdpage_startoffset;
1236 u8 h2c_txcmd_seq;
1237
1238 /* FW Cmd IO related */
1239 u16 fwcmd_iomap;
1240 u32 fwcmd_ioparam;
1241 bool set_fwcmd_inprogress;
1242 u8 current_fwcmd_io;
1243
1244 struct p2p_ps_offload_t p2p_ps_offload;
1245 bool fw_clk_change_in_progress;
1246 bool allow_sw_to_change_hwclc;
1247 u8 fw_ps_state;
1248 /**/
1249 bool driver_going2unload;
1250
1251 /*AMPDU init min space*/
1252 u8 minspace_cfg; /*For Min spacing configurations */
1253
1254 /* Dual mac */
1255 enum macphy_mode macphymode;
1256 enum band_type current_bandtype; /* 0:2.4G, 1:5G */
1257 enum band_type current_bandtypebackup;
1258 enum band_type bandset;
1259 /* dual MAC 0--Mac0 1--Mac1 */
1260 u32 interfaceindex;
1261 /* just for DualMac S3S4 */
1262 u8 macphyctl_reg;
1263 bool earlymode_enable;
1264 u8 max_earlymode_num;
1265 /* Dual mac*/
1266 bool during_mac0init_radiob;
1267 bool during_mac1init_radioa;
1268 bool reloadtxpowerindex;
1269 /* True if IMR or IQK have done
1270 for 2.4G in scan progress */
1271 bool load_imrandiqk_setting_for2g;
1272
1273 bool disable_amsdu_8k;
1274 bool master_of_dmsp;
1275 bool slave_of_dmsp;
1276 };
1277
1278 struct rtl_security {
1279 /*default 0 */
1280 bool use_sw_sec;
1281
1282 bool being_setkey;
1283 bool use_defaultkey;
1284 /*Encryption Algorithm for Unicast Packet */
1285 enum rt_enc_alg pairwise_enc_algorithm;
1286 /*Encryption Algorithm for Brocast/Multicast */
1287 enum rt_enc_alg group_enc_algorithm;
1288 /*Cam Entry Bitmap */
1289 u32 hwsec_cam_bitmap;
1290 u8 hwsec_cam_sta_addr[TOTAL_CAM_ENTRY][ETH_ALEN];
1291 /*local Key buffer, indx 0 is for
1292 pairwise key 1-4 is for agoup key. */
1293 u8 key_buf[KEY_BUF_SIZE][MAX_KEY_LEN];
1294 u8 key_len[KEY_BUF_SIZE];
1295
1296 /*The pointer of Pairwise Key,
1297 it always points to KeyBuf[4] */
1298 u8 *pairwise_key;
1299 };
1300
1301 #define ASSOCIATE_ENTRY_NUM 33
1302
1303 struct fast_ant_training {
1304 u8 bssid[6];
1305 u8 antsel_rx_keep_0;
1306 u8 antsel_rx_keep_1;
1307 u8 antsel_rx_keep_2;
1308 u32 ant_sum[7];
1309 u32 ant_cnt[7];
1310 u32 ant_ave[7];
1311 u8 fat_state;
1312 u32 train_idx;
1313 u8 antsel_a[ASSOCIATE_ENTRY_NUM];
1314 u8 antsel_b[ASSOCIATE_ENTRY_NUM];
1315 u8 antsel_c[ASSOCIATE_ENTRY_NUM];
1316 u32 main_ant_sum[ASSOCIATE_ENTRY_NUM];
1317 u32 aux_ant_sum[ASSOCIATE_ENTRY_NUM];
1318 u32 main_ant_cnt[ASSOCIATE_ENTRY_NUM];
1319 u32 aux_ant_cnt[ASSOCIATE_ENTRY_NUM];
1320 u8 rx_idle_ant;
1321 bool becomelinked;
1322 };
1323
1324 struct rtl_dm {
1325 /*PHY status for Dynamic Management */
1326 long entry_min_undec_sm_pwdb;
1327 long undec_sm_cck;
1328 long undec_sm_pwdb; /*out dm */
1329 long entry_max_undec_sm_pwdb;
1330 s32 ofdm_pkt_cnt;
1331 bool dm_initialgain_enable;
1332 bool dynamic_txpower_enable;
1333 bool current_turbo_edca;
1334 bool is_any_nonbepkts; /*out dm */
1335 bool is_cur_rdlstate;
1336 bool txpower_trackinginit;
1337 bool disable_framebursting;
1338 bool cck_inch14;
1339 bool txpower_tracking;
1340 bool useramask;
1341 bool rfpath_rxenable[4];
1342 bool inform_fw_driverctrldm;
1343 bool current_mrc_switch;
1344 u8 txpowercount;
1345 u8 powerindex_backup[6];
1346
1347 u8 thermalvalue_rxgain;
1348 u8 thermalvalue_iqk;
1349 u8 thermalvalue_lck;
1350 u8 thermalvalue;
1351 u8 last_dtp_lvl;
1352 u8 thermalvalue_avg[AVG_THERMAL_NUM];
1353 u8 thermalvalue_avg_index;
1354 bool done_txpower;
1355 u8 dynamic_txhighpower_lvl; /*Tx high power level */
1356 u8 dm_flag; /*Indicate each dynamic mechanism's status. */
1357 u8 dm_flag_tmp;
1358 u8 dm_type;
1359 u8 dm_rssi_sel;
1360 u8 txpower_track_control;
1361 bool interrupt_migration;
1362 bool disable_tx_int;
1363 char ofdm_index[2];
1364 char cck_index;
1365 char delta_power_index;
1366 char delta_power_index_last;
1367 char power_index_offset;
1368
1369 /*88e tx power tracking*/
1370 u8 swing_idx_ofdm[2];
1371 u8 swing_idx_ofdm_cur;
1372 u8 swing_idx_ofdm_base;
1373 bool swing_flag_ofdm;
1374 u8 swing_idx_cck;
1375 u8 swing_idx_cck_cur;
1376 u8 swing_idx_cck_base;
1377 bool swing_flag_cck;
1378
1379 /* DMSP */
1380 bool supp_phymode_switch;
1381
1382 struct fast_ant_training fat_table;
1383 };
1384
1385 #define EFUSE_MAX_LOGICAL_SIZE 256
1386
1387 struct rtl_efuse {
1388 bool autoLoad_ok;
1389 bool bootfromefuse;
1390 u16 max_physical_size;
1391
1392 u8 efuse_map[2][EFUSE_MAX_LOGICAL_SIZE];
1393 u16 efuse_usedbytes;
1394 u8 efuse_usedpercentage;
1395 #ifdef EFUSE_REPG_WORKAROUND
1396 bool efuse_re_pg_sec1flag;
1397 u8 efuse_re_pg_data[8];
1398 #endif
1399
1400 u8 autoload_failflag;
1401 u8 autoload_status;
1402
1403 short epromtype;
1404 u16 eeprom_vid;
1405 u16 eeprom_did;
1406 u16 eeprom_svid;
1407 u16 eeprom_smid;
1408 u8 eeprom_oemid;
1409 u16 eeprom_channelplan;
1410 u8 eeprom_version;
1411 u8 board_type;
1412 u8 external_pa;
1413
1414 u8 dev_addr[6];
1415 u8 wowlan_enable;
1416 u8 antenna_div_cfg;
1417 u8 antenna_div_type;
1418
1419 bool txpwr_fromeprom;
1420 u8 eeprom_crystalcap;
1421 u8 eeprom_tssi[2];
1422 u8 eeprom_tssi_5g[3][2]; /* for 5GL/5GM/5GH band. */
1423 u8 eeprom_pwrlimit_ht20[CHANNEL_GROUP_MAX];
1424 u8 eeprom_pwrlimit_ht40[CHANNEL_GROUP_MAX];
1425 u8 eeprom_chnlarea_txpwr_cck[2][CHANNEL_GROUP_MAX_2G];
1426 u8 eeprom_chnlarea_txpwr_ht40_1s[2][CHANNEL_GROUP_MAX];
1427 u8 eprom_chnl_txpwr_ht40_2sdf[2][CHANNEL_GROUP_MAX];
1428 u8 txpwrlevel_cck[2][CHANNEL_MAX_NUMBER_2G];
1429 u8 txpwrlevel_ht40_1s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1430 u8 txpwrlevel_ht40_2s[2][CHANNEL_MAX_NUMBER]; /*For HT 40MHZ pwr */
1431
1432 u8 internal_pa_5g[2]; /* pathA / pathB */
1433 u8 eeprom_c9;
1434 u8 eeprom_cc;
1435
1436 /*For power group */
1437 u8 eeprom_pwrgroup[2][3];
1438 u8 pwrgroup_ht20[2][CHANNEL_MAX_NUMBER];
1439 u8 pwrgroup_ht40[2][CHANNEL_MAX_NUMBER];
1440
1441 char txpwr_ht20diff[2][CHANNEL_MAX_NUMBER]; /*HT 20<->40 Pwr diff */
1442 /*For HT<->legacy pwr diff*/
1443 u8 txpwr_legacyhtdiff[2][CHANNEL_MAX_NUMBER];
1444 u8 txpwr_safetyflag; /* Band edge enable flag */
1445 u16 eeprom_txpowerdiff;
1446 u8 legacy_httxpowerdiff; /* Legacy to HT rate power diff */
1447 u8 antenna_txpwdiff[3];
1448
1449 u8 eeprom_regulatory;
1450 u8 eeprom_thermalmeter;
1451 u8 thermalmeter[2]; /*ThermalMeter, index 0 for RFIC0, 1 for RFIC1 */
1452 u16 tssi_13dbm;
1453 u8 crystalcap; /* CrystalCap. */
1454 u8 delta_iqk;
1455 u8 delta_lck;
1456
1457 u8 legacy_ht_txpowerdiff; /*Legacy to HT rate power diff */
1458 bool apk_thermalmeterignore;
1459
1460 bool b1x1_recvcombine;
1461 bool b1ss_support;
1462
1463 /*channel plan */
1464 u8 channel_plan;
1465 };
1466
1467 struct rtl_ps_ctl {
1468 bool pwrdomain_protect;
1469 bool in_powersavemode;
1470 bool rfchange_inprogress;
1471 bool swrf_processing;
1472 bool hwradiooff;
1473 /*
1474 * just for PCIE ASPM
1475 * If it supports ASPM, Offset[560h] = 0x40,
1476 * otherwise Offset[560h] = 0x00.
1477 * */
1478 bool support_aspm;
1479 bool support_backdoor;
1480
1481 /*for LPS */
1482 enum rt_psmode dot11_psmode; /*Power save mode configured. */
1483 bool swctrl_lps;
1484 bool leisure_ps;
1485 bool fwctrl_lps;
1486 u8 fwctrl_psmode;
1487 /*For Fw control LPS mode */
1488 u8 reg_fwctrl_lps;
1489 /*Record Fw PS mode status. */
1490 bool fw_current_inpsmode;
1491 u8 reg_max_lps_awakeintvl;
1492 bool report_linked;
1493 bool low_power_enable;/*for 32k*/
1494
1495 /*for IPS */
1496 bool inactiveps;
1497
1498 u32 rfoff_reason;
1499
1500 /*RF OFF Level */
1501 u32 cur_ps_level;
1502 u32 reg_rfps_level;
1503
1504 /*just for PCIE ASPM */
1505 u8 const_amdpci_aspm;
1506 bool pwrdown_mode;
1507
1508 enum rf_pwrstate inactive_pwrstate;
1509 enum rf_pwrstate rfpwr_state; /*cur power state */
1510
1511 /* for SW LPS*/
1512 bool sw_ps_enabled;
1513 bool state;
1514 bool state_inap;
1515 bool multi_buffered;
1516 u16 nullfunc_seq;
1517 unsigned int dtim_counter;
1518 unsigned int sleep_ms;
1519 unsigned long last_sleep_jiffies;
1520 unsigned long last_awake_jiffies;
1521 unsigned long last_delaylps_stamp_jiffies;
1522 unsigned long last_dtim;
1523 unsigned long last_beacon;
1524 unsigned long last_action;
1525 unsigned long last_slept;
1526
1527 /*For P2P PS */
1528 struct rtl_p2p_ps_info p2p_ps_info;
1529 u8 pwr_mode;
1530 u8 smart_ps;
1531 };
1532
1533 struct rtl_stats {
1534 u8 psaddr[ETH_ALEN];
1535 u32 mac_time[2];
1536 s8 rssi;
1537 u8 signal;
1538 u8 noise;
1539 u8 rate; /* hw desc rate */
1540 u8 received_channel;
1541 u8 control;
1542 u8 mask;
1543 u8 freq;
1544 u16 len;
1545 u64 tsf;
1546 u32 beacon_time;
1547 u8 nic_type;
1548 u16 length;
1549 u8 signalquality; /*in 0-100 index. */
1550 /*
1551 * Real power in dBm for this packet,
1552 * no beautification and aggregation.
1553 * */
1554 s32 recvsignalpower;
1555 s8 rxpower; /*in dBm Translate from PWdB */
1556 u8 signalstrength; /*in 0-100 index. */
1557 u16 hwerror:1;
1558 u16 crc:1;
1559 u16 icv:1;
1560 u16 shortpreamble:1;
1561 u16 antenna:1;
1562 u16 decrypted:1;
1563 u16 wakeup:1;
1564 u32 timestamp_low;
1565 u32 timestamp_high;
1566
1567 u8 rx_drvinfo_size;
1568 u8 rx_bufshift;
1569 bool isampdu;
1570 bool isfirst_ampdu;
1571 bool rx_is40Mhzpacket;
1572 u32 rx_pwdb_all;
1573 u8 rx_mimo_signalstrength[4]; /*in 0~100 index */
1574 s8 rx_mimo_sig_qual[2];
1575 bool packet_matchbssid;
1576 bool is_cck;
1577 bool is_ht;
1578 bool packet_toself;
1579 bool packet_beacon; /*for rssi */
1580 char cck_adc_pwdb[4]; /*for rx path selection */
1581
1582 u8 packet_report_type;
1583
1584 u32 macid;
1585 u8 wake_match;
1586 u32 bt_rx_rssi_percentage;
1587 u32 macid_valid_entry[2];
1588 };
1589
1590
1591 struct rt_link_detect {
1592 /* count for roaming */
1593 u32 bcn_rx_inperiod;
1594 u32 roam_times;
1595
1596 u32 num_tx_in4period[4];
1597 u32 num_rx_in4period[4];
1598
1599 u32 num_tx_inperiod;
1600 u32 num_rx_inperiod;
1601
1602 bool busytraffic;
1603 bool tx_busy_traffic;
1604 bool rx_busy_traffic;
1605 bool higher_busytraffic;
1606 bool higher_busyrxtraffic;
1607
1608 u32 tidtx_in4period[MAX_TID_COUNT][4];
1609 u32 tidtx_inperiod[MAX_TID_COUNT];
1610 bool higher_busytxtraffic[MAX_TID_COUNT];
1611 };
1612
1613 struct rtl_tcb_desc {
1614 u8 packet_bw:1;
1615 u8 multicast:1;
1616 u8 broadcast:1;
1617
1618 u8 rts_stbc:1;
1619 u8 rts_enable:1;
1620 u8 cts_enable:1;
1621 u8 rts_use_shortpreamble:1;
1622 u8 rts_use_shortgi:1;
1623 u8 rts_sc:1;
1624 u8 rts_bw:1;
1625 u8 rts_rate;
1626
1627 u8 use_shortgi:1;
1628 u8 use_shortpreamble:1;
1629 u8 use_driver_rate:1;
1630 u8 disable_ratefallback:1;
1631
1632 u8 ratr_index;
1633 u8 mac_id;
1634 u8 hw_rate;
1635
1636 u8 last_inipkt:1;
1637 u8 cmd_or_init:1;
1638 u8 queue_index;
1639
1640 /* early mode */
1641 u8 empkt_num;
1642 /* The max value by HW */
1643 u32 empkt_len[10];
1644 bool btx_enable_sw_calc_duration;
1645 };
1646
1647 struct rtl_hal_ops {
1648 int (*init_sw_vars) (struct ieee80211_hw *hw);
1649 void (*deinit_sw_vars) (struct ieee80211_hw *hw);
1650 void (*read_chip_version)(struct ieee80211_hw *hw);
1651 void (*read_eeprom_info) (struct ieee80211_hw *hw);
1652 void (*interrupt_recognized) (struct ieee80211_hw *hw,
1653 u32 *p_inta, u32 *p_intb);
1654 int (*hw_init) (struct ieee80211_hw *hw);
1655 void (*hw_disable) (struct ieee80211_hw *hw);
1656 void (*hw_suspend) (struct ieee80211_hw *hw);
1657 void (*hw_resume) (struct ieee80211_hw *hw);
1658 void (*enable_interrupt) (struct ieee80211_hw *hw);
1659 void (*disable_interrupt) (struct ieee80211_hw *hw);
1660 int (*set_network_type) (struct ieee80211_hw *hw,
1661 enum nl80211_iftype type);
1662 void (*set_chk_bssid)(struct ieee80211_hw *hw,
1663 bool check_bssid);
1664 void (*set_bw_mode) (struct ieee80211_hw *hw,
1665 enum nl80211_channel_type ch_type);
1666 u8(*switch_channel) (struct ieee80211_hw *hw);
1667 void (*set_qos) (struct ieee80211_hw *hw, int aci);
1668 void (*set_bcn_reg) (struct ieee80211_hw *hw);
1669 void (*set_bcn_intv) (struct ieee80211_hw *hw);
1670 void (*update_interrupt_mask) (struct ieee80211_hw *hw,
1671 u32 add_msr, u32 rm_msr);
1672 void (*get_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1673 void (*set_hw_reg) (struct ieee80211_hw *hw, u8 variable, u8 *val);
1674 void (*update_rate_tbl) (struct ieee80211_hw *hw,
1675 struct ieee80211_sta *sta, u8 rssi_level);
1676 void (*update_rate_mask) (struct ieee80211_hw *hw, u8 rssi_level);
1677 void (*fill_tx_desc) (struct ieee80211_hw *hw,
1678 struct ieee80211_hdr *hdr, u8 *pdesc_tx,
1679 struct ieee80211_tx_info *info,
1680 struct ieee80211_sta *sta,
1681 struct sk_buff *skb, u8 hw_queue,
1682 struct rtl_tcb_desc *ptcb_desc);
1683 void (*fill_fake_txdesc) (struct ieee80211_hw *hw, u8 *pDesc,
1684 u32 buffer_len, bool bIsPsPoll);
1685 void (*fill_tx_cmddesc) (struct ieee80211_hw *hw, u8 *pdesc,
1686 bool firstseg, bool lastseg,
1687 struct sk_buff *skb);
1688 bool (*cmd_send_packet)(struct ieee80211_hw *hw, struct sk_buff *skb);
1689 bool (*query_rx_desc) (struct ieee80211_hw *hw,
1690 struct rtl_stats *stats,
1691 struct ieee80211_rx_status *rx_status,
1692 u8 *pdesc, struct sk_buff *skb);
1693 void (*set_channel_access) (struct ieee80211_hw *hw);
1694 bool (*radio_onoff_checking) (struct ieee80211_hw *hw, u8 *valid);
1695 void (*dm_watchdog) (struct ieee80211_hw *hw);
1696 void (*scan_operation_backup) (struct ieee80211_hw *hw, u8 operation);
1697 bool (*set_rf_power_state) (struct ieee80211_hw *hw,
1698 enum rf_pwrstate rfpwr_state);
1699 void (*led_control) (struct ieee80211_hw *hw,
1700 enum led_ctl_mode ledaction);
1701 void (*set_desc) (u8 *pdesc, bool istx, u8 desc_name, u8 *val);
1702 u32 (*get_desc) (u8 *pdesc, bool istx, u8 desc_name);
1703 void (*tx_polling) (struct ieee80211_hw *hw, u8 hw_queue);
1704 void (*enable_hw_sec) (struct ieee80211_hw *hw);
1705 void (*set_key) (struct ieee80211_hw *hw, u32 key_index,
1706 u8 *macaddr, bool is_group, u8 enc_algo,
1707 bool is_wepkey, bool clear_all);
1708 void (*init_sw_leds) (struct ieee80211_hw *hw);
1709 void (*deinit_sw_leds) (struct ieee80211_hw *hw);
1710 u32 (*get_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask);
1711 void (*set_bbreg) (struct ieee80211_hw *hw, u32 regaddr, u32 bitmask,
1712 u32 data);
1713 u32 (*get_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1714 u32 regaddr, u32 bitmask);
1715 void (*set_rfreg) (struct ieee80211_hw *hw, enum radio_path rfpath,
1716 u32 regaddr, u32 bitmask, u32 data);
1717 void (*allow_all_destaddr)(struct ieee80211_hw *hw,
1718 bool allow_all_da, bool write_into_reg);
1719 void (*linked_set_reg) (struct ieee80211_hw *hw);
1720 void (*chk_switch_dmdp) (struct ieee80211_hw *hw);
1721 void (*dualmac_easy_concurrent) (struct ieee80211_hw *hw);
1722 void (*dualmac_switch_to_dmdp) (struct ieee80211_hw *hw);
1723 bool (*phy_rf6052_config) (struct ieee80211_hw *hw);
1724 void (*phy_rf6052_set_cck_txpower) (struct ieee80211_hw *hw,
1725 u8 *powerlevel);
1726 void (*phy_rf6052_set_ofdm_txpower) (struct ieee80211_hw *hw,
1727 u8 *ppowerlevel, u8 channel);
1728 bool (*config_bb_with_headerfile) (struct ieee80211_hw *hw,
1729 u8 configtype);
1730 bool (*config_bb_with_pgheaderfile) (struct ieee80211_hw *hw,
1731 u8 configtype);
1732 void (*phy_lc_calibrate) (struct ieee80211_hw *hw, bool is2t);
1733 void (*phy_set_bw_mode_callback) (struct ieee80211_hw *hw);
1734 void (*dm_dynamic_txpower) (struct ieee80211_hw *hw);
1735 void (*c2h_command_handle) (struct ieee80211_hw *hw);
1736 void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
1737 bool mstate);
1738 void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
1739 void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
1740 u32 cmd_len, u8 *p_cmdbuffer);
1741 };
1742
1743 struct rtl_intf_ops {
1744 /*com */
1745 void (*read_efuse_byte)(struct ieee80211_hw *hw, u16 _offset, u8 *pbuf);
1746 int (*adapter_start) (struct ieee80211_hw *hw);
1747 void (*adapter_stop) (struct ieee80211_hw *hw);
1748 bool (*check_buddy_priv)(struct ieee80211_hw *hw,
1749 struct rtl_priv **buddy_priv);
1750
1751 int (*adapter_tx) (struct ieee80211_hw *hw,
1752 struct ieee80211_sta *sta,
1753 struct sk_buff *skb,
1754 struct rtl_tcb_desc *ptcb_desc);
1755 void (*flush)(struct ieee80211_hw *hw, bool drop);
1756 int (*reset_trx_ring) (struct ieee80211_hw *hw);
1757 bool (*waitq_insert) (struct ieee80211_hw *hw,
1758 struct ieee80211_sta *sta,
1759 struct sk_buff *skb);
1760
1761 /*pci */
1762 void (*disable_aspm) (struct ieee80211_hw *hw);
1763 void (*enable_aspm) (struct ieee80211_hw *hw);
1764
1765 /*usb */
1766 };
1767
1768 struct rtl_mod_params {
1769 /* default: 0 = using hardware encryption */
1770 bool sw_crypto;
1771
1772 /* default: 0 = DBG_EMERG (0)*/
1773 int debug;
1774
1775 /* default: 1 = using no linked power save */
1776 bool inactiveps;
1777
1778 /* default: 1 = using linked sw power save */
1779 bool swctrl_lps;
1780
1781 /* default: 1 = using linked fw power save */
1782 bool fwctrl_lps;
1783 };
1784
1785 struct rtl_hal_usbint_cfg {
1786 /* data - rx */
1787 u32 in_ep_num;
1788 u32 rx_urb_num;
1789 u32 rx_max_size;
1790
1791 /* op - rx */
1792 void (*usb_rx_hdl)(struct ieee80211_hw *, struct sk_buff *);
1793 void (*usb_rx_segregate_hdl)(struct ieee80211_hw *, struct sk_buff *,
1794 struct sk_buff_head *);
1795
1796 /* tx */
1797 void (*usb_tx_cleanup)(struct ieee80211_hw *, struct sk_buff *);
1798 int (*usb_tx_post_hdl)(struct ieee80211_hw *, struct urb *,
1799 struct sk_buff *);
1800 struct sk_buff *(*usb_tx_aggregate_hdl)(struct ieee80211_hw *,
1801 struct sk_buff_head *);
1802
1803 /* endpoint mapping */
1804 int (*usb_endpoint_mapping)(struct ieee80211_hw *hw);
1805 u16 (*usb_mq_to_hwq)(__le16 fc, u16 mac80211_queue_index);
1806 };
1807
1808 struct rtl_hal_cfg {
1809 u8 bar_id;
1810 bool write_readback;
1811 char *name;
1812 char *fw_name;
1813 char *alt_fw_name;
1814 struct rtl_hal_ops *ops;
1815 struct rtl_mod_params *mod_params;
1816 struct rtl_hal_usbint_cfg *usb_interface_cfg;
1817
1818 /*this map used for some registers or vars
1819 defined int HAL but used in MAIN */
1820 u32 maps[RTL_VAR_MAP_MAX];
1821
1822 };
1823
1824 struct rtl_locks {
1825 /* mutex */
1826 struct mutex conf_mutex;
1827 struct mutex ps_mutex;
1828
1829 /*spin lock */
1830 spinlock_t ips_lock;
1831 spinlock_t irq_th_lock;
1832 spinlock_t irq_pci_lock;
1833 spinlock_t tx_lock;
1834 spinlock_t h2c_lock;
1835 spinlock_t rf_ps_lock;
1836 spinlock_t rf_lock;
1837 spinlock_t lps_lock;
1838 spinlock_t waitq_lock;
1839 spinlock_t entry_list_lock;
1840 spinlock_t usb_lock;
1841
1842 /*FW clock change */
1843 spinlock_t fw_ps_lock;
1844
1845 /*Dual mac*/
1846 spinlock_t cck_and_rw_pagea_lock;
1847
1848 /*Easy concurrent*/
1849 spinlock_t check_sendpkt_lock;
1850 };
1851
1852 struct rtl_works {
1853 struct ieee80211_hw *hw;
1854
1855 /*timer */
1856 struct timer_list watchdog_timer;
1857 struct timer_list dualmac_easyconcurrent_retrytimer;
1858 struct timer_list fw_clockoff_timer;
1859 struct timer_list fast_antenna_training_timer;
1860 /*task */
1861 struct tasklet_struct irq_tasklet;
1862 struct tasklet_struct irq_prepare_bcn_tasklet;
1863
1864 /*work queue */
1865 struct workqueue_struct *rtl_wq;
1866 struct delayed_work watchdog_wq;
1867 struct delayed_work ips_nic_off_wq;
1868
1869 /* For SW LPS */
1870 struct delayed_work ps_work;
1871 struct delayed_work ps_rfon_wq;
1872 struct delayed_work fwevt_wq;
1873
1874 struct work_struct lps_change_work;
1875 struct work_struct fill_h2c_cmd;
1876 };
1877
1878 struct rtl_debug {
1879 u32 dbgp_type[DBGP_TYPE_MAX];
1880 int global_debuglevel;
1881 u64 global_debugcomponents;
1882
1883 /* add for proc debug */
1884 struct proc_dir_entry *proc_dir;
1885 char proc_name[20];
1886 };
1887
1888 #define MIMO_PS_STATIC 0
1889 #define MIMO_PS_DYNAMIC 1
1890 #define MIMO_PS_NOLIMIT 3
1891
1892 struct rtl_dualmac_easy_concurrent_ctl {
1893 enum band_type currentbandtype_backfordmdp;
1894 bool close_bbandrf_for_dmsp;
1895 bool change_to_dmdp;
1896 bool change_to_dmsp;
1897 bool switch_in_process;
1898 };
1899
1900 struct rtl_dmsp_ctl {
1901 bool activescan_for_slaveofdmsp;
1902 bool scan_for_anothermac_fordmsp;
1903 bool scan_for_itself_fordmsp;
1904 bool writedig_for_anothermacofdmsp;
1905 u32 curdigvalue_for_anothermacofdmsp;
1906 bool changecckpdstate_for_anothermacofdmsp;
1907 u8 curcckpdstate_for_anothermacofdmsp;
1908 bool changetxhighpowerlvl_for_anothermacofdmsp;
1909 u8 curtxhighlvl_for_anothermacofdmsp;
1910 long rssivalmin_for_anothermacofdmsp;
1911 };
1912
1913 struct ps_t {
1914 u8 pre_ccastate;
1915 u8 cur_ccasate;
1916 u8 pre_rfstate;
1917 u8 cur_rfstate;
1918 long rssi_val_min;
1919 };
1920
1921 struct dig_t {
1922 u32 rssi_lowthresh;
1923 u32 rssi_highthresh;
1924 u32 fa_lowthresh;
1925 u32 fa_highthresh;
1926 long last_min_undec_pwdb_for_dm;
1927 long rssi_highpower_lowthresh;
1928 long rssi_highpower_highthresh;
1929 u32 recover_cnt;
1930 u32 pre_igvalue;
1931 u32 cur_igvalue;
1932 long rssi_val;
1933 u8 dig_enable_flag;
1934 u8 dig_ext_port_stage;
1935 u8 dig_algorithm;
1936 u8 dig_twoport_algorithm;
1937 u8 dig_dbgmode;
1938 u8 dig_slgorithm_switch;
1939 u8 cursta_cstate;
1940 u8 presta_cstate;
1941 u8 curmultista_cstate;
1942 char back_val;
1943 char back_range_max;
1944 char back_range_min;
1945 u8 rx_gain_max;
1946 u8 rx_gain_min;
1947 u8 min_undec_pwdb_for_dm;
1948 u8 rssi_val_min;
1949 u8 pre_cck_cca_thres;
1950 u8 cur_cck_cca_thres;
1951 u8 pre_cck_pd_state;
1952 u8 cur_cck_pd_state;
1953 u8 pre_cck_fa_state;
1954 u8 cur_cck_fa_state;
1955 u8 pre_ccastate;
1956 u8 cur_ccasate;
1957 u8 large_fa_hit;
1958 u8 dig_dynamic_min;
1959 u8 forbidden_igi;
1960 u8 dig_state;
1961 u8 dig_highpwrstate;
1962 u8 cur_sta_cstate;
1963 u8 pre_sta_cstate;
1964 u8 cur_ap_cstate;
1965 u8 pre_ap_cstate;
1966 u8 cur_pd_thstate;
1967 u8 pre_pd_thstate;
1968 u8 cur_cs_ratiostate;
1969 u8 pre_cs_ratiostate;
1970 u8 backoff_enable_flag;
1971 char backoffval_range_max;
1972 char backoffval_range_min;
1973 u8 dig_min_0;
1974 u8 dig_min_1;
1975 bool media_connect_0;
1976 bool media_connect_1;
1977
1978 u32 antdiv_rssi_max;
1979 u32 rssi_max;
1980 };
1981
1982 struct rtl_global_var {
1983 /* from this list we can get
1984 * other adapter's rtl_priv */
1985 struct list_head glb_priv_list;
1986 spinlock_t glb_list_lock;
1987 };
1988
1989 struct rtl_priv {
1990 struct ieee80211_hw *hw;
1991 struct completion firmware_loading_complete;
1992 struct list_head list;
1993 struct rtl_priv *buddy_priv;
1994 struct rtl_global_var *glb_var;
1995 struct rtl_dualmac_easy_concurrent_ctl easy_concurrent_ctl;
1996 struct rtl_dmsp_ctl dmsp_ctl;
1997 struct rtl_locks locks;
1998 struct rtl_works works;
1999 struct rtl_mac mac80211;
2000 struct rtl_hal rtlhal;
2001 struct rtl_regulatory regd;
2002 struct rtl_rfkill rfkill;
2003 struct rtl_io io;
2004 struct rtl_phy phy;
2005 struct rtl_dm dm;
2006 struct rtl_security sec;
2007 struct rtl_efuse efuse;
2008
2009 struct rtl_ps_ctl psc;
2010 struct rate_adaptive ra;
2011 struct wireless_stats stats;
2012 struct rt_link_detect link_info;
2013 struct false_alarm_statistics falsealm_cnt;
2014
2015 struct rtl_rate_priv *rate_priv;
2016
2017 /* sta entry list for ap adhoc or mesh */
2018 struct list_head entry_list;
2019
2020 struct rtl_debug dbg;
2021 int max_fw_size;
2022
2023 /*
2024 *hal_cfg : for diff cards
2025 *intf_ops : for diff interrface usb/pcie
2026 */
2027 struct rtl_hal_cfg *cfg;
2028 struct rtl_intf_ops *intf_ops;
2029
2030 /*this var will be set by set_bit,
2031 and was used to indicate status of
2032 interface or hardware */
2033 unsigned long status;
2034
2035 /* tables for dm */
2036 struct dig_t dm_digtable;
2037 struct ps_t dm_pstable;
2038
2039 u32 reg_874;
2040 u32 reg_c70;
2041 u32 reg_85c;
2042 u32 reg_a74;
2043 bool reg_init; /* true if regs saved */
2044 bool bt_operation_on;
2045 __le32 *usb_data;
2046 int usb_data_index;
2047 bool initialized;
2048 bool enter_ps; /* true when entering PS */
2049 u8 rate_mask[5];
2050
2051 /*This must be the last item so
2052 that it points to the data allocated
2053 beyond this structure like:
2054 rtl_pci_priv or rtl_usb_priv */
2055 u8 priv[0] __aligned(sizeof(void *));
2056 };
2057
2058 #define rtl_priv(hw) (((struct rtl_priv *)(hw)->priv))
2059 #define rtl_mac(rtlpriv) (&((rtlpriv)->mac80211))
2060 #define rtl_hal(rtlpriv) (&((rtlpriv)->rtlhal))
2061 #define rtl_efuse(rtlpriv) (&((rtlpriv)->efuse))
2062 #define rtl_psc(rtlpriv) (&((rtlpriv)->psc))
2063
2064
2065 /***************************************
2066 Bluetooth Co-existence Related
2067 ****************************************/
2068
2069 enum bt_ant_num {
2070 ANT_X2 = 0,
2071 ANT_X1 = 1,
2072 };
2073
2074 enum bt_co_type {
2075 BT_2WIRE = 0,
2076 BT_ISSC_3WIRE = 1,
2077 BT_ACCEL = 2,
2078 BT_CSR_BC4 = 3,
2079 BT_CSR_BC8 = 4,
2080 BT_RTL8756 = 5,
2081 BT_RTL8723A = 6,
2082 };
2083
2084 enum bt_cur_state {
2085 BT_OFF = 0,
2086 BT_ON = 1,
2087 };
2088
2089 enum bt_service_type {
2090 BT_SCO = 0,
2091 BT_A2DP = 1,
2092 BT_HID = 2,
2093 BT_HID_IDLE = 3,
2094 BT_SCAN = 4,
2095 BT_IDLE = 5,
2096 BT_OTHER_ACTION = 6,
2097 BT_BUSY = 7,
2098 BT_OTHERBUSY = 8,
2099 BT_PAN = 9,
2100 };
2101
2102 enum bt_radio_shared {
2103 BT_RADIO_SHARED = 0,
2104 BT_RADIO_INDIVIDUAL = 1,
2105 };
2106
2107 struct bt_coexist_info {
2108
2109 /* EEPROM BT info. */
2110 u8 eeprom_bt_coexist;
2111 u8 eeprom_bt_type;
2112 u8 eeprom_bt_ant_num;
2113 u8 eeprom_bt_ant_isol;
2114 u8 eeprom_bt_radio_shared;
2115
2116 u8 bt_coexistence;
2117 u8 bt_ant_num;
2118 u8 bt_coexist_type;
2119 u8 bt_state;
2120 u8 bt_cur_state; /* 0:on, 1:off */
2121 u8 bt_ant_isolation; /* 0:good, 1:bad */
2122 u8 bt_pape_ctrl; /* 0:SW, 1:SW/HW dynamic */
2123 u8 bt_service;
2124 u8 bt_radio_shared_type;
2125 u8 bt_rfreg_origin_1e;
2126 u8 bt_rfreg_origin_1f;
2127 u8 bt_rssi_state;
2128 u32 ratio_tx;
2129 u32 ratio_pri;
2130 u32 bt_edca_ul;
2131 u32 bt_edca_dl;
2132
2133 bool init_set;
2134 bool bt_busy_traffic;
2135 bool bt_traffic_mode_set;
2136 bool bt_non_traffic_mode_set;
2137
2138 bool fw_coexist_all_off;
2139 bool sw_coexist_all_off;
2140 bool hw_coexist_all_off;
2141 u32 cstate;
2142 u32 previous_state;
2143 u32 cstate_h;
2144 u32 previous_state_h;
2145
2146 u8 bt_pre_rssi_state;
2147 u8 bt_pre_rssi_state1;
2148
2149 u8 reg_bt_iso;
2150 u8 reg_bt_sco;
2151 bool balance_on;
2152 u8 bt_active_zero_cnt;
2153 bool cur_bt_disabled;
2154 bool pre_bt_disabled;
2155
2156 u8 bt_profile_case;
2157 u8 bt_profile_action;
2158 bool bt_busy;
2159 bool hold_for_bt_operation;
2160 u8 lps_counter;
2161 };
2162
2163
2164 /****************************************
2165 mem access macro define start
2166 Call endian free function when
2167 1. Read/write packet content.
2168 2. Before write integer to IO.
2169 3. After read integer from IO.
2170 ****************************************/
2171 /* Convert little data endian to host ordering */
2172 #define EF1BYTE(_val) \
2173 ((u8)(_val))
2174 #define EF2BYTE(_val) \
2175 (le16_to_cpu(_val))
2176 #define EF4BYTE(_val) \
2177 (le32_to_cpu(_val))
2178
2179 /* Read data from memory */
2180 #define READEF1BYTE(_ptr) \
2181 EF1BYTE(*((u8 *)(_ptr)))
2182 /* Read le16 data from memory and convert to host ordering */
2183 #define READEF2BYTE(_ptr) \
2184 EF2BYTE(*(_ptr))
2185 #define READEF4BYTE(_ptr) \
2186 EF4BYTE(*(_ptr))
2187
2188 /* Write data to memory */
2189 #define WRITEEF1BYTE(_ptr, _val) \
2190 (*((u8 *)(_ptr))) = EF1BYTE(_val)
2191 /* Write le16 data to memory in host ordering */
2192 #define WRITEEF2BYTE(_ptr, _val) \
2193 (*((u16 *)(_ptr))) = EF2BYTE(_val)
2194 #define WRITEEF4BYTE(_ptr, _val) \
2195 (*((u32 *)(_ptr))) = EF2BYTE(_val)
2196
2197 /* Create a bit mask
2198 * Examples:
2199 * BIT_LEN_MASK_32(0) => 0x00000000
2200 * BIT_LEN_MASK_32(1) => 0x00000001
2201 * BIT_LEN_MASK_32(2) => 0x00000003
2202 * BIT_LEN_MASK_32(32) => 0xFFFFFFFF
2203 */
2204 #define BIT_LEN_MASK_32(__bitlen) \
2205 (0xFFFFFFFF >> (32 - (__bitlen)))
2206 #define BIT_LEN_MASK_16(__bitlen) \
2207 (0xFFFF >> (16 - (__bitlen)))
2208 #define BIT_LEN_MASK_8(__bitlen) \
2209 (0xFF >> (8 - (__bitlen)))
2210
2211 /* Create an offset bit mask
2212 * Examples:
2213 * BIT_OFFSET_LEN_MASK_32(0, 2) => 0x00000003
2214 * BIT_OFFSET_LEN_MASK_32(16, 2) => 0x00030000
2215 */
2216 #define BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen) \
2217 (BIT_LEN_MASK_32(__bitlen) << (__bitoffset))
2218 #define BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen) \
2219 (BIT_LEN_MASK_16(__bitlen) << (__bitoffset))
2220 #define BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen) \
2221 (BIT_LEN_MASK_8(__bitlen) << (__bitoffset))
2222
2223 /*Description:
2224 * Return 4-byte value in host byte ordering from
2225 * 4-byte pointer in little-endian system.
2226 */
2227 #define LE_P4BYTE_TO_HOST_4BYTE(__pstart) \
2228 (EF4BYTE(*((__le32 *)(__pstart))))
2229 #define LE_P2BYTE_TO_HOST_2BYTE(__pstart) \
2230 (EF2BYTE(*((__le16 *)(__pstart))))
2231 #define LE_P1BYTE_TO_HOST_1BYTE(__pstart) \
2232 (EF1BYTE(*((u8 *)(__pstart))))
2233
2234 /*Description:
2235 Translate subfield (continuous bits in little-endian) of 4-byte
2236 value to host byte ordering.*/
2237 #define LE_BITS_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2238 ( \
2239 (LE_P4BYTE_TO_HOST_4BYTE(__pstart) >> (__bitoffset)) & \
2240 BIT_LEN_MASK_32(__bitlen) \
2241 )
2242 #define LE_BITS_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2243 ( \
2244 (LE_P2BYTE_TO_HOST_2BYTE(__pstart) >> (__bitoffset)) & \
2245 BIT_LEN_MASK_16(__bitlen) \
2246 )
2247 #define LE_BITS_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2248 ( \
2249 (LE_P1BYTE_TO_HOST_1BYTE(__pstart) >> (__bitoffset)) & \
2250 BIT_LEN_MASK_8(__bitlen) \
2251 )
2252
2253 /* Description:
2254 * Mask subfield (continuous bits in little-endian) of 4-byte value
2255 * and return the result in 4-byte value in host byte ordering.
2256 */
2257 #define LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) \
2258 ( \
2259 LE_P4BYTE_TO_HOST_4BYTE(__pstart) & \
2260 (~BIT_OFFSET_LEN_MASK_32(__bitoffset, __bitlen)) \
2261 )
2262 #define LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) \
2263 ( \
2264 LE_P2BYTE_TO_HOST_2BYTE(__pstart) & \
2265 (~BIT_OFFSET_LEN_MASK_16(__bitoffset, __bitlen)) \
2266 )
2267 #define LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) \
2268 ( \
2269 LE_P1BYTE_TO_HOST_1BYTE(__pstart) & \
2270 (~BIT_OFFSET_LEN_MASK_8(__bitoffset, __bitlen)) \
2271 )
2272
2273 /* Description:
2274 * Set subfield of little-endian 4-byte value to specified value.
2275 */
2276 #define SET_BITS_TO_LE_4BYTE(__pstart, __bitoffset, __bitlen, __val) \
2277 *((u32 *)(__pstart)) = \
2278 ( \
2279 LE_BITS_CLEARED_TO_4BYTE(__pstart, __bitoffset, __bitlen) | \
2280 ((((u32)__val) & BIT_LEN_MASK_32(__bitlen)) << (__bitoffset)) \
2281 );
2282 #define SET_BITS_TO_LE_2BYTE(__pstart, __bitoffset, __bitlen, __val) \
2283 *((u16 *)(__pstart)) = \
2284 ( \
2285 LE_BITS_CLEARED_TO_2BYTE(__pstart, __bitoffset, __bitlen) | \
2286 ((((u16)__val) & BIT_LEN_MASK_16(__bitlen)) << (__bitoffset)) \
2287 );
2288 #define SET_BITS_TO_LE_1BYTE(__pstart, __bitoffset, __bitlen, __val) \
2289 *((u8 *)(__pstart)) = EF1BYTE \
2290 ( \
2291 LE_BITS_CLEARED_TO_1BYTE(__pstart, __bitoffset, __bitlen) | \
2292 ((((u8)__val) & BIT_LEN_MASK_8(__bitlen)) << (__bitoffset)) \
2293 );
2294
2295 #define N_BYTE_ALIGMENT(__value, __aligment) ((__aligment == 1) ? \
2296 (__value) : (((__value + __aligment - 1) / __aligment) * __aligment))
2297
2298 /****************************************
2299 mem access macro define end
2300 ****************************************/
2301
2302 #define byte(x, n) ((x >> (8 * n)) & 0xff)
2303
2304 #define packet_get_type(_packet) (EF1BYTE((_packet).octet[0]) & 0xFC)
2305 #define RTL_WATCH_DOG_TIME 2000
2306 #define MSECS(t) msecs_to_jiffies(t)
2307 #define WLAN_FC_GET_VERS(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_VERS)
2308 #define WLAN_FC_GET_TYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_FTYPE)
2309 #define WLAN_FC_GET_STYPE(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_STYPE)
2310 #define WLAN_FC_MORE_DATA(fc) (le16_to_cpu(fc) & IEEE80211_FCTL_MOREDATA)
2311 #define rtl_dm(rtlpriv) (&((rtlpriv)->dm))
2312
2313 #define RT_RF_OFF_LEVL_ASPM BIT(0) /*PCI ASPM */
2314 #define RT_RF_OFF_LEVL_CLK_REQ BIT(1) /*PCI clock request */
2315 #define RT_RF_OFF_LEVL_PCI_D3 BIT(2) /*PCI D3 mode */
2316 /*NIC halt, re-initialize hw parameters*/
2317 #define RT_RF_OFF_LEVL_HALT_NIC BIT(3)
2318 #define RT_RF_OFF_LEVL_FREE_FW BIT(4) /*FW free, re-download the FW */
2319 #define RT_RF_OFF_LEVL_FW_32K BIT(5) /*FW in 32k */
2320 /*Always enable ASPM and Clock Req in initialization.*/
2321 #define RT_RF_PS_LEVEL_ALWAYS_ASPM BIT(6)
2322 /* no matter RFOFF or SLEEP we set PS_ASPM_LEVL*/
2323 #define RT_PS_LEVEL_ASPM BIT(7)
2324 /*When LPS is on, disable 2R if no packet is received or transmittd.*/
2325 #define RT_RF_LPS_DISALBE_2R BIT(30)
2326 #define RT_RF_LPS_LEVEL_ASPM BIT(31) /*LPS with ASPM */
2327 #define RT_IN_PS_LEVEL(ppsc, _ps_flg) \
2328 ((ppsc->cur_ps_level & _ps_flg) ? true : false)
2329 #define RT_CLEAR_PS_LEVEL(ppsc, _ps_flg) \
2330 (ppsc->cur_ps_level &= (~(_ps_flg)))
2331 #define RT_SET_PS_LEVEL(ppsc, _ps_flg) \
2332 (ppsc->cur_ps_level |= _ps_flg)
2333
2334 #define container_of_dwork_rtl(x, y, z) \
2335 container_of(container_of(x, struct delayed_work, work), y, z)
2336
2337 #define FILL_OCTET_STRING(_os, _octet, _len) \
2338 (_os).octet = (u8 *)(_octet); \
2339 (_os).length = (_len);
2340
2341 #define CP_MACADDR(des, src) \
2342 ((des)[0] = (src)[0], (des)[1] = (src)[1],\
2343 (des)[2] = (src)[2], (des)[3] = (src)[3],\
2344 (des)[4] = (src)[4], (des)[5] = (src)[5])
2345
2346 static inline u8 rtl_read_byte(struct rtl_priv *rtlpriv, u32 addr)
2347 {
2348 return rtlpriv->io.read8_sync(rtlpriv, addr);
2349 }
2350
2351 static inline u16 rtl_read_word(struct rtl_priv *rtlpriv, u32 addr)
2352 {
2353 return rtlpriv->io.read16_sync(rtlpriv, addr);
2354 }
2355
2356 static inline u32 rtl_read_dword(struct rtl_priv *rtlpriv, u32 addr)
2357 {
2358 return rtlpriv->io.read32_sync(rtlpriv, addr);
2359 }
2360
2361 static inline void rtl_write_byte(struct rtl_priv *rtlpriv, u32 addr, u8 val8)
2362 {
2363 rtlpriv->io.write8_async(rtlpriv, addr, val8);
2364
2365 if (rtlpriv->cfg->write_readback)
2366 rtlpriv->io.read8_sync(rtlpriv, addr);
2367 }
2368
2369 static inline void rtl_write_word(struct rtl_priv *rtlpriv, u32 addr, u16 val16)
2370 {
2371 rtlpriv->io.write16_async(rtlpriv, addr, val16);
2372
2373 if (rtlpriv->cfg->write_readback)
2374 rtlpriv->io.read16_sync(rtlpriv, addr);
2375 }
2376
2377 static inline void rtl_write_dword(struct rtl_priv *rtlpriv,
2378 u32 addr, u32 val32)
2379 {
2380 rtlpriv->io.write32_async(rtlpriv, addr, val32);
2381
2382 if (rtlpriv->cfg->write_readback)
2383 rtlpriv->io.read32_sync(rtlpriv, addr);
2384 }
2385
2386 static inline u32 rtl_get_bbreg(struct ieee80211_hw *hw,
2387 u32 regaddr, u32 bitmask)
2388 {
2389 struct rtl_priv *rtlpriv = hw->priv;
2390
2391 return rtlpriv->cfg->ops->get_bbreg(hw, regaddr, bitmask);
2392 }
2393
2394 static inline void rtl_set_bbreg(struct ieee80211_hw *hw, u32 regaddr,
2395 u32 bitmask, u32 data)
2396 {
2397 struct rtl_priv *rtlpriv = hw->priv;
2398
2399 rtlpriv->cfg->ops->set_bbreg(hw, regaddr, bitmask, data);
2400 }
2401
2402 static inline u32 rtl_get_rfreg(struct ieee80211_hw *hw,
2403 enum radio_path rfpath, u32 regaddr,
2404 u32 bitmask)
2405 {
2406 struct rtl_priv *rtlpriv = hw->priv;
2407
2408 return rtlpriv->cfg->ops->get_rfreg(hw, rfpath, regaddr, bitmask);
2409 }
2410
2411 static inline void rtl_set_rfreg(struct ieee80211_hw *hw,
2412 enum radio_path rfpath, u32 regaddr,
2413 u32 bitmask, u32 data)
2414 {
2415 struct rtl_priv *rtlpriv = hw->priv;
2416
2417 rtlpriv->cfg->ops->set_rfreg(hw, rfpath, regaddr, bitmask, data);
2418 }
2419
2420 static inline bool is_hal_stop(struct rtl_hal *rtlhal)
2421 {
2422 return (_HAL_STATE_STOP == rtlhal->state);
2423 }
2424
2425 static inline void set_hal_start(struct rtl_hal *rtlhal)
2426 {
2427 rtlhal->state = _HAL_STATE_START;
2428 }
2429
2430 static inline void set_hal_stop(struct rtl_hal *rtlhal)
2431 {
2432 rtlhal->state = _HAL_STATE_STOP;
2433 }
2434
2435 static inline u8 get_rf_type(struct rtl_phy *rtlphy)
2436 {
2437 return rtlphy->rf_type;
2438 }
2439
2440 static inline struct ieee80211_hdr *rtl_get_hdr(struct sk_buff *skb)
2441 {
2442 return (struct ieee80211_hdr *)(skb->data);
2443 }
2444
2445 static inline __le16 rtl_get_fc(struct sk_buff *skb)
2446 {
2447 return rtl_get_hdr(skb)->frame_control;
2448 }
2449
2450 static inline u16 rtl_get_tid_h(struct ieee80211_hdr *hdr)
2451 {
2452 return (ieee80211_get_qos_ctl(hdr))[0] & IEEE80211_QOS_CTL_TID_MASK;
2453 }
2454
2455 static inline u16 rtl_get_tid(struct sk_buff *skb)
2456 {
2457 return rtl_get_tid_h(rtl_get_hdr(skb));
2458 }
2459
2460 static inline struct ieee80211_sta *get_sta(struct ieee80211_hw *hw,
2461 struct ieee80211_vif *vif,
2462 const u8 *bssid)
2463 {
2464 return ieee80211_find_sta(vif, bssid);
2465 }
2466
2467 static inline struct ieee80211_sta *rtl_find_sta(struct ieee80211_hw *hw,
2468 u8 *mac_addr)
2469 {
2470 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2471 return ieee80211_find_sta(mac->vif, mac_addr);
2472 }
2473
2474 #endif
Linux with added FPC-III support