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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / pci / host / pci-mvebu.c
blob13478ecd411306115b666a9e344754966ce3012b
1 /*
2 * PCIe driver for Marvell Armada 370 and Armada XP SoCs
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/module.h>
15 #include <linux/mbus.h>
16 #include <linux/msi.h>
17 #include <linux/slab.h>
18 #include <linux/platform_device.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_pci.h>
23 #include <linux/of_platform.h>
24
25 /*
26 * PCIe unit register offsets.
27 */
28 #define PCIE_DEV_ID_OFF 0x0000
29 #define PCIE_CMD_OFF 0x0004
30 #define PCIE_DEV_REV_OFF 0x0008
31 #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
32 #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
33 #define PCIE_HEADER_LOG_4_OFF 0x0128
34 #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
35 #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
36 #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
37 #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
38 #define PCIE_WIN5_CTRL_OFF 0x1880
39 #define PCIE_WIN5_BASE_OFF 0x1884
40 #define PCIE_WIN5_REMAP_OFF 0x188c
41 #define PCIE_CONF_ADDR_OFF 0x18f8
42 #define PCIE_CONF_ADDR_EN 0x80000000
43 #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
44 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
45 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
46 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
47 #define PCIE_CONF_ADDR(bus, devfn, where) \
48 (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
49 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
50 PCIE_CONF_ADDR_EN)
51 #define PCIE_CONF_DATA_OFF 0x18fc
52 #define PCIE_MASK_OFF 0x1910
53 #define PCIE_MASK_ENABLE_INTS 0x0f000000
54 #define PCIE_CTRL_OFF 0x1a00
55 #define PCIE_CTRL_X1_MODE 0x0001
56 #define PCIE_STAT_OFF 0x1a04
57 #define PCIE_STAT_BUS 0xff00
58 #define PCIE_STAT_DEV 0x1f0000
59 #define PCIE_STAT_LINK_DOWN BIT(0)
60 #define PCIE_DEBUG_CTRL 0x1a60
61 #define PCIE_DEBUG_SOFT_RESET BIT(20)
62
63 /*
64 * This product ID is registered by Marvell, and used when the Marvell
65 * SoC is not the root complex, but an endpoint on the PCIe bus. It is
66 * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
67 * bridge.
68 */
69 #define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
70
71 /* PCI configuration space of a PCI-to-PCI bridge */
72 struct mvebu_sw_pci_bridge {
73 u16 vendor;
74 u16 device;
75 u16 command;
76 u16 class;
77 u8 interface;
78 u8 revision;
79 u8 bist;
80 u8 header_type;
81 u8 latency_timer;
82 u8 cache_line_size;
83 u32 bar[2];
84 u8 primary_bus;
85 u8 secondary_bus;
86 u8 subordinate_bus;
87 u8 secondary_latency_timer;
88 u8 iobase;
89 u8 iolimit;
90 u16 secondary_status;
91 u16 membase;
92 u16 memlimit;
93 u16 iobaseupper;
94 u16 iolimitupper;
95 u8 cappointer;
96 u8 reserved1;
97 u16 reserved2;
98 u32 romaddr;
99 u8 intline;
100 u8 intpin;
101 u16 bridgectrl;
102 };
103
104 struct mvebu_pcie_port;
105
106 /* Structure representing all PCIe interfaces */
107 struct mvebu_pcie {
108 struct platform_device *pdev;
109 struct mvebu_pcie_port *ports;
110 struct msi_chip *msi;
111 struct resource io;
112 struct resource realio;
113 struct resource mem;
114 struct resource busn;
115 int nports;
116 };
117
118 /* Structure representing one PCIe interface */
119 struct mvebu_pcie_port {
120 char *name;
121 void __iomem *base;
122 spinlock_t conf_lock;
123 u32 port;
124 u32 lane;
125 int devfn;
126 unsigned int mem_target;
127 unsigned int mem_attr;
128 unsigned int io_target;
129 unsigned int io_attr;
130 struct clk *clk;
131 int reset_gpio;
132 int reset_active_low;
133 char *reset_name;
134 struct mvebu_sw_pci_bridge bridge;
135 struct device_node *dn;
136 struct mvebu_pcie *pcie;
137 phys_addr_t memwin_base;
138 size_t memwin_size;
139 phys_addr_t iowin_base;
140 size_t iowin_size;
141 };
142
143 static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
144 {
145 writel(val, port->base + reg);
146 }
147
148 static inline u32 mvebu_readl(struct mvebu_pcie_port *port, u32 reg)
149 {
150 return readl(port->base + reg);
151 }
152
153 static inline bool mvebu_has_ioport(struct mvebu_pcie_port *port)
154 {
155 return port->io_target != -1 && port->io_attr != -1;
156 }
157
158 static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
159 {
160 return !(mvebu_readl(port, PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
161 }
162
163 static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
164 {
165 u32 stat;
166
167 stat = mvebu_readl(port, PCIE_STAT_OFF);
168 stat &= ~PCIE_STAT_BUS;
169 stat |= nr << 8;
170 mvebu_writel(port, stat, PCIE_STAT_OFF);
171 }
172
173 static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
174 {
175 u32 stat;
176
177 stat = mvebu_readl(port, PCIE_STAT_OFF);
178 stat &= ~PCIE_STAT_DEV;
179 stat |= nr << 16;
180 mvebu_writel(port, stat, PCIE_STAT_OFF);
181 }
182
183 /*
184 * Setup PCIE BARs and Address Decode Wins:
185 * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
186 * WIN[0-3] -> DRAM bank[0-3]
187 */
188 static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
189 {
190 const struct mbus_dram_target_info *dram;
191 u32 size;
192 int i;
193
194 dram = mv_mbus_dram_info();
195
196 /* First, disable and clear BARs and windows. */
197 for (i = 1; i < 3; i++) {
198 mvebu_writel(port, 0, PCIE_BAR_CTRL_OFF(i));
199 mvebu_writel(port, 0, PCIE_BAR_LO_OFF(i));
200 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(i));
201 }
202
203 for (i = 0; i < 5; i++) {
204 mvebu_writel(port, 0, PCIE_WIN04_CTRL_OFF(i));
205 mvebu_writel(port, 0, PCIE_WIN04_BASE_OFF(i));
206 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
207 }
208
209 mvebu_writel(port, 0, PCIE_WIN5_CTRL_OFF);
210 mvebu_writel(port, 0, PCIE_WIN5_BASE_OFF);
211 mvebu_writel(port, 0, PCIE_WIN5_REMAP_OFF);
212
213 /* Setup windows for DDR banks. Count total DDR size on the fly. */
214 size = 0;
215 for (i = 0; i < dram->num_cs; i++) {
216 const struct mbus_dram_window *cs = dram->cs + i;
217
218 mvebu_writel(port, cs->base & 0xffff0000,
219 PCIE_WIN04_BASE_OFF(i));
220 mvebu_writel(port, 0, PCIE_WIN04_REMAP_OFF(i));
221 mvebu_writel(port,
222 ((cs->size - 1) & 0xffff0000) |
223 (cs->mbus_attr << 8) |
224 (dram->mbus_dram_target_id << 4) | 1,
225 PCIE_WIN04_CTRL_OFF(i));
226
227 size += cs->size;
228 }
229
230 /* Round up 'size' to the nearest power of two. */
231 if ((size & (size - 1)) != 0)
232 size = 1 << fls(size);
233
234 /* Setup BAR[1] to all DRAM banks. */
235 mvebu_writel(port, dram->cs[0].base, PCIE_BAR_LO_OFF(1));
236 mvebu_writel(port, 0, PCIE_BAR_HI_OFF(1));
237 mvebu_writel(port, ((size - 1) & 0xffff0000) | 1,
238 PCIE_BAR_CTRL_OFF(1));
239 }
240
241 static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
242 {
243 u32 cmd, mask;
244
245 /* Point PCIe unit MBUS decode windows to DRAM space. */
246 mvebu_pcie_setup_wins(port);
247
248 /* Master + slave enable. */
249 cmd = mvebu_readl(port, PCIE_CMD_OFF);
250 cmd |= PCI_COMMAND_IO;
251 cmd |= PCI_COMMAND_MEMORY;
252 cmd |= PCI_COMMAND_MASTER;
253 mvebu_writel(port, cmd, PCIE_CMD_OFF);
254
255 /* Enable interrupt lines A-D. */
256 mask = mvebu_readl(port, PCIE_MASK_OFF);
257 mask |= PCIE_MASK_ENABLE_INTS;
258 mvebu_writel(port, mask, PCIE_MASK_OFF);
259 }
260
261 static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
262 struct pci_bus *bus,
263 u32 devfn, int where, int size, u32 *val)
264 {
265 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
266 PCIE_CONF_ADDR_OFF);
267
268 *val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
269
270 if (size == 1)
271 *val = (*val >> (8 * (where & 3))) & 0xff;
272 else if (size == 2)
273 *val = (*val >> (8 * (where & 3))) & 0xffff;
274
275 return PCIBIOS_SUCCESSFUL;
276 }
277
278 static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
279 struct pci_bus *bus,
280 u32 devfn, int where, int size, u32 val)
281 {
282 u32 _val, shift = 8 * (where & 3);
283
284 mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
285 PCIE_CONF_ADDR_OFF);
286 _val = mvebu_readl(port, PCIE_CONF_DATA_OFF);
287
288 if (size == 4)
289 _val = val;
290 else if (size == 2)
291 _val = (_val & ~(0xffff << shift)) | ((val & 0xffff) << shift);
292 else if (size == 1)
293 _val = (_val & ~(0xff << shift)) | ((val & 0xff) << shift);
294 else
295 return PCIBIOS_BAD_REGISTER_NUMBER;
296
297 mvebu_writel(port, _val, PCIE_CONF_DATA_OFF);
298
299 return PCIBIOS_SUCCESSFUL;
300 }
301
302 static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
303 {
304 phys_addr_t iobase;
305
306 /* Are the new iobase/iolimit values invalid? */
307 if (port->bridge.iolimit < port->bridge.iobase ||
308 port->bridge.iolimitupper < port->bridge.iobaseupper ||
309 !(port->bridge.command & PCI_COMMAND_IO)) {
310
311 /* If a window was configured, remove it */
312 if (port->iowin_base) {
313 mvebu_mbus_del_window(port->iowin_base,
314 port->iowin_size);
315 port->iowin_base = 0;
316 port->iowin_size = 0;
317 }
318
319 return;
320 }
321
322 if (!mvebu_has_ioport(port)) {
323 dev_WARN(&port->pcie->pdev->dev,
324 "Attempt to set IO when IO is disabled\n");
325 return;
326 }
327
328 /*
329 * We read the PCI-to-PCI bridge emulated registers, and
330 * calculate the base address and size of the address decoding
331 * window to setup, according to the PCI-to-PCI bridge
332 * specifications. iobase is the bus address, port->iowin_base
333 * is the CPU address.
334 */
335 iobase = ((port->bridge.iobase & 0xF0) << 8) |
336 (port->bridge.iobaseupper << 16);
337 port->iowin_base = port->pcie->io.start + iobase;
338 port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
339 (port->bridge.iolimitupper << 16)) -
340 iobase);
341
342 mvebu_mbus_add_window_remap_by_id(port->io_target, port->io_attr,
343 port->iowin_base, port->iowin_size,
344 iobase);
345 }
346
347 static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
348 {
349 /* Are the new membase/memlimit values invalid? */
350 if (port->bridge.memlimit < port->bridge.membase ||
351 !(port->bridge.command & PCI_COMMAND_MEMORY)) {
352
353 /* If a window was configured, remove it */
354 if (port->memwin_base) {
355 mvebu_mbus_del_window(port->memwin_base,
356 port->memwin_size);
357 port->memwin_base = 0;
358 port->memwin_size = 0;
359 }
360
361 return;
362 }
363
364 /*
365 * We read the PCI-to-PCI bridge emulated registers, and
366 * calculate the base address and size of the address decoding
367 * window to setup, according to the PCI-to-PCI bridge
368 * specifications.
369 */
370 port->memwin_base = ((port->bridge.membase & 0xFFF0) << 16);
371 port->memwin_size =
372 (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
373 port->memwin_base;
374
375 mvebu_mbus_add_window_by_id(port->mem_target, port->mem_attr,
376 port->memwin_base, port->memwin_size);
377 }
378
379 /*
380 * Initialize the configuration space of the PCI-to-PCI bridge
381 * associated with the given PCIe interface.
382 */
383 static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
384 {
385 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
386
387 memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
388
389 bridge->class = PCI_CLASS_BRIDGE_PCI;
390 bridge->vendor = PCI_VENDOR_ID_MARVELL;
391 bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
392 bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
393 bridge->cache_line_size = 0x10;
394
395 /* We support 32 bits I/O addressing */
396 bridge->iobase = PCI_IO_RANGE_TYPE_32;
397 bridge->iolimit = PCI_IO_RANGE_TYPE_32;
398 }
399
400 /*
401 * Read the configuration space of the PCI-to-PCI bridge associated to
402 * the given PCIe interface.
403 */
404 static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
405 unsigned int where, int size, u32 *value)
406 {
407 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
408
409 switch (where & ~3) {
410 case PCI_VENDOR_ID:
411 *value = bridge->device << 16 | bridge->vendor;
412 break;
413
414 case PCI_COMMAND:
415 *value = bridge->command;
416 break;
417
418 case PCI_CLASS_REVISION:
419 *value = bridge->class << 16 | bridge->interface << 8 |
420 bridge->revision;
421 break;
422
423 case PCI_CACHE_LINE_SIZE:
424 *value = bridge->bist << 24 | bridge->header_type << 16 |
425 bridge->latency_timer << 8 | bridge->cache_line_size;
426 break;
427
428 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
429 *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
430 break;
431
432 case PCI_PRIMARY_BUS:
433 *value = (bridge->secondary_latency_timer << 24 |
434 bridge->subordinate_bus << 16 |
435 bridge->secondary_bus << 8 |
436 bridge->primary_bus);
437 break;
438
439 case PCI_IO_BASE:
440 if (!mvebu_has_ioport(port))
441 *value = bridge->secondary_status << 16;
442 else
443 *value = (bridge->secondary_status << 16 |
444 bridge->iolimit << 8 |
445 bridge->iobase);
446 break;
447
448 case PCI_MEMORY_BASE:
449 *value = (bridge->memlimit << 16 | bridge->membase);
450 break;
451
452 case PCI_PREF_MEMORY_BASE:
453 *value = 0;
454 break;
455
456 case PCI_IO_BASE_UPPER16:
457 *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
458 break;
459
460 case PCI_ROM_ADDRESS1:
461 *value = 0;
462 break;
463
464 case PCI_INTERRUPT_LINE:
465 /* LINE PIN MIN_GNT MAX_LAT */
466 *value = 0;
467 break;
468
469 default:
470 *value = 0xffffffff;
471 return PCIBIOS_BAD_REGISTER_NUMBER;
472 }
473
474 if (size == 2)
475 *value = (*value >> (8 * (where & 3))) & 0xffff;
476 else if (size == 1)
477 *value = (*value >> (8 * (where & 3))) & 0xff;
478
479 return PCIBIOS_SUCCESSFUL;
480 }
481
482 /* Write to the PCI-to-PCI bridge configuration space */
483 static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
484 unsigned int where, int size, u32 value)
485 {
486 struct mvebu_sw_pci_bridge *bridge = &port->bridge;
487 u32 mask, reg;
488 int err;
489
490 if (size == 4)
491 mask = 0x0;
492 else if (size == 2)
493 mask = ~(0xffff << ((where & 3) * 8));
494 else if (size == 1)
495 mask = ~(0xff << ((where & 3) * 8));
496 else
497 return PCIBIOS_BAD_REGISTER_NUMBER;
498
499 err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
500 if (err)
501 return err;
502
503 value = (reg & mask) | value << ((where & 3) * 8);
504
505 switch (where & ~3) {
506 case PCI_COMMAND:
507 {
508 u32 old = bridge->command;
509
510 if (!mvebu_has_ioport(port))
511 value &= ~PCI_COMMAND_IO;
512
513 bridge->command = value & 0xffff;
514 if ((old ^ bridge->command) & PCI_COMMAND_IO)
515 mvebu_pcie_handle_iobase_change(port);
516 if ((old ^ bridge->command) & PCI_COMMAND_MEMORY)
517 mvebu_pcie_handle_membase_change(port);
518 break;
519 }
520
521 case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
522 bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
523 break;
524
525 case PCI_IO_BASE:
526 /*
527 * We also keep bit 1 set, it is a read-only bit that
528 * indicates we support 32 bits addressing for the
529 * I/O
530 */
531 bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
532 bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
533 mvebu_pcie_handle_iobase_change(port);
534 break;
535
536 case PCI_MEMORY_BASE:
537 bridge->membase = value & 0xffff;
538 bridge->memlimit = value >> 16;
539 mvebu_pcie_handle_membase_change(port);
540 break;
541
542 case PCI_IO_BASE_UPPER16:
543 bridge->iobaseupper = value & 0xffff;
544 bridge->iolimitupper = value >> 16;
545 mvebu_pcie_handle_iobase_change(port);
546 break;
547
548 case PCI_PRIMARY_BUS:
549 bridge->primary_bus = value & 0xff;
550 bridge->secondary_bus = (value >> 8) & 0xff;
551 bridge->subordinate_bus = (value >> 16) & 0xff;
552 bridge->secondary_latency_timer = (value >> 24) & 0xff;
553 mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
554 break;
555
556 default:
557 break;
558 }
559
560 return PCIBIOS_SUCCESSFUL;
561 }
562
563 static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
564 {
565 return sys->private_data;
566 }
567
568 static struct mvebu_pcie_port *
569 mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
570 int devfn)
571 {
572 int i;
573
574 for (i = 0; i < pcie->nports; i++) {
575 struct mvebu_pcie_port *port = &pcie->ports[i];
576 if (bus->number == 0 && port->devfn == devfn)
577 return port;
578 if (bus->number != 0 &&
579 bus->number >= port->bridge.secondary_bus &&
580 bus->number <= port->bridge.subordinate_bus)
581 return port;
582 }
583
584 return NULL;
585 }
586
587 /* PCI configuration space write function */
588 static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
589 int where, int size, u32 val)
590 {
591 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
592 struct mvebu_pcie_port *port;
593 unsigned long flags;
594 int ret;
595
596 port = mvebu_pcie_find_port(pcie, bus, devfn);
597 if (!port)
598 return PCIBIOS_DEVICE_NOT_FOUND;
599
600 /* Access the emulated PCI-to-PCI bridge */
601 if (bus->number == 0)
602 return mvebu_sw_pci_bridge_write(port, where, size, val);
603
604 if (!mvebu_pcie_link_up(port))
605 return PCIBIOS_DEVICE_NOT_FOUND;
606
607 /*
608 * On the secondary bus, we don't want to expose any other
609 * device than the device physically connected in the PCIe
610 * slot, visible in slot 0. In slot 1, there's a special
611 * Marvell device that only makes sense when the Armada is
612 * used as a PCIe endpoint.
613 */
614 if (bus->number == port->bridge.secondary_bus &&
615 PCI_SLOT(devfn) != 0)
616 return PCIBIOS_DEVICE_NOT_FOUND;
617
618 /* Access the real PCIe interface */
619 spin_lock_irqsave(&port->conf_lock, flags);
620 ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
621 where, size, val);
622 spin_unlock_irqrestore(&port->conf_lock, flags);
623
624 return ret;
625 }
626
627 /* PCI configuration space read function */
628 static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
629 int size, u32 *val)
630 {
631 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
632 struct mvebu_pcie_port *port;
633 unsigned long flags;
634 int ret;
635
636 port = mvebu_pcie_find_port(pcie, bus, devfn);
637 if (!port) {
638 *val = 0xffffffff;
639 return PCIBIOS_DEVICE_NOT_FOUND;
640 }
641
642 /* Access the emulated PCI-to-PCI bridge */
643 if (bus->number == 0)
644 return mvebu_sw_pci_bridge_read(port, where, size, val);
645
646 if (!mvebu_pcie_link_up(port)) {
647 *val = 0xffffffff;
648 return PCIBIOS_DEVICE_NOT_FOUND;
649 }
650
651 /*
652 * On the secondary bus, we don't want to expose any other
653 * device than the device physically connected in the PCIe
654 * slot, visible in slot 0. In slot 1, there's a special
655 * Marvell device that only makes sense when the Armada is
656 * used as a PCIe endpoint.
657 */
658 if (bus->number == port->bridge.secondary_bus &&
659 PCI_SLOT(devfn) != 0) {
660 *val = 0xffffffff;
661 return PCIBIOS_DEVICE_NOT_FOUND;
662 }
663
664 /* Access the real PCIe interface */
665 spin_lock_irqsave(&port->conf_lock, flags);
666 ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
667 where, size, val);
668 spin_unlock_irqrestore(&port->conf_lock, flags);
669
670 return ret;
671 }
672
673 static struct pci_ops mvebu_pcie_ops = {
674 .read = mvebu_pcie_rd_conf,
675 .write = mvebu_pcie_wr_conf,
676 };
677
678 static int mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
679 {
680 struct mvebu_pcie *pcie = sys_to_pcie(sys);
681 int i;
682
683 if (resource_size(&pcie->realio) != 0)
684 pci_add_resource_offset(&sys->resources, &pcie->realio,
685 sys->io_offset);
686 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
687 pci_add_resource(&sys->resources, &pcie->busn);
688
689 for (i = 0; i < pcie->nports; i++) {
690 struct mvebu_pcie_port *port = &pcie->ports[i];
691 if (!port->base)
692 continue;
693 mvebu_pcie_setup_hw(port);
694 }
695
696 return 1;
697 }
698
699 static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
700 {
701 struct mvebu_pcie *pcie = sys_to_pcie(sys);
702 struct pci_bus *bus;
703
704 bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
705 &mvebu_pcie_ops, sys, &sys->resources);
706 if (!bus)
707 return NULL;
708
709 pci_scan_child_bus(bus);
710
711 return bus;
712 }
713
714 static void mvebu_pcie_add_bus(struct pci_bus *bus)
715 {
716 struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
717 bus->msi = pcie->msi;
718 }
719
720 static resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
721 const struct resource *res,
722 resource_size_t start,
723 resource_size_t size,
724 resource_size_t align)
725 {
726 if (dev->bus->number != 0)
727 return start;
728
729 /*
730 * On the PCI-to-PCI bridge side, the I/O windows must have at
731 * least a 64 KB size and be aligned on their size, and the
732 * memory windows must have at least a 1 MB size and be
733 * aligned on their size
734 */
735 if (res->flags & IORESOURCE_IO)
736 return round_up(start, max_t(resource_size_t, SZ_64K, size));
737 else if (res->flags & IORESOURCE_MEM)
738 return round_up(start, max_t(resource_size_t, SZ_1M, size));
739 else
740 return start;
741 }
742
743 static void mvebu_pcie_enable(struct mvebu_pcie *pcie)
744 {
745 struct hw_pci hw;
746
747 memset(&hw, 0, sizeof(hw));
748
749 hw.nr_controllers = 1;
750 hw.private_data = (void **)&pcie;
751 hw.setup = mvebu_pcie_setup;
752 hw.scan = mvebu_pcie_scan_bus;
753 hw.map_irq = of_irq_parse_and_map_pci;
754 hw.ops = &mvebu_pcie_ops;
755 hw.align_resource = mvebu_pcie_align_resource;
756 hw.add_bus = mvebu_pcie_add_bus;
757
758 pci_common_init(&hw);
759 }
760
761 /*
762 * Looks up the list of register addresses encoded into the reg =
763 * <...> property for one that matches the given port/lane. Once
764 * found, maps it.
765 */
766 static void __iomem *mvebu_pcie_map_registers(struct platform_device *pdev,
767 struct device_node *np, struct mvebu_pcie_port *port)
768 {
769 struct resource regs;
770 int ret = 0;
771
772 ret = of_address_to_resource(np, 0, &regs);
773 if (ret)
774 return ERR_PTR(ret);
775
776 return devm_ioremap_resource(&pdev->dev, &regs);
777 }
778
779 #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
780 #define DT_TYPE_IO 0x1
781 #define DT_TYPE_MEM32 0x2
782 #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
783 #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
784
785 static int mvebu_get_tgt_attr(struct device_node *np, int devfn,
786 unsigned long type,
787 unsigned int *tgt,
788 unsigned int *attr)
789 {
790 const int na = 3, ns = 2;
791 const __be32 *range;
792 int rlen, nranges, rangesz, pna, i;
793
794 *tgt = -1;
795 *attr = -1;
796
797 range = of_get_property(np, "ranges", &rlen);
798 if (!range)
799 return -EINVAL;
800
801 pna = of_n_addr_cells(np);
802 rangesz = pna + na + ns;
803 nranges = rlen / sizeof(__be32) / rangesz;
804
805 for (i = 0; i < nranges; i++) {
806 u32 flags = of_read_number(range, 1);
807 u32 slot = of_read_number(range, 2);
808 u64 cpuaddr = of_read_number(range + na, pna);
809 unsigned long rtype;
810
811 if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
812 rtype = IORESOURCE_IO;
813 else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
814 rtype = IORESOURCE_MEM;
815
816 if (slot == PCI_SLOT(devfn) && type == rtype) {
817 *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
818 *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
819 return 0;
820 }
821
822 range += rangesz;
823 }
824
825 return -ENOENT;
826 }
827
828 static void mvebu_pcie_msi_enable(struct mvebu_pcie *pcie)
829 {
830 struct device_node *msi_node;
831
832 msi_node = of_parse_phandle(pcie->pdev->dev.of_node,
833 "msi-parent", 0);
834 if (!msi_node)
835 return;
836
837 pcie->msi = of_pci_find_msi_chip_by_node(msi_node);
838
839 if (pcie->msi)
840 pcie->msi->dev = &pcie->pdev->dev;
841 }
842
843 static int mvebu_pcie_probe(struct platform_device *pdev)
844 {
845 struct mvebu_pcie *pcie;
846 struct device_node *np = pdev->dev.of_node;
847 struct device_node *child;
848 int i, ret;
849
850 pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
851 GFP_KERNEL);
852 if (!pcie)
853 return -ENOMEM;
854
855 pcie->pdev = pdev;
856 platform_set_drvdata(pdev, pcie);
857
858 /* Get the PCIe memory and I/O aperture */
859 mvebu_mbus_get_pcie_mem_aperture(&pcie->mem);
860 if (resource_size(&pcie->mem) == 0) {
861 dev_err(&pdev->dev, "invalid memory aperture size\n");
862 return -EINVAL;
863 }
864
865 mvebu_mbus_get_pcie_io_aperture(&pcie->io);
866
867 if (resource_size(&pcie->io) != 0) {
868 pcie->realio.flags = pcie->io.flags;
869 pcie->realio.start = PCIBIOS_MIN_IO;
870 pcie->realio.end = min_t(resource_size_t,
871 IO_SPACE_LIMIT,
872 resource_size(&pcie->io));
873 } else
874 pcie->realio = pcie->io;
875
876 /* Get the bus range */
877 ret = of_pci_parse_bus_range(np, &pcie->busn);
878 if (ret) {
879 dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
880 ret);
881 return ret;
882 }
883
884 i = 0;
885 for_each_child_of_node(pdev->dev.of_node, child) {
886 if (!of_device_is_available(child))
887 continue;
888 i++;
889 }
890
891 pcie->ports = devm_kzalloc(&pdev->dev, i *
892 sizeof(struct mvebu_pcie_port),
893 GFP_KERNEL);
894 if (!pcie->ports)
895 return -ENOMEM;
896
897 i = 0;
898 for_each_child_of_node(pdev->dev.of_node, child) {
899 struct mvebu_pcie_port *port = &pcie->ports[i];
900 enum of_gpio_flags flags;
901
902 if (!of_device_is_available(child))
903 continue;
904
905 port->pcie = pcie;
906
907 if (of_property_read_u32(child, "marvell,pcie-port",
908 &port->port)) {
909 dev_warn(&pdev->dev,
910 "ignoring PCIe DT node, missing pcie-port property\n");
911 continue;
912 }
913
914 if (of_property_read_u32(child, "marvell,pcie-lane",
915 &port->lane))
916 port->lane = 0;
917
918 port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
919 port->port, port->lane);
920
921 port->devfn = of_pci_get_devfn(child);
922 if (port->devfn < 0)
923 continue;
924
925 ret = mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_MEM,
926 &port->mem_target, &port->mem_attr);
927 if (ret < 0) {
928 dev_err(&pdev->dev, "PCIe%d.%d: cannot get tgt/attr for mem window\n",
929 port->port, port->lane);
930 continue;
931 }
932
933 if (resource_size(&pcie->io) != 0)
934 mvebu_get_tgt_attr(np, port->devfn, IORESOURCE_IO,
935 &port->io_target, &port->io_attr);
936 else {
937 port->io_target = -1;
938 port->io_attr = -1;
939 }
940
941 port->reset_gpio = of_get_named_gpio_flags(child,
942 "reset-gpios", 0, &flags);
943 if (gpio_is_valid(port->reset_gpio)) {
944 u32 reset_udelay = 20000;
945
946 port->reset_active_low = flags & OF_GPIO_ACTIVE_LOW;
947 port->reset_name = kasprintf(GFP_KERNEL,
948 "pcie%d.%d-reset", port->port, port->lane);
949 of_property_read_u32(child, "reset-delay-us",
950 &reset_udelay);
951
952 ret = devm_gpio_request_one(&pdev->dev,
953 port->reset_gpio, GPIOF_DIR_OUT, port->reset_name);
954 if (ret) {
955 if (ret == -EPROBE_DEFER)
956 return ret;
957 continue;
958 }
959
960 gpio_set_value(port->reset_gpio,
961 (port->reset_active_low) ? 1 : 0);
962 msleep(reset_udelay/1000);
963 }
964
965 port->clk = of_clk_get_by_name(child, NULL);
966 if (IS_ERR(port->clk)) {
967 dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
968 port->port, port->lane);
969 continue;
970 }
971
972 ret = clk_prepare_enable(port->clk);
973 if (ret)
974 continue;
975
976 port->base = mvebu_pcie_map_registers(pdev, child, port);
977 if (IS_ERR(port->base)) {
978 dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
979 port->port, port->lane);
980 port->base = NULL;
981 clk_disable_unprepare(port->clk);
982 continue;
983 }
984
985 mvebu_pcie_set_local_dev_nr(port, 1);
986
987 port->dn = child;
988 spin_lock_init(&port->conf_lock);
989 mvebu_sw_pci_bridge_init(port);
990 i++;
991 }
992
993 pcie->nports = i;
994
995 for (i = 0; i < (IO_SPACE_LIMIT - SZ_64K); i += SZ_64K)
996 pci_ioremap_io(i, pcie->io.start + i);
997
998 mvebu_pcie_msi_enable(pcie);
999 mvebu_pcie_enable(pcie);
1000
1001 return 0;
1002 }
1003
1004 static const struct of_device_id mvebu_pcie_of_match_table[] = {
1005 { .compatible = "marvell,armada-xp-pcie", },
1006 { .compatible = "marvell,armada-370-pcie", },
1007 { .compatible = "marvell,dove-pcie", },
1008 { .compatible = "marvell,kirkwood-pcie", },
1009 {},
1010 };
1011 MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
1012
1013 static struct platform_driver mvebu_pcie_driver = {
1014 .driver = {
1015 .owner = THIS_MODULE,
1016 .name = "mvebu-pcie",
1017 .of_match_table = mvebu_pcie_of_match_table,
1018 /* driver unloading/unbinding currently not supported */
1019 .suppress_bind_attrs = true,
1020 },
1021 .probe = mvebu_pcie_probe,
1022 };
1023 module_platform_driver(mvebu_pcie_driver);
1024
1025 MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
1026 MODULE_DESCRIPTION("Marvell EBU PCIe driver");
1027 MODULE_LICENSE("GPLv2");
Linux with added FPC-III support