drivers/pci/host/pci-rcar-gen2.c

   1 /*
   2  *  pci-rcar-gen2: internal PCI bus support
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/pci.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/slab.h>
  22
  23 /* AHB-PCI Bridge PCI communication registers */
  24 #define RCAR_AHBPCI_PCICOM_OFFSET       0x800
  25
  26 #define RCAR_PCIAHB_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  27 #define RCAR_PCIAHB_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  28 #define RCAR_PCIAHB_PREFETCH0           0x0
  29 #define RCAR_PCIAHB_PREFETCH4           0x1
  30 #define RCAR_PCIAHB_PREFETCH8           0x2
  31 #define RCAR_PCIAHB_PREFETCH16          0x3
  32
  33 #define RCAR_AHBPCI_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  34 #define RCAR_AHBPCI_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  35 #define RCAR_AHBPCI_WIN_CTR_MEM         (3 << 1)
  36 #define RCAR_AHBPCI_WIN_CTR_CFG         (5 << 1)
  37 #define RCAR_AHBPCI_WIN1_HOST           (1 << 30)
  38 #define RCAR_AHBPCI_WIN1_DEVICE         (1 << 31)
  39
  40 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  41 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  42 #define RCAR_PCI_INT_A                  (1 << 16)
  43 #define RCAR_PCI_INT_B                  (1 << 17)
  44 #define RCAR_PCI_INT_PME                (1 << 19)
  45
  46 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  47 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
  48 #define RCAR_AHB_BUS_MMODE_BYTE_BURST   (1 << 1)
  49 #define RCAR_AHB_BUS_MMODE_WR_INCR      (1 << 2)
  50 #define RCAR_AHB_BUS_MMODE_HBUS_REQ     (1 << 7)
  51 #define RCAR_AHB_BUS_SMODE_READYCTR     (1 << 17)
  52 #define RCAR_AHB_BUS_MODE               (RCAR_AHB_BUS_MMODE_HTRANS |    \
  53                                         RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  54                                         RCAR_AHB_BUS_MMODE_WR_INCR |    \
  55                                         RCAR_AHB_BUS_MMODE_HBUS_REQ |   \
  56                                         RCAR_AHB_BUS_SMODE_READYCTR)
  57
  58 #define RCAR_USBCTR_REG                 (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  59 #define RCAR_USBCTR_USBH_RST            (1 << 0)
  60 #define RCAR_USBCTR_PCICLK_MASK         (1 << 1)
  61 #define RCAR_USBCTR_PLL_RST             (1 << 2)
  62 #define RCAR_USBCTR_DIRPD               (1 << 8)
  63 #define RCAR_USBCTR_PCIAHB_WIN2_EN      (1 << 9)
  64 #define RCAR_USBCTR_PCIAHB_WIN1_256M    (0 << 10)
  65 #define RCAR_USBCTR_PCIAHB_WIN1_512M    (1 << 10)
  66 #define RCAR_USBCTR_PCIAHB_WIN1_1G      (2 << 10)
  67 #define RCAR_USBCTR_PCIAHB_WIN1_2G      (3 << 10)
  68 #define RCAR_USBCTR_PCIAHB_WIN1_MASK    (3 << 10)
  69
  70 #define RCAR_PCI_ARBITER_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  71 #define RCAR_PCI_ARBITER_PCIREQ0        (1 << 0)
  72 #define RCAR_PCI_ARBITER_PCIREQ1        (1 << 1)
  73 #define RCAR_PCI_ARBITER_PCIBP_MODE     (1 << 12)
  74
  75 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  76
  77 /* Number of internal PCI controllers */
  78 #define RCAR_PCI_NR_CONTROLLERS         3
  79
  80 struct rcar_pci_priv {
  81         struct device *dev;
  82         void __iomem *reg;
  83         struct resource io_res;
  84         struct resource mem_res;
  85         struct resource *cfg_res;
  86         int irq;
  87 };
  88
  89 /* PCI configuration space operations */
  90 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
  91                                        int where)
  92 {
  93         struct pci_sys_data *sys = bus->sysdata;
  94         struct rcar_pci_priv *priv = sys->private_data;
  95         int slot, val;
  96
  97         if (sys->busnr != bus->number || PCI_FUNC(devfn))
  98                 return NULL;
  99
 100         /* Only one EHCI/OHCI device built-in */
 101         slot = PCI_SLOT(devfn);
 102         if (slot > 2)
 103                 return NULL;
 104
 105         val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
 106                      RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
 107
 108         iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
 109         return priv->reg + (slot >> 1) * 0x100 + where;
 110 }
 111
 112 static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
 113                                 int where, int size, u32 *val)
 114 {
 115         void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
 116
 117         if (!reg)
 118                 return PCIBIOS_DEVICE_NOT_FOUND;
 119
 120         switch (size) {
 121         case 1:
 122                 *val = ioread8(reg);
 123                 break;
 124         case 2:
 125                 *val = ioread16(reg);
 126                 break;
 127         default:
 128                 *val = ioread32(reg);
 129                 break;
 130         }
 131
 132         return PCIBIOS_SUCCESSFUL;
 133 }
 134
 135 static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 136                                  int where, int size, u32 val)
 137 {
 138         void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
 139
 140         if (!reg)
 141                 return PCIBIOS_DEVICE_NOT_FOUND;
 142
 143         switch (size) {
 144         case 1:
 145                 iowrite8(val, reg);
 146                 break;
 147         case 2:
 148                 iowrite16(val, reg);
 149                 break;
 150         default:
 151                 iowrite32(val, reg);
 152                 break;
 153         }
 154
 155         return PCIBIOS_SUCCESSFUL;
 156 }
 157
 158 /* PCI interrupt mapping */
 159 static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 160 {
 161         struct pci_sys_data *sys = dev->bus->sysdata;
 162         struct rcar_pci_priv *priv = sys->private_data;
 163
 164         return priv->irq;
 165 }
 166
 167 /* PCI host controller setup */
 168 static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
 169 {
 170         struct rcar_pci_priv *priv = sys->private_data;
 171         void __iomem *reg = priv->reg;
 172         u32 val;
 173
 174         pm_runtime_enable(priv->dev);
 175         pm_runtime_get_sync(priv->dev);
 176
 177         val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
 178         dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
 179
 180         /* Disable Direct Power Down State and assert reset */
 181         val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
 182         val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
 183         iowrite32(val, reg + RCAR_USBCTR_REG);
 184         udelay(4);
 185
 186         /* De-assert reset and set PCIAHB window1 size to 1GB */
 187         val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
 188                  RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
 189         iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
 190
 191         /* Configure AHB master and slave modes */
 192         iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
 193
 194         /* Configure PCI arbiter */
 195         val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
 196         val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
 197                RCAR_PCI_ARBITER_PCIBP_MODE;
 198         iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
 199
 200         /* PCI-AHB mapping: 0x40000000-0x80000000 */
 201         iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
 202                   reg + RCAR_PCIAHB_WIN1_CTR_REG);
 203
 204         /* AHB-PCI mapping: OHCI/EHCI registers */
 205         val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
 206         iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
 207
 208         /* Enable AHB-PCI bridge PCI configuration access */
 209         iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
 210                   reg + RCAR_AHBPCI_WIN1_CTR_REG);
 211         /* Set PCI-AHB Window1 address */
 212         iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
 213                   reg + PCI_BASE_ADDRESS_1);
 214         /* Set AHB-PCI bridge PCI communication area address */
 215         val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
 216         iowrite32(val, reg + PCI_BASE_ADDRESS_0);
 217
 218         val = ioread32(reg + PCI_COMMAND);
 219         val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 220                PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 221         iowrite32(val, reg + PCI_COMMAND);
 222
 223         /* Enable PCI interrupts */
 224         iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
 225                   reg + RCAR_PCI_INT_ENABLE_REG);
 226
 227         /* Add PCI resources */
 228         pci_add_resource(&sys->resources, &priv->io_res);
 229         pci_add_resource(&sys->resources, &priv->mem_res);
 230
 231         return 1;
 232 }
 233
 234 static struct pci_ops rcar_pci_ops = {
 235         .read   = rcar_pci_read_config,
 236         .write  = rcar_pci_write_config,
 237 };
 238
 239 static struct hw_pci rcar_hw_pci __initdata = {
 240         .map_irq        = rcar_pci_map_irq,
 241         .ops            = &rcar_pci_ops,
 242         .setup          = rcar_pci_setup,
 243 };
 244
 245 static int rcar_pci_count __initdata;
 246
 247 static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
 248 {
 249         void **private_data;
 250         int count;
 251
 252         if (rcar_hw_pci.nr_controllers < rcar_pci_count)
 253                 goto add_priv;
 254
 255         /* (Re)allocate private data pointer array if needed */
 256         count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
 257         private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
 258         if (!private_data)
 259                 return -ENOMEM;
 260
 261         rcar_pci_count = count;
 262         if (rcar_hw_pci.private_data) {
 263                 memcpy(private_data, rcar_hw_pci.private_data,
 264                        rcar_hw_pci.nr_controllers * sizeof(void *));
 265                 kfree(rcar_hw_pci.private_data);
 266         }
 267
 268         rcar_hw_pci.private_data = private_data;
 269
 270 add_priv:
 271         /* Add private data pointer to the array */
 272         rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
 273         return 0;
 274 }
 275
 276 static int __init rcar_pci_probe(struct platform_device *pdev)
 277 {
 278         struct resource *cfg_res, *mem_res;
 279         struct rcar_pci_priv *priv;
 280         void __iomem *reg;
 281
 282         cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 283         reg = devm_ioremap_resource(&pdev->dev, cfg_res);
 284         if (IS_ERR(reg))
 285                 return PTR_ERR(reg);
 286
 287         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 288         if (!mem_res || !mem_res->start)
 289                 return -ENODEV;
 290
 291         priv = devm_kzalloc(&pdev->dev,
 292                             sizeof(struct rcar_pci_priv), GFP_KERNEL);
 293         if (!priv)
 294                 return -ENOMEM;
 295
 296         priv->mem_res = *mem_res;
 297         /*
 298          * The controller does not support/use port I/O,
 299          * so setup a dummy port I/O region here.
 300          */
 301         priv->io_res.start = priv->mem_res.start;
 302         priv->io_res.end = priv->mem_res.end;
 303         priv->io_res.flags = IORESOURCE_IO;
 304
 305         priv->cfg_res = cfg_res;
 306
 307         priv->irq = platform_get_irq(pdev, 0);
 308         priv->reg = reg;
 309         priv->dev = &pdev->dev;
 310
 311         return rcar_pci_add_controller(priv);
 312 }
 313
 314 static struct platform_driver rcar_pci_driver = {
 315         .driver = {
 316                 .name = "pci-rcar-gen2",
 317         },
 318 };
 319
 320 static int __init rcar_pci_init(void)
 321 {
 322         int retval;
 323
 324         retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
 325         if (!retval)
 326                 pci_common_init(&rcar_hw_pci);
 327
 328         /* Private data pointer array is not needed any more */
 329         kfree(rcar_hw_pci.private_data);
 330         rcar_hw_pci.private_data = NULL;
 331
 332         return retval;
 333 }
 334
 335 subsys_initcall(rcar_pci_init);
 336
 337 MODULE_LICENSE("GPL v2");
 338 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
 339 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");