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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-as3722.c
blob92ed4b2e3c0716cf3f21580b49434fc6e9952fc6
1 /*
2 * ams AS3722 pin control and GPIO driver.
3 *
4 * Copyright (c) 2013, NVIDIA Corporation.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13 * whether express or implied; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307, USA
21 */
22
23 #include <linux/delay.h>
24 #include <linux/gpio.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mfd/as3722.h>
28 #include <linux/of.h>
29 #include <linux/of_device.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pinctrl/machine.h>
33 #include <linux/pinctrl/pinctrl.h>
34 #include <linux/pinctrl/pinconf-generic.h>
35 #include <linux/pinctrl/pinconf.h>
36 #include <linux/pinctrl/pinmux.h>
37 #include <linux/pm.h>
38 #include <linux/slab.h>
39
40 #include "core.h"
41 #include "pinconf.h"
42 #include "pinctrl-utils.h"
43
44 #define AS3722_PIN_GPIO0 0
45 #define AS3722_PIN_GPIO1 1
46 #define AS3722_PIN_GPIO2 2
47 #define AS3722_PIN_GPIO3 3
48 #define AS3722_PIN_GPIO4 4
49 #define AS3722_PIN_GPIO5 5
50 #define AS3722_PIN_GPIO6 6
51 #define AS3722_PIN_GPIO7 7
52 #define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
53
54 #define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
55 #define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
56 #define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
57 #define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
58
59 struct as3722_pin_function {
60 const char *name;
61 const char * const *groups;
62 unsigned ngroups;
63 int mux_option;
64 };
65
66 struct as3722_gpio_pin_control {
67 bool enable_gpio_invert;
68 unsigned mode_prop;
69 int io_function;
70 };
71
72 struct as3722_pingroup {
73 const char *name;
74 const unsigned pins[1];
75 unsigned npins;
76 };
77
78 struct as3722_pctrl_info {
79 struct device *dev;
80 struct pinctrl_dev *pctl;
81 struct as3722 *as3722;
82 struct gpio_chip gpio_chip;
83 int pins_current_opt[AS3722_PIN_NUM];
84 const struct as3722_pin_function *functions;
85 unsigned num_functions;
86 const struct as3722_pingroup *pin_groups;
87 int num_pin_groups;
88 const struct pinctrl_pin_desc *pins;
89 unsigned num_pins;
90 struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
91 };
92
93 static const struct pinctrl_pin_desc as3722_pins_desc[] = {
94 PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
95 PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
96 PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
97 PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
98 PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
99 PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
100 PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
101 PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
102 };
103
104 static const char * const gpio_groups[] = {
105 "gpio0",
106 "gpio1",
107 "gpio2",
108 "gpio3",
109 "gpio4",
110 "gpio5",
111 "gpio6",
112 "gpio7",
113 };
114
115 enum as3722_pinmux_option {
116 AS3722_PINMUX_GPIO = 0,
117 AS3722_PINMUX_INTERRUPT_OUT = 1,
118 AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
119 AS3722_PINMUX_GPIO_INTERRUPT = 3,
120 AS3722_PINMUX_PWM_INPUT = 4,
121 AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
122 AS3722_PINMUX_OC_PG_SD0 = 6,
123 AS3722_PINMUX_PG_OUT = 7,
124 AS3722_PINMUX_CLK32K_OUT = 8,
125 AS3722_PINMUX_WATCHDOG_INPUT = 9,
126 AS3722_PINMUX_SOFT_RESET_IN = 11,
127 AS3722_PINMUX_PWM_OUTPUT = 12,
128 AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
129 AS3722_PINMUX_OC_PG_SD6 = 14,
130 };
131
132 #define FUNCTION_GROUP(fname, mux) \
133 { \
134 .name = #fname, \
135 .groups = gpio_groups, \
136 .ngroups = ARRAY_SIZE(gpio_groups), \
137 .mux_option = AS3722_PINMUX_##mux, \
138 }
139
140 static const struct as3722_pin_function as3722_pin_function[] = {
141 FUNCTION_GROUP(gpio, GPIO),
142 FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
143 FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
144 FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
145 FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
146 FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
147 FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
148 FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
149 FUNCTION_GROUP(powergood-out, PG_OUT),
150 FUNCTION_GROUP(pwm-in, PWM_INPUT),
151 FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
152 FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
153 FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
154 FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
155 };
156
157 #define AS3722_PINGROUP(pg_name, pin_id) \
158 { \
159 .name = #pg_name, \
160 .pins = {AS3722_PIN_##pin_id}, \
161 .npins = 1, \
162 }
163
164 static const struct as3722_pingroup as3722_pingroups[] = {
165 AS3722_PINGROUP(gpio0, GPIO0),
166 AS3722_PINGROUP(gpio1, GPIO1),
167 AS3722_PINGROUP(gpio2, GPIO2),
168 AS3722_PINGROUP(gpio3, GPIO3),
169 AS3722_PINGROUP(gpio4, GPIO4),
170 AS3722_PINGROUP(gpio5, GPIO5),
171 AS3722_PINGROUP(gpio6, GPIO6),
172 AS3722_PINGROUP(gpio7, GPIO7),
173 };
174
175 static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
176 {
177 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
178
179 return as_pci->num_pin_groups;
180 }
181
182 static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
183 unsigned group)
184 {
185 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
186
187 return as_pci->pin_groups[group].name;
188 }
189
190 static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
191 unsigned group, const unsigned **pins, unsigned *num_pins)
192 {
193 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
194
195 *pins = as_pci->pin_groups[group].pins;
196 *num_pins = as_pci->pin_groups[group].npins;
197 return 0;
198 }
199
200 static const struct pinctrl_ops as3722_pinctrl_ops = {
201 .get_groups_count = as3722_pinctrl_get_groups_count,
202 .get_group_name = as3722_pinctrl_get_group_name,
203 .get_group_pins = as3722_pinctrl_get_group_pins,
204 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
205 .dt_free_map = pinctrl_utils_dt_free_map,
206 };
207
208 static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
209 {
210 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
211
212 return as_pci->num_functions;
213 }
214
215 static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
216 unsigned function)
217 {
218 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
219
220 return as_pci->functions[function].name;
221 }
222
223 static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
224 unsigned function, const char * const **groups,
225 unsigned * const num_groups)
226 {
227 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
228
229 *groups = as_pci->functions[function].groups;
230 *num_groups = as_pci->functions[function].ngroups;
231 return 0;
232 }
233
234 static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
235 unsigned group)
236 {
237 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
238 int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
239 u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
240 int ret;
241
242 dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
243 __func__, group, function, val);
244
245 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
246 AS3722_GPIO_IOSF_MASK, val);
247 if (ret < 0) {
248 dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
249 group, ret);
250 return ret;
251 }
252 as_pci->gpio_control[group].io_function = function;
253
254 switch (val) {
255 case AS3722_GPIO_IOSF_SD0_OUT:
256 case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
257 case AS3722_GPIO_IOSF_Q32K_OUT:
258 case AS3722_GPIO_IOSF_PWM_OUT:
259 case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
260 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
261 AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
262 if (ret < 0) {
263 dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
264 group, ret);
265 return ret;
266 }
267 as_pci->gpio_control[group].mode_prop =
268 AS3722_GPIO_MODE_OUTPUT_VDDH;
269 break;
270 default:
271 break;
272 }
273 return ret;
274 }
275
276 static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
277 {
278 if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
279 return -EINVAL;
280
281 if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
282 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
283 return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
284 return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
285 }
286 if (input) {
287 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
288 return AS3722_GPIO_MODE_INPUT_PULL_UP;
289 else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
290 return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
291 return AS3722_GPIO_MODE_INPUT;
292 }
293 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
294 return AS3722_GPIO_MODE_OUTPUT_VDDL;
295 return AS3722_GPIO_MODE_OUTPUT_VDDH;
296 }
297
298 static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
299 struct pinctrl_gpio_range *range, unsigned offset)
300 {
301 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
302
303 if (as_pci->gpio_control[offset].io_function)
304 return -EBUSY;
305 return 0;
306 }
307
308 static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
309 struct pinctrl_gpio_range *range, unsigned offset, bool input)
310 {
311 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
312 struct as3722 *as3722 = as_pci->as3722;
313 int mode;
314
315 mode = as3722_pinctrl_gpio_get_mode(
316 as_pci->gpio_control[offset].mode_prop, input);
317 if (mode < 0) {
318 dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
319 (input) ? "Input" : "Output", offset);
320 return mode;
321 }
322
323 if (as_pci->gpio_control[offset].enable_gpio_invert)
324 mode |= AS3722_GPIO_INV;
325
326 return as3722_write(as3722, AS3722_GPIOn_CONTROL_REG(offset), mode);
327 }
328
329 static const struct pinmux_ops as3722_pinmux_ops = {
330 .get_functions_count = as3722_pinctrl_get_funcs_count,
331 .get_function_name = as3722_pinctrl_get_func_name,
332 .get_function_groups = as3722_pinctrl_get_func_groups,
333 .enable = as3722_pinctrl_enable,
334 .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
335 .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
336 };
337
338 static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
339 unsigned pin, unsigned long *config)
340 {
341 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
342 enum pin_config_param param = pinconf_to_config_param(*config);
343 int arg = 0;
344 u16 prop;
345
346 switch (param) {
347 case PIN_CONFIG_BIAS_DISABLE:
348 prop = AS3722_GPIO_MODE_PULL_UP |
349 AS3722_GPIO_MODE_PULL_DOWN;
350 if (!(as_pci->gpio_control[pin].mode_prop & prop))
351 arg = 1;
352 prop = 0;
353 break;
354
355 case PIN_CONFIG_BIAS_PULL_UP:
356 prop = AS3722_GPIO_MODE_PULL_UP;
357 break;
358
359 case PIN_CONFIG_BIAS_PULL_DOWN:
360 prop = AS3722_GPIO_MODE_PULL_DOWN;
361 break;
362
363 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
364 prop = AS3722_GPIO_MODE_OPEN_DRAIN;
365 break;
366
367 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
368 prop = AS3722_GPIO_MODE_HIGH_IMPED;
369 break;
370
371 default:
372 dev_err(as_pci->dev, "Properties not supported\n");
373 return -ENOTSUPP;
374 }
375
376 if (as_pci->gpio_control[pin].mode_prop & prop)
377 arg = 1;
378
379 *config = pinconf_to_config_packed(param, (u16)arg);
380 return 0;
381 }
382
383 static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
384 unsigned pin, unsigned long *configs,
385 unsigned num_configs)
386 {
387 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
388 enum pin_config_param param;
389 int mode_prop;
390 int i;
391
392 for (i = 0; i < num_configs; i++) {
393 param = pinconf_to_config_param(configs[i]);
394 mode_prop = as_pci->gpio_control[pin].mode_prop;
395
396 switch (param) {
397 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
398 break;
399
400 case PIN_CONFIG_BIAS_DISABLE:
401 mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
402 AS3722_GPIO_MODE_PULL_DOWN);
403 break;
404 case PIN_CONFIG_BIAS_PULL_UP:
405 mode_prop |= AS3722_GPIO_MODE_PULL_UP;
406 break;
407
408 case PIN_CONFIG_BIAS_PULL_DOWN:
409 mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
410 break;
411
412 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
413 mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
414 break;
415
416 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
417 mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
418 break;
419
420 default:
421 dev_err(as_pci->dev, "Properties not supported\n");
422 return -ENOTSUPP;
423 }
424
425 as_pci->gpio_control[pin].mode_prop = mode_prop;
426 }
427 return 0;
428 }
429
430 static const struct pinconf_ops as3722_pinconf_ops = {
431 .pin_config_get = as3722_pinconf_get,
432 .pin_config_set = as3722_pinconf_set,
433 };
434
435 static struct pinctrl_desc as3722_pinctrl_desc = {
436 .pctlops = &as3722_pinctrl_ops,
437 .pmxops = &as3722_pinmux_ops,
438 .confops = &as3722_pinconf_ops,
439 .owner = THIS_MODULE,
440 };
441
442 static inline struct as3722_pctrl_info *to_as_pci(struct gpio_chip *chip)
443 {
444 return container_of(chip, struct as3722_pctrl_info, gpio_chip);
445 }
446
447 static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
448 {
449 struct as3722_pctrl_info *as_pci = to_as_pci(chip);
450 struct as3722 *as3722 = as_pci->as3722;
451 int ret;
452 u32 reg;
453 u32 control;
454 u32 val;
455 int mode;
456 int invert_enable;
457
458 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
459 if (ret < 0) {
460 dev_err(as_pci->dev,
461 "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
462 return ret;
463 }
464
465 invert_enable = !!(control & AS3722_GPIO_INV);
466 mode = control & AS3722_GPIO_MODE_MASK;
467 switch (mode) {
468 case AS3722_GPIO_MODE_INPUT:
469 case AS3722_GPIO_MODE_INPUT_PULL_UP:
470 case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
471 case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
472 case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
473 reg = AS3722_GPIO_SIGNAL_IN_REG;
474 break;
475 case AS3722_GPIO_MODE_OUTPUT_VDDH:
476 case AS3722_GPIO_MODE_OUTPUT_VDDL:
477 reg = AS3722_GPIO_SIGNAL_OUT_REG;
478 break;
479 default:
480 return -EINVAL;
481 }
482
483 ret = as3722_read(as3722, reg, &val);
484 if (ret < 0) {
485 dev_err(as_pci->dev,
486 "GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
487 return ret;
488 }
489
490 val = !!(val & AS3722_GPIOn_SIGNAL(offset));
491 return (invert_enable) ? !val : val;
492 }
493
494 static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
495 int value)
496 {
497 struct as3722_pctrl_info *as_pci = to_as_pci(chip);
498 struct as3722 *as3722 = as_pci->as3722;
499 int en_invert = as_pci->gpio_control[offset].enable_gpio_invert;
500 u32 val;
501 int ret;
502
503 if (value)
504 val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
505 else
506 val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
507
508 ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
509 AS3722_GPIOn_SIGNAL(offset), val);
510 if (ret < 0)
511 dev_err(as_pci->dev,
512 "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
513 }
514
515 static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
516 {
517 return pinctrl_gpio_direction_input(chip->base + offset);
518 }
519
520 static int as3722_gpio_direction_output(struct gpio_chip *chip,
521 unsigned offset, int value)
522 {
523 as3722_gpio_set(chip, offset, value);
524 return pinctrl_gpio_direction_output(chip->base + offset);
525 }
526
527 static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
528 {
529 struct as3722_pctrl_info *as_pci = to_as_pci(chip);
530
531 return as3722_irq_get_virq(as_pci->as3722, offset);
532 }
533
534 static int as3722_gpio_request(struct gpio_chip *chip, unsigned offset)
535 {
536 return pinctrl_request_gpio(chip->base + offset);
537 }
538
539 static void as3722_gpio_free(struct gpio_chip *chip, unsigned offset)
540 {
541 pinctrl_free_gpio(chip->base + offset);
542 }
543
544 static const struct gpio_chip as3722_gpio_chip = {
545 .label = "as3722-gpio",
546 .owner = THIS_MODULE,
547 .request = as3722_gpio_request,
548 .free = as3722_gpio_free,
549 .get = as3722_gpio_get,
550 .set = as3722_gpio_set,
551 .direction_input = as3722_gpio_direction_input,
552 .direction_output = as3722_gpio_direction_output,
553 .to_irq = as3722_gpio_to_irq,
554 .can_sleep = true,
555 .ngpio = AS3722_PIN_NUM,
556 .base = -1,
557 };
558
559 static int as3722_pinctrl_probe(struct platform_device *pdev)
560 {
561 struct as3722_pctrl_info *as_pci;
562 int ret;
563 int tret;
564
565 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
566 if (!as_pci)
567 return -ENOMEM;
568
569 as_pci->dev = &pdev->dev;
570 as_pci->dev->of_node = pdev->dev.parent->of_node;
571 as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
572 platform_set_drvdata(pdev, as_pci);
573
574 as_pci->pins = as3722_pins_desc;
575 as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
576 as_pci->functions = as3722_pin_function;
577 as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
578 as_pci->pin_groups = as3722_pingroups;
579 as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
580 as3722_pinctrl_desc.name = dev_name(&pdev->dev);
581 as3722_pinctrl_desc.pins = as3722_pins_desc;
582 as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
583 as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc,
584 &pdev->dev, as_pci);
585 if (!as_pci->pctl) {
586 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
587 return -EINVAL;
588 }
589
590 as_pci->gpio_chip = as3722_gpio_chip;
591 as_pci->gpio_chip.dev = &pdev->dev;
592 as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
593 ret = gpiochip_add(&as_pci->gpio_chip);
594 if (ret < 0) {
595 dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
596 goto fail_chip_add;
597 }
598
599 ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
600 0, 0, AS3722_PIN_NUM);
601 if (ret < 0) {
602 dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
603 goto fail_range_add;
604 }
605
606 return 0;
607
608 fail_range_add:
609 tret = gpiochip_remove(&as_pci->gpio_chip);
610 if (tret < 0)
611 dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret);
612
613 fail_chip_add:
614 pinctrl_unregister(as_pci->pctl);
615 return ret;
616 }
617
618 static int as3722_pinctrl_remove(struct platform_device *pdev)
619 {
620 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
621 int ret;
622
623 ret = gpiochip_remove(&as_pci->gpio_chip);
624 if (ret < 0)
625 return ret;
626 pinctrl_unregister(as_pci->pctl);
627 return 0;
628 }
629
630 static struct of_device_id as3722_pinctrl_of_match[] = {
631 { .compatible = "ams,as3722-pinctrl", },
632 { },
633 };
634 MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
635
636 static struct platform_driver as3722_pinctrl_driver = {
637 .driver = {
638 .name = "as3722-pinctrl",
639 .owner = THIS_MODULE,
640 .of_match_table = as3722_pinctrl_of_match,
641 },
642 .probe = as3722_pinctrl_probe,
643 .remove = as3722_pinctrl_remove,
644 };
645 module_platform_driver(as3722_pinctrl_driver);
646
647 MODULE_ALIAS("platform:as3722-pinctrl");
648 MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
649 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
650 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support