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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / pinctrl / pinctrl-capri.c
blob4669c53f99b0a4fc8e30ab4678263be292f014fd
1 /*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13 #include <linux/err.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/pinctrl/pinctrl.h>
19 #include <linux/pinctrl/pinmux.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/regmap.h>
23 #include <linux/slab.h>
24 #include "core.h"
25 #include "pinctrl-utils.h"
26
27 /* Capri Pin Control Registers Definitions */
28
29 /* Function Select bits are the same for all pin control registers */
30 #define CAPRI_PIN_REG_F_SEL_MASK 0x0700
31 #define CAPRI_PIN_REG_F_SEL_SHIFT 8
32
33 /* Standard pin register */
34 #define CAPRI_STD_PIN_REG_DRV_STR_MASK 0x0007
35 #define CAPRI_STD_PIN_REG_DRV_STR_SHIFT 0
36 #define CAPRI_STD_PIN_REG_INPUT_DIS_MASK 0x0008
37 #define CAPRI_STD_PIN_REG_INPUT_DIS_SHIFT 3
38 #define CAPRI_STD_PIN_REG_SLEW_MASK 0x0010
39 #define CAPRI_STD_PIN_REG_SLEW_SHIFT 4
40 #define CAPRI_STD_PIN_REG_PULL_UP_MASK 0x0020
41 #define CAPRI_STD_PIN_REG_PULL_UP_SHIFT 5
42 #define CAPRI_STD_PIN_REG_PULL_DN_MASK 0x0040
43 #define CAPRI_STD_PIN_REG_PULL_DN_SHIFT 6
44 #define CAPRI_STD_PIN_REG_HYST_MASK 0x0080
45 #define CAPRI_STD_PIN_REG_HYST_SHIFT 7
46
47 /* I2C pin register */
48 #define CAPRI_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
49 #define CAPRI_I2C_PIN_REG_INPUT_DIS_SHIFT 2
50 #define CAPRI_I2C_PIN_REG_SLEW_MASK 0x0008
51 #define CAPRI_I2C_PIN_REG_SLEW_SHIFT 3
52 #define CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
53 #define CAPRI_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
54
55 /* HDMI pin register */
56 #define CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
57 #define CAPRI_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
58 #define CAPRI_HDMI_PIN_REG_MODE_MASK 0x0010
59 #define CAPRI_HDMI_PIN_REG_MODE_SHIFT 4
60
61 /**
62 * capri_pin_type - types of pin register
63 */
64 enum capri_pin_type {
65 CAPRI_PIN_TYPE_UNKNOWN = 0,
66 CAPRI_PIN_TYPE_STD,
67 CAPRI_PIN_TYPE_I2C,
68 CAPRI_PIN_TYPE_HDMI,
69 };
70
71 static enum capri_pin_type std_pin = CAPRI_PIN_TYPE_STD;
72 static enum capri_pin_type i2c_pin = CAPRI_PIN_TYPE_I2C;
73 static enum capri_pin_type hdmi_pin = CAPRI_PIN_TYPE_HDMI;
74
75 /**
76 * capri_pin_function- define pin function
77 */
78 struct capri_pin_function {
79 const char *name;
80 const char * const *groups;
81 const unsigned ngroups;
82 };
83
84 /**
85 * capri_pinctrl_data - Broadcom-specific pinctrl data
86 * @reg_base - base of pinctrl registers
87 */
88 struct capri_pinctrl_data {
89 void __iomem *reg_base;
90
91 /* List of all pins */
92 const struct pinctrl_pin_desc *pins;
93 const unsigned npins;
94
95 const struct capri_pin_function *functions;
96 const unsigned nfunctions;
97
98 struct regmap *regmap;
99 };
100
101 /*
102 * Pin number definition. The order here must be the same as defined in the
103 * PADCTRLREG block in the RDB.
104 */
105 #define CAPRI_PIN_ADCSYNC 0
106 #define CAPRI_PIN_BAT_RM 1
107 #define CAPRI_PIN_BSC1_SCL 2
108 #define CAPRI_PIN_BSC1_SDA 3
109 #define CAPRI_PIN_BSC2_SCL 4
110 #define CAPRI_PIN_BSC2_SDA 5
111 #define CAPRI_PIN_CLASSGPWR 6
112 #define CAPRI_PIN_CLK_CX8 7
113 #define CAPRI_PIN_CLKOUT_0 8
114 #define CAPRI_PIN_CLKOUT_1 9
115 #define CAPRI_PIN_CLKOUT_2 10
116 #define CAPRI_PIN_CLKOUT_3 11
117 #define CAPRI_PIN_CLKREQ_IN_0 12
118 #define CAPRI_PIN_CLKREQ_IN_1 13
119 #define CAPRI_PIN_CWS_SYS_REQ1 14
120 #define CAPRI_PIN_CWS_SYS_REQ2 15
121 #define CAPRI_PIN_CWS_SYS_REQ3 16
122 #define CAPRI_PIN_DIGMIC1_CLK 17
123 #define CAPRI_PIN_DIGMIC1_DQ 18
124 #define CAPRI_PIN_DIGMIC2_CLK 19
125 #define CAPRI_PIN_DIGMIC2_DQ 20
126 #define CAPRI_PIN_GPEN13 21
127 #define CAPRI_PIN_GPEN14 22
128 #define CAPRI_PIN_GPEN15 23
129 #define CAPRI_PIN_GPIO00 24
130 #define CAPRI_PIN_GPIO01 25
131 #define CAPRI_PIN_GPIO02 26
132 #define CAPRI_PIN_GPIO03 27
133 #define CAPRI_PIN_GPIO04 28
134 #define CAPRI_PIN_GPIO05 29
135 #define CAPRI_PIN_GPIO06 30
136 #define CAPRI_PIN_GPIO07 31
137 #define CAPRI_PIN_GPIO08 32
138 #define CAPRI_PIN_GPIO09 33
139 #define CAPRI_PIN_GPIO10 34
140 #define CAPRI_PIN_GPIO11 35
141 #define CAPRI_PIN_GPIO12 36
142 #define CAPRI_PIN_GPIO13 37
143 #define CAPRI_PIN_GPIO14 38
144 #define CAPRI_PIN_GPS_PABLANK 39
145 #define CAPRI_PIN_GPS_TMARK 40
146 #define CAPRI_PIN_HDMI_SCL 41
147 #define CAPRI_PIN_HDMI_SDA 42
148 #define CAPRI_PIN_IC_DM 43
149 #define CAPRI_PIN_IC_DP 44
150 #define CAPRI_PIN_KP_COL_IP_0 45
151 #define CAPRI_PIN_KP_COL_IP_1 46
152 #define CAPRI_PIN_KP_COL_IP_2 47
153 #define CAPRI_PIN_KP_COL_IP_3 48
154 #define CAPRI_PIN_KP_ROW_OP_0 49
155 #define CAPRI_PIN_KP_ROW_OP_1 50
156 #define CAPRI_PIN_KP_ROW_OP_2 51
157 #define CAPRI_PIN_KP_ROW_OP_3 52
158 #define CAPRI_PIN_LCD_B_0 53
159 #define CAPRI_PIN_LCD_B_1 54
160 #define CAPRI_PIN_LCD_B_2 55
161 #define CAPRI_PIN_LCD_B_3 56
162 #define CAPRI_PIN_LCD_B_4 57
163 #define CAPRI_PIN_LCD_B_5 58
164 #define CAPRI_PIN_LCD_B_6 59
165 #define CAPRI_PIN_LCD_B_7 60
166 #define CAPRI_PIN_LCD_G_0 61
167 #define CAPRI_PIN_LCD_G_1 62
168 #define CAPRI_PIN_LCD_G_2 63
169 #define CAPRI_PIN_LCD_G_3 64
170 #define CAPRI_PIN_LCD_G_4 65
171 #define CAPRI_PIN_LCD_G_5 66
172 #define CAPRI_PIN_LCD_G_6 67
173 #define CAPRI_PIN_LCD_G_7 68
174 #define CAPRI_PIN_LCD_HSYNC 69
175 #define CAPRI_PIN_LCD_OE 70
176 #define CAPRI_PIN_LCD_PCLK 71
177 #define CAPRI_PIN_LCD_R_0 72
178 #define CAPRI_PIN_LCD_R_1 73
179 #define CAPRI_PIN_LCD_R_2 74
180 #define CAPRI_PIN_LCD_R_3 75
181 #define CAPRI_PIN_LCD_R_4 76
182 #define CAPRI_PIN_LCD_R_5 77
183 #define CAPRI_PIN_LCD_R_6 78
184 #define CAPRI_PIN_LCD_R_7 79
185 #define CAPRI_PIN_LCD_VSYNC 80
186 #define CAPRI_PIN_MDMGPIO0 81
187 #define CAPRI_PIN_MDMGPIO1 82
188 #define CAPRI_PIN_MDMGPIO2 83
189 #define CAPRI_PIN_MDMGPIO3 84
190 #define CAPRI_PIN_MDMGPIO4 85
191 #define CAPRI_PIN_MDMGPIO5 86
192 #define CAPRI_PIN_MDMGPIO6 87
193 #define CAPRI_PIN_MDMGPIO7 88
194 #define CAPRI_PIN_MDMGPIO8 89
195 #define CAPRI_PIN_MPHI_DATA_0 90
196 #define CAPRI_PIN_MPHI_DATA_1 91
197 #define CAPRI_PIN_MPHI_DATA_2 92
198 #define CAPRI_PIN_MPHI_DATA_3 93
199 #define CAPRI_PIN_MPHI_DATA_4 94
200 #define CAPRI_PIN_MPHI_DATA_5 95
201 #define CAPRI_PIN_MPHI_DATA_6 96
202 #define CAPRI_PIN_MPHI_DATA_7 97
203 #define CAPRI_PIN_MPHI_DATA_8 98
204 #define CAPRI_PIN_MPHI_DATA_9 99
205 #define CAPRI_PIN_MPHI_DATA_10 100
206 #define CAPRI_PIN_MPHI_DATA_11 101
207 #define CAPRI_PIN_MPHI_DATA_12 102
208 #define CAPRI_PIN_MPHI_DATA_13 103
209 #define CAPRI_PIN_MPHI_DATA_14 104
210 #define CAPRI_PIN_MPHI_DATA_15 105
211 #define CAPRI_PIN_MPHI_HA0 106
212 #define CAPRI_PIN_MPHI_HAT0 107
213 #define CAPRI_PIN_MPHI_HAT1 108
214 #define CAPRI_PIN_MPHI_HCE0_N 109
215 #define CAPRI_PIN_MPHI_HCE1_N 110
216 #define CAPRI_PIN_MPHI_HRD_N 111
217 #define CAPRI_PIN_MPHI_HWR_N 112
218 #define CAPRI_PIN_MPHI_RUN0 113
219 #define CAPRI_PIN_MPHI_RUN1 114
220 #define CAPRI_PIN_MTX_SCAN_CLK 115
221 #define CAPRI_PIN_MTX_SCAN_DATA 116
222 #define CAPRI_PIN_NAND_AD_0 117
223 #define CAPRI_PIN_NAND_AD_1 118
224 #define CAPRI_PIN_NAND_AD_2 119
225 #define CAPRI_PIN_NAND_AD_3 120
226 #define CAPRI_PIN_NAND_AD_4 121
227 #define CAPRI_PIN_NAND_AD_5 122
228 #define CAPRI_PIN_NAND_AD_6 123
229 #define CAPRI_PIN_NAND_AD_7 124
230 #define CAPRI_PIN_NAND_ALE 125
231 #define CAPRI_PIN_NAND_CEN_0 126
232 #define CAPRI_PIN_NAND_CEN_1 127
233 #define CAPRI_PIN_NAND_CLE 128
234 #define CAPRI_PIN_NAND_OEN 129
235 #define CAPRI_PIN_NAND_RDY_0 130
236 #define CAPRI_PIN_NAND_RDY_1 131
237 #define CAPRI_PIN_NAND_WEN 132
238 #define CAPRI_PIN_NAND_WP 133
239 #define CAPRI_PIN_PC1 134
240 #define CAPRI_PIN_PC2 135
241 #define CAPRI_PIN_PMU_INT 136
242 #define CAPRI_PIN_PMU_SCL 137
243 #define CAPRI_PIN_PMU_SDA 138
244 #define CAPRI_PIN_RFST2G_MTSLOTEN3G 139
245 #define CAPRI_PIN_RGMII_0_RX_CTL 140
246 #define CAPRI_PIN_RGMII_0_RXC 141
247 #define CAPRI_PIN_RGMII_0_RXD_0 142
248 #define CAPRI_PIN_RGMII_0_RXD_1 143
249 #define CAPRI_PIN_RGMII_0_RXD_2 144
250 #define CAPRI_PIN_RGMII_0_RXD_3 145
251 #define CAPRI_PIN_RGMII_0_TX_CTL 146
252 #define CAPRI_PIN_RGMII_0_TXC 147
253 #define CAPRI_PIN_RGMII_0_TXD_0 148
254 #define CAPRI_PIN_RGMII_0_TXD_1 149
255 #define CAPRI_PIN_RGMII_0_TXD_2 150
256 #define CAPRI_PIN_RGMII_0_TXD_3 151
257 #define CAPRI_PIN_RGMII_1_RX_CTL 152
258 #define CAPRI_PIN_RGMII_1_RXC 153
259 #define CAPRI_PIN_RGMII_1_RXD_0 154
260 #define CAPRI_PIN_RGMII_1_RXD_1 155
261 #define CAPRI_PIN_RGMII_1_RXD_2 156
262 #define CAPRI_PIN_RGMII_1_RXD_3 157
263 #define CAPRI_PIN_RGMII_1_TX_CTL 158
264 #define CAPRI_PIN_RGMII_1_TXC 159
265 #define CAPRI_PIN_RGMII_1_TXD_0 160
266 #define CAPRI_PIN_RGMII_1_TXD_1 161
267 #define CAPRI_PIN_RGMII_1_TXD_2 162
268 #define CAPRI_PIN_RGMII_1_TXD_3 163
269 #define CAPRI_PIN_RGMII_GPIO_0 164
270 #define CAPRI_PIN_RGMII_GPIO_1 165
271 #define CAPRI_PIN_RGMII_GPIO_2 166
272 #define CAPRI_PIN_RGMII_GPIO_3 167
273 #define CAPRI_PIN_RTXDATA2G_TXDATA3G1 168
274 #define CAPRI_PIN_RTXEN2G_TXDATA3G2 169
275 #define CAPRI_PIN_RXDATA3G0 170
276 #define CAPRI_PIN_RXDATA3G1 171
277 #define CAPRI_PIN_RXDATA3G2 172
278 #define CAPRI_PIN_SDIO1_CLK 173
279 #define CAPRI_PIN_SDIO1_CMD 174
280 #define CAPRI_PIN_SDIO1_DATA_0 175
281 #define CAPRI_PIN_SDIO1_DATA_1 176
282 #define CAPRI_PIN_SDIO1_DATA_2 177
283 #define CAPRI_PIN_SDIO1_DATA_3 178
284 #define CAPRI_PIN_SDIO4_CLK 179
285 #define CAPRI_PIN_SDIO4_CMD 180
286 #define CAPRI_PIN_SDIO4_DATA_0 181
287 #define CAPRI_PIN_SDIO4_DATA_1 182
288 #define CAPRI_PIN_SDIO4_DATA_2 183
289 #define CAPRI_PIN_SDIO4_DATA_3 184
290 #define CAPRI_PIN_SIM_CLK 185
291 #define CAPRI_PIN_SIM_DATA 186
292 #define CAPRI_PIN_SIM_DET 187
293 #define CAPRI_PIN_SIM_RESETN 188
294 #define CAPRI_PIN_SIM2_CLK 189
295 #define CAPRI_PIN_SIM2_DATA 190
296 #define CAPRI_PIN_SIM2_DET 191
297 #define CAPRI_PIN_SIM2_RESETN 192
298 #define CAPRI_PIN_SRI_C 193
299 #define CAPRI_PIN_SRI_D 194
300 #define CAPRI_PIN_SRI_E 195
301 #define CAPRI_PIN_SSP_EXTCLK 196
302 #define CAPRI_PIN_SSP0_CLK 197
303 #define CAPRI_PIN_SSP0_FS 198
304 #define CAPRI_PIN_SSP0_RXD 199
305 #define CAPRI_PIN_SSP0_TXD 200
306 #define CAPRI_PIN_SSP2_CLK 201
307 #define CAPRI_PIN_SSP2_FS_0 202
308 #define CAPRI_PIN_SSP2_FS_1 203
309 #define CAPRI_PIN_SSP2_FS_2 204
310 #define CAPRI_PIN_SSP2_FS_3 205
311 #define CAPRI_PIN_SSP2_RXD_0 206
312 #define CAPRI_PIN_SSP2_RXD_1 207
313 #define CAPRI_PIN_SSP2_TXD_0 208
314 #define CAPRI_PIN_SSP2_TXD_1 209
315 #define CAPRI_PIN_SSP3_CLK 210
316 #define CAPRI_PIN_SSP3_FS 211
317 #define CAPRI_PIN_SSP3_RXD 212
318 #define CAPRI_PIN_SSP3_TXD 213
319 #define CAPRI_PIN_SSP4_CLK 214
320 #define CAPRI_PIN_SSP4_FS 215
321 #define CAPRI_PIN_SSP4_RXD 216
322 #define CAPRI_PIN_SSP4_TXD 217
323 #define CAPRI_PIN_SSP5_CLK 218
324 #define CAPRI_PIN_SSP5_FS 219
325 #define CAPRI_PIN_SSP5_RXD 220
326 #define CAPRI_PIN_SSP5_TXD 221
327 #define CAPRI_PIN_SSP6_CLK 222
328 #define CAPRI_PIN_SSP6_FS 223
329 #define CAPRI_PIN_SSP6_RXD 224
330 #define CAPRI_PIN_SSP6_TXD 225
331 #define CAPRI_PIN_STAT_1 226
332 #define CAPRI_PIN_STAT_2 227
333 #define CAPRI_PIN_SYSCLKEN 228
334 #define CAPRI_PIN_TRACECLK 229
335 #define CAPRI_PIN_TRACEDT00 230
336 #define CAPRI_PIN_TRACEDT01 231
337 #define CAPRI_PIN_TRACEDT02 232
338 #define CAPRI_PIN_TRACEDT03 233
339 #define CAPRI_PIN_TRACEDT04 234
340 #define CAPRI_PIN_TRACEDT05 235
341 #define CAPRI_PIN_TRACEDT06 236
342 #define CAPRI_PIN_TRACEDT07 237
343 #define CAPRI_PIN_TRACEDT08 238
344 #define CAPRI_PIN_TRACEDT09 239
345 #define CAPRI_PIN_TRACEDT10 240
346 #define CAPRI_PIN_TRACEDT11 241
347 #define CAPRI_PIN_TRACEDT12 242
348 #define CAPRI_PIN_TRACEDT13 243
349 #define CAPRI_PIN_TRACEDT14 244
350 #define CAPRI_PIN_TRACEDT15 245
351 #define CAPRI_PIN_TXDATA3G0 246
352 #define CAPRI_PIN_TXPWRIND 247
353 #define CAPRI_PIN_UARTB1_UCTS 248
354 #define CAPRI_PIN_UARTB1_URTS 249
355 #define CAPRI_PIN_UARTB1_URXD 250
356 #define CAPRI_PIN_UARTB1_UTXD 251
357 #define CAPRI_PIN_UARTB2_URXD 252
358 #define CAPRI_PIN_UARTB2_UTXD 253
359 #define CAPRI_PIN_UARTB3_UCTS 254
360 #define CAPRI_PIN_UARTB3_URTS 255
361 #define CAPRI_PIN_UARTB3_URXD 256
362 #define CAPRI_PIN_UARTB3_UTXD 257
363 #define CAPRI_PIN_UARTB4_UCTS 258
364 #define CAPRI_PIN_UARTB4_URTS 259
365 #define CAPRI_PIN_UARTB4_URXD 260
366 #define CAPRI_PIN_UARTB4_UTXD 261
367 #define CAPRI_PIN_VC_CAM1_SCL 262
368 #define CAPRI_PIN_VC_CAM1_SDA 263
369 #define CAPRI_PIN_VC_CAM2_SCL 264
370 #define CAPRI_PIN_VC_CAM2_SDA 265
371 #define CAPRI_PIN_VC_CAM3_SCL 266
372 #define CAPRI_PIN_VC_CAM3_SDA 267
373
374 #define CAPRI_PIN_DESC(a, b, c) \
375 { .number = a, .name = b, .drv_data = &c##_pin }
376
377 /*
378 * Pin description definition. The order here must be the same as defined in
379 * the PADCTRLREG block in the RDB, since the pin number is used as an index
380 * into this array.
381 */
382 static const struct pinctrl_pin_desc capri_pinctrl_pins[] = {
383 CAPRI_PIN_DESC(CAPRI_PIN_ADCSYNC, "adcsync", std),
384 CAPRI_PIN_DESC(CAPRI_PIN_BAT_RM, "bat_rm", std),
385 CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SCL, "bsc1_scl", i2c),
386 CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SDA, "bsc1_sda", i2c),
387 CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SCL, "bsc2_scl", i2c),
388 CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SDA, "bsc2_sda", i2c),
389 CAPRI_PIN_DESC(CAPRI_PIN_CLASSGPWR, "classgpwr", std),
390 CAPRI_PIN_DESC(CAPRI_PIN_CLK_CX8, "clk_cx8", std),
391 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_0, "clkout_0", std),
392 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_1, "clkout_1", std),
393 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_2, "clkout_2", std),
394 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_3, "clkout_3", std),
395 CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
396 CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
397 CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
398 CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
399 CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
400 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_CLK, "digmic1_clk", std),
401 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_DQ, "digmic1_dq", std),
402 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_CLK, "digmic2_clk", std),
403 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_DQ, "digmic2_dq", std),
404 CAPRI_PIN_DESC(CAPRI_PIN_GPEN13, "gpen13", std),
405 CAPRI_PIN_DESC(CAPRI_PIN_GPEN14, "gpen14", std),
406 CAPRI_PIN_DESC(CAPRI_PIN_GPEN15, "gpen15", std),
407 CAPRI_PIN_DESC(CAPRI_PIN_GPIO00, "gpio00", std),
408 CAPRI_PIN_DESC(CAPRI_PIN_GPIO01, "gpio01", std),
409 CAPRI_PIN_DESC(CAPRI_PIN_GPIO02, "gpio02", std),
410 CAPRI_PIN_DESC(CAPRI_PIN_GPIO03, "gpio03", std),
411 CAPRI_PIN_DESC(CAPRI_PIN_GPIO04, "gpio04", std),
412 CAPRI_PIN_DESC(CAPRI_PIN_GPIO05, "gpio05", std),
413 CAPRI_PIN_DESC(CAPRI_PIN_GPIO06, "gpio06", std),
414 CAPRI_PIN_DESC(CAPRI_PIN_GPIO07, "gpio07", std),
415 CAPRI_PIN_DESC(CAPRI_PIN_GPIO08, "gpio08", std),
416 CAPRI_PIN_DESC(CAPRI_PIN_GPIO09, "gpio09", std),
417 CAPRI_PIN_DESC(CAPRI_PIN_GPIO10, "gpio10", std),
418 CAPRI_PIN_DESC(CAPRI_PIN_GPIO11, "gpio11", std),
419 CAPRI_PIN_DESC(CAPRI_PIN_GPIO12, "gpio12", std),
420 CAPRI_PIN_DESC(CAPRI_PIN_GPIO13, "gpio13", std),
421 CAPRI_PIN_DESC(CAPRI_PIN_GPIO14, "gpio14", std),
422 CAPRI_PIN_DESC(CAPRI_PIN_GPS_PABLANK, "gps_pablank", std),
423 CAPRI_PIN_DESC(CAPRI_PIN_GPS_TMARK, "gps_tmark", std),
424 CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SCL, "hdmi_scl", hdmi),
425 CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SDA, "hdmi_sda", hdmi),
426 CAPRI_PIN_DESC(CAPRI_PIN_IC_DM, "ic_dm", std),
427 CAPRI_PIN_DESC(CAPRI_PIN_IC_DP, "ic_dp", std),
428 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
429 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
430 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
431 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
432 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
433 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
434 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
435 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
436 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_0, "lcd_b_0", std),
437 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_1, "lcd_b_1", std),
438 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_2, "lcd_b_2", std),
439 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_3, "lcd_b_3", std),
440 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_4, "lcd_b_4", std),
441 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_5, "lcd_b_5", std),
442 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_6, "lcd_b_6", std),
443 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_7, "lcd_b_7", std),
444 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_0, "lcd_g_0", std),
445 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_1, "lcd_g_1", std),
446 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_2, "lcd_g_2", std),
447 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_3, "lcd_g_3", std),
448 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_4, "lcd_g_4", std),
449 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_5, "lcd_g_5", std),
450 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_6, "lcd_g_6", std),
451 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_7, "lcd_g_7", std),
452 CAPRI_PIN_DESC(CAPRI_PIN_LCD_HSYNC, "lcd_hsync", std),
453 CAPRI_PIN_DESC(CAPRI_PIN_LCD_OE, "lcd_oe", std),
454 CAPRI_PIN_DESC(CAPRI_PIN_LCD_PCLK, "lcd_pclk", std),
455 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_0, "lcd_r_0", std),
456 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_1, "lcd_r_1", std),
457 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_2, "lcd_r_2", std),
458 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_3, "lcd_r_3", std),
459 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_4, "lcd_r_4", std),
460 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_5, "lcd_r_5", std),
461 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_6, "lcd_r_6", std),
462 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_7, "lcd_r_7", std),
463 CAPRI_PIN_DESC(CAPRI_PIN_LCD_VSYNC, "lcd_vsync", std),
464 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO0, "mdmgpio0", std),
465 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO1, "mdmgpio1", std),
466 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO2, "mdmgpio2", std),
467 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO3, "mdmgpio3", std),
468 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO4, "mdmgpio4", std),
469 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO5, "mdmgpio5", std),
470 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO6, "mdmgpio6", std),
471 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO7, "mdmgpio7", std),
472 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO8, "mdmgpio8", std),
473 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_0, "mphi_data_0", std),
474 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_1, "mphi_data_1", std),
475 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_2, "mphi_data_2", std),
476 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_3, "mphi_data_3", std),
477 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_4, "mphi_data_4", std),
478 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_5, "mphi_data_5", std),
479 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_6, "mphi_data_6", std),
480 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_7, "mphi_data_7", std),
481 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_8, "mphi_data_8", std),
482 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_9, "mphi_data_9", std),
483 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_10, "mphi_data_10", std),
484 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_11, "mphi_data_11", std),
485 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_12, "mphi_data_12", std),
486 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_13, "mphi_data_13", std),
487 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_14, "mphi_data_14", std),
488 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_15, "mphi_data_15", std),
489 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HA0, "mphi_ha0", std),
490 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT0, "mphi_hat0", std),
491 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT1, "mphi_hat1", std),
492 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
493 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
494 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
495 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
496 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN0, "mphi_run0", std),
497 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN1, "mphi_run1", std),
498 CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
499 CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
500 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_0, "nand_ad_0", std),
501 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_1, "nand_ad_1", std),
502 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_2, "nand_ad_2", std),
503 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_3, "nand_ad_3", std),
504 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_4, "nand_ad_4", std),
505 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_5, "nand_ad_5", std),
506 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_6, "nand_ad_6", std),
507 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_7, "nand_ad_7", std),
508 CAPRI_PIN_DESC(CAPRI_PIN_NAND_ALE, "nand_ale", std),
509 CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_0, "nand_cen_0", std),
510 CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_1, "nand_cen_1", std),
511 CAPRI_PIN_DESC(CAPRI_PIN_NAND_CLE, "nand_cle", std),
512 CAPRI_PIN_DESC(CAPRI_PIN_NAND_OEN, "nand_oen", std),
513 CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_0, "nand_rdy_0", std),
514 CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_1, "nand_rdy_1", std),
515 CAPRI_PIN_DESC(CAPRI_PIN_NAND_WEN, "nand_wen", std),
516 CAPRI_PIN_DESC(CAPRI_PIN_NAND_WP, "nand_wp", std),
517 CAPRI_PIN_DESC(CAPRI_PIN_PC1, "pc1", std),
518 CAPRI_PIN_DESC(CAPRI_PIN_PC2, "pc2", std),
519 CAPRI_PIN_DESC(CAPRI_PIN_PMU_INT, "pmu_int", std),
520 CAPRI_PIN_DESC(CAPRI_PIN_PMU_SCL, "pmu_scl", i2c),
521 CAPRI_PIN_DESC(CAPRI_PIN_PMU_SDA, "pmu_sda", i2c),
522 CAPRI_PIN_DESC(CAPRI_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std),
523 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
524 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
525 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
526 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
527 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
528 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
529 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
530 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
531 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
532 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
533 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
534 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
535 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
536 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
537 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
538 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
539 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
540 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
541 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
542 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
543 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
544 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
545 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
546 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
547 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
548 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
549 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
550 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
551 CAPRI_PIN_DESC(CAPRI_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1",
552 std),
553 CAPRI_PIN_DESC(CAPRI_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std),
554 CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G0, "rxdata3g0", std),
555 CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G1, "rxdata3g1", std),
556 CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G2, "rxdata3g2", std),
557 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CLK, "sdio1_clk", std),
558 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CMD, "sdio1_cmd", std),
559 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
560 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
561 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
562 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
563 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CLK, "sdio4_clk", std),
564 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CMD, "sdio4_cmd", std),
565 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
566 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
567 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
568 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
569 CAPRI_PIN_DESC(CAPRI_PIN_SIM_CLK, "sim_clk", std),
570 CAPRI_PIN_DESC(CAPRI_PIN_SIM_DATA, "sim_data", std),
571 CAPRI_PIN_DESC(CAPRI_PIN_SIM_DET, "sim_det", std),
572 CAPRI_PIN_DESC(CAPRI_PIN_SIM_RESETN, "sim_resetn", std),
573 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_CLK, "sim2_clk", std),
574 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DATA, "sim2_data", std),
575 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DET, "sim2_det", std),
576 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_RESETN, "sim2_resetn", std),
577 CAPRI_PIN_DESC(CAPRI_PIN_SRI_C, "sri_c", std),
578 CAPRI_PIN_DESC(CAPRI_PIN_SRI_D, "sri_d", std),
579 CAPRI_PIN_DESC(CAPRI_PIN_SRI_E, "sri_e", std),
580 CAPRI_PIN_DESC(CAPRI_PIN_SSP_EXTCLK, "ssp_extclk", std),
581 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_CLK, "ssp0_clk", std),
582 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_FS, "ssp0_fs", std),
583 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_RXD, "ssp0_rxd", std),
584 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_TXD, "ssp0_txd", std),
585 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_CLK, "ssp2_clk", std),
586 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_0, "ssp2_fs_0", std),
587 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_1, "ssp2_fs_1", std),
588 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_2, "ssp2_fs_2", std),
589 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_3, "ssp2_fs_3", std),
590 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
591 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
592 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
593 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
594 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_CLK, "ssp3_clk", std),
595 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_FS, "ssp3_fs", std),
596 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_RXD, "ssp3_rxd", std),
597 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_TXD, "ssp3_txd", std),
598 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_CLK, "ssp4_clk", std),
599 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_FS, "ssp4_fs", std),
600 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_RXD, "ssp4_rxd", std),
601 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_TXD, "ssp4_txd", std),
602 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_CLK, "ssp5_clk", std),
603 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_FS, "ssp5_fs", std),
604 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_RXD, "ssp5_rxd", std),
605 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_TXD, "ssp5_txd", std),
606 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_CLK, "ssp6_clk", std),
607 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_FS, "ssp6_fs", std),
608 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_RXD, "ssp6_rxd", std),
609 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_TXD, "ssp6_txd", std),
610 CAPRI_PIN_DESC(CAPRI_PIN_STAT_1, "stat_1", std),
611 CAPRI_PIN_DESC(CAPRI_PIN_STAT_2, "stat_2", std),
612 CAPRI_PIN_DESC(CAPRI_PIN_SYSCLKEN, "sysclken", std),
613 CAPRI_PIN_DESC(CAPRI_PIN_TRACECLK, "traceclk", std),
614 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT00, "tracedt00", std),
615 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT01, "tracedt01", std),
616 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT02, "tracedt02", std),
617 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT03, "tracedt03", std),
618 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT04, "tracedt04", std),
619 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT05, "tracedt05", std),
620 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT06, "tracedt06", std),
621 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT07, "tracedt07", std),
622 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT08, "tracedt08", std),
623 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT09, "tracedt09", std),
624 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT10, "tracedt10", std),
625 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT11, "tracedt11", std),
626 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT12, "tracedt12", std),
627 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT13, "tracedt13", std),
628 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT14, "tracedt14", std),
629 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT15, "tracedt15", std),
630 CAPRI_PIN_DESC(CAPRI_PIN_TXDATA3G0, "txdata3g0", std),
631 CAPRI_PIN_DESC(CAPRI_PIN_TXPWRIND, "txpwrind", std),
632 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UCTS, "uartb1_ucts", std),
633 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URTS, "uartb1_urts", std),
634 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URXD, "uartb1_urxd", std),
635 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UTXD, "uartb1_utxd", std),
636 CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_URXD, "uartb2_urxd", std),
637 CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_UTXD, "uartb2_utxd", std),
638 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UCTS, "uartb3_ucts", std),
639 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URTS, "uartb3_urts", std),
640 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URXD, "uartb3_urxd", std),
641 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UTXD, "uartb3_utxd", std),
642 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UCTS, "uartb4_ucts", std),
643 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URTS, "uartb4_urts", std),
644 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URXD, "uartb4_urxd", std),
645 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UTXD, "uartb4_utxd", std),
646 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
647 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
648 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
649 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
650 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
651 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
652 };
653
654 static const char * const capri_alt_groups[] = {
655 "adcsync",
656 "bat_rm",
657 "bsc1_scl",
658 "bsc1_sda",
659 "bsc2_scl",
660 "bsc2_sda",
661 "classgpwr",
662 "clk_cx8",
663 "clkout_0",
664 "clkout_1",
665 "clkout_2",
666 "clkout_3",
667 "clkreq_in_0",
668 "clkreq_in_1",
669 "cws_sys_req1",
670 "cws_sys_req2",
671 "cws_sys_req3",
672 "digmic1_clk",
673 "digmic1_dq",
674 "digmic2_clk",
675 "digmic2_dq",
676 "gpen13",
677 "gpen14",
678 "gpen15",
679 "gpio00",
680 "gpio01",
681 "gpio02",
682 "gpio03",
683 "gpio04",
684 "gpio05",
685 "gpio06",
686 "gpio07",
687 "gpio08",
688 "gpio09",
689 "gpio10",
690 "gpio11",
691 "gpio12",
692 "gpio13",
693 "gpio14",
694 "gps_pablank",
695 "gps_tmark",
696 "hdmi_scl",
697 "hdmi_sda",
698 "ic_dm",
699 "ic_dp",
700 "kp_col_ip_0",
701 "kp_col_ip_1",
702 "kp_col_ip_2",
703 "kp_col_ip_3",
704 "kp_row_op_0",
705 "kp_row_op_1",
706 "kp_row_op_2",
707 "kp_row_op_3",
708 "lcd_b_0",
709 "lcd_b_1",
710 "lcd_b_2",
711 "lcd_b_3",
712 "lcd_b_4",
713 "lcd_b_5",
714 "lcd_b_6",
715 "lcd_b_7",
716 "lcd_g_0",
717 "lcd_g_1",
718 "lcd_g_2",
719 "lcd_g_3",
720 "lcd_g_4",
721 "lcd_g_5",
722 "lcd_g_6",
723 "lcd_g_7",
724 "lcd_hsync",
725 "lcd_oe",
726 "lcd_pclk",
727 "lcd_r_0",
728 "lcd_r_1",
729 "lcd_r_2",
730 "lcd_r_3",
731 "lcd_r_4",
732 "lcd_r_5",
733 "lcd_r_6",
734 "lcd_r_7",
735 "lcd_vsync",
736 "mdmgpio0",
737 "mdmgpio1",
738 "mdmgpio2",
739 "mdmgpio3",
740 "mdmgpio4",
741 "mdmgpio5",
742 "mdmgpio6",
743 "mdmgpio7",
744 "mdmgpio8",
745 "mphi_data_0",
746 "mphi_data_1",
747 "mphi_data_2",
748 "mphi_data_3",
749 "mphi_data_4",
750 "mphi_data_5",
751 "mphi_data_6",
752 "mphi_data_7",
753 "mphi_data_8",
754 "mphi_data_9",
755 "mphi_data_10",
756 "mphi_data_11",
757 "mphi_data_12",
758 "mphi_data_13",
759 "mphi_data_14",
760 "mphi_data_15",
761 "mphi_ha0",
762 "mphi_hat0",
763 "mphi_hat1",
764 "mphi_hce0_n",
765 "mphi_hce1_n",
766 "mphi_hrd_n",
767 "mphi_hwr_n",
768 "mphi_run0",
769 "mphi_run1",
770 "mtx_scan_clk",
771 "mtx_scan_data",
772 "nand_ad_0",
773 "nand_ad_1",
774 "nand_ad_2",
775 "nand_ad_3",
776 "nand_ad_4",
777 "nand_ad_5",
778 "nand_ad_6",
779 "nand_ad_7",
780 "nand_ale",
781 "nand_cen_0",
782 "nand_cen_1",
783 "nand_cle",
784 "nand_oen",
785 "nand_rdy_0",
786 "nand_rdy_1",
787 "nand_wen",
788 "nand_wp",
789 "pc1",
790 "pc2",
791 "pmu_int",
792 "pmu_scl",
793 "pmu_sda",
794 "rfst2g_mtsloten3g",
795 "rgmii_0_rx_ctl",
796 "rgmii_0_rxc",
797 "rgmii_0_rxd_0",
798 "rgmii_0_rxd_1",
799 "rgmii_0_rxd_2",
800 "rgmii_0_rxd_3",
801 "rgmii_0_tx_ctl",
802 "rgmii_0_txc",
803 "rgmii_0_txd_0",
804 "rgmii_0_txd_1",
805 "rgmii_0_txd_2",
806 "rgmii_0_txd_3",
807 "rgmii_1_rx_ctl",
808 "rgmii_1_rxc",
809 "rgmii_1_rxd_0",
810 "rgmii_1_rxd_1",
811 "rgmii_1_rxd_2",
812 "rgmii_1_rxd_3",
813 "rgmii_1_tx_ctl",
814 "rgmii_1_txc",
815 "rgmii_1_txd_0",
816 "rgmii_1_txd_1",
817 "rgmii_1_txd_2",
818 "rgmii_1_txd_3",
819 "rgmii_gpio_0",
820 "rgmii_gpio_1",
821 "rgmii_gpio_2",
822 "rgmii_gpio_3",
823 "rtxdata2g_txdata3g1",
824 "rtxen2g_txdata3g2",
825 "rxdata3g0",
826 "rxdata3g1",
827 "rxdata3g2",
828 "sdio1_clk",
829 "sdio1_cmd",
830 "sdio1_data_0",
831 "sdio1_data_1",
832 "sdio1_data_2",
833 "sdio1_data_3",
834 "sdio4_clk",
835 "sdio4_cmd",
836 "sdio4_data_0",
837 "sdio4_data_1",
838 "sdio4_data_2",
839 "sdio4_data_3",
840 "sim_clk",
841 "sim_data",
842 "sim_det",
843 "sim_resetn",
844 "sim2_clk",
845 "sim2_data",
846 "sim2_det",
847 "sim2_resetn",
848 "sri_c",
849 "sri_d",
850 "sri_e",
851 "ssp_extclk",
852 "ssp0_clk",
853 "ssp0_fs",
854 "ssp0_rxd",
855 "ssp0_txd",
856 "ssp2_clk",
857 "ssp2_fs_0",
858 "ssp2_fs_1",
859 "ssp2_fs_2",
860 "ssp2_fs_3",
861 "ssp2_rxd_0",
862 "ssp2_rxd_1",
863 "ssp2_txd_0",
864 "ssp2_txd_1",
865 "ssp3_clk",
866 "ssp3_fs",
867 "ssp3_rxd",
868 "ssp3_txd",
869 "ssp4_clk",
870 "ssp4_fs",
871 "ssp4_rxd",
872 "ssp4_txd",
873 "ssp5_clk",
874 "ssp5_fs",
875 "ssp5_rxd",
876 "ssp5_txd",
877 "ssp6_clk",
878 "ssp6_fs",
879 "ssp6_rxd",
880 "ssp6_txd",
881 "stat_1",
882 "stat_2",
883 "sysclken",
884 "traceclk",
885 "tracedt00",
886 "tracedt01",
887 "tracedt02",
888 "tracedt03",
889 "tracedt04",
890 "tracedt05",
891 "tracedt06",
892 "tracedt07",
893 "tracedt08",
894 "tracedt09",
895 "tracedt10",
896 "tracedt11",
897 "tracedt12",
898 "tracedt13",
899 "tracedt14",
900 "tracedt15",
901 "txdata3g0",
902 "txpwrind",
903 "uartb1_ucts",
904 "uartb1_urts",
905 "uartb1_urxd",
906 "uartb1_utxd",
907 "uartb2_urxd",
908 "uartb2_utxd",
909 "uartb3_ucts",
910 "uartb3_urts",
911 "uartb3_urxd",
912 "uartb3_utxd",
913 "uartb4_ucts",
914 "uartb4_urts",
915 "uartb4_urxd",
916 "uartb4_utxd",
917 "vc_cam1_scl",
918 "vc_cam1_sda",
919 "vc_cam2_scl",
920 "vc_cam2_sda",
921 "vc_cam3_scl",
922 "vc_cam3_sda",
923 };
924
925 /* Every pin can implement all ALT1-ALT4 functions */
926 #define CAPRI_PIN_FUNCTION(fcn_name) \
927 { \
928 .name = #fcn_name, \
929 .groups = capri_alt_groups, \
930 .ngroups = ARRAY_SIZE(capri_alt_groups), \
931 }
932
933 static const struct capri_pin_function capri_functions[] = {
934 CAPRI_PIN_FUNCTION(alt1),
935 CAPRI_PIN_FUNCTION(alt2),
936 CAPRI_PIN_FUNCTION(alt3),
937 CAPRI_PIN_FUNCTION(alt4),
938 };
939
940 static struct capri_pinctrl_data capri_pinctrl = {
941 .pins = capri_pinctrl_pins,
942 .npins = ARRAY_SIZE(capri_pinctrl_pins),
943 .functions = capri_functions,
944 .nfunctions = ARRAY_SIZE(capri_functions),
945 };
946
947 static inline enum capri_pin_type pin_type_get(struct pinctrl_dev *pctldev,
948 unsigned pin)
949 {
950 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
951
952 if (pin >= pdata->npins)
953 return CAPRI_PIN_TYPE_UNKNOWN;
954
955 return *(enum capri_pin_type *)(pdata->pins[pin].drv_data);
956 }
957
958 #define CAPRI_PIN_SHIFT(type, param) \
959 (CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT)
960
961 #define CAPRI_PIN_MASK(type, param) \
962 (CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK)
963
964 /*
965 * This helper function is used to build up the value and mask used to write to
966 * a pin register, but does not actually write to the register.
967 */
968 static inline void capri_pin_update(u32 *reg_val, u32 *reg_mask, u32 param_val,
969 u32 param_shift, u32 param_mask)
970 {
971 *reg_val &= ~param_mask;
972 *reg_val |= (param_val << param_shift) & param_mask;
973 *reg_mask |= param_mask;
974 }
975
976 static struct regmap_config capri_pinctrl_regmap_config = {
977 .reg_bits = 32,
978 .reg_stride = 4,
979 .val_bits = 32,
980 .max_register = CAPRI_PIN_VC_CAM3_SDA,
981 };
982
983 static int capri_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
984 {
985 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
986
987 return pdata->npins;
988 }
989
990 static const char *capri_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
991 unsigned group)
992 {
993 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
994
995 return pdata->pins[group].name;
996 }
997
998 static int capri_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
999 unsigned group,
1000 const unsigned **pins,
1001 unsigned *num_pins)
1002 {
1003 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1004
1005 *pins = &pdata->pins[group].number;
1006 *num_pins = 1;
1007
1008 return 0;
1009 }
1010
1011 static void capri_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1012 struct seq_file *s,
1013 unsigned offset)
1014 {
1015 seq_printf(s, " %s", dev_name(pctldev->dev));
1016 }
1017
1018 static struct pinctrl_ops capri_pinctrl_ops = {
1019 .get_groups_count = capri_pinctrl_get_groups_count,
1020 .get_group_name = capri_pinctrl_get_group_name,
1021 .get_group_pins = capri_pinctrl_get_group_pins,
1022 .pin_dbg_show = capri_pinctrl_pin_dbg_show,
1023 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1024 .dt_free_map = pinctrl_utils_dt_free_map,
1025 };
1026
1027 static int capri_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1028 {
1029 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1030
1031 return pdata->nfunctions;
1032 }
1033
1034 static const char *capri_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1035 unsigned function)
1036 {
1037 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1038
1039 return pdata->functions[function].name;
1040 }
1041
1042 static int capri_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1043 unsigned function,
1044 const char * const **groups,
1045 unsigned * const num_groups)
1046 {
1047 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1048
1049 *groups = pdata->functions[function].groups;
1050 *num_groups = pdata->functions[function].ngroups;
1051
1052 return 0;
1053 }
1054
1055 static int capri_pinmux_enable(struct pinctrl_dev *pctldev,
1056 unsigned function,
1057 unsigned group)
1058 {
1059 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1060 const struct capri_pin_function *f = &pdata->functions[function];
1061 u32 offset = 4 * pdata->pins[group].number;
1062 int rc = 0;
1063
1064 dev_dbg(pctldev->dev,
1065 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1066 __func__, f->name, function, pdata->pins[group].name,
1067 pdata->pins[group].number, offset);
1068
1069 rc = regmap_update_bits(pdata->regmap, offset, CAPRI_PIN_REG_F_SEL_MASK,
1070 function << CAPRI_PIN_REG_F_SEL_SHIFT);
1071 if (rc)
1072 dev_err(pctldev->dev,
1073 "Error updating register for pin %s (%d).\n",
1074 pdata->pins[group].name, pdata->pins[group].number);
1075
1076 return rc;
1077 }
1078
1079 static struct pinmux_ops capri_pinctrl_pinmux_ops = {
1080 .get_functions_count = capri_pinctrl_get_fcns_count,
1081 .get_function_name = capri_pinctrl_get_fcn_name,
1082 .get_function_groups = capri_pinctrl_get_fcn_groups,
1083 .enable = capri_pinmux_enable,
1084 };
1085
1086 static int capri_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1087 unsigned pin,
1088 unsigned long *config)
1089 {
1090 return -ENOTSUPP;
1091 }
1092
1093
1094 /* Goes through the configs and update register val/mask */
1095 static int capri_std_pin_update(struct pinctrl_dev *pctldev,
1096 unsigned pin,
1097 unsigned long *configs,
1098 unsigned num_configs,
1099 u32 *val,
1100 u32 *mask)
1101 {
1102 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1103 int i;
1104 enum pin_config_param param;
1105 u16 arg;
1106
1107 for (i = 0; i < num_configs; i++) {
1108 param = pinconf_to_config_param(configs[i]);
1109 arg = pinconf_to_config_argument(configs[i]);
1110
1111 switch (param) {
1112 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1113 arg = (arg >= 1 ? 1 : 0);
1114 capri_pin_update(val, mask, arg,
1115 CAPRI_PIN_SHIFT(STD, HYST),
1116 CAPRI_PIN_MASK(STD, HYST));
1117 break;
1118 /*
1119 * The pin bias can only be one of pull-up, pull-down, or
1120 * disable. The user does not need to specify a value for the
1121 * property, and the default value from pinconf-generic is
1122 * ignored.
1123 */
1124 case PIN_CONFIG_BIAS_DISABLE:
1125 capri_pin_update(val, mask, 0,
1126 CAPRI_PIN_SHIFT(STD, PULL_UP),
1127 CAPRI_PIN_MASK(STD, PULL_UP));
1128 capri_pin_update(val, mask, 0,
1129 CAPRI_PIN_SHIFT(STD, PULL_DN),
1130 CAPRI_PIN_MASK(STD, PULL_DN));
1131 break;
1132
1133 case PIN_CONFIG_BIAS_PULL_UP:
1134 capri_pin_update(val, mask, 1,
1135 CAPRI_PIN_SHIFT(STD, PULL_UP),
1136 CAPRI_PIN_MASK(STD, PULL_UP));
1137 capri_pin_update(val, mask, 0,
1138 CAPRI_PIN_SHIFT(STD, PULL_DN),
1139 CAPRI_PIN_MASK(STD, PULL_DN));
1140 break;
1141
1142 case PIN_CONFIG_BIAS_PULL_DOWN:
1143 capri_pin_update(val, mask, 0,
1144 CAPRI_PIN_SHIFT(STD, PULL_UP),
1145 CAPRI_PIN_MASK(STD, PULL_UP));
1146 capri_pin_update(val, mask, 1,
1147 CAPRI_PIN_SHIFT(STD, PULL_DN),
1148 CAPRI_PIN_MASK(STD, PULL_DN));
1149 break;
1150
1151 case PIN_CONFIG_SLEW_RATE:
1152 arg = (arg >= 1 ? 1 : 0);
1153 capri_pin_update(val, mask, arg,
1154 CAPRI_PIN_SHIFT(STD, SLEW),
1155 CAPRI_PIN_MASK(STD, SLEW));
1156 break;
1157
1158 case PIN_CONFIG_INPUT_ENABLE:
1159 /* inversed since register is for input _disable_ */
1160 arg = (arg >= 1 ? 0 : 1);
1161 capri_pin_update(val, mask, arg,
1162 CAPRI_PIN_SHIFT(STD, INPUT_DIS),
1163 CAPRI_PIN_MASK(STD, INPUT_DIS));
1164 break;
1165
1166 case PIN_CONFIG_DRIVE_STRENGTH:
1167 /* Valid range is 2-16 mA, even numbers only */
1168 if ((arg < 2) || (arg > 16) || (arg % 2)) {
1169 dev_err(pctldev->dev,
1170 "Invalid Drive Strength value (%d) for "
1171 "pin %s (%d). Valid values are "
1172 "(2..16) mA, even numbers only.\n",
1173 arg, pdata->pins[pin].name, pin);
1174 return -EINVAL;
1175 }
1176 capri_pin_update(val, mask, (arg/2)-1,
1177 CAPRI_PIN_SHIFT(STD, DRV_STR),
1178 CAPRI_PIN_MASK(STD, DRV_STR));
1179 break;
1180
1181 default:
1182 dev_err(pctldev->dev,
1183 "Unrecognized pin config %d for pin %s (%d).\n",
1184 param, pdata->pins[pin].name, pin);
1185 return -EINVAL;
1186
1187 } /* switch config */
1188 } /* for each config */
1189
1190 return 0;
1191 }
1192
1193 /*
1194 * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1195 * register with the following mapping:
1196 * 0b000: No pull-up
1197 * 0b001: 1200 Ohm
1198 * 0b010: 1800 Ohm
1199 * 0b011: 720 Ohm
1200 * 0b100: 2700 Ohm
1201 * 0b101: 831 Ohm
1202 * 0b110: 1080 Ohm
1203 * 0b111: 568 Ohm
1204 * This array maps pull-up strength in Ohms to register values (1+index).
1205 */
1206 static const u16 capri_pullup_map[] = {1200, 1800, 720, 2700, 831, 1080, 568};
1207
1208 /* Goes through the configs and update register val/mask */
1209 static int capri_i2c_pin_update(struct pinctrl_dev *pctldev,
1210 unsigned pin,
1211 unsigned long *configs,
1212 unsigned num_configs,
1213 u32 *val,
1214 u32 *mask)
1215 {
1216 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1217 int i, j;
1218 enum pin_config_param param;
1219 u16 arg;
1220
1221 for (i = 0; i < num_configs; i++) {
1222 param = pinconf_to_config_param(configs[i]);
1223 arg = pinconf_to_config_argument(configs[i]);
1224
1225 switch (param) {
1226 case PIN_CONFIG_BIAS_PULL_UP:
1227 for (j = 0; j < ARRAY_SIZE(capri_pullup_map); j++)
1228 if (capri_pullup_map[j] == arg)
1229 break;
1230
1231 if (j == ARRAY_SIZE(capri_pullup_map)) {
1232 dev_err(pctldev->dev,
1233 "Invalid pull-up value (%d) for pin %s "
1234 "(%d). Valid values are 568, 720, 831, "
1235 "1080, 1200, 1800, 2700 Ohms.\n",
1236 arg, pdata->pins[pin].name, pin);
1237 return -EINVAL;
1238 }
1239
1240 capri_pin_update(val, mask, j+1,
1241 CAPRI_PIN_SHIFT(I2C, PULL_UP_STR),
1242 CAPRI_PIN_MASK(I2C, PULL_UP_STR));
1243 break;
1244
1245 case PIN_CONFIG_BIAS_DISABLE:
1246 capri_pin_update(val, mask, 0,
1247 CAPRI_PIN_SHIFT(I2C, PULL_UP_STR),
1248 CAPRI_PIN_MASK(I2C, PULL_UP_STR));
1249 break;
1250
1251 case PIN_CONFIG_SLEW_RATE:
1252 arg = (arg >= 1 ? 1 : 0);
1253 capri_pin_update(val, mask, arg,
1254 CAPRI_PIN_SHIFT(I2C, SLEW),
1255 CAPRI_PIN_MASK(I2C, SLEW));
1256 break;
1257
1258 case PIN_CONFIG_INPUT_ENABLE:
1259 /* inversed since register is for input _disable_ */
1260 arg = (arg >= 1 ? 0 : 1);
1261 capri_pin_update(val, mask, arg,
1262 CAPRI_PIN_SHIFT(I2C, INPUT_DIS),
1263 CAPRI_PIN_MASK(I2C, INPUT_DIS));
1264 break;
1265
1266 default:
1267 dev_err(pctldev->dev,
1268 "Unrecognized pin config %d for pin %s (%d).\n",
1269 param, pdata->pins[pin].name, pin);
1270 return -EINVAL;
1271
1272 } /* switch config */
1273 } /* for each config */
1274
1275 return 0;
1276 }
1277
1278 /* Goes through the configs and update register val/mask */
1279 static int capri_hdmi_pin_update(struct pinctrl_dev *pctldev,
1280 unsigned pin,
1281 unsigned long *configs,
1282 unsigned num_configs,
1283 u32 *val,
1284 u32 *mask)
1285 {
1286 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1287 int i;
1288 enum pin_config_param param;
1289 u16 arg;
1290
1291 for (i = 0; i < num_configs; i++) {
1292 param = pinconf_to_config_param(configs[i]);
1293 arg = pinconf_to_config_argument(configs[i]);
1294
1295 switch (param) {
1296 case PIN_CONFIG_SLEW_RATE:
1297 arg = (arg >= 1 ? 1 : 0);
1298 capri_pin_update(val, mask, arg,
1299 CAPRI_PIN_SHIFT(HDMI, MODE),
1300 CAPRI_PIN_MASK(HDMI, MODE));
1301 break;
1302
1303 case PIN_CONFIG_INPUT_ENABLE:
1304 /* inversed since register is for input _disable_ */
1305 arg = (arg >= 1 ? 0 : 1);
1306 capri_pin_update(val, mask, arg,
1307 CAPRI_PIN_SHIFT(HDMI, INPUT_DIS),
1308 CAPRI_PIN_MASK(HDMI, INPUT_DIS));
1309 break;
1310
1311 default:
1312 dev_err(pctldev->dev,
1313 "Unrecognized pin config %d for pin %s (%d).\n",
1314 param, pdata->pins[pin].name, pin);
1315 return -EINVAL;
1316
1317 } /* switch config */
1318 } /* for each config */
1319
1320 return 0;
1321 }
1322
1323 static int capri_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1324 unsigned pin,
1325 unsigned long *configs,
1326 unsigned num_configs)
1327 {
1328 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1329 enum capri_pin_type pin_type;
1330 u32 offset = 4 * pin;
1331 u32 cfg_val, cfg_mask;
1332 int rc;
1333
1334 cfg_val = 0;
1335 cfg_mask = 0;
1336 pin_type = pin_type_get(pctldev, pin);
1337
1338 /* Different pins have different configuration options */
1339 switch (pin_type) {
1340 case CAPRI_PIN_TYPE_STD:
1341 rc = capri_std_pin_update(pctldev, pin, configs, num_configs,
1342 &cfg_val, &cfg_mask);
1343 break;
1344
1345 case CAPRI_PIN_TYPE_I2C:
1346 rc = capri_i2c_pin_update(pctldev, pin, configs, num_configs,
1347 &cfg_val, &cfg_mask);
1348 break;
1349
1350 case CAPRI_PIN_TYPE_HDMI:
1351 rc = capri_hdmi_pin_update(pctldev, pin, configs, num_configs,
1352 &cfg_val, &cfg_mask);
1353 break;
1354
1355 default:
1356 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1357 pdata->pins[pin].name, pin);
1358 return -EINVAL;
1359
1360 } /* switch pin type */
1361
1362 if (rc)
1363 return rc;
1364
1365 dev_dbg(pctldev->dev,
1366 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1367 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1368
1369 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1370 if (rc) {
1371 dev_err(pctldev->dev,
1372 "Error updating register for pin %s (%d).\n",
1373 pdata->pins[pin].name, pin);
1374 return rc;
1375 }
1376
1377 return 0;
1378 }
1379
1380 static struct pinconf_ops capri_pinctrl_pinconf_ops = {
1381 .pin_config_get = capri_pinctrl_pin_config_get,
1382 .pin_config_set = capri_pinctrl_pin_config_set,
1383 };
1384
1385 static struct pinctrl_desc capri_pinctrl_desc = {
1386 /* name, pins, npins members initialized in probe function */
1387 .pctlops = &capri_pinctrl_ops,
1388 .pmxops = &capri_pinctrl_pinmux_ops,
1389 .confops = &capri_pinctrl_pinconf_ops,
1390 .owner = THIS_MODULE,
1391 };
1392
1393 int __init capri_pinctrl_probe(struct platform_device *pdev)
1394 {
1395 struct capri_pinctrl_data *pdata = &capri_pinctrl;
1396 struct resource *res;
1397 struct pinctrl_dev *pctl;
1398
1399 /* So far We can assume there is only 1 bank of registers */
1400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1401 if (!res) {
1402 dev_err(&pdev->dev, "Missing MEM resource\n");
1403 return -ENODEV;
1404 }
1405
1406 pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
1407 if (IS_ERR(pdata->reg_base)) {
1408 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1409 return -ENODEV;
1410 }
1411
1412 /* Initialize the dynamic part of pinctrl_desc */
1413 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1414 &capri_pinctrl_regmap_config);
1415 if (IS_ERR(pdata->regmap)) {
1416 dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1417 return -ENODEV;
1418 }
1419
1420 capri_pinctrl_desc.name = dev_name(&pdev->dev);
1421 capri_pinctrl_desc.pins = capri_pinctrl.pins;
1422 capri_pinctrl_desc.npins = capri_pinctrl.npins;
1423
1424 pctl = pinctrl_register(&capri_pinctrl_desc,
1425 &pdev->dev,
1426 pdata);
1427 if (!pctl) {
1428 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1429 return -ENODEV;
1430 }
1431
1432 platform_set_drvdata(pdev, pdata);
1433
1434 return 0;
1435 }
1436
1437 static struct of_device_id capri_pinctrl_of_match[] = {
1438 { .compatible = "brcm,capri-pinctrl", },
1439 { },
1440 };
1441
1442 static struct platform_driver capri_pinctrl_driver = {
1443 .driver = {
1444 .name = "bcm-capri-pinctrl",
1445 .owner = THIS_MODULE,
1446 .of_match_table = capri_pinctrl_of_match,
1447 },
1448 };
1449
1450 module_platform_driver_probe(capri_pinctrl_driver, capri_pinctrl_probe);
1451
1452 MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>");
1453 MODULE_DESCRIPTION("Broadcom Capri pinctrl driver");
1454 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support