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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a7740.c
blob6c83ce43a9400cd0018c6fe8b11785068030b438
1 /*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24
25 #include <mach/irqs.h>
26
27 #include "core.h"
28 #include "sh_pfc.h"
29
30 #define CPU_ALL_PORT(fn, pfx, sfx) \
31 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
32 PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
33 PORT_10(200, fn, pfx##20, sfx), \
34 PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
35
36 #define IRQC_PIN_MUX(irq, pin) \
37 static const unsigned int intc_irq##irq##_pins[] = { \
38 pin, \
39 }; \
40 static const unsigned int intc_irq##irq##_mux[] = { \
41 IRQ##irq##_MARK, \
42 }
43
44 #define IRQC_PINS_MUX(irq, idx, pin) \
45 static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
46 pin, \
47 }; \
48 static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
49 IRQ##irq##_PORT##pin##_MARK, \
50 }
51
52 enum {
53 PINMUX_RESERVED = 0,
54
55 /* PORT0_DATA -> PORT211_DATA */
56 PINMUX_DATA_BEGIN,
57 PORT_ALL(DATA),
58 PINMUX_DATA_END,
59
60 /* PORT0_IN -> PORT211_IN */
61 PINMUX_INPUT_BEGIN,
62 PORT_ALL(IN),
63 PINMUX_INPUT_END,
64
65 /* PORT0_OUT -> PORT211_OUT */
66 PINMUX_OUTPUT_BEGIN,
67 PORT_ALL(OUT),
68 PINMUX_OUTPUT_END,
69
70 PINMUX_FUNCTION_BEGIN,
71 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
72 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
73 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
74 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
75 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
76 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
77 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
78 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
79 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
80 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
81
82 MSEL1CR_31_0, MSEL1CR_31_1,
83 MSEL1CR_30_0, MSEL1CR_30_1,
84 MSEL1CR_29_0, MSEL1CR_29_1,
85 MSEL1CR_28_0, MSEL1CR_28_1,
86 MSEL1CR_27_0, MSEL1CR_27_1,
87 MSEL1CR_26_0, MSEL1CR_26_1,
88 MSEL1CR_16_0, MSEL1CR_16_1,
89 MSEL1CR_15_0, MSEL1CR_15_1,
90 MSEL1CR_14_0, MSEL1CR_14_1,
91 MSEL1CR_13_0, MSEL1CR_13_1,
92 MSEL1CR_12_0, MSEL1CR_12_1,
93 MSEL1CR_9_0, MSEL1CR_9_1,
94 MSEL1CR_7_0, MSEL1CR_7_1,
95 MSEL1CR_6_0, MSEL1CR_6_1,
96 MSEL1CR_5_0, MSEL1CR_5_1,
97 MSEL1CR_4_0, MSEL1CR_4_1,
98 MSEL1CR_3_0, MSEL1CR_3_1,
99 MSEL1CR_2_0, MSEL1CR_2_1,
100 MSEL1CR_0_0, MSEL1CR_0_1,
101
102 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
103 MSEL3CR_6_0, MSEL3CR_6_1,
104
105 MSEL4CR_19_0, MSEL4CR_19_1,
106 MSEL4CR_18_0, MSEL4CR_18_1,
107 MSEL4CR_15_0, MSEL4CR_15_1,
108 MSEL4CR_10_0, MSEL4CR_10_1,
109 MSEL4CR_6_0, MSEL4CR_6_1,
110 MSEL4CR_4_0, MSEL4CR_4_1,
111 MSEL4CR_1_0, MSEL4CR_1_1,
112
113 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
114 MSEL5CR_30_0, MSEL5CR_30_1,
115 MSEL5CR_29_0, MSEL5CR_29_1,
116 MSEL5CR_27_0, MSEL5CR_27_1,
117 MSEL5CR_25_0, MSEL5CR_25_1,
118 MSEL5CR_23_0, MSEL5CR_23_1,
119 MSEL5CR_21_0, MSEL5CR_21_1,
120 MSEL5CR_19_0, MSEL5CR_19_1,
121 MSEL5CR_17_0, MSEL5CR_17_1,
122 MSEL5CR_15_0, MSEL5CR_15_1,
123 MSEL5CR_14_0, MSEL5CR_14_1,
124 MSEL5CR_13_0, MSEL5CR_13_1,
125 MSEL5CR_12_0, MSEL5CR_12_1,
126 MSEL5CR_11_0, MSEL5CR_11_1,
127 MSEL5CR_10_0, MSEL5CR_10_1,
128 MSEL5CR_8_0, MSEL5CR_8_1,
129 MSEL5CR_7_0, MSEL5CR_7_1,
130 MSEL5CR_6_0, MSEL5CR_6_1,
131 MSEL5CR_5_0, MSEL5CR_5_1,
132 MSEL5CR_4_0, MSEL5CR_4_1,
133 MSEL5CR_3_0, MSEL5CR_3_1,
134 MSEL5CR_2_0, MSEL5CR_2_1,
135 MSEL5CR_0_0, MSEL5CR_0_1,
136 PINMUX_FUNCTION_END,
137
138 PINMUX_MARK_BEGIN,
139
140 /* IRQ */
141 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
142 IRQ1_MARK,
143 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
144 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
145 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
146 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
147 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
148 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
149 IRQ8_MARK,
150 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
151 IRQ10_MARK,
152 IRQ11_MARK,
153 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
154 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
155 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
156 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
157 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
158 IRQ17_MARK,
159 IRQ18_MARK,
160 IRQ19_MARK,
161 IRQ20_MARK,
162 IRQ21_MARK,
163 IRQ22_MARK,
164 IRQ23_MARK,
165 IRQ24_MARK,
166 IRQ25_MARK,
167 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
168 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
169 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
170 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
171 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
172 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
173
174 /* Function */
175
176 /* DBGT */
177 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
178 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
179 DBGMD21_MARK,
180
181 /* FSI-A */
182 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
183 FSIAISLD_PORT5_MARK,
184 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
185 FSIASPDIF_PORT18_MARK,
186 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
187 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
188 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
189
190 /* FSI-B */
191 FSIBCK_MARK,
192
193 /* FMSI */
194 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
195 FMSISLD_PORT6_MARK,
196 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
197 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
198 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
199
200 /* SCIFA0 */
201 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
202 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
203
204 /* SCIFA1 */
205 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
206 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
207
208 /* SCIFA2 */
209 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
210 SCIFA2_SCK_PORT199_MARK,
211 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
212 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
213
214 /* SCIFA3 */
215 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
216 SCIFA3_SCK_PORT116_MARK,
217 SCIFA3_CTS_PORT117_MARK,
218 SCIFA3_RXD_PORT174_MARK,
219 SCIFA3_TXD_PORT175_MARK,
220
221 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
222 SCIFA3_SCK_PORT158_MARK,
223 SCIFA3_CTS_PORT162_MARK,
224 SCIFA3_RXD_PORT159_MARK,
225 SCIFA3_TXD_PORT160_MARK,
226
227 /* SCIFA4 */
228 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
229 SCIFA4_TXD_PORT13_MARK,
230
231 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
232 SCIFA4_TXD_PORT203_MARK,
233
234 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
235 SCIFA4_TXD_PORT93_MARK,
236
237 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
238 SCIFA4_SCK_PORT205_MARK,
239
240 /* SCIFA5 */
241 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
242 SCIFA5_RXD_PORT10_MARK,
243
244 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
245 SCIFA5_TXD_PORT208_MARK,
246
247 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
248 SCIFA5_RXD_PORT92_MARK,
249
250 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
251 SCIFA5_SCK_PORT206_MARK,
252
253 /* SCIFA6 */
254 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
255
256 /* SCIFA7 */
257 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
258
259 /* SCIFAB */
260 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
261 SCIFB_RXD_PORT191_MARK,
262 SCIFB_TXD_PORT192_MARK,
263 SCIFB_RTS_PORT186_MARK,
264 SCIFB_CTS_PORT187_MARK,
265
266 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
267 SCIFB_RXD_PORT3_MARK,
268 SCIFB_TXD_PORT4_MARK,
269 SCIFB_RTS_PORT172_MARK,
270 SCIFB_CTS_PORT173_MARK,
271
272 /* LCD0 */
273 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
274 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
275 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
276 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
277 LCD0_D16_MARK, LCD0_D17_MARK,
278 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
279 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
280 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
281 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
282 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
283
284 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
285 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
286 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
287 LCD0_LCLK_PORT165_MARK,
288
289 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
290 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
291 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
292 LCD0_LCLK_PORT102_MARK,
293
294 /* LCD1 */
295 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
296 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
297 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
298 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
299 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
300 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
301 LCD1_DON_MARK, LCD1_VCPWC_MARK,
302 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
303
304 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
305 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
306 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
307 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
308
309 /* RSPI */
310 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
311 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
312 RSPI_MISO_A_MARK,
313
314 /* VIO CKO */
315 VIO_CKO1_MARK, /* needs fixup */
316 VIO_CKO2_MARK,
317 VIO_CKO_1_MARK,
318 VIO_CKO_MARK,
319
320 /* VIO0 */
321 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
322 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
323 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
324 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
325 VIO0_FIELD_MARK,
326
327 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
328 VIO0_D14_PORT25_MARK,
329 VIO0_D15_PORT24_MARK,
330
331 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
332 VIO0_D14_PORT95_MARK,
333 VIO0_D15_PORT96_MARK,
334
335 /* VIO1 */
336 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
337 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
338 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
339
340 /* TPU0 */
341 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
342 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
343 TPU0TO2_PORT202_MARK,
344
345 /* SSP1 0 */
346 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
347 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
348 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
349
350 /* SSP1 1 */
351 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
352 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
353 STP1_IPSYNC_MARK,
354
355 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
356 STP1_IPEN_PORT187_MARK,
357
358 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
359 STP1_IPEN_PORT193_MARK,
360
361 /* SIM */
362 SIM_RST_MARK, SIM_CLK_MARK,
363 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
364 SIM_D_PORT199_MARK,
365
366 /* SDHI0 */
367 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
368 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
369
370 /* SDHI1 */
371 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
372 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
373
374 /* SDHI2 */
375 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
376 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
377
378 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
379 SDHI2_WP_PORT25_MARK,
380
381 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
382 SDHI2_CD_PORT202_MARK,
383
384 /* MSIOF2 */
385 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
386 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
387 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
388 MSIOF2_RSCK_MARK,
389
390 /* KEYSC */
391 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
392 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
393 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
394
395 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
396 KEYIN1_PORT44_MARK,
397 KEYIN2_PORT45_MARK,
398 KEYIN3_PORT46_MARK,
399
400 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
401 KEYIN1_PORT57_MARK,
402 KEYIN2_PORT56_MARK,
403 KEYIN3_PORT55_MARK,
404
405 /* VOU */
406 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
407 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
408 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
409 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
410 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
411
412 /* MEMC */
413 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
414 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
415 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
416 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
417 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
418
419 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
420 MEMC_ADV_MARK,
421 MEMC_WAIT_MARK,
422 MEMC_BUSCLK_MARK,
423
424 MEMC_A1_MARK, /* MSEL4CR_6_1 */
425 MEMC_DREQ0_MARK,
426 MEMC_DREQ1_MARK,
427 MEMC_A0_MARK,
428
429 /* MMC */
430 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
431 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
432 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
433 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
434
435 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
436 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
437 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
438 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
439
440 /* MSIOF0 */
441 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
442 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
443 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
444 MSIOF0_TSYNC_MARK,
445
446 /* MSIOF1 */
447 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
448 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
449
450 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
451 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
452 MSIOF1_TSYNC_PORT120_MARK,
453 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
454
455 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
456 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
457 MSIOF1_RXD_PORT75_MARK,
458 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
459
460 /* GPIO */
461 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
462
463 /* USB0 */
464 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
465
466 /* USB1 */
467 USB1_OCI_MARK, USB1_PPON_MARK,
468
469 /* BBIF1 */
470 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
471 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
472 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
473
474 /* BBIF2 */
475 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
476 BBIF2_RXD2_PORT60_MARK,
477 BBIF2_TSYNC2_PORT6_MARK,
478 BBIF2_TSCK2_PORT59_MARK,
479
480 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
481 BBIF2_TXD2_PORT183_MARK,
482 BBIF2_TSCK2_PORT89_MARK,
483 BBIF2_TSYNC2_PORT184_MARK,
484
485 /* BSC / FLCTL / PCMCIA */
486 CS0_MARK, CS2_MARK, CS4_MARK,
487 CS5B_MARK, CS6A_MARK,
488 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
489 CS5A_PORT19_MARK,
490 IOIS16_MARK, /* ? */
491
492 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
493 A4_FOE_MARK, /* share with FLCTL */
494 A5_FCDE_MARK, /* share with FLCTL */
495 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
496 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
497 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
498 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
499 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
500 A26_MARK,
501
502 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
503 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
504 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
505 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
506 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
507 D15_NAF15_MARK, /* share with FLCTL */
508 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
509 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
510 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
511 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
512
513 WE0_FWE_MARK, /* share with FLCTL */
514 WE1_MARK,
515 WE2_ICIORD_MARK, /* share with PCMCIA */
516 WE3_ICIOWR_MARK, /* share with PCMCIA */
517 CKO_MARK, BS_MARK, RDWR_MARK,
518 RD_FSC_MARK, /* share with FLCTL */
519 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
520 WAIT_PORT90_MARK,
521
522 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
523
524 /* IRDA */
525 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
526
527 /* ATAPI */
528 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
529 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
530 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
531 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
532 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
533 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
534 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
535 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
536
537 /* RMII */
538 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
539 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
540 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
541 RMII_REF50CK_MARK, /* for RMII */
542 RMII_REF125CK_MARK, /* for GMII */
543
544 /* GEther */
545 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
546 ET_ETXD2_MARK, ET_ETXD3_MARK,
547 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
548 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
549 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
550 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
551 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
552 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
553 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
554 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
555
556 /* DMA0 */
557 DREQ0_MARK, DACK0_MARK,
558
559 /* DMA1 */
560 DREQ1_MARK, DACK1_MARK,
561
562 /* SYSC */
563 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
564
565 /* IRREM */
566 IROUT_MARK,
567
568 /* SDENC */
569 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
570
571 /* HDMI */
572 HDMI_HPD_MARK, HDMI_CEC_MARK,
573
574 /* DEBUG */
575 EDEBGREQ_PULLUP_MARK, /* for JTAG */
576 EDEBGREQ_PULLDOWN_MARK,
577
578 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
579 TRACEAUD_FROM_LCDC0_MARK,
580 TRACEAUD_FROM_MEMC_MARK,
581
582 PINMUX_MARK_END,
583 };
584
585 static const u16 pinmux_data[] = {
586 PINMUX_DATA_ALL(),
587
588 /* Port0 */
589 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
590 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
591 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
592 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
593 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
594 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
595 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
596
597 /* Port1 */
598 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
599 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
600 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
601 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
602 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
603 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
604 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
605
606 /* Port2 */
607 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
608 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
609 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
610 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
611 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
612
613 /* Port3 */
614 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
615 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
616 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
617 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
618
619 /* Port4 */
620 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
621 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
622 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
623 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
624
625 /* Port5 */
626 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
627 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
628 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
629 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
630 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
631
632 /* Port6 */
633 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
634 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
635 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
636 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
637 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
638
639 /* Port7 */
640 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
641
642 /* Port8 */
643 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
644
645 /* Port9 */
646 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
647 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
648
649 /* Port10 */
650 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
651 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
652 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
653
654 /* Port11 */
655 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
656 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
657 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
658
659 /* Port12 */
660 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
661 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
662 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
663 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
664 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
665
666 /* Port13 */
667 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
668 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
669 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
670 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
671
672 /* Port14 */
673 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
674 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
675 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
676 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
677 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
678
679 /* Port15 */
680 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
681 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
682 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
683 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
684 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
685
686 /* Port16 */
687 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
688 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
689
690 /* Port17 */
691 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
692 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
693
694 /* Port18 */
695 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
696 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
697
698 /* Port19 */
699 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
700 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
701 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
702
703 /* Port20 */
704 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
705 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
706 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
707
708 /* Port21 */
709 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
710 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
711 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
712 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
713 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
714 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
715
716 /* Port22 */
717 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
718 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
719 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
720
721 /* Port23 */
722 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
723 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
724 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
725 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
726 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
727 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
728
729 /* Port24 */
730 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
731 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
732 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
733 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
734
735 /* Port25 */
736 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
737 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
738 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
739 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
740
741 /* Port26 */
742 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
743 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
744 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
745
746 /* Port27 - Port39 Function */
747 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
748 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
749 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
750 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
751 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
752 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
753 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
754 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
755 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
756 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
757 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
758 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
759 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
760
761 /* Port38 IRQ */
762 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
763
764 /* Port40 */
765 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
766 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
767 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
768
769 /* Port41 */
770 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
771 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
772 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
773
774 /* Port42 */
775 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
776 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
777 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
778
779 /* Port43 */
780 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
781 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
782 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
783 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
784
785 /* Port44 */
786 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
787 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
788 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
789 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
790
791 /* Port45 */
792 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
793 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
794 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
795 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
796
797 /* Port46 */
798 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
799 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
800 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
801
802 /* Port47 */
803 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
804 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
805 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
806
807 /* Port48 */
808 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
809 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
810 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
811
812 /* Port49 */
813 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
814 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
815 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
816 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
817
818 /* Port50 */
819 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
820 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
821 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
822 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
823
824 /* Port51 */
825 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
826 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
827 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
828
829 /* Port52 */
830 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
831 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
832 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
833
834 /* Port53 */
835 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
836 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
837 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
838
839 /* Port54 */
840 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
841 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
842 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
843
844 /* Port55 */
845 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
846 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
847 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
848 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
849
850 /* Port56 */
851 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
852 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
853 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
854 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
855 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
856
857 /* Port57 */
858 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
859 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
860 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
861 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
862 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
863
864 /* Port58 */
865 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
866 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
867 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
868 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
869 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
870
871 /* Port59 */
872 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
873 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
874 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
875
876 /* Port60 */
877 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
878 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
879 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
880
881 /* Port61 */
882 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
883 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
884
885 /* Port62 */
886 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
887 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
888 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
889 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
890
891 /* Port63 */
892 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
893 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
894 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
895
896 /* Port64 */
897 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
898 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
899 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
900 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
901
902 /* Port65 */
903 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
904 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
905 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
906
907 /* Port66 */
908 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
909 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
910 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
911 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
912
913 /* Port67 - Port73 Function1 */
914 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
915 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
916 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
917 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
918 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
919 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
920 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
921
922 /* Port67 - Port73 Function2 */
923 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
924 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
925 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
926 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
927 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
928 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
929 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
930
931 /* Port67 - Port73 Function4 */
932 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
933 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
934 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
935 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
936 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
937 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
938 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
939
940 /* Port67 - Port73 Function6 */
941 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
942 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
943 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
944 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
945 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
946 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
947 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
948
949 /* Port67 - Port71 IRQ */
950 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
951 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
952 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
953 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
954 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
955
956 /* Port74 */
957 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
958 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
959 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
960 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
961 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
962
963 /* Port75 */
964 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
965 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
966 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
967 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
968 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
969
970 /* Port76 - Port80 Function */
971 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
972 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
973 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
974 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
975 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
976
977 /* Port81 */
978 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
979 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
980
981 /* Port82 - Port88 Function */
982 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
983 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
984 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
985 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
986 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
987 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
988 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
989
990 /* Port89 */
991 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
992 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
993 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
994
995 /* Port90 */
996 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
997 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
998 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
999 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
1000
1001 /* Port91 */
1002 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1003 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1004 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1005 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1006
1007 /* Port92 */
1008 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1009 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1010 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1011 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1012 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1013
1014 /* Port93 */
1015 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1016 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1017 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1018 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1019 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1020
1021 /* Port94 */
1022 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1023 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1024 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1025 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1026 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1027
1028 /* Port95 */
1029 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1030 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1031
1032 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1033 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1034 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1035 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1036
1037 /* Port96 */
1038 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1039 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1040
1041 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1042 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1043 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1044 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1045
1046 /* Port97 */
1047 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1048 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1049 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1050 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1051 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1052
1053 /* Port98 */
1054 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1055 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1056 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1057 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1058
1059 /* Port99 */
1060 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1061 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1062 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1063 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1064 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1065
1066 /* Port100 */
1067 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1068 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1069 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1070 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1071
1072 /* Port101 */
1073 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1074
1075 /* Port102 */
1076 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1077 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1078
1079 /* Port103 */
1080 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1081 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1082 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1083
1084 /* Port104 */
1085 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1086 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1087 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1088
1089 /* Port105 */
1090 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1091 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1092
1093 /* Port106 */
1094 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1095 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1096
1097 /* Port107 - Port115 Function */
1098 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1099 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1100 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1101 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1102 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1103 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1104 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1105 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1106 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1107
1108 /* Port116 */
1109 PINMUX_DATA(A25_MARK, PORT116_FN1),
1110 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1111 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1112 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1113 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1114
1115 /* Port117 */
1116 PINMUX_DATA(A24_MARK, PORT117_FN1),
1117 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1118 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1119 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1120 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1121
1122 /* Port118 */
1123 PINMUX_DATA(A23_MARK, PORT118_FN1),
1124 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1125 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1126 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1127 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1128
1129 /* Port119 */
1130 PINMUX_DATA(A22_MARK, PORT119_FN1),
1131 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1132 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1133 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1134 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1135
1136 /* Port120 */
1137 PINMUX_DATA(A21_MARK, PORT120_FN1),
1138 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1139 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1140 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1141
1142 /* Port121 */
1143 PINMUX_DATA(A20_MARK, PORT121_FN1),
1144 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1145 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1146 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1147
1148 /* Port122 */
1149 PINMUX_DATA(A19_MARK, PORT122_FN1),
1150 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1151
1152 /* Port123 */
1153 PINMUX_DATA(A18_MARK, PORT123_FN1),
1154 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1155
1156 /* Port124 */
1157 PINMUX_DATA(A17_MARK, PORT124_FN1),
1158 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1159
1160 /* Port125 - Port141 Function */
1161 PINMUX_DATA(A16_MARK, PORT125_FN1),
1162 PINMUX_DATA(A15_MARK, PORT126_FN1),
1163 PINMUX_DATA(A14_MARK, PORT127_FN1),
1164 PINMUX_DATA(A13_MARK, PORT128_FN1),
1165 PINMUX_DATA(A12_MARK, PORT129_FN1),
1166 PINMUX_DATA(A11_MARK, PORT130_FN1),
1167 PINMUX_DATA(A10_MARK, PORT131_FN1),
1168 PINMUX_DATA(A9_MARK, PORT132_FN1),
1169 PINMUX_DATA(A8_MARK, PORT133_FN1),
1170 PINMUX_DATA(A7_MARK, PORT134_FN1),
1171 PINMUX_DATA(A6_MARK, PORT135_FN1),
1172 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1173 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1174 PINMUX_DATA(A3_MARK, PORT138_FN1),
1175 PINMUX_DATA(A2_MARK, PORT139_FN1),
1176 PINMUX_DATA(A1_MARK, PORT140_FN1),
1177 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1178
1179 /* Port142 - Port157 Function1 */
1180 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1181 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1182 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1183 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1184 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1185 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1186 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1187 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1188 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1189 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1190 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1191 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1192 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1193 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1194 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1195 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1196
1197 /* Port142 - Port149 Function3 */
1198 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1199 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1200 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1201 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1202 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1203 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1204 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1205 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1206
1207 /* Port158 */
1208 PINMUX_DATA(D31_MARK, PORT158_FN1),
1209 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1210 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1211 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1212 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1213 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1214
1215 /* Port159 */
1216 PINMUX_DATA(D30_MARK, PORT159_FN1),
1217 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1218 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1219 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1220 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1221
1222 /* Port160 */
1223 PINMUX_DATA(D29_MARK, PORT160_FN1),
1224 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1225 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1226 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1227 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1228
1229 /* Port161 */
1230 PINMUX_DATA(D28_MARK, PORT161_FN1),
1231 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1232 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1233 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1234 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1235 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1236
1237 /* Port162 */
1238 PINMUX_DATA(D27_MARK, PORT162_FN1),
1239 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1240 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1241 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1242 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1243
1244 /* Port163 */
1245 PINMUX_DATA(D26_MARK, PORT163_FN1),
1246 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1247 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1248 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1249 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1250 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1251
1252 /* Port164 */
1253 PINMUX_DATA(D25_MARK, PORT164_FN1),
1254 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1255 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1256 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1257 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1258
1259 /* Port165 */
1260 PINMUX_DATA(D24_MARK, PORT165_FN1),
1261 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1262 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1263 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1264
1265 /* Port166 - Port171 Function1 */
1266 PINMUX_DATA(D21_MARK, PORT166_FN1),
1267 PINMUX_DATA(D20_MARK, PORT167_FN1),
1268 PINMUX_DATA(D19_MARK, PORT168_FN1),
1269 PINMUX_DATA(D18_MARK, PORT169_FN1),
1270 PINMUX_DATA(D17_MARK, PORT170_FN1),
1271 PINMUX_DATA(D16_MARK, PORT171_FN1),
1272
1273 /* Port166 - Port171 Function3 */
1274 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1275 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1276 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1277 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1278 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1279 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1280
1281 /* Port166 - Port171 Function6 */
1282 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1283 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1284 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1285 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1286 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1287 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1288
1289 /* Port167 - Port171 IRQ */
1290 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1291 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1292 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1293 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1294 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1295
1296 /* Port172 */
1297 PINMUX_DATA(D23_MARK, PORT172_FN1),
1298 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1299 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1300 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1301 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1302
1303 /* Port173 */
1304 PINMUX_DATA(D22_MARK, PORT173_FN1),
1305 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1306 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1307 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1308 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1309
1310 /* Port174 */
1311 PINMUX_DATA(A26_MARK, PORT174_FN1),
1312 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1313 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1314 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1315
1316 /* Port175 */
1317 PINMUX_DATA(A0_MARK, PORT175_FN1),
1318 PINMUX_DATA(BS_MARK, PORT175_FN2),
1319 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1320 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1321
1322 /* Port176 */
1323 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1324
1325 /* Port177 */
1326 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1327 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1328 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1329 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1330
1331 /* Port178 */
1332 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1333 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1334 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1335
1336 /* Port179 */
1337 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1338 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1339 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1340
1341 /* Port180 */
1342 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1343 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1344 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1345 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1346 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1347
1348 /* Port181 */
1349 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1350 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1351 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1352
1353 /* Port182 */
1354 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1355 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1356 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1357
1358 /* Port183 */
1359 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1360 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1361 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1362
1363 /* Port184 */
1364 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1365 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1366 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1367
1368 /* Port185 - Port192 Function1 */
1369 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1370 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1371 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1372 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1373 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1374 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1375 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1376
1377 /* Port185 - Port192 Function3 */
1378 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1379 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1380 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1381 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1382 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1383 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1384 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1385 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1386
1387 /* Port185 - Port192 Function6 */
1388 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1389 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1390 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1391 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1392 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1393 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1394 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1395 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1396
1397 /* Port193 */
1398 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1399 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1400 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1401 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1402
1403 /* Port194 */
1404 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1405 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1406 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1407 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1408
1409 /* Port195 */
1410 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1411 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1412 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1413 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1414
1415 /* Port196 */
1416 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1417 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1418 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1419 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1420
1421 /* Port197 */
1422 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1423 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1424 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1425 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1426
1427 /* Port198 */
1428 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1429 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1430 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1431 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1432
1433 /* Port199 */
1434 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1435 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1436 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1437 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1438 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1439 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1440
1441 /* Port200 */
1442 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1443 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1444 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1445 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1446 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1447
1448 /* Port201 */
1449 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1450 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1451
1452 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1453 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1454 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1455 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1456
1457 /* Port202 */
1458 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1459 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1460
1461 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1462 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1463 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1464 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1465 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1466 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1467
1468 /* Port203 - Port208 Function1 */
1469 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1470 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1471 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1472 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1473 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1474 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1475
1476 /* Port203 - Port208 Function3 */
1477 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1478 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1479 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1480 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1481 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1482 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1483
1484 /* Port203 - Port208 Function6 */
1485 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1486 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1487 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1488 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1489 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1490 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1491
1492 /* Port203 - Port208 Function7 */
1493 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1494 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1495 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1496 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1497 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1498 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1499
1500 /* Port209 */
1501 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1502 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1503
1504 /* Port210 */
1505 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1506 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1507
1508 /* Port211 */
1509 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1510 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1511
1512 /* SDENC */
1513 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1514 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1515
1516 /* SYSC */
1517 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1518 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1519
1520 /* DEBUG */
1521 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1522 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1523
1524 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1525 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1526 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1527 };
1528
1529 #define __I (SH_PFC_PIN_CFG_INPUT)
1530 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1531 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1532 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1533 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
1534 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1535
1536 #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
1537 #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
1538 #define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
1539 #define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
1540 #define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
1541 #define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
1542 #define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1543 #define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1544 #define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
1545
1546 static const struct sh_pfc_pin pinmux_pins[] = {
1547 /* Table 56-1 (I/O and Pull U/D) */
1548 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1549 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1550 R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1551 R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1552 R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1553 R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1554 R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1555 R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1556 R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1557 R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1558 R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1559 R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1560 R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1561 R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1562 R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1563 R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1564 R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1565 R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1566 R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1567 R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1568 R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1569 R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1570 R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1571 R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1572 R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1573 R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1574 R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1575 R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1576 R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1577 R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1578 R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1579 R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1580 R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1581 R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1582 R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1583 R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1584 R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1585 R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1586 R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1587 R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1588 R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1589 R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1590 R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1591 R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1592 R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1593 R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1594 R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1595 R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1596 R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1597 R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1598 R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1599 R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1600 R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1601 R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1602 R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1603 R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1604 R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1605 R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1606 R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1607 R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1608 R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1609 R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1610 R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1611 R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1612 R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1613 R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1614 R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1615 R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1616 R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1617 R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1618 R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1619 R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1620 R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1621 R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1622 R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1623 R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1624 R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1625 R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1626 R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1627 R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1628 R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1629 R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1630 R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1631 R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1632 R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1633 R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1634 R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1635 R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1636 R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1637 R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1638 R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1639 R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1640 R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1641 R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1642 R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1643 R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1644 R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1645 R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1646 R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1647 R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1648 R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1649 R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1650 R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1651 R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1652 R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1653 R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
1654 };
1655
1656 /* - BSC -------------------------------------------------------------------- */
1657 static const unsigned int bsc_data8_pins[] = {
1658 /* D[0:7] */
1659 157, 156, 155, 154, 153, 152, 151, 150,
1660 };
1661 static const unsigned int bsc_data8_mux[] = {
1662 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1663 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1664 };
1665 static const unsigned int bsc_data16_pins[] = {
1666 /* D[0:15] */
1667 157, 156, 155, 154, 153, 152, 151, 150,
1668 149, 148, 147, 146, 145, 144, 143, 142,
1669 };
1670 static const unsigned int bsc_data16_mux[] = {
1671 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1672 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1673 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1674 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1675 };
1676 static const unsigned int bsc_data32_pins[] = {
1677 /* D[0:31] */
1678 157, 156, 155, 154, 153, 152, 151, 150,
1679 149, 148, 147, 146, 145, 144, 143, 142,
1680 171, 170, 169, 168, 167, 166, 173, 172,
1681 165, 164, 163, 162, 161, 160, 159, 158,
1682 };
1683 static const unsigned int bsc_data32_mux[] = {
1684 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1685 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1686 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1687 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1688 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1689 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1690 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1691 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1692 };
1693 static const unsigned int bsc_cs0_pins[] = {
1694 /* CS */
1695 109,
1696 };
1697 static const unsigned int bsc_cs0_mux[] = {
1698 CS0_MARK,
1699 };
1700 static const unsigned int bsc_cs2_pins[] = {
1701 /* CS */
1702 110,
1703 };
1704 static const unsigned int bsc_cs2_mux[] = {
1705 CS2_MARK,
1706 };
1707 static const unsigned int bsc_cs4_pins[] = {
1708 /* CS */
1709 111,
1710 };
1711 static const unsigned int bsc_cs4_mux[] = {
1712 CS4_MARK,
1713 };
1714 static const unsigned int bsc_cs5a_0_pins[] = {
1715 /* CS */
1716 105,
1717 };
1718 static const unsigned int bsc_cs5a_0_mux[] = {
1719 CS5A_PORT105_MARK,
1720 };
1721 static const unsigned int bsc_cs5a_1_pins[] = {
1722 /* CS */
1723 19,
1724 };
1725 static const unsigned int bsc_cs5a_1_mux[] = {
1726 CS5A_PORT19_MARK,
1727 };
1728 static const unsigned int bsc_cs5b_pins[] = {
1729 /* CS */
1730 103,
1731 };
1732 static const unsigned int bsc_cs5b_mux[] = {
1733 CS5B_MARK,
1734 };
1735 static const unsigned int bsc_cs6a_pins[] = {
1736 /* CS */
1737 104,
1738 };
1739 static const unsigned int bsc_cs6a_mux[] = {
1740 CS6A_MARK,
1741 };
1742 static const unsigned int bsc_rd_we8_pins[] = {
1743 /* RD, WE[0] */
1744 115, 113,
1745 };
1746 static const unsigned int bsc_rd_we8_mux[] = {
1747 RD_FSC_MARK, WE0_FWE_MARK,
1748 };
1749 static const unsigned int bsc_rd_we16_pins[] = {
1750 /* RD, WE[0:1] */
1751 115, 113, 112,
1752 };
1753 static const unsigned int bsc_rd_we16_mux[] = {
1754 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1755 };
1756 static const unsigned int bsc_rd_we32_pins[] = {
1757 /* RD, WE[0:3] */
1758 115, 113, 112, 108, 107,
1759 };
1760 static const unsigned int bsc_rd_we32_mux[] = {
1761 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1762 };
1763 static const unsigned int bsc_bs_pins[] = {
1764 /* BS */
1765 175,
1766 };
1767 static const unsigned int bsc_bs_mux[] = {
1768 BS_MARK,
1769 };
1770 static const unsigned int bsc_rdwr_pins[] = {
1771 /* RDWR */
1772 114,
1773 };
1774 static const unsigned int bsc_rdwr_mux[] = {
1775 RDWR_MARK,
1776 };
1777 /* - CEU0 ------------------------------------------------------------------- */
1778 static const unsigned int ceu0_data_0_7_pins[] = {
1779 /* D[0:7] */
1780 34, 33, 32, 31, 30, 29, 28, 27,
1781 };
1782 static const unsigned int ceu0_data_0_7_mux[] = {
1783 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1784 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1785 };
1786 static const unsigned int ceu0_data_8_15_0_pins[] = {
1787 /* D[8:15] */
1788 182, 181, 180, 179, 178, 26, 25, 24,
1789 };
1790 static const unsigned int ceu0_data_8_15_0_mux[] = {
1791 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1792 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1793 VIO0_D15_PORT24_MARK,
1794 };
1795 static const unsigned int ceu0_data_8_15_1_pins[] = {
1796 /* D[8:15] */
1797 182, 181, 180, 179, 178, 22, 95, 96,
1798 };
1799 static const unsigned int ceu0_data_8_15_1_mux[] = {
1800 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1801 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1802 VIO0_D15_PORT96_MARK,
1803 };
1804 static const unsigned int ceu0_clk_0_pins[] = {
1805 /* CKO */
1806 36,
1807 };
1808 static const unsigned int ceu0_clk_0_mux[] = {
1809 VIO_CKO_MARK,
1810 };
1811 static const unsigned int ceu0_clk_1_pins[] = {
1812 /* CKO */
1813 14,
1814 };
1815 static const unsigned int ceu0_clk_1_mux[] = {
1816 VIO_CKO1_MARK,
1817 };
1818 static const unsigned int ceu0_clk_2_pins[] = {
1819 /* CKO */
1820 15,
1821 };
1822 static const unsigned int ceu0_clk_2_mux[] = {
1823 VIO_CKO2_MARK,
1824 };
1825 static const unsigned int ceu0_sync_pins[] = {
1826 /* CLK, VD, HD */
1827 35, 39, 37,
1828 };
1829 static const unsigned int ceu0_sync_mux[] = {
1830 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1831 };
1832 static const unsigned int ceu0_field_pins[] = {
1833 /* FIELD */
1834 38,
1835 };
1836 static const unsigned int ceu0_field_mux[] = {
1837 VIO0_FIELD_MARK,
1838 };
1839 /* - CEU1 ------------------------------------------------------------------- */
1840 static const unsigned int ceu1_data_pins[] = {
1841 /* D[0:7] */
1842 182, 181, 180, 179, 178, 26, 25, 24,
1843 };
1844 static const unsigned int ceu1_data_mux[] = {
1845 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1846 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1847 };
1848 static const unsigned int ceu1_clk_pins[] = {
1849 /* CKO */
1850 23,
1851 };
1852 static const unsigned int ceu1_clk_mux[] = {
1853 VIO_CKO_1_MARK,
1854 };
1855 static const unsigned int ceu1_sync_pins[] = {
1856 /* CLK, VD, HD */
1857 197, 198, 160,
1858 };
1859 static const unsigned int ceu1_sync_mux[] = {
1860 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1861 };
1862 static const unsigned int ceu1_field_pins[] = {
1863 /* FIELD */
1864 21,
1865 };
1866 static const unsigned int ceu1_field_mux[] = {
1867 VIO1_FIELD_MARK,
1868 };
1869 /* - FSIA ------------------------------------------------------------------- */
1870 static const unsigned int fsia_mclk_in_pins[] = {
1871 /* CK */
1872 11,
1873 };
1874 static const unsigned int fsia_mclk_in_mux[] = {
1875 FSIACK_MARK,
1876 };
1877 static const unsigned int fsia_mclk_out_pins[] = {
1878 /* OMC */
1879 10,
1880 };
1881 static const unsigned int fsia_mclk_out_mux[] = {
1882 FSIAOMC_MARK,
1883 };
1884 static const unsigned int fsia_sclk_in_pins[] = {
1885 /* ILR, IBT */
1886 12, 13,
1887 };
1888 static const unsigned int fsia_sclk_in_mux[] = {
1889 FSIAILR_MARK, FSIAIBT_MARK,
1890 };
1891 static const unsigned int fsia_sclk_out_pins[] = {
1892 /* OLR, OBT */
1893 7, 8,
1894 };
1895 static const unsigned int fsia_sclk_out_mux[] = {
1896 FSIAOLR_MARK, FSIAOBT_MARK,
1897 };
1898 static const unsigned int fsia_data_in_0_pins[] = {
1899 /* ISLD */
1900 0,
1901 };
1902 static const unsigned int fsia_data_in_0_mux[] = {
1903 FSIAISLD_PORT0_MARK,
1904 };
1905 static const unsigned int fsia_data_in_1_pins[] = {
1906 /* ISLD */
1907 5,
1908 };
1909 static const unsigned int fsia_data_in_1_mux[] = {
1910 FSIAISLD_PORT5_MARK,
1911 };
1912 static const unsigned int fsia_data_out_0_pins[] = {
1913 /* OSLD */
1914 9,
1915 };
1916 static const unsigned int fsia_data_out_0_mux[] = {
1917 FSIAOSLD_MARK,
1918 };
1919 static const unsigned int fsia_data_out_1_pins[] = {
1920 /* OSLD */
1921 0,
1922 };
1923 static const unsigned int fsia_data_out_1_mux[] = {
1924 FSIAOSLD1_MARK,
1925 };
1926 static const unsigned int fsia_data_out_2_pins[] = {
1927 /* OSLD */
1928 1,
1929 };
1930 static const unsigned int fsia_data_out_2_mux[] = {
1931 FSIAOSLD2_MARK,
1932 };
1933 static const unsigned int fsia_spdif_0_pins[] = {
1934 /* SPDIF */
1935 9,
1936 };
1937 static const unsigned int fsia_spdif_0_mux[] = {
1938 FSIASPDIF_PORT9_MARK,
1939 };
1940 static const unsigned int fsia_spdif_1_pins[] = {
1941 /* SPDIF */
1942 18,
1943 };
1944 static const unsigned int fsia_spdif_1_mux[] = {
1945 FSIASPDIF_PORT18_MARK,
1946 };
1947 /* - FSIB ------------------------------------------------------------------- */
1948 static const unsigned int fsib_mclk_in_pins[] = {
1949 /* CK */
1950 11,
1951 };
1952 static const unsigned int fsib_mclk_in_mux[] = {
1953 FSIBCK_MARK,
1954 };
1955 /* - GETHER ----------------------------------------------------------------- */
1956 static const unsigned int gether_rmii_pins[] = {
1957 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1958 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1959 };
1960 static const unsigned int gether_rmii_mux[] = {
1961 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1962 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1963 RMII_MDC_MARK, RMII_MDIO_MARK,
1964 };
1965 static const unsigned int gether_mii_pins[] = {
1966 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1967 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1968 * CRS, COL, MDC, MDIO,
1969 */
1970 185, 186, 187, 188, 174, 161, 204,
1971 171, 170, 169, 168, 184, 183, 203,
1972 205, 163, 206, 207,
1973 };
1974 static const unsigned int gether_mii_mux[] = {
1975 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1976 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1977 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1978 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1979 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1980 };
1981 static const unsigned int gether_gmii_pins[] = {
1982 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
1983 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1984 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1985 */
1986 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1987 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1988 205, 163, 206, 207,
1989 };
1990 static const unsigned int gether_gmii_mux[] = {
1991 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1992 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
1993 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1994 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1995 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
1996 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1997 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1998 RMII_REF125CK_MARK,
1999 };
2000 static const unsigned int gether_int_pins[] = {
2001 /* PHY_INT */
2002 164,
2003 };
2004 static const unsigned int gether_int_mux[] = {
2005 ET_PHY_INT_MARK,
2006 };
2007 static const unsigned int gether_link_pins[] = {
2008 /* LINK */
2009 177,
2010 };
2011 static const unsigned int gether_link_mux[] = {
2012 ET_LINK_MARK,
2013 };
2014 static const unsigned int gether_wol_pins[] = {
2015 /* WOL */
2016 175,
2017 };
2018 static const unsigned int gether_wol_mux[] = {
2019 ET_WOL_MARK,
2020 };
2021 /* - HDMI ------------------------------------------------------------------- */
2022 static const unsigned int hdmi_pins[] = {
2023 /* HPD, CEC */
2024 210, 211,
2025 };
2026 static const unsigned int hdmi_mux[] = {
2027 HDMI_HPD_MARK, HDMI_CEC_MARK,
2028 };
2029 /* - INTC ------------------------------------------------------------------- */
2030 IRQC_PINS_MUX(0, 0, 2);
2031 IRQC_PINS_MUX(0, 1, 13);
2032 IRQC_PIN_MUX(1, 20);
2033 IRQC_PINS_MUX(2, 0, 11);
2034 IRQC_PINS_MUX(2, 1, 12);
2035 IRQC_PINS_MUX(3, 0, 10);
2036 IRQC_PINS_MUX(3, 1, 14);
2037 IRQC_PINS_MUX(4, 0, 15);
2038 IRQC_PINS_MUX(4, 1, 172);
2039 IRQC_PINS_MUX(5, 0, 0);
2040 IRQC_PINS_MUX(5, 1, 1);
2041 IRQC_PINS_MUX(6, 0, 121);
2042 IRQC_PINS_MUX(6, 1, 173);
2043 IRQC_PINS_MUX(7, 0, 120);
2044 IRQC_PINS_MUX(7, 1, 209);
2045 IRQC_PIN_MUX(8, 119);
2046 IRQC_PINS_MUX(9, 0, 118);
2047 IRQC_PINS_MUX(9, 1, 210);
2048 IRQC_PIN_MUX(10, 19);
2049 IRQC_PIN_MUX(11, 104);
2050 IRQC_PINS_MUX(12, 0, 42);
2051 IRQC_PINS_MUX(12, 1, 97);
2052 IRQC_PINS_MUX(13, 0, 64);
2053 IRQC_PINS_MUX(13, 1, 98);
2054 IRQC_PINS_MUX(14, 0, 63);
2055 IRQC_PINS_MUX(14, 1, 99);
2056 IRQC_PINS_MUX(15, 0, 62);
2057 IRQC_PINS_MUX(15, 1, 100);
2058 IRQC_PINS_MUX(16, 0, 68);
2059 IRQC_PINS_MUX(16, 1, 211);
2060 IRQC_PIN_MUX(17, 69);
2061 IRQC_PIN_MUX(18, 70);
2062 IRQC_PIN_MUX(19, 71);
2063 IRQC_PIN_MUX(20, 67);
2064 IRQC_PIN_MUX(21, 202);
2065 IRQC_PIN_MUX(22, 95);
2066 IRQC_PIN_MUX(23, 96);
2067 IRQC_PIN_MUX(24, 180);
2068 IRQC_PIN_MUX(25, 38);
2069 IRQC_PINS_MUX(26, 0, 58);
2070 IRQC_PINS_MUX(26, 1, 81);
2071 IRQC_PINS_MUX(27, 0, 57);
2072 IRQC_PINS_MUX(27, 1, 168);
2073 IRQC_PINS_MUX(28, 0, 56);
2074 IRQC_PINS_MUX(28, 1, 169);
2075 IRQC_PINS_MUX(29, 0, 50);
2076 IRQC_PINS_MUX(29, 1, 170);
2077 IRQC_PINS_MUX(30, 0, 49);
2078 IRQC_PINS_MUX(30, 1, 171);
2079 IRQC_PINS_MUX(31, 0, 41);
2080 IRQC_PINS_MUX(31, 1, 167);
2081
2082 /* - LCD0 ------------------------------------------------------------------- */
2083 static const unsigned int lcd0_data8_pins[] = {
2084 /* D[0:7] */
2085 58, 57, 56, 55, 54, 53, 52, 51,
2086 };
2087 static const unsigned int lcd0_data8_mux[] = {
2088 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2089 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2090 };
2091 static const unsigned int lcd0_data9_pins[] = {
2092 /* D[0:8] */
2093 58, 57, 56, 55, 54, 53, 52, 51,
2094 50,
2095 };
2096 static const unsigned int lcd0_data9_mux[] = {
2097 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2098 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2099 LCD0_D8_MARK,
2100 };
2101 static const unsigned int lcd0_data12_pins[] = {
2102 /* D[0:11] */
2103 58, 57, 56, 55, 54, 53, 52, 51,
2104 50, 49, 48, 47,
2105 };
2106 static const unsigned int lcd0_data12_mux[] = {
2107 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2108 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2109 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2110 };
2111 static const unsigned int lcd0_data16_pins[] = {
2112 /* D[0:15] */
2113 58, 57, 56, 55, 54, 53, 52, 51,
2114 50, 49, 48, 47, 46, 45, 44, 43,
2115 };
2116 static const unsigned int lcd0_data16_mux[] = {
2117 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2118 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2119 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2120 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2121 };
2122 static const unsigned int lcd0_data18_pins[] = {
2123 /* D[0:17] */
2124 58, 57, 56, 55, 54, 53, 52, 51,
2125 50, 49, 48, 47, 46, 45, 44, 43,
2126 42, 41,
2127 };
2128 static const unsigned int lcd0_data18_mux[] = {
2129 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2130 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2131 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2132 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2133 LCD0_D16_MARK, LCD0_D17_MARK,
2134 };
2135 static const unsigned int lcd0_data24_0_pins[] = {
2136 /* D[0:23] */
2137 58, 57, 56, 55, 54, 53, 52, 51,
2138 50, 49, 48, 47, 46, 45, 44, 43,
2139 42, 41, 40, 4, 3, 2, 0, 1,
2140 };
2141 static const unsigned int lcd0_data24_0_mux[] = {
2142 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2143 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2144 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2145 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2146 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2147 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2148 LCD0_D23_PORT1_MARK,
2149 };
2150 static const unsigned int lcd0_data24_1_pins[] = {
2151 /* D[0:23] */
2152 58, 57, 56, 55, 54, 53, 52, 51,
2153 50, 49, 48, 47, 46, 45, 44, 43,
2154 42, 41, 163, 162, 161, 158, 160, 159,
2155 };
2156 static const unsigned int lcd0_data24_1_mux[] = {
2157 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2158 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2159 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2160 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2161 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2162 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2163 };
2164 static const unsigned int lcd0_display_pins[] = {
2165 /* DON, VCPWC, VEPWC */
2166 61, 59, 60,
2167 };
2168 static const unsigned int lcd0_display_mux[] = {
2169 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2170 };
2171 static const unsigned int lcd0_lclk_0_pins[] = {
2172 /* LCLK */
2173 102,
2174 };
2175 static const unsigned int lcd0_lclk_0_mux[] = {
2176 LCD0_LCLK_PORT102_MARK,
2177 };
2178 static const unsigned int lcd0_lclk_1_pins[] = {
2179 /* LCLK */
2180 165,
2181 };
2182 static const unsigned int lcd0_lclk_1_mux[] = {
2183 LCD0_LCLK_PORT165_MARK,
2184 };
2185 static const unsigned int lcd0_sync_pins[] = {
2186 /* VSYN, HSYN, DCK, DISP */
2187 63, 64, 62, 65,
2188 };
2189 static const unsigned int lcd0_sync_mux[] = {
2190 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2191 };
2192 static const unsigned int lcd0_sys_pins[] = {
2193 /* CS, WR, RD, RS */
2194 64, 62, 164, 65,
2195 };
2196 static const unsigned int lcd0_sys_mux[] = {
2197 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2198 };
2199 /* - LCD1 ------------------------------------------------------------------- */
2200 static const unsigned int lcd1_data8_pins[] = {
2201 /* D[0:7] */
2202 4, 3, 2, 1, 0, 91, 92, 23,
2203 };
2204 static const unsigned int lcd1_data8_mux[] = {
2205 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2206 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2207 };
2208 static const unsigned int lcd1_data9_pins[] = {
2209 /* D[0:8] */
2210 4, 3, 2, 1, 0, 91, 92, 23,
2211 93,
2212 };
2213 static const unsigned int lcd1_data9_mux[] = {
2214 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2215 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2216 LCD1_D8_MARK,
2217 };
2218 static const unsigned int lcd1_data12_pins[] = {
2219 /* D[0:12] */
2220 4, 3, 2, 1, 0, 91, 92, 23,
2221 93, 94, 21, 201,
2222 };
2223 static const unsigned int lcd1_data12_mux[] = {
2224 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2225 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2226 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2227 };
2228 static const unsigned int lcd1_data16_pins[] = {
2229 /* D[0:15] */
2230 4, 3, 2, 1, 0, 91, 92, 23,
2231 93, 94, 21, 201, 200, 199, 196, 195,
2232 };
2233 static const unsigned int lcd1_data16_mux[] = {
2234 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2235 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2236 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2237 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2238 };
2239 static const unsigned int lcd1_data18_pins[] = {
2240 /* D[0:17] */
2241 4, 3, 2, 1, 0, 91, 92, 23,
2242 93, 94, 21, 201, 200, 199, 196, 195,
2243 194, 193,
2244 };
2245 static const unsigned int lcd1_data18_mux[] = {
2246 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2247 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2248 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2249 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2250 LCD1_D16_MARK, LCD1_D17_MARK,
2251 };
2252 static const unsigned int lcd1_data24_pins[] = {
2253 /* D[0:23] */
2254 4, 3, 2, 1, 0, 91, 92, 23,
2255 93, 94, 21, 201, 200, 199, 196, 195,
2256 194, 193, 198, 197, 75, 74, 15, 14,
2257 };
2258 static const unsigned int lcd1_data24_mux[] = {
2259 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2260 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2261 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2262 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2263 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2264 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2265 };
2266 static const unsigned int lcd1_display_pins[] = {
2267 /* DON, VCPWC, VEPWC */
2268 100, 5, 6,
2269 };
2270 static const unsigned int lcd1_display_mux[] = {
2271 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2272 };
2273 static const unsigned int lcd1_lclk_pins[] = {
2274 /* LCLK */
2275 40,
2276 };
2277 static const unsigned int lcd1_lclk_mux[] = {
2278 LCD1_LCLK_MARK,
2279 };
2280 static const unsigned int lcd1_sync_pins[] = {
2281 /* VSYN, HSYN, DCK, DISP */
2282 98, 97, 99, 12,
2283 };
2284 static const unsigned int lcd1_sync_mux[] = {
2285 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2286 };
2287 static const unsigned int lcd1_sys_pins[] = {
2288 /* CS, WR, RD, RS */
2289 97, 99, 13, 12,
2290 };
2291 static const unsigned int lcd1_sys_mux[] = {
2292 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2293 };
2294 /* - MMCIF ------------------------------------------------------------------ */
2295 static const unsigned int mmc0_data1_0_pins[] = {
2296 /* D[0] */
2297 68,
2298 };
2299 static const unsigned int mmc0_data1_0_mux[] = {
2300 MMC0_D0_PORT68_MARK,
2301 };
2302 static const unsigned int mmc0_data4_0_pins[] = {
2303 /* D[0:3] */
2304 68, 69, 70, 71,
2305 };
2306 static const unsigned int mmc0_data4_0_mux[] = {
2307 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2308 };
2309 static const unsigned int mmc0_data8_0_pins[] = {
2310 /* D[0:7] */
2311 68, 69, 70, 71, 72, 73, 74, 75,
2312 };
2313 static const unsigned int mmc0_data8_0_mux[] = {
2314 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2315 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2316 };
2317 static const unsigned int mmc0_ctrl_0_pins[] = {
2318 /* CMD, CLK */
2319 67, 66,
2320 };
2321 static const unsigned int mmc0_ctrl_0_mux[] = {
2322 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2323 };
2324
2325 static const unsigned int mmc0_data1_1_pins[] = {
2326 /* D[0] */
2327 149,
2328 };
2329 static const unsigned int mmc0_data1_1_mux[] = {
2330 MMC1_D0_PORT149_MARK,
2331 };
2332 static const unsigned int mmc0_data4_1_pins[] = {
2333 /* D[0:3] */
2334 149, 148, 147, 146,
2335 };
2336 static const unsigned int mmc0_data4_1_mux[] = {
2337 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2338 };
2339 static const unsigned int mmc0_data8_1_pins[] = {
2340 /* D[0:7] */
2341 149, 148, 147, 146, 145, 144, 143, 142,
2342 };
2343 static const unsigned int mmc0_data8_1_mux[] = {
2344 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2345 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2346 };
2347 static const unsigned int mmc0_ctrl_1_pins[] = {
2348 /* CMD, CLK */
2349 104, 103,
2350 };
2351 static const unsigned int mmc0_ctrl_1_mux[] = {
2352 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2353 };
2354 /* - SCIFA0 ----------------------------------------------------------------- */
2355 static const unsigned int scifa0_data_pins[] = {
2356 /* RXD, TXD */
2357 197, 198,
2358 };
2359 static const unsigned int scifa0_data_mux[] = {
2360 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2361 };
2362 static const unsigned int scifa0_clk_pins[] = {
2363 /* SCK */
2364 188,
2365 };
2366 static const unsigned int scifa0_clk_mux[] = {
2367 SCIFA0_SCK_MARK,
2368 };
2369 static const unsigned int scifa0_ctrl_pins[] = {
2370 /* RTS, CTS */
2371 194, 193,
2372 };
2373 static const unsigned int scifa0_ctrl_mux[] = {
2374 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2375 };
2376 /* - SCIFA1 ----------------------------------------------------------------- */
2377 static const unsigned int scifa1_data_pins[] = {
2378 /* RXD, TXD */
2379 195, 196,
2380 };
2381 static const unsigned int scifa1_data_mux[] = {
2382 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2383 };
2384 static const unsigned int scifa1_clk_pins[] = {
2385 /* SCK */
2386 185,
2387 };
2388 static const unsigned int scifa1_clk_mux[] = {
2389 SCIFA1_SCK_MARK,
2390 };
2391 static const unsigned int scifa1_ctrl_pins[] = {
2392 /* RTS, CTS */
2393 23, 21,
2394 };
2395 static const unsigned int scifa1_ctrl_mux[] = {
2396 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2397 };
2398 /* - SCIFA2 ----------------------------------------------------------------- */
2399 static const unsigned int scifa2_data_pins[] = {
2400 /* RXD, TXD */
2401 200, 201,
2402 };
2403 static const unsigned int scifa2_data_mux[] = {
2404 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2405 };
2406 static const unsigned int scifa2_clk_0_pins[] = {
2407 /* SCK */
2408 22,
2409 };
2410 static const unsigned int scifa2_clk_0_mux[] = {
2411 SCIFA2_SCK_PORT22_MARK,
2412 };
2413 static const unsigned int scifa2_clk_1_pins[] = {
2414 /* SCK */
2415 199,
2416 };
2417 static const unsigned int scifa2_clk_1_mux[] = {
2418 SCIFA2_SCK_PORT199_MARK,
2419 };
2420 static const unsigned int scifa2_ctrl_pins[] = {
2421 /* RTS, CTS */
2422 96, 95,
2423 };
2424 static const unsigned int scifa2_ctrl_mux[] = {
2425 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2426 };
2427 /* - SCIFA3 ----------------------------------------------------------------- */
2428 static const unsigned int scifa3_data_0_pins[] = {
2429 /* RXD, TXD */
2430 174, 175,
2431 };
2432 static const unsigned int scifa3_data_0_mux[] = {
2433 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2434 };
2435 static const unsigned int scifa3_clk_0_pins[] = {
2436 /* SCK */
2437 116,
2438 };
2439 static const unsigned int scifa3_clk_0_mux[] = {
2440 SCIFA3_SCK_PORT116_MARK,
2441 };
2442 static const unsigned int scifa3_ctrl_0_pins[] = {
2443 /* RTS, CTS */
2444 105, 117,
2445 };
2446 static const unsigned int scifa3_ctrl_0_mux[] = {
2447 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2448 };
2449 static const unsigned int scifa3_data_1_pins[] = {
2450 /* RXD, TXD */
2451 159, 160,
2452 };
2453 static const unsigned int scifa3_data_1_mux[] = {
2454 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2455 };
2456 static const unsigned int scifa3_clk_1_pins[] = {
2457 /* SCK */
2458 158,
2459 };
2460 static const unsigned int scifa3_clk_1_mux[] = {
2461 SCIFA3_SCK_PORT158_MARK,
2462 };
2463 static const unsigned int scifa3_ctrl_1_pins[] = {
2464 /* RTS, CTS */
2465 161, 162,
2466 };
2467 static const unsigned int scifa3_ctrl_1_mux[] = {
2468 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2469 };
2470 /* - SCIFA4 ----------------------------------------------------------------- */
2471 static const unsigned int scifa4_data_0_pins[] = {
2472 /* RXD, TXD */
2473 12, 13,
2474 };
2475 static const unsigned int scifa4_data_0_mux[] = {
2476 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2477 };
2478 static const unsigned int scifa4_data_1_pins[] = {
2479 /* RXD, TXD */
2480 204, 203,
2481 };
2482 static const unsigned int scifa4_data_1_mux[] = {
2483 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2484 };
2485 static const unsigned int scifa4_data_2_pins[] = {
2486 /* RXD, TXD */
2487 94, 93,
2488 };
2489 static const unsigned int scifa4_data_2_mux[] = {
2490 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2491 };
2492 static const unsigned int scifa4_clk_0_pins[] = {
2493 /* SCK */
2494 21,
2495 };
2496 static const unsigned int scifa4_clk_0_mux[] = {
2497 SCIFA4_SCK_PORT21_MARK,
2498 };
2499 static const unsigned int scifa4_clk_1_pins[] = {
2500 /* SCK */
2501 205,
2502 };
2503 static const unsigned int scifa4_clk_1_mux[] = {
2504 SCIFA4_SCK_PORT205_MARK,
2505 };
2506 /* - SCIFA5 ----------------------------------------------------------------- */
2507 static const unsigned int scifa5_data_0_pins[] = {
2508 /* RXD, TXD */
2509 10, 20,
2510 };
2511 static const unsigned int scifa5_data_0_mux[] = {
2512 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2513 };
2514 static const unsigned int scifa5_data_1_pins[] = {
2515 /* RXD, TXD */
2516 207, 208,
2517 };
2518 static const unsigned int scifa5_data_1_mux[] = {
2519 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2520 };
2521 static const unsigned int scifa5_data_2_pins[] = {
2522 /* RXD, TXD */
2523 92, 91,
2524 };
2525 static const unsigned int scifa5_data_2_mux[] = {
2526 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2527 };
2528 static const unsigned int scifa5_clk_0_pins[] = {
2529 /* SCK */
2530 23,
2531 };
2532 static const unsigned int scifa5_clk_0_mux[] = {
2533 SCIFA5_SCK_PORT23_MARK,
2534 };
2535 static const unsigned int scifa5_clk_1_pins[] = {
2536 /* SCK */
2537 206,
2538 };
2539 static const unsigned int scifa5_clk_1_mux[] = {
2540 SCIFA5_SCK_PORT206_MARK,
2541 };
2542 /* - SCIFA6 ----------------------------------------------------------------- */
2543 static const unsigned int scifa6_data_pins[] = {
2544 /* RXD, TXD */
2545 25, 26,
2546 };
2547 static const unsigned int scifa6_data_mux[] = {
2548 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2549 };
2550 static const unsigned int scifa6_clk_pins[] = {
2551 /* SCK */
2552 24,
2553 };
2554 static const unsigned int scifa6_clk_mux[] = {
2555 SCIFA6_SCK_MARK,
2556 };
2557 /* - SCIFA7 ----------------------------------------------------------------- */
2558 static const unsigned int scifa7_data_pins[] = {
2559 /* RXD, TXD */
2560 0, 1,
2561 };
2562 static const unsigned int scifa7_data_mux[] = {
2563 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2564 };
2565 /* - SCIFB ------------------------------------------------------------------ */
2566 static const unsigned int scifb_data_0_pins[] = {
2567 /* RXD, TXD */
2568 191, 192,
2569 };
2570 static const unsigned int scifb_data_0_mux[] = {
2571 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2572 };
2573 static const unsigned int scifb_clk_0_pins[] = {
2574 /* SCK */
2575 190,
2576 };
2577 static const unsigned int scifb_clk_0_mux[] = {
2578 SCIFB_SCK_PORT190_MARK,
2579 };
2580 static const unsigned int scifb_ctrl_0_pins[] = {
2581 /* RTS, CTS */
2582 186, 187,
2583 };
2584 static const unsigned int scifb_ctrl_0_mux[] = {
2585 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2586 };
2587 static const unsigned int scifb_data_1_pins[] = {
2588 /* RXD, TXD */
2589 3, 4,
2590 };
2591 static const unsigned int scifb_data_1_mux[] = {
2592 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2593 };
2594 static const unsigned int scifb_clk_1_pins[] = {
2595 /* SCK */
2596 2,
2597 };
2598 static const unsigned int scifb_clk_1_mux[] = {
2599 SCIFB_SCK_PORT2_MARK,
2600 };
2601 static const unsigned int scifb_ctrl_1_pins[] = {
2602 /* RTS, CTS */
2603 172, 173,
2604 };
2605 static const unsigned int scifb_ctrl_1_mux[] = {
2606 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2607 };
2608 /* - SDHI0 ------------------------------------------------------------------ */
2609 static const unsigned int sdhi0_data1_pins[] = {
2610 /* D0 */
2611 77,
2612 };
2613 static const unsigned int sdhi0_data1_mux[] = {
2614 SDHI0_D0_MARK,
2615 };
2616 static const unsigned int sdhi0_data4_pins[] = {
2617 /* D[0:3] */
2618 77, 78, 79, 80,
2619 };
2620 static const unsigned int sdhi0_data4_mux[] = {
2621 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2622 };
2623 static const unsigned int sdhi0_ctrl_pins[] = {
2624 /* CMD, CLK */
2625 76, 82,
2626 };
2627 static const unsigned int sdhi0_ctrl_mux[] = {
2628 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2629 };
2630 static const unsigned int sdhi0_cd_pins[] = {
2631 /* CD */
2632 81,
2633 };
2634 static const unsigned int sdhi0_cd_mux[] = {
2635 SDHI0_CD_MARK,
2636 };
2637 static const unsigned int sdhi0_wp_pins[] = {
2638 /* WP */
2639 83,
2640 };
2641 static const unsigned int sdhi0_wp_mux[] = {
2642 SDHI0_WP_MARK,
2643 };
2644 /* - SDHI1 ------------------------------------------------------------------ */
2645 static const unsigned int sdhi1_data1_pins[] = {
2646 /* D0 */
2647 68,
2648 };
2649 static const unsigned int sdhi1_data1_mux[] = {
2650 SDHI1_D0_MARK,
2651 };
2652 static const unsigned int sdhi1_data4_pins[] = {
2653 /* D[0:3] */
2654 68, 69, 70, 71,
2655 };
2656 static const unsigned int sdhi1_data4_mux[] = {
2657 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2658 };
2659 static const unsigned int sdhi1_ctrl_pins[] = {
2660 /* CMD, CLK */
2661 67, 66,
2662 };
2663 static const unsigned int sdhi1_ctrl_mux[] = {
2664 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2665 };
2666 static const unsigned int sdhi1_cd_pins[] = {
2667 /* CD */
2668 72,
2669 };
2670 static const unsigned int sdhi1_cd_mux[] = {
2671 SDHI1_CD_MARK,
2672 };
2673 static const unsigned int sdhi1_wp_pins[] = {
2674 /* WP */
2675 73,
2676 };
2677 static const unsigned int sdhi1_wp_mux[] = {
2678 SDHI1_WP_MARK,
2679 };
2680 /* - SDHI2 ------------------------------------------------------------------ */
2681 static const unsigned int sdhi2_data1_pins[] = {
2682 /* D0 */
2683 205,
2684 };
2685 static const unsigned int sdhi2_data1_mux[] = {
2686 SDHI2_D0_MARK,
2687 };
2688 static const unsigned int sdhi2_data4_pins[] = {
2689 /* D[0:3] */
2690 205, 206, 207, 208,
2691 };
2692 static const unsigned int sdhi2_data4_mux[] = {
2693 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2694 };
2695 static const unsigned int sdhi2_ctrl_pins[] = {
2696 /* CMD, CLK */
2697 204, 203,
2698 };
2699 static const unsigned int sdhi2_ctrl_mux[] = {
2700 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2701 };
2702 static const unsigned int sdhi2_cd_0_pins[] = {
2703 /* CD */
2704 202,
2705 };
2706 static const unsigned int sdhi2_cd_0_mux[] = {
2707 SDHI2_CD_PORT202_MARK,
2708 };
2709 static const unsigned int sdhi2_wp_0_pins[] = {
2710 /* WP */
2711 177,
2712 };
2713 static const unsigned int sdhi2_wp_0_mux[] = {
2714 SDHI2_WP_PORT177_MARK,
2715 };
2716 static const unsigned int sdhi2_cd_1_pins[] = {
2717 /* CD */
2718 24,
2719 };
2720 static const unsigned int sdhi2_cd_1_mux[] = {
2721 SDHI2_CD_PORT24_MARK,
2722 };
2723 static const unsigned int sdhi2_wp_1_pins[] = {
2724 /* WP */
2725 25,
2726 };
2727 static const unsigned int sdhi2_wp_1_mux[] = {
2728 SDHI2_WP_PORT25_MARK,
2729 };
2730 /* - TPU0 ------------------------------------------------------------------- */
2731 static const unsigned int tpu0_to0_pins[] = {
2732 /* TO */
2733 23,
2734 };
2735 static const unsigned int tpu0_to0_mux[] = {
2736 TPU0TO0_MARK,
2737 };
2738 static const unsigned int tpu0_to1_pins[] = {
2739 /* TO */
2740 21,
2741 };
2742 static const unsigned int tpu0_to1_mux[] = {
2743 TPU0TO1_MARK,
2744 };
2745 static const unsigned int tpu0_to2_0_pins[] = {
2746 /* TO */
2747 66,
2748 };
2749 static const unsigned int tpu0_to2_0_mux[] = {
2750 TPU0TO2_PORT66_MARK,
2751 };
2752 static const unsigned int tpu0_to2_1_pins[] = {
2753 /* TO */
2754 202,
2755 };
2756 static const unsigned int tpu0_to2_1_mux[] = {
2757 TPU0TO2_PORT202_MARK,
2758 };
2759 static const unsigned int tpu0_to3_pins[] = {
2760 /* TO */
2761 180,
2762 };
2763 static const unsigned int tpu0_to3_mux[] = {
2764 TPU0TO3_MARK,
2765 };
2766
2767 static const struct sh_pfc_pin_group pinmux_groups[] = {
2768 SH_PFC_PIN_GROUP(bsc_data8),
2769 SH_PFC_PIN_GROUP(bsc_data16),
2770 SH_PFC_PIN_GROUP(bsc_data32),
2771 SH_PFC_PIN_GROUP(bsc_cs0),
2772 SH_PFC_PIN_GROUP(bsc_cs2),
2773 SH_PFC_PIN_GROUP(bsc_cs4),
2774 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2775 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2776 SH_PFC_PIN_GROUP(bsc_cs5b),
2777 SH_PFC_PIN_GROUP(bsc_cs6a),
2778 SH_PFC_PIN_GROUP(bsc_rd_we8),
2779 SH_PFC_PIN_GROUP(bsc_rd_we16),
2780 SH_PFC_PIN_GROUP(bsc_rd_we32),
2781 SH_PFC_PIN_GROUP(bsc_bs),
2782 SH_PFC_PIN_GROUP(bsc_rdwr),
2783 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2784 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2785 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2786 SH_PFC_PIN_GROUP(ceu0_clk_0),
2787 SH_PFC_PIN_GROUP(ceu0_clk_1),
2788 SH_PFC_PIN_GROUP(ceu0_clk_2),
2789 SH_PFC_PIN_GROUP(ceu0_sync),
2790 SH_PFC_PIN_GROUP(ceu0_field),
2791 SH_PFC_PIN_GROUP(ceu1_data),
2792 SH_PFC_PIN_GROUP(ceu1_clk),
2793 SH_PFC_PIN_GROUP(ceu1_sync),
2794 SH_PFC_PIN_GROUP(ceu1_field),
2795 SH_PFC_PIN_GROUP(fsia_mclk_in),
2796 SH_PFC_PIN_GROUP(fsia_mclk_out),
2797 SH_PFC_PIN_GROUP(fsia_sclk_in),
2798 SH_PFC_PIN_GROUP(fsia_sclk_out),
2799 SH_PFC_PIN_GROUP(fsia_data_in_0),
2800 SH_PFC_PIN_GROUP(fsia_data_in_1),
2801 SH_PFC_PIN_GROUP(fsia_data_out_0),
2802 SH_PFC_PIN_GROUP(fsia_data_out_1),
2803 SH_PFC_PIN_GROUP(fsia_data_out_2),
2804 SH_PFC_PIN_GROUP(fsia_spdif_0),
2805 SH_PFC_PIN_GROUP(fsia_spdif_1),
2806 SH_PFC_PIN_GROUP(fsib_mclk_in),
2807 SH_PFC_PIN_GROUP(gether_rmii),
2808 SH_PFC_PIN_GROUP(gether_mii),
2809 SH_PFC_PIN_GROUP(gether_gmii),
2810 SH_PFC_PIN_GROUP(gether_int),
2811 SH_PFC_PIN_GROUP(gether_link),
2812 SH_PFC_PIN_GROUP(gether_wol),
2813 SH_PFC_PIN_GROUP(hdmi),
2814 SH_PFC_PIN_GROUP(intc_irq0_0),
2815 SH_PFC_PIN_GROUP(intc_irq0_1),
2816 SH_PFC_PIN_GROUP(intc_irq1),
2817 SH_PFC_PIN_GROUP(intc_irq2_0),
2818 SH_PFC_PIN_GROUP(intc_irq2_1),
2819 SH_PFC_PIN_GROUP(intc_irq3_0),
2820 SH_PFC_PIN_GROUP(intc_irq3_1),
2821 SH_PFC_PIN_GROUP(intc_irq4_0),
2822 SH_PFC_PIN_GROUP(intc_irq4_1),
2823 SH_PFC_PIN_GROUP(intc_irq5_0),
2824 SH_PFC_PIN_GROUP(intc_irq5_1),
2825 SH_PFC_PIN_GROUP(intc_irq6_0),
2826 SH_PFC_PIN_GROUP(intc_irq6_1),
2827 SH_PFC_PIN_GROUP(intc_irq7_0),
2828 SH_PFC_PIN_GROUP(intc_irq7_1),
2829 SH_PFC_PIN_GROUP(intc_irq8),
2830 SH_PFC_PIN_GROUP(intc_irq9_0),
2831 SH_PFC_PIN_GROUP(intc_irq9_1),
2832 SH_PFC_PIN_GROUP(intc_irq10),
2833 SH_PFC_PIN_GROUP(intc_irq11),
2834 SH_PFC_PIN_GROUP(intc_irq12_0),
2835 SH_PFC_PIN_GROUP(intc_irq12_1),
2836 SH_PFC_PIN_GROUP(intc_irq13_0),
2837 SH_PFC_PIN_GROUP(intc_irq13_1),
2838 SH_PFC_PIN_GROUP(intc_irq14_0),
2839 SH_PFC_PIN_GROUP(intc_irq14_1),
2840 SH_PFC_PIN_GROUP(intc_irq15_0),
2841 SH_PFC_PIN_GROUP(intc_irq15_1),
2842 SH_PFC_PIN_GROUP(intc_irq16_0),
2843 SH_PFC_PIN_GROUP(intc_irq16_1),
2844 SH_PFC_PIN_GROUP(intc_irq17),
2845 SH_PFC_PIN_GROUP(intc_irq18),
2846 SH_PFC_PIN_GROUP(intc_irq19),
2847 SH_PFC_PIN_GROUP(intc_irq20),
2848 SH_PFC_PIN_GROUP(intc_irq21),
2849 SH_PFC_PIN_GROUP(intc_irq22),
2850 SH_PFC_PIN_GROUP(intc_irq23),
2851 SH_PFC_PIN_GROUP(intc_irq24),
2852 SH_PFC_PIN_GROUP(intc_irq25),
2853 SH_PFC_PIN_GROUP(intc_irq26_0),
2854 SH_PFC_PIN_GROUP(intc_irq26_1),
2855 SH_PFC_PIN_GROUP(intc_irq27_0),
2856 SH_PFC_PIN_GROUP(intc_irq27_1),
2857 SH_PFC_PIN_GROUP(intc_irq28_0),
2858 SH_PFC_PIN_GROUP(intc_irq28_1),
2859 SH_PFC_PIN_GROUP(intc_irq29_0),
2860 SH_PFC_PIN_GROUP(intc_irq29_1),
2861 SH_PFC_PIN_GROUP(intc_irq30_0),
2862 SH_PFC_PIN_GROUP(intc_irq30_1),
2863 SH_PFC_PIN_GROUP(intc_irq31_0),
2864 SH_PFC_PIN_GROUP(intc_irq31_1),
2865 SH_PFC_PIN_GROUP(lcd0_data8),
2866 SH_PFC_PIN_GROUP(lcd0_data9),
2867 SH_PFC_PIN_GROUP(lcd0_data12),
2868 SH_PFC_PIN_GROUP(lcd0_data16),
2869 SH_PFC_PIN_GROUP(lcd0_data18),
2870 SH_PFC_PIN_GROUP(lcd0_data24_0),
2871 SH_PFC_PIN_GROUP(lcd0_data24_1),
2872 SH_PFC_PIN_GROUP(lcd0_display),
2873 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2874 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2875 SH_PFC_PIN_GROUP(lcd0_sync),
2876 SH_PFC_PIN_GROUP(lcd0_sys),
2877 SH_PFC_PIN_GROUP(lcd1_data8),
2878 SH_PFC_PIN_GROUP(lcd1_data9),
2879 SH_PFC_PIN_GROUP(lcd1_data12),
2880 SH_PFC_PIN_GROUP(lcd1_data16),
2881 SH_PFC_PIN_GROUP(lcd1_data18),
2882 SH_PFC_PIN_GROUP(lcd1_data24),
2883 SH_PFC_PIN_GROUP(lcd1_display),
2884 SH_PFC_PIN_GROUP(lcd1_lclk),
2885 SH_PFC_PIN_GROUP(lcd1_sync),
2886 SH_PFC_PIN_GROUP(lcd1_sys),
2887 SH_PFC_PIN_GROUP(mmc0_data1_0),
2888 SH_PFC_PIN_GROUP(mmc0_data4_0),
2889 SH_PFC_PIN_GROUP(mmc0_data8_0),
2890 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2891 SH_PFC_PIN_GROUP(mmc0_data1_1),
2892 SH_PFC_PIN_GROUP(mmc0_data4_1),
2893 SH_PFC_PIN_GROUP(mmc0_data8_1),
2894 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2895 SH_PFC_PIN_GROUP(scifa0_data),
2896 SH_PFC_PIN_GROUP(scifa0_clk),
2897 SH_PFC_PIN_GROUP(scifa0_ctrl),
2898 SH_PFC_PIN_GROUP(scifa1_data),
2899 SH_PFC_PIN_GROUP(scifa1_clk),
2900 SH_PFC_PIN_GROUP(scifa1_ctrl),
2901 SH_PFC_PIN_GROUP(scifa2_data),
2902 SH_PFC_PIN_GROUP(scifa2_clk_0),
2903 SH_PFC_PIN_GROUP(scifa2_clk_1),
2904 SH_PFC_PIN_GROUP(scifa2_ctrl),
2905 SH_PFC_PIN_GROUP(scifa3_data_0),
2906 SH_PFC_PIN_GROUP(scifa3_clk_0),
2907 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2908 SH_PFC_PIN_GROUP(scifa3_data_1),
2909 SH_PFC_PIN_GROUP(scifa3_clk_1),
2910 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2911 SH_PFC_PIN_GROUP(scifa4_data_0),
2912 SH_PFC_PIN_GROUP(scifa4_data_1),
2913 SH_PFC_PIN_GROUP(scifa4_data_2),
2914 SH_PFC_PIN_GROUP(scifa4_clk_0),
2915 SH_PFC_PIN_GROUP(scifa4_clk_1),
2916 SH_PFC_PIN_GROUP(scifa5_data_0),
2917 SH_PFC_PIN_GROUP(scifa5_data_1),
2918 SH_PFC_PIN_GROUP(scifa5_data_2),
2919 SH_PFC_PIN_GROUP(scifa5_clk_0),
2920 SH_PFC_PIN_GROUP(scifa5_clk_1),
2921 SH_PFC_PIN_GROUP(scifa6_data),
2922 SH_PFC_PIN_GROUP(scifa6_clk),
2923 SH_PFC_PIN_GROUP(scifa7_data),
2924 SH_PFC_PIN_GROUP(scifb_data_0),
2925 SH_PFC_PIN_GROUP(scifb_clk_0),
2926 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2927 SH_PFC_PIN_GROUP(scifb_data_1),
2928 SH_PFC_PIN_GROUP(scifb_clk_1),
2929 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2930 SH_PFC_PIN_GROUP(sdhi0_data1),
2931 SH_PFC_PIN_GROUP(sdhi0_data4),
2932 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2933 SH_PFC_PIN_GROUP(sdhi0_cd),
2934 SH_PFC_PIN_GROUP(sdhi0_wp),
2935 SH_PFC_PIN_GROUP(sdhi1_data1),
2936 SH_PFC_PIN_GROUP(sdhi1_data4),
2937 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2938 SH_PFC_PIN_GROUP(sdhi1_cd),
2939 SH_PFC_PIN_GROUP(sdhi1_wp),
2940 SH_PFC_PIN_GROUP(sdhi2_data1),
2941 SH_PFC_PIN_GROUP(sdhi2_data4),
2942 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2943 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2944 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2945 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2946 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2947 SH_PFC_PIN_GROUP(tpu0_to0),
2948 SH_PFC_PIN_GROUP(tpu0_to1),
2949 SH_PFC_PIN_GROUP(tpu0_to2_0),
2950 SH_PFC_PIN_GROUP(tpu0_to2_1),
2951 SH_PFC_PIN_GROUP(tpu0_to3),
2952 };
2953
2954 static const char * const bsc_groups[] = {
2955 "bsc_data8",
2956 "bsc_data16",
2957 "bsc_data32",
2958 "bsc_cs0",
2959 "bsc_cs2",
2960 "bsc_cs4",
2961 "bsc_cs5a_0",
2962 "bsc_cs5a_1",
2963 "bsc_cs5b",
2964 "bsc_cs6a",
2965 "bsc_rd_we8",
2966 "bsc_rd_we16",
2967 "bsc_rd_we32",
2968 "bsc_bs",
2969 "bsc_rdwr",
2970 };
2971
2972 static const char * const ceu0_groups[] = {
2973 "ceu0_data_0_7",
2974 "ceu0_data_8_15_0",
2975 "ceu0_data_8_15_1",
2976 "ceu0_clk_0",
2977 "ceu0_clk_1",
2978 "ceu0_clk_2",
2979 "ceu0_sync",
2980 "ceu0_field",
2981 };
2982
2983 static const char * const ceu1_groups[] = {
2984 "ceu1_data",
2985 "ceu1_clk",
2986 "ceu1_sync",
2987 "ceu1_field",
2988 };
2989
2990 static const char * const fsia_groups[] = {
2991 "fsia_mclk_in",
2992 "fsia_mclk_out",
2993 "fsia_sclk_in",
2994 "fsia_sclk_out",
2995 "fsia_data_in_0",
2996 "fsia_data_in_1",
2997 "fsia_data_out_0",
2998 "fsia_data_out_1",
2999 "fsia_data_out_2",
3000 "fsia_spdif_0",
3001 "fsia_spdif_1",
3002 };
3003
3004 static const char * const fsib_groups[] = {
3005 "fsib_mclk_in",
3006 };
3007
3008 static const char * const gether_groups[] = {
3009 "gether_rmii",
3010 "gether_mii",
3011 "gether_gmii",
3012 "gether_int",
3013 "gether_link",
3014 "gether_wol",
3015 };
3016
3017 static const char * const hdmi_groups[] = {
3018 "hdmi",
3019 };
3020
3021 static const char * const intc_groups[] = {
3022 "intc_irq0_0",
3023 "intc_irq0_1",
3024 "intc_irq1",
3025 "intc_irq2_0",
3026 "intc_irq2_1",
3027 "intc_irq3_0",
3028 "intc_irq3_1",
3029 "intc_irq4_0",
3030 "intc_irq4_1",
3031 "intc_irq5_0",
3032 "intc_irq5_1",
3033 "intc_irq6_0",
3034 "intc_irq6_1",
3035 "intc_irq7_0",
3036 "intc_irq7_1",
3037 "intc_irq8",
3038 "intc_irq9_0",
3039 "intc_irq9_1",
3040 "intc_irq10",
3041 "intc_irq11",
3042 "intc_irq12_0",
3043 "intc_irq12_1",
3044 "intc_irq13_0",
3045 "intc_irq13_1",
3046 "intc_irq14_0",
3047 "intc_irq14_1",
3048 "intc_irq15_0",
3049 "intc_irq15_1",
3050 "intc_irq16_0",
3051 "intc_irq16_1",
3052 "intc_irq17",
3053 "intc_irq18",
3054 "intc_irq19",
3055 "intc_irq20",
3056 "intc_irq21",
3057 "intc_irq22",
3058 "intc_irq23",
3059 "intc_irq24",
3060 "intc_irq25",
3061 "intc_irq26_0",
3062 "intc_irq26_1",
3063 "intc_irq27_0",
3064 "intc_irq27_1",
3065 "intc_irq28_0",
3066 "intc_irq28_1",
3067 "intc_irq29_0",
3068 "intc_irq29_1",
3069 "intc_irq30_0",
3070 "intc_irq30_1",
3071 "intc_irq31_0",
3072 "intc_irq31_1",
3073 };
3074
3075 static const char * const lcd0_groups[] = {
3076 "lcd0_data8",
3077 "lcd0_data9",
3078 "lcd0_data12",
3079 "lcd0_data16",
3080 "lcd0_data18",
3081 "lcd0_data24_0",
3082 "lcd0_data24_1",
3083 "lcd0_display",
3084 "lcd0_lclk_0",
3085 "lcd0_lclk_1",
3086 "lcd0_sync",
3087 "lcd0_sys",
3088 };
3089
3090 static const char * const lcd1_groups[] = {
3091 "lcd1_data8",
3092 "lcd1_data9",
3093 "lcd1_data12",
3094 "lcd1_data16",
3095 "lcd1_data18",
3096 "lcd1_data24",
3097 "lcd1_display",
3098 "lcd1_lclk",
3099 "lcd1_sync",
3100 "lcd1_sys",
3101 };
3102
3103 static const char * const mmc0_groups[] = {
3104 "mmc0_data1_0",
3105 "mmc0_data4_0",
3106 "mmc0_data8_0",
3107 "mmc0_ctrl_0",
3108 "mmc0_data1_1",
3109 "mmc0_data4_1",
3110 "mmc0_data8_1",
3111 "mmc0_ctrl_1",
3112 };
3113
3114 static const char * const scifa0_groups[] = {
3115 "scifa0_data",
3116 "scifa0_clk",
3117 "scifa0_ctrl",
3118 };
3119
3120 static const char * const scifa1_groups[] = {
3121 "scifa1_data",
3122 "scifa1_clk",
3123 "scifa1_ctrl",
3124 };
3125
3126 static const char * const scifa2_groups[] = {
3127 "scifa2_data",
3128 "scifa2_clk_0",
3129 "scifa2_clk_1",
3130 "scifa2_ctrl",
3131 };
3132
3133 static const char * const scifa3_groups[] = {
3134 "scifa3_data_0",
3135 "scifa3_clk_0",
3136 "scifa3_ctrl_0",
3137 "scifa3_data_1",
3138 "scifa3_clk_1",
3139 "scifa3_ctrl_1",
3140 };
3141
3142 static const char * const scifa4_groups[] = {
3143 "scifa4_data_0",
3144 "scifa4_data_1",
3145 "scifa4_data_2",
3146 "scifa4_clk_0",
3147 "scifa4_clk_1",
3148 };
3149
3150 static const char * const scifa5_groups[] = {
3151 "scifa5_data_0",
3152 "scifa5_data_1",
3153 "scifa5_data_2",
3154 "scifa5_clk_0",
3155 "scifa5_clk_1",
3156 };
3157
3158 static const char * const scifa6_groups[] = {
3159 "scifa6_data",
3160 "scifa6_clk",
3161 };
3162
3163 static const char * const scifa7_groups[] = {
3164 "scifa7_data",
3165 };
3166
3167 static const char * const scifb_groups[] = {
3168 "scifb_data_0",
3169 "scifb_clk_0",
3170 "scifb_ctrl_0",
3171 "scifb_data_1",
3172 "scifb_clk_1",
3173 "scifb_ctrl_1",
3174 };
3175
3176 static const char * const sdhi0_groups[] = {
3177 "sdhi0_data1",
3178 "sdhi0_data4",
3179 "sdhi0_ctrl",
3180 "sdhi0_cd",
3181 "sdhi0_wp",
3182 };
3183
3184 static const char * const sdhi1_groups[] = {
3185 "sdhi1_data1",
3186 "sdhi1_data4",
3187 "sdhi1_ctrl",
3188 "sdhi1_cd",
3189 "sdhi1_wp",
3190 };
3191
3192 static const char * const sdhi2_groups[] = {
3193 "sdhi2_data1",
3194 "sdhi2_data4",
3195 "sdhi2_ctrl",
3196 "sdhi2_cd_0",
3197 "sdhi2_wp_0",
3198 "sdhi2_cd_1",
3199 "sdhi2_wp_1",
3200 };
3201
3202 static const char * const tpu0_groups[] = {
3203 "tpu0_to0",
3204 "tpu0_to1",
3205 "tpu0_to2_0",
3206 "tpu0_to2_1",
3207 "tpu0_to3",
3208 };
3209
3210 static const struct sh_pfc_function pinmux_functions[] = {
3211 SH_PFC_FUNCTION(bsc),
3212 SH_PFC_FUNCTION(ceu0),
3213 SH_PFC_FUNCTION(ceu1),
3214 SH_PFC_FUNCTION(fsia),
3215 SH_PFC_FUNCTION(fsib),
3216 SH_PFC_FUNCTION(gether),
3217 SH_PFC_FUNCTION(hdmi),
3218 SH_PFC_FUNCTION(intc),
3219 SH_PFC_FUNCTION(lcd0),
3220 SH_PFC_FUNCTION(lcd1),
3221 SH_PFC_FUNCTION(mmc0),
3222 SH_PFC_FUNCTION(scifa0),
3223 SH_PFC_FUNCTION(scifa1),
3224 SH_PFC_FUNCTION(scifa2),
3225 SH_PFC_FUNCTION(scifa3),
3226 SH_PFC_FUNCTION(scifa4),
3227 SH_PFC_FUNCTION(scifa5),
3228 SH_PFC_FUNCTION(scifa6),
3229 SH_PFC_FUNCTION(scifa7),
3230 SH_PFC_FUNCTION(scifb),
3231 SH_PFC_FUNCTION(sdhi0),
3232 SH_PFC_FUNCTION(sdhi1),
3233 SH_PFC_FUNCTION(sdhi2),
3234 SH_PFC_FUNCTION(tpu0),
3235 };
3236
3237 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3238 PORTCR(0, 0xe6050000), /* PORT0CR */
3239 PORTCR(1, 0xe6050001), /* PORT1CR */
3240 PORTCR(2, 0xe6050002), /* PORT2CR */
3241 PORTCR(3, 0xe6050003), /* PORT3CR */
3242 PORTCR(4, 0xe6050004), /* PORT4CR */
3243 PORTCR(5, 0xe6050005), /* PORT5CR */
3244 PORTCR(6, 0xe6050006), /* PORT6CR */
3245 PORTCR(7, 0xe6050007), /* PORT7CR */
3246 PORTCR(8, 0xe6050008), /* PORT8CR */
3247 PORTCR(9, 0xe6050009), /* PORT9CR */
3248 PORTCR(10, 0xe605000a), /* PORT10CR */
3249 PORTCR(11, 0xe605000b), /* PORT11CR */
3250 PORTCR(12, 0xe605000c), /* PORT12CR */
3251 PORTCR(13, 0xe605000d), /* PORT13CR */
3252 PORTCR(14, 0xe605000e), /* PORT14CR */
3253 PORTCR(15, 0xe605000f), /* PORT15CR */
3254 PORTCR(16, 0xe6050010), /* PORT16CR */
3255 PORTCR(17, 0xe6050011), /* PORT17CR */
3256 PORTCR(18, 0xe6050012), /* PORT18CR */
3257 PORTCR(19, 0xe6050013), /* PORT19CR */
3258 PORTCR(20, 0xe6050014), /* PORT20CR */
3259 PORTCR(21, 0xe6050015), /* PORT21CR */
3260 PORTCR(22, 0xe6050016), /* PORT22CR */
3261 PORTCR(23, 0xe6050017), /* PORT23CR */
3262 PORTCR(24, 0xe6050018), /* PORT24CR */
3263 PORTCR(25, 0xe6050019), /* PORT25CR */
3264 PORTCR(26, 0xe605001a), /* PORT26CR */
3265 PORTCR(27, 0xe605001b), /* PORT27CR */
3266 PORTCR(28, 0xe605001c), /* PORT28CR */
3267 PORTCR(29, 0xe605001d), /* PORT29CR */
3268 PORTCR(30, 0xe605001e), /* PORT30CR */
3269 PORTCR(31, 0xe605001f), /* PORT31CR */
3270 PORTCR(32, 0xe6050020), /* PORT32CR */
3271 PORTCR(33, 0xe6050021), /* PORT33CR */
3272 PORTCR(34, 0xe6050022), /* PORT34CR */
3273 PORTCR(35, 0xe6050023), /* PORT35CR */
3274 PORTCR(36, 0xe6050024), /* PORT36CR */
3275 PORTCR(37, 0xe6050025), /* PORT37CR */
3276 PORTCR(38, 0xe6050026), /* PORT38CR */
3277 PORTCR(39, 0xe6050027), /* PORT39CR */
3278 PORTCR(40, 0xe6050028), /* PORT40CR */
3279 PORTCR(41, 0xe6050029), /* PORT41CR */
3280 PORTCR(42, 0xe605002a), /* PORT42CR */
3281 PORTCR(43, 0xe605002b), /* PORT43CR */
3282 PORTCR(44, 0xe605002c), /* PORT44CR */
3283 PORTCR(45, 0xe605002d), /* PORT45CR */
3284 PORTCR(46, 0xe605002e), /* PORT46CR */
3285 PORTCR(47, 0xe605002f), /* PORT47CR */
3286 PORTCR(48, 0xe6050030), /* PORT48CR */
3287 PORTCR(49, 0xe6050031), /* PORT49CR */
3288 PORTCR(50, 0xe6050032), /* PORT50CR */
3289 PORTCR(51, 0xe6050033), /* PORT51CR */
3290 PORTCR(52, 0xe6050034), /* PORT52CR */
3291 PORTCR(53, 0xe6050035), /* PORT53CR */
3292 PORTCR(54, 0xe6050036), /* PORT54CR */
3293 PORTCR(55, 0xe6050037), /* PORT55CR */
3294 PORTCR(56, 0xe6050038), /* PORT56CR */
3295 PORTCR(57, 0xe6050039), /* PORT57CR */
3296 PORTCR(58, 0xe605003a), /* PORT58CR */
3297 PORTCR(59, 0xe605003b), /* PORT59CR */
3298 PORTCR(60, 0xe605003c), /* PORT60CR */
3299 PORTCR(61, 0xe605003d), /* PORT61CR */
3300 PORTCR(62, 0xe605003e), /* PORT62CR */
3301 PORTCR(63, 0xe605003f), /* PORT63CR */
3302 PORTCR(64, 0xe6050040), /* PORT64CR */
3303 PORTCR(65, 0xe6050041), /* PORT65CR */
3304 PORTCR(66, 0xe6050042), /* PORT66CR */
3305 PORTCR(67, 0xe6050043), /* PORT67CR */
3306 PORTCR(68, 0xe6050044), /* PORT68CR */
3307 PORTCR(69, 0xe6050045), /* PORT69CR */
3308 PORTCR(70, 0xe6050046), /* PORT70CR */
3309 PORTCR(71, 0xe6050047), /* PORT71CR */
3310 PORTCR(72, 0xe6050048), /* PORT72CR */
3311 PORTCR(73, 0xe6050049), /* PORT73CR */
3312 PORTCR(74, 0xe605004a), /* PORT74CR */
3313 PORTCR(75, 0xe605004b), /* PORT75CR */
3314 PORTCR(76, 0xe605004c), /* PORT76CR */
3315 PORTCR(77, 0xe605004d), /* PORT77CR */
3316 PORTCR(78, 0xe605004e), /* PORT78CR */
3317 PORTCR(79, 0xe605004f), /* PORT79CR */
3318 PORTCR(80, 0xe6050050), /* PORT80CR */
3319 PORTCR(81, 0xe6050051), /* PORT81CR */
3320 PORTCR(82, 0xe6050052), /* PORT82CR */
3321 PORTCR(83, 0xe6050053), /* PORT83CR */
3322
3323 PORTCR(84, 0xe6051054), /* PORT84CR */
3324 PORTCR(85, 0xe6051055), /* PORT85CR */
3325 PORTCR(86, 0xe6051056), /* PORT86CR */
3326 PORTCR(87, 0xe6051057), /* PORT87CR */
3327 PORTCR(88, 0xe6051058), /* PORT88CR */
3328 PORTCR(89, 0xe6051059), /* PORT89CR */
3329 PORTCR(90, 0xe605105a), /* PORT90CR */
3330 PORTCR(91, 0xe605105b), /* PORT91CR */
3331 PORTCR(92, 0xe605105c), /* PORT92CR */
3332 PORTCR(93, 0xe605105d), /* PORT93CR */
3333 PORTCR(94, 0xe605105e), /* PORT94CR */
3334 PORTCR(95, 0xe605105f), /* PORT95CR */
3335 PORTCR(96, 0xe6051060), /* PORT96CR */
3336 PORTCR(97, 0xe6051061), /* PORT97CR */
3337 PORTCR(98, 0xe6051062), /* PORT98CR */
3338 PORTCR(99, 0xe6051063), /* PORT99CR */
3339 PORTCR(100, 0xe6051064), /* PORT100CR */
3340 PORTCR(101, 0xe6051065), /* PORT101CR */
3341 PORTCR(102, 0xe6051066), /* PORT102CR */
3342 PORTCR(103, 0xe6051067), /* PORT103CR */
3343 PORTCR(104, 0xe6051068), /* PORT104CR */
3344 PORTCR(105, 0xe6051069), /* PORT105CR */
3345 PORTCR(106, 0xe605106a), /* PORT106CR */
3346 PORTCR(107, 0xe605106b), /* PORT107CR */
3347 PORTCR(108, 0xe605106c), /* PORT108CR */
3348 PORTCR(109, 0xe605106d), /* PORT109CR */
3349 PORTCR(110, 0xe605106e), /* PORT110CR */
3350 PORTCR(111, 0xe605106f), /* PORT111CR */
3351 PORTCR(112, 0xe6051070), /* PORT112CR */
3352 PORTCR(113, 0xe6051071), /* PORT113CR */
3353 PORTCR(114, 0xe6051072), /* PORT114CR */
3354
3355 PORTCR(115, 0xe6052073), /* PORT115CR */
3356 PORTCR(116, 0xe6052074), /* PORT116CR */
3357 PORTCR(117, 0xe6052075), /* PORT117CR */
3358 PORTCR(118, 0xe6052076), /* PORT118CR */
3359 PORTCR(119, 0xe6052077), /* PORT119CR */
3360 PORTCR(120, 0xe6052078), /* PORT120CR */
3361 PORTCR(121, 0xe6052079), /* PORT121CR */
3362 PORTCR(122, 0xe605207a), /* PORT122CR */
3363 PORTCR(123, 0xe605207b), /* PORT123CR */
3364 PORTCR(124, 0xe605207c), /* PORT124CR */
3365 PORTCR(125, 0xe605207d), /* PORT125CR */
3366 PORTCR(126, 0xe605207e), /* PORT126CR */
3367 PORTCR(127, 0xe605207f), /* PORT127CR */
3368 PORTCR(128, 0xe6052080), /* PORT128CR */
3369 PORTCR(129, 0xe6052081), /* PORT129CR */
3370 PORTCR(130, 0xe6052082), /* PORT130CR */
3371 PORTCR(131, 0xe6052083), /* PORT131CR */
3372 PORTCR(132, 0xe6052084), /* PORT132CR */
3373 PORTCR(133, 0xe6052085), /* PORT133CR */
3374 PORTCR(134, 0xe6052086), /* PORT134CR */
3375 PORTCR(135, 0xe6052087), /* PORT135CR */
3376 PORTCR(136, 0xe6052088), /* PORT136CR */
3377 PORTCR(137, 0xe6052089), /* PORT137CR */
3378 PORTCR(138, 0xe605208a), /* PORT138CR */
3379 PORTCR(139, 0xe605208b), /* PORT139CR */
3380 PORTCR(140, 0xe605208c), /* PORT140CR */
3381 PORTCR(141, 0xe605208d), /* PORT141CR */
3382 PORTCR(142, 0xe605208e), /* PORT142CR */
3383 PORTCR(143, 0xe605208f), /* PORT143CR */
3384 PORTCR(144, 0xe6052090), /* PORT144CR */
3385 PORTCR(145, 0xe6052091), /* PORT145CR */
3386 PORTCR(146, 0xe6052092), /* PORT146CR */
3387 PORTCR(147, 0xe6052093), /* PORT147CR */
3388 PORTCR(148, 0xe6052094), /* PORT148CR */
3389 PORTCR(149, 0xe6052095), /* PORT149CR */
3390 PORTCR(150, 0xe6052096), /* PORT150CR */
3391 PORTCR(151, 0xe6052097), /* PORT151CR */
3392 PORTCR(152, 0xe6052098), /* PORT152CR */
3393 PORTCR(153, 0xe6052099), /* PORT153CR */
3394 PORTCR(154, 0xe605209a), /* PORT154CR */
3395 PORTCR(155, 0xe605209b), /* PORT155CR */
3396 PORTCR(156, 0xe605209c), /* PORT156CR */
3397 PORTCR(157, 0xe605209d), /* PORT157CR */
3398 PORTCR(158, 0xe605209e), /* PORT158CR */
3399 PORTCR(159, 0xe605209f), /* PORT159CR */
3400 PORTCR(160, 0xe60520a0), /* PORT160CR */
3401 PORTCR(161, 0xe60520a1), /* PORT161CR */
3402 PORTCR(162, 0xe60520a2), /* PORT162CR */
3403 PORTCR(163, 0xe60520a3), /* PORT163CR */
3404 PORTCR(164, 0xe60520a4), /* PORT164CR */
3405 PORTCR(165, 0xe60520a5), /* PORT165CR */
3406 PORTCR(166, 0xe60520a6), /* PORT166CR */
3407 PORTCR(167, 0xe60520a7), /* PORT167CR */
3408 PORTCR(168, 0xe60520a8), /* PORT168CR */
3409 PORTCR(169, 0xe60520a9), /* PORT169CR */
3410 PORTCR(170, 0xe60520aa), /* PORT170CR */
3411 PORTCR(171, 0xe60520ab), /* PORT171CR */
3412 PORTCR(172, 0xe60520ac), /* PORT172CR */
3413 PORTCR(173, 0xe60520ad), /* PORT173CR */
3414 PORTCR(174, 0xe60520ae), /* PORT174CR */
3415 PORTCR(175, 0xe60520af), /* PORT175CR */
3416 PORTCR(176, 0xe60520b0), /* PORT176CR */
3417 PORTCR(177, 0xe60520b1), /* PORT177CR */
3418 PORTCR(178, 0xe60520b2), /* PORT178CR */
3419 PORTCR(179, 0xe60520b3), /* PORT179CR */
3420 PORTCR(180, 0xe60520b4), /* PORT180CR */
3421 PORTCR(181, 0xe60520b5), /* PORT181CR */
3422 PORTCR(182, 0xe60520b6), /* PORT182CR */
3423 PORTCR(183, 0xe60520b7), /* PORT183CR */
3424 PORTCR(184, 0xe60520b8), /* PORT184CR */
3425 PORTCR(185, 0xe60520b9), /* PORT185CR */
3426 PORTCR(186, 0xe60520ba), /* PORT186CR */
3427 PORTCR(187, 0xe60520bb), /* PORT187CR */
3428 PORTCR(188, 0xe60520bc), /* PORT188CR */
3429 PORTCR(189, 0xe60520bd), /* PORT189CR */
3430 PORTCR(190, 0xe60520be), /* PORT190CR */
3431 PORTCR(191, 0xe60520bf), /* PORT191CR */
3432 PORTCR(192, 0xe60520c0), /* PORT192CR */
3433 PORTCR(193, 0xe60520c1), /* PORT193CR */
3434 PORTCR(194, 0xe60520c2), /* PORT194CR */
3435 PORTCR(195, 0xe60520c3), /* PORT195CR */
3436 PORTCR(196, 0xe60520c4), /* PORT196CR */
3437 PORTCR(197, 0xe60520c5), /* PORT197CR */
3438 PORTCR(198, 0xe60520c6), /* PORT198CR */
3439 PORTCR(199, 0xe60520c7), /* PORT199CR */
3440 PORTCR(200, 0xe60520c8), /* PORT200CR */
3441 PORTCR(201, 0xe60520c9), /* PORT201CR */
3442 PORTCR(202, 0xe60520ca), /* PORT202CR */
3443 PORTCR(203, 0xe60520cb), /* PORT203CR */
3444 PORTCR(204, 0xe60520cc), /* PORT204CR */
3445 PORTCR(205, 0xe60520cd), /* PORT205CR */
3446 PORTCR(206, 0xe60520ce), /* PORT206CR */
3447 PORTCR(207, 0xe60520cf), /* PORT207CR */
3448 PORTCR(208, 0xe60520d0), /* PORT208CR */
3449 PORTCR(209, 0xe60520d1), /* PORT209CR */
3450
3451 PORTCR(210, 0xe60530d2), /* PORT210CR */
3452 PORTCR(211, 0xe60530d3), /* PORT211CR */
3453
3454 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3455 MSEL1CR_31_0, MSEL1CR_31_1,
3456 MSEL1CR_30_0, MSEL1CR_30_1,
3457 MSEL1CR_29_0, MSEL1CR_29_1,
3458 MSEL1CR_28_0, MSEL1CR_28_1,
3459 MSEL1CR_27_0, MSEL1CR_27_1,
3460 MSEL1CR_26_0, MSEL1CR_26_1,
3461 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3462 0, 0, 0, 0, 0, 0, 0, 0,
3463 MSEL1CR_16_0, MSEL1CR_16_1,
3464 MSEL1CR_15_0, MSEL1CR_15_1,
3465 MSEL1CR_14_0, MSEL1CR_14_1,
3466 MSEL1CR_13_0, MSEL1CR_13_1,
3467 MSEL1CR_12_0, MSEL1CR_12_1,
3468 0, 0, 0, 0,
3469 MSEL1CR_9_0, MSEL1CR_9_1,
3470 0, 0,
3471 MSEL1CR_7_0, MSEL1CR_7_1,
3472 MSEL1CR_6_0, MSEL1CR_6_1,
3473 MSEL1CR_5_0, MSEL1CR_5_1,
3474 MSEL1CR_4_0, MSEL1CR_4_1,
3475 MSEL1CR_3_0, MSEL1CR_3_1,
3476 MSEL1CR_2_0, MSEL1CR_2_1,
3477 0, 0,
3478 MSEL1CR_0_0, MSEL1CR_0_1,
3479 }
3480 },
3481 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3482 0, 0, 0, 0, 0, 0, 0, 0,
3483 0, 0, 0, 0, 0, 0, 0, 0,
3484 0, 0, 0, 0, 0, 0, 0, 0,
3485 0, 0, 0, 0, 0, 0, 0, 0,
3486 MSEL3CR_15_0, MSEL3CR_15_1,
3487 0, 0, 0, 0, 0, 0, 0, 0,
3488 0, 0, 0, 0, 0, 0, 0, 0,
3489 MSEL3CR_6_0, MSEL3CR_6_1,
3490 0, 0, 0, 0, 0, 0, 0, 0,
3491 0, 0, 0, 0,
3492 }
3493 },
3494 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3495 0, 0, 0, 0, 0, 0, 0, 0,
3496 0, 0, 0, 0, 0, 0, 0, 0,
3497 0, 0, 0, 0, 0, 0, 0, 0,
3498 MSEL4CR_19_0, MSEL4CR_19_1,
3499 MSEL4CR_18_0, MSEL4CR_18_1,
3500 0, 0, 0, 0,
3501 MSEL4CR_15_0, MSEL4CR_15_1,
3502 0, 0, 0, 0, 0, 0, 0, 0,
3503 MSEL4CR_10_0, MSEL4CR_10_1,
3504 0, 0, 0, 0, 0, 0,
3505 MSEL4CR_6_0, MSEL4CR_6_1,
3506 0, 0,
3507 MSEL4CR_4_0, MSEL4CR_4_1,
3508 0, 0, 0, 0,
3509 MSEL4CR_1_0, MSEL4CR_1_1,
3510 0, 0,
3511 }
3512 },
3513 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3514 MSEL5CR_31_0, MSEL5CR_31_1,
3515 MSEL5CR_30_0, MSEL5CR_30_1,
3516 MSEL5CR_29_0, MSEL5CR_29_1,
3517 0, 0,
3518 MSEL5CR_27_0, MSEL5CR_27_1,
3519 0, 0,
3520 MSEL5CR_25_0, MSEL5CR_25_1,
3521 0, 0,
3522 MSEL5CR_23_0, MSEL5CR_23_1,
3523 0, 0,
3524 MSEL5CR_21_0, MSEL5CR_21_1,
3525 0, 0,
3526 MSEL5CR_19_0, MSEL5CR_19_1,
3527 0, 0,
3528 MSEL5CR_17_0, MSEL5CR_17_1,
3529 0, 0,
3530 MSEL5CR_15_0, MSEL5CR_15_1,
3531 MSEL5CR_14_0, MSEL5CR_14_1,
3532 MSEL5CR_13_0, MSEL5CR_13_1,
3533 MSEL5CR_12_0, MSEL5CR_12_1,
3534 MSEL5CR_11_0, MSEL5CR_11_1,
3535 MSEL5CR_10_0, MSEL5CR_10_1,
3536 0, 0,
3537 MSEL5CR_8_0, MSEL5CR_8_1,
3538 MSEL5CR_7_0, MSEL5CR_7_1,
3539 MSEL5CR_6_0, MSEL5CR_6_1,
3540 MSEL5CR_5_0, MSEL5CR_5_1,
3541 MSEL5CR_4_0, MSEL5CR_4_1,
3542 MSEL5CR_3_0, MSEL5CR_3_1,
3543 MSEL5CR_2_0, MSEL5CR_2_1,
3544 0, 0,
3545 MSEL5CR_0_0, MSEL5CR_0_1,
3546 }
3547 },
3548 { },
3549 };
3550
3551 static const struct pinmux_data_reg pinmux_data_regs[] = {
3552 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3553 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3554 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3555 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3556 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3557 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3558 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3559 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3560 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3561 },
3562 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3563 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3564 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3565 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3566 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3567 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3568 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3569 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3570 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3571 },
3572 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3573 0, 0, 0, 0,
3574 0, 0, 0, 0,
3575 0, 0, 0, 0,
3576 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3577 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3578 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3579 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3580 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3581 },
3582 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3583 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3584 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3585 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3586 0, 0, 0, 0,
3587 0, 0, 0, 0,
3588 0, 0, 0, 0,
3589 0, 0, 0, 0,
3590 0, 0, 0, 0 }
3591 },
3592 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3593 0, 0, 0, 0,
3594 0, 0, 0, 0,
3595 0, 0, 0, 0,
3596 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3597 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3598 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3599 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3600 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3601 },
3602 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3603 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3604 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3605 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3606 PORT115_DATA, 0, 0, 0,
3607 0, 0, 0, 0,
3608 0, 0, 0, 0,
3609 0, 0, 0, 0,
3610 0, 0, 0, 0 }
3611 },
3612 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3613 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3614 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3615 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3616 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3617 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3618 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3619 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3620 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3621 },
3622 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3623 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3624 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3625 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3626 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3627 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3628 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3629 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3630 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3631 },
3632 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3633 0, 0, 0, 0,
3634 0, 0, 0, 0,
3635 0, 0, 0, 0,
3636 0, 0, PORT209_DATA, PORT208_DATA,
3637 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3638 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3639 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3640 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3641 },
3642 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3643 0, 0, 0, 0,
3644 0, 0, 0, 0,
3645 0, 0, 0, 0,
3646 PORT211_DATA, PORT210_DATA, 0, 0,
3647 0, 0, 0, 0,
3648 0, 0, 0, 0,
3649 0, 0, 0, 0,
3650 0, 0, 0, 0 }
3651 },
3652 { },
3653 };
3654
3655 static const struct pinmux_irq pinmux_irqs[] = {
3656 PINMUX_IRQ(irq_pin(0), 2, 13), /* IRQ0A */
3657 PINMUX_IRQ(irq_pin(1), 20), /* IRQ1A */
3658 PINMUX_IRQ(irq_pin(2), 11, 12), /* IRQ2A */
3659 PINMUX_IRQ(irq_pin(3), 10, 14), /* IRQ3A */
3660 PINMUX_IRQ(irq_pin(4), 15, 172), /* IRQ4A */
3661 PINMUX_IRQ(irq_pin(5), 0, 1), /* IRQ5A */
3662 PINMUX_IRQ(irq_pin(6), 121, 173), /* IRQ6A */
3663 PINMUX_IRQ(irq_pin(7), 120, 209), /* IRQ7A */
3664 PINMUX_IRQ(irq_pin(8), 119), /* IRQ8A */
3665 PINMUX_IRQ(irq_pin(9), 118, 210), /* IRQ9A */
3666 PINMUX_IRQ(irq_pin(10), 19), /* IRQ10A */
3667 PINMUX_IRQ(irq_pin(11), 104), /* IRQ11A */
3668 PINMUX_IRQ(irq_pin(12), 42, 97), /* IRQ12A */
3669 PINMUX_IRQ(irq_pin(13), 64, 98), /* IRQ13A */
3670 PINMUX_IRQ(irq_pin(14), 63, 99), /* IRQ14A */
3671 PINMUX_IRQ(irq_pin(15), 62, 100), /* IRQ15A */
3672 PINMUX_IRQ(irq_pin(16), 68, 211), /* IRQ16A */
3673 PINMUX_IRQ(irq_pin(17), 69), /* IRQ17A */
3674 PINMUX_IRQ(irq_pin(18), 70), /* IRQ18A */
3675 PINMUX_IRQ(irq_pin(19), 71), /* IRQ19A */
3676 PINMUX_IRQ(irq_pin(20), 67), /* IRQ20A */
3677 PINMUX_IRQ(irq_pin(21), 202), /* IRQ21A */
3678 PINMUX_IRQ(irq_pin(22), 95), /* IRQ22A */
3679 PINMUX_IRQ(irq_pin(23), 96), /* IRQ23A */
3680 PINMUX_IRQ(irq_pin(24), 180), /* IRQ24A */
3681 PINMUX_IRQ(irq_pin(25), 38), /* IRQ25A */
3682 PINMUX_IRQ(irq_pin(26), 58, 81), /* IRQ26A */
3683 PINMUX_IRQ(irq_pin(27), 57, 168), /* IRQ27A */
3684 PINMUX_IRQ(irq_pin(28), 56, 169), /* IRQ28A */
3685 PINMUX_IRQ(irq_pin(29), 50, 170), /* IRQ29A */
3686 PINMUX_IRQ(irq_pin(30), 49, 171), /* IRQ30A */
3687 PINMUX_IRQ(irq_pin(31), 41, 167), /* IRQ31A */
3688 };
3689
3690 #define PORTnCR_PULMD_OFF (0 << 6)
3691 #define PORTnCR_PULMD_DOWN (2 << 6)
3692 #define PORTnCR_PULMD_UP (3 << 6)
3693 #define PORTnCR_PULMD_MASK (3 << 6)
3694
3695 struct r8a7740_portcr_group {
3696 unsigned int end_pin;
3697 unsigned int offset;
3698 };
3699
3700 static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3701 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3702 };
3703
3704 static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3705 {
3706 unsigned int i;
3707
3708 for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3709 const struct r8a7740_portcr_group *group =
3710 &r8a7740_portcr_offsets[i];
3711
3712 if (pin <= group->end_pin)
3713 return pfc->windows->virt + group->offset + pin;
3714 }
3715
3716 return NULL;
3717 }
3718
3719 static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3720 {
3721 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3722 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3723
3724 switch (value) {
3725 case PORTnCR_PULMD_UP:
3726 return PIN_CONFIG_BIAS_PULL_UP;
3727 case PORTnCR_PULMD_DOWN:
3728 return PIN_CONFIG_BIAS_PULL_DOWN;
3729 case PORTnCR_PULMD_OFF:
3730 default:
3731 return PIN_CONFIG_BIAS_DISABLE;
3732 }
3733 }
3734
3735 static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3736 unsigned int bias)
3737 {
3738 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3739 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3740
3741 switch (bias) {
3742 case PIN_CONFIG_BIAS_PULL_UP:
3743 value |= PORTnCR_PULMD_UP;
3744 break;
3745 case PIN_CONFIG_BIAS_PULL_DOWN:
3746 value |= PORTnCR_PULMD_DOWN;
3747 break;
3748 }
3749
3750 iowrite8(value, addr);
3751 }
3752
3753 static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
3754 .get_bias = r8a7740_pinmux_get_bias,
3755 .set_bias = r8a7740_pinmux_set_bias,
3756 };
3757
3758 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3759 .name = "r8a7740_pfc",
3760 .ops = &r8a7740_pinmux_ops,
3761
3762 .input = { PINMUX_INPUT_BEGIN,
3763 PINMUX_INPUT_END },
3764 .output = { PINMUX_OUTPUT_BEGIN,
3765 PINMUX_OUTPUT_END },
3766 .function = { PINMUX_FUNCTION_BEGIN,
3767 PINMUX_FUNCTION_END },
3768
3769 .pins = pinmux_pins,
3770 .nr_pins = ARRAY_SIZE(pinmux_pins),
3771 .groups = pinmux_groups,
3772 .nr_groups = ARRAY_SIZE(pinmux_groups),
3773 .functions = pinmux_functions,
3774 .nr_functions = ARRAY_SIZE(pinmux_functions),
3775
3776 .cfg_regs = pinmux_config_regs,
3777 .data_regs = pinmux_data_regs,
3778
3779 .gpio_data = pinmux_data,
3780 .gpio_data_size = ARRAY_SIZE(pinmux_data),
3781
3782 .gpio_irq = pinmux_irqs,
3783 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3784 };
Linux with added FPC-III support