drivers/pinctrl/sh-pfc/pfc-sh73a0.c

   1 /*
   2  * sh73a0 processor support - PFC hardware block
   3  *
   4  * Copyright (C) 2010 Renesas Solutions Corp.
   5  * Copyright (C) 2010 NISHIMOTO Hiroki
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; version 2 of the
  10  * License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21 #include <linux/io.h>
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/pinctrl/pinconf-generic.h>
  25 #include <linux/regulator/driver.h>
  26 #include <linux/regulator/machine.h>
  27 #include <linux/slab.h>
  28
  29 #include <mach/irqs.h>
  30
  31 #include "core.h"
  32 #include "sh_pfc.h"
  33
  34 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
  35         PORT_10(0,  fn, pfx, sfx), PORT_90(0, fn, pfx, sfx),            \
  36         PORT_10(100, fn, pfx##10, sfx),                                 \
  37         PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
  38         PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
  39         PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
  40         PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
  41         PORT_1(118, fn, pfx##118, sfx),                                 \
  42         PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
  43         PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
  44         PORT_10(150, fn, pfx##15, sfx),                                 \
  45         PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
  46         PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
  47         PORT_1(164, fn, pfx##164, sfx),                                 \
  48         PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
  49         PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
  50         PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
  51         PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
  52         PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
  53         PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
  54         PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
  55         PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
  56         PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
  57         PORT_1(282, fn, pfx##282, sfx),                                 \
  58         PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
  59         PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
  60
  61 enum {
  62         PINMUX_RESERVED = 0,
  63
  64         PINMUX_DATA_BEGIN,
  65         PORT_ALL(DATA),                 /* PORT0_DATA -> PORT309_DATA */
  66         PINMUX_DATA_END,
  67
  68         PINMUX_INPUT_BEGIN,
  69         PORT_ALL(IN),                   /* PORT0_IN -> PORT309_IN */
  70         PINMUX_INPUT_END,
  71
  72         PINMUX_OUTPUT_BEGIN,
  73         PORT_ALL(OUT),                  /* PORT0_OUT -> PORT309_OUT */
  74         PINMUX_OUTPUT_END,
  75
  76         PINMUX_FUNCTION_BEGIN,
  77         PORT_ALL(FN_IN),                /* PORT0_FN_IN -> PORT309_FN_IN */
  78         PORT_ALL(FN_OUT),               /* PORT0_FN_OUT -> PORT309_FN_OUT */
  79         PORT_ALL(FN0),                  /* PORT0_FN0 -> PORT309_FN0 */
  80         PORT_ALL(FN1),                  /* PORT0_FN1 -> PORT309_FN1 */
  81         PORT_ALL(FN2),                  /* PORT0_FN2 -> PORT309_FN2 */
  82         PORT_ALL(FN3),                  /* PORT0_FN3 -> PORT309_FN3 */
  83         PORT_ALL(FN4),                  /* PORT0_FN4 -> PORT309_FN4 */
  84         PORT_ALL(FN5),                  /* PORT0_FN5 -> PORT309_FN5 */
  85         PORT_ALL(FN6),                  /* PORT0_FN6 -> PORT309_FN6 */
  86         PORT_ALL(FN7),                  /* PORT0_FN7 -> PORT309_FN7 */
  87
  88         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
  89         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
  90         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
  91         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
  92         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
  93         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
  94         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
  95         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
  96         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
  97         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
  98         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
  99         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
 100         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
 101         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
 102         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
 103         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
 104         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
 105         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
 106         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
 107         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
 108         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
 109         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
 110         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
 111         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
 112         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
 113         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
 114         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
 115         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
 116         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
 117         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
 118         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
 119         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
 120         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
 121         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
 122         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
 123         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
 124         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
 125         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
 126         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
 127         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
 128         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
 129         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
 130         PINMUX_FUNCTION_END,
 131
 132         PINMUX_MARK_BEGIN,
 133         /* Hardware manual Table 25-1 (Function 0-7) */
 134         VBUS_0_MARK,
 135         GPI0_MARK,
 136         GPI1_MARK,
 137         GPI2_MARK,
 138         GPI3_MARK,
 139         GPI4_MARK,
 140         GPI5_MARK,
 141         GPI6_MARK,
 142         GPI7_MARK,
 143         SCIFA7_RXD_MARK,
 144         SCIFA7_CTS__MARK,
 145         GPO7_MARK, MFG0_OUT2_MARK,
 146         GPO6_MARK, MFG1_OUT2_MARK,
 147         GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
 148         SCIFA0_TXD_MARK,
 149         SCIFA7_TXD_MARK,
 150         SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
 151         GPO0_MARK,
 152         GPO1_MARK,
 153         GPO2_MARK, STATUS0_MARK,
 154         GPO3_MARK, STATUS1_MARK,
 155         GPO4_MARK, STATUS2_MARK,
 156         VINT_MARK,
 157         TCKON_MARK,
 158         XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
 159         MFG0_OUT1_MARK, PORT27_IROUT_MARK,
 160         XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
 161         PORT28_TPU1TO1_MARK,
 162         SIM_RST_MARK, PORT29_TPU1TO1_MARK,
 163         SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
 164         SIM_D_MARK, PORT31_IROUT_MARK,
 165         SCIFA4_TXD_MARK,
 166         SCIFA4_RXD_MARK, XWUP_MARK,
 167         SCIFA4_RTS__MARK,
 168         SCIFA4_CTS__MARK,
 169         FSIBOBT_MARK, FSIBIBT_MARK,
 170         FSIBOLR_MARK, FSIBILR_MARK,
 171         FSIBOSLD_MARK,
 172         FSIBISLD_MARK,
 173         VACK_MARK,
 174         XTAL1L_MARK,
 175         SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
 176         SCIFA0_RXD_MARK,
 177         SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
 178         FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
 179         FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
 180         FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
 181         FSICISLD_MARK, FSIDISLD_MARK,
 182         FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
 183         FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
 184
 185         FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
 186         FSIAOSLD_MARK, BBIF2_TXD2_MARK,
 187         FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
 188         PORT53_FSICSPDIF_MARK,
 189         FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
 190         FSICCK_MARK, FSICOMC_MARK,
 191         FSIAISLD_MARK, TPU0TO0_MARK,
 192         A0_MARK, BS__MARK,
 193         A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
 194         A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
 195         A14_MARK, KEYOUT5_MARK,
 196         A15_MARK, KEYOUT4_MARK,
 197         A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
 198         A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
 199         A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
 200         A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
 201         A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
 202         A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
 203         A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
 204         A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
 205         A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
 206         A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
 207         A26_MARK, KEYIN6_MARK,
 208         KEYIN7_MARK,
 209         D0_NAF0_MARK,
 210         D1_NAF1_MARK,
 211         D2_NAF2_MARK,
 212         D3_NAF3_MARK,
 213         D4_NAF4_MARK,
 214         D5_NAF5_MARK,
 215         D6_NAF6_MARK,
 216         D7_NAF7_MARK,
 217         D8_NAF8_MARK,
 218         D9_NAF9_MARK,
 219         D10_NAF10_MARK,
 220         D11_NAF11_MARK,
 221         D12_NAF12_MARK,
 222         D13_NAF13_MARK,
 223         D14_NAF14_MARK,
 224         D15_NAF15_MARK,
 225         CS4__MARK,
 226         CS5A__MARK, PORT91_RDWR_MARK,
 227         CS5B__MARK, FCE1__MARK,
 228         CS6B__MARK, DACK0_MARK,
 229         FCE0__MARK, CS6A__MARK,
 230         WAIT__MARK, DREQ0_MARK,
 231         RD__FSC_MARK,
 232         WE0__FWE_MARK, RDWR_FWE_MARK,
 233         WE1__MARK,
 234         FRB_MARK,
 235         CKO_MARK,
 236         NBRSTOUT__MARK,
 237         NBRST__MARK,
 238         BBIF2_TXD_MARK,
 239         BBIF2_RXD_MARK,
 240         BBIF2_SYNC_MARK,
 241         BBIF2_SCK_MARK,
 242         SCIFA3_CTS__MARK, MFG3_IN2_MARK,
 243         SCIFA3_RXD_MARK, MFG3_IN1_MARK,
 244         BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
 245         SCIFA3_TXD_MARK,
 246         HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
 247         HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
 248         HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
 249         HSI_TX_READY_MARK, BBIF1_TXD_MARK,
 250         HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
 251         PORT115_I2C_SCL3_MARK,
 252         HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
 253         PORT116_I2C_SDA3_MARK,
 254         HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
 255         HSI_TX_FLAG_MARK,
 256         VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
 257
 258         VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
 259         VIO2_HD_MARK, LCD2D1_MARK,
 260         VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
 261         VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
 262         PORT131_KEYOUT11_MARK, LCD2D11_MARK,
 263         VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
 264         PORT132_KEYOUT10_MARK, LCD2D12_MARK,
 265         VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
 266         VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
 267         VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
 268         VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
 269         VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
 270         VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
 271         VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
 272         VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
 273         VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
 274         VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
 275         VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
 276         VIO2_D5_MARK, LCD2D3_MARK,
 277         VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
 278         VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
 279         PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
 280         VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
 281         LCD2D18_MARK,
 282         VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
 283         VIO_CKO_MARK,
 284         A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
 285         MFG0_IN2_MARK,
 286         TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
 287         TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
 288         TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
 289         SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
 290         SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
 291         SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
 292         SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
 293         DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
 294         PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
 295         PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
 296         PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
 297         PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
 298         PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
 299         LCDD0_MARK,
 300         LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
 301         LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
 302         LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
 303         LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
 304         LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
 305         LCDD6_MARK,
 306         LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
 307         LCDD8_MARK, D16_MARK,
 308         LCDD9_MARK, D17_MARK,
 309         LCDD10_MARK, D18_MARK,
 310         LCDD11_MARK, D19_MARK,
 311         LCDD12_MARK, D20_MARK,
 312         LCDD13_MARK, D21_MARK,
 313         LCDD14_MARK, D22_MARK,
 314         LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
 315         LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
 316         LCDD17_MARK, D25_MARK,
 317         LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
 318         LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
 319         LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
 320         LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
 321         LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
 322         LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
 323         LCDDCK_MARK, LCDWR__MARK,
 324         LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
 325         VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
 326         LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
 327         PORT218_VIO_CKOR_MARK,
 328         LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
 329         MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
 330         LCDVSYN_MARK, LCDVSYN2_MARK,
 331         LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
 332         MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
 333         LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
 334         VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
 335
 336         SCIFA1_TXD_MARK, OVCN2_MARK,
 337         EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
 338         SCIFA1_RTS__MARK, IDIN_MARK,
 339         SCIFA1_RXD_MARK,
 340         SCIFA1_CTS__MARK, MFG1_IN1_MARK,
 341         MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
 342         MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
 343         MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
 344         MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
 345         MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
 346         MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
 347         MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
 348         MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
 349         MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
 350         MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
 351         SCIFA6_TXD_MARK,
 352         PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
 353         PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
 354         PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
 355         PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
 356         MSIOF2R_RXD_MARK,
 357         PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
 358         MSIOF2R_TXD_MARK,
 359         PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
 360         TPU1TO0_MARK,
 361         PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
 362         TPU3TO1_MARK,
 363         PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
 364         TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
 365         PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
 366         MSIOF2R_TSYNC_MARK,
 367         SDHICLK0_MARK,
 368         SDHICD0_MARK,
 369         SDHID0_0_MARK,
 370         SDHID0_1_MARK,
 371         SDHID0_2_MARK,
 372         SDHID0_3_MARK,
 373         SDHICMD0_MARK,
 374         SDHIWP0_MARK,
 375         SDHICLK1_MARK,
 376         SDHID1_0_MARK, TS_SPSYNC2_MARK,
 377         SDHID1_1_MARK, TS_SDAT2_MARK,
 378         SDHID1_2_MARK, TS_SDEN2_MARK,
 379         SDHID1_3_MARK, TS_SCK2_MARK,
 380         SDHICMD1_MARK,
 381         SDHICLK2_MARK,
 382         SDHID2_0_MARK, TS_SPSYNC4_MARK,
 383         SDHID2_1_MARK, TS_SDAT4_MARK,
 384         SDHID2_2_MARK, TS_SDEN4_MARK,
 385         SDHID2_3_MARK, TS_SCK4_MARK,
 386         SDHICMD2_MARK,
 387         MMCCLK0_MARK,
 388         MMCD0_0_MARK,
 389         MMCD0_1_MARK,
 390         MMCD0_2_MARK,
 391         MMCD0_3_MARK,
 392         MMCD0_4_MARK, TS_SPSYNC5_MARK,
 393         MMCD0_5_MARK, TS_SDAT5_MARK,
 394         MMCD0_6_MARK, TS_SDEN5_MARK,
 395         MMCD0_7_MARK, TS_SCK5_MARK,
 396         MMCCMD0_MARK,
 397         RESETOUTS__MARK, EXTAL2OUT_MARK,
 398         MCP_WAIT__MCP_FRB_MARK,
 399         MCP_CKO_MARK, MMCCLK1_MARK,
 400         MCP_D15_MCP_NAF15_MARK,
 401         MCP_D14_MCP_NAF14_MARK,
 402         MCP_D13_MCP_NAF13_MARK,
 403         MCP_D12_MCP_NAF12_MARK,
 404         MCP_D11_MCP_NAF11_MARK,
 405         MCP_D10_MCP_NAF10_MARK,
 406         MCP_D9_MCP_NAF9_MARK,
 407         MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
 408         MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
 409
 410         MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
 411         MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
 412         MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
 413         MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
 414         MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
 415         MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
 416         MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
 417         MCP_NBRSTOUT__MARK,
 418         MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
 419
 420         /* MSEL2 special cases */
 421         TSIF2_TS_XX1_MARK,
 422         TSIF2_TS_XX2_MARK,
 423         TSIF2_TS_XX3_MARK,
 424         TSIF2_TS_XX4_MARK,
 425         TSIF2_TS_XX5_MARK,
 426         TSIF1_TS_XX1_MARK,
 427         TSIF1_TS_XX2_MARK,
 428         TSIF1_TS_XX3_MARK,
 429         TSIF1_TS_XX4_MARK,
 430         TSIF1_TS_XX5_MARK,
 431         TSIF0_TS_XX1_MARK,
 432         TSIF0_TS_XX2_MARK,
 433         TSIF0_TS_XX3_MARK,
 434         TSIF0_TS_XX4_MARK,
 435         TSIF0_TS_XX5_MARK,
 436         MST1_TS_XX1_MARK,
 437         MST1_TS_XX2_MARK,
 438         MST1_TS_XX3_MARK,
 439         MST1_TS_XX4_MARK,
 440         MST1_TS_XX5_MARK,
 441         MST0_TS_XX1_MARK,
 442         MST0_TS_XX2_MARK,
 443         MST0_TS_XX3_MARK,
 444         MST0_TS_XX4_MARK,
 445         MST0_TS_XX5_MARK,
 446
 447         /* MSEL3 special cases */
 448         SDHI0_VCCQ_MC0_ON_MARK,
 449         SDHI0_VCCQ_MC0_OFF_MARK,
 450         DEBUG_MON_VIO_MARK,
 451         DEBUG_MON_LCDD_MARK,
 452         LCDC_LCDC0_MARK,
 453         LCDC_LCDC1_MARK,
 454
 455         /* MSEL4 special cases */
 456         IRQ9_MEM_INT_MARK,
 457         IRQ9_MCP_INT_MARK,
 458         A11_MARK,
 459         KEYOUT8_MARK,
 460         TPU4TO3_MARK,
 461         RESETA_N_PU_ON_MARK,
 462         RESETA_N_PU_OFF_MARK,
 463         EDBGREQ_PD_MARK,
 464         EDBGREQ_PU_MARK,
 465
 466         PINMUX_MARK_END,
 467 };
 468
 469 static const u16 pinmux_data[] = {
 470         /* specify valid pin states for each pin in GPIO mode */
 471         PINMUX_DATA_ALL(),
 472
 473         /* Table 25-1 (Function 0-7) */
 474         PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
 475         PINMUX_DATA(GPI0_MARK, PORT1_FN1),
 476         PINMUX_DATA(GPI1_MARK, PORT2_FN1),
 477         PINMUX_DATA(GPI2_MARK, PORT3_FN1),
 478         PINMUX_DATA(GPI3_MARK, PORT4_FN1),
 479         PINMUX_DATA(GPI4_MARK, PORT5_FN1),
 480         PINMUX_DATA(GPI5_MARK, PORT6_FN1),
 481         PINMUX_DATA(GPI6_MARK, PORT7_FN1),
 482         PINMUX_DATA(GPI7_MARK, PORT8_FN1),
 483         PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
 484         PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
 485         PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
 486         PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
 487         PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
 488         PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
 489         PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
 490         PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
 491         PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
 492         PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
 493         PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
 494         PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
 495         PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
 496         PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
 497         PINMUX_DATA(GPO0_MARK, PORT20_FN1),
 498         PINMUX_DATA(GPO1_MARK, PORT21_FN1),
 499         PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
 500         PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
 501         PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
 502         PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
 503         PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
 504         PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
 505         PINMUX_DATA(VINT_MARK, PORT25_FN1),
 506         PINMUX_DATA(TCKON_MARK, PORT26_FN1),
 507         PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
 508         PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
 509                 MSEL2CR_MSEL16_1), \
 510         PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
 511                 MSEL2CR_MSEL18_1), \
 512         PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
 513         PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
 514         PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
 515         PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
 516                 MSEL2CR_MSEL16_1), \
 517         PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
 518                 MSEL2CR_MSEL18_1), \
 519         PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
 520         PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
 521         PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
 522         PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
 523         PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
 524         PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
 525         PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
 526         PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
 527         PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
 528         PINMUX_DATA(XWUP_MARK, PORT33_FN3),
 529         PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
 530         PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
 531         PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
 532         PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
 533         PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
 534         PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
 535         PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
 536         PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
 537         PINMUX_DATA(VACK_MARK, PORT40_FN1),
 538         PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
 539         PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
 540         PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
 541         PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
 542         PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
 543         PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
 544         PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
 545         PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
 546         PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
 547         PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
 548         PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
 549         PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
 550         PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
 551         PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
 552         PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
 553         PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
 554         PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
 555         PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
 556         PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
 557         PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
 558         PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
 559         PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
 560         PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
 561         PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
 562         PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
 563         PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
 564
 565         PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
 566         PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
 567         PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
 568         PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
 569         PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
 570         PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
 571         PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
 572         PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
 573         PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
 574         PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
 575         PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
 576         PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
 577         PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
 578         PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
 579         PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
 580         PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
 581         PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
 582         PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
 583         PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
 584         PINMUX_DATA(A0_MARK, PORT57_FN1), \
 585         PINMUX_DATA(BS__MARK, PORT57_FN2),
 586         PINMUX_DATA(A12_MARK, PORT58_FN1), \
 587         PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
 588         PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
 589         PINMUX_DATA(A13_MARK, PORT59_FN1), \
 590         PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
 591         PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
 592         PINMUX_DATA(A14_MARK, PORT60_FN1), \
 593         PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
 594         PINMUX_DATA(A15_MARK, PORT61_FN1), \
 595         PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
 596         PINMUX_DATA(A16_MARK, PORT62_FN1), \
 597         PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
 598         PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
 599         PINMUX_DATA(A17_MARK, PORT63_FN1), \
 600         PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
 601         PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
 602         PINMUX_DATA(A18_MARK, PORT64_FN1), \
 603         PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
 604         PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
 605         PINMUX_DATA(A19_MARK, PORT65_FN1), \
 606         PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
 607         PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
 608         PINMUX_DATA(A20_MARK, PORT66_FN1), \
 609         PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
 610         PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
 611         PINMUX_DATA(A21_MARK, PORT67_FN1), \
 612         PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
 613         PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
 614         PINMUX_DATA(A22_MARK, PORT68_FN1), \
 615         PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
 616         PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
 617         PINMUX_DATA(A23_MARK, PORT69_FN1), \
 618         PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
 619         PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
 620         PINMUX_DATA(A24_MARK, PORT70_FN1), \
 621         PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
 622         PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
 623         PINMUX_DATA(A25_MARK, PORT71_FN1), \
 624         PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
 625         PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
 626         PINMUX_DATA(A26_MARK, PORT72_FN1), \
 627         PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
 628         PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
 629         PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
 630         PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
 631         PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
 632         PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
 633         PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
 634         PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
 635         PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
 636         PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
 637         PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
 638         PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
 639         PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
 640         PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
 641         PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
 642         PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
 643         PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
 644         PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
 645         PINMUX_DATA(CS4__MARK, PORT90_FN1),
 646         PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
 647         PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
 648         PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
 649         PINMUX_DATA(FCE1__MARK, PORT92_FN2),
 650         PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
 651         PINMUX_DATA(DACK0_MARK, PORT93_FN4),
 652         PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
 653         PINMUX_DATA(CS6A__MARK, PORT94_FN2),
 654         PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
 655         PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
 656         PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
 657         PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
 658         PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
 659         PINMUX_DATA(WE1__MARK, PORT98_FN1),
 660         PINMUX_DATA(FRB_MARK, PORT99_FN1),
 661         PINMUX_DATA(CKO_MARK, PORT100_FN1),
 662         PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
 663         PINMUX_DATA(NBRST__MARK, PORT102_FN1),
 664         PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
 665         PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
 666         PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
 667         PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
 668         PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
 669         PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
 670         PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
 671         PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
 672         PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
 673         PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
 674         PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
 675         PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
 676         PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
 677         PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
 678         PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
 679         PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
 680         PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
 681         PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
 682         PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
 683         PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
 684         PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
 685         PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
 686         PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
 687         PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
 688         PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
 689         PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
 690         PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
 691         PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
 692         PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
 693         PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
 694         PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
 695         PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
 696         PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
 697         PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
 698         PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
 699         PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
 700
 701         PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
 702         PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
 703         PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
 704         PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
 705         PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
 706         PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
 707         PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
 708                 MSEL4CR_MSEL10_1), \
 709         PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
 710         PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
 711         PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
 712         PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
 713         PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
 714         PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
 715         PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
 716         PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
 717         PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
 718         PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
 719         PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
 720         PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
 721         PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
 722         PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
 723         PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
 724         PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
 725         PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
 726         PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
 727         PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
 728         PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
 729         PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
 730         PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
 731         PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
 732         PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
 733         PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
 734         PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
 735         PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
 736         PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
 737         PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
 738         PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
 739         PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
 740         PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
 741         PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
 742         PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
 743         PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
 744         PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
 745         PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
 746         PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
 747         PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
 748         PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
 749         PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
 750         PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
 751         PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
 752         PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
 753         PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
 754         PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
 755         PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
 756         PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
 757         PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
 758         PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
 759         PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
 760         PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
 761         PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
 762         PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
 763         PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
 764         PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
 765         PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
 766         PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
 767         PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
 768         PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
 769         PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
 770         PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
 771         PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
 772         PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
 773         PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
 774         PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
 775         PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
 776         PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
 777         PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
 778         PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
 779         PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
 780         PINMUX_DATA(A27_MARK, PORT149_FN1), \
 781         PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
 782         PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
 783         PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
 784         PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
 785         PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
 786         PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
 787         PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
 788         PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
 789         PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
 790         PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
 791         PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
 792         PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
 793         PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
 794         PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
 795         PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
 796         PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
 797         PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
 798         PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
 799         PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
 800                 MSEL4CR_MSEL10_0),
 801         PINMUX_DATA(DINT__MARK, PORT158_FN1), \
 802         PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
 803         PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
 804         PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
 805         PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
 806         PINMUX_DATA(NMI_MARK, PORT159_FN3),
 807         PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
 808         PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
 809         PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
 810         PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
 811         PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
 812         PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
 813         PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
 814         PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
 815         PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
 816         PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
 817         PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
 818         PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
 819                 MSEL4CR_MSEL20_1), \
 820         PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
 821         PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
 822         PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
 823                 MSEL4CR_MSEL20_1), \
 824         PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
 825         PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
 826         PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
 827                 MSEL4CR_MSEL20_1), \
 828         PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
 829         PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
 830         PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
 831                 MSEL4CR_MSEL20_1),
 832         PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
 833         PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
 834                 MSEL4CR_MSEL20_1), \
 835         PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
 836         PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
 837         PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
 838         PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
 839         PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
 840         PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
 841         PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
 842         PINMUX_DATA(D16_MARK, PORT200_FN6),
 843         PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
 844         PINMUX_DATA(D17_MARK, PORT201_FN6),
 845         PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
 846         PINMUX_DATA(D18_MARK, PORT202_FN6),
 847         PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
 848         PINMUX_DATA(D19_MARK, PORT203_FN6),
 849         PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
 850         PINMUX_DATA(D20_MARK, PORT204_FN6),
 851         PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
 852         PINMUX_DATA(D21_MARK, PORT205_FN6),
 853         PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
 854         PINMUX_DATA(D22_MARK, PORT206_FN6),
 855         PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
 856         PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
 857         PINMUX_DATA(D23_MARK, PORT207_FN6),
 858         PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
 859         PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
 860         PINMUX_DATA(D24_MARK, PORT208_FN6),
 861         PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
 862         PINMUX_DATA(D25_MARK, PORT209_FN6),
 863         PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
 864         PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
 865         PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
 866         PINMUX_DATA(D26_MARK, PORT210_FN6),
 867         PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
 868         PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
 869         PINMUX_DATA(D27_MARK, PORT211_FN6),
 870         PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
 871         PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
 872         PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
 873         PINMUX_DATA(D28_MARK, PORT212_FN6),
 874         PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
 875         PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
 876         PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
 877         PINMUX_DATA(D29_MARK, PORT213_FN6),
 878         PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
 879         PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
 880         PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
 881         PINMUX_DATA(D30_MARK, PORT214_FN6),
 882         PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
 883         PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
 884         PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
 885         PINMUX_DATA(D31_MARK, PORT215_FN6),
 886         PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
 887         PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
 888         PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
 889         PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
 890         PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
 891         PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
 892         PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
 893                 MSEL4CR_MSEL26_1), \
 894         PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
 895         PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
 896         PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
 897         PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
 898         PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
 899         PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
 900         PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
 901         PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
 902         PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
 903         PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
 904         PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
 905         PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
 906                 MSEL4CR_MSEL26_1), \
 907         PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
 908         PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
 909         PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
 910         PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
 911         PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
 912         PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
 913         PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
 914         PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
 915         PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
 916                 MSEL4CR_MSEL26_1), \
 917         PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
 918         PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
 919         PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
 920         PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
 921         PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
 922         PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
 923         PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
 924                 MSEL4CR_MSEL26_1), \
 925         PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
 926
 927         PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
 928         PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
 929         PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
 930         PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
 931         PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
 932         PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
 933         PINMUX_DATA(IDIN_MARK, PORT227_FN4),
 934         PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
 935         PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
 936         PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
 937         PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
 938         PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
 939         PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
 940         PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
 941         PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
 942         PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
 943         PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
 944         PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
 945         PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
 946         PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
 947         PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
 948                 MSEL4CR_MSEL26_0), \
 949         PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
 950         PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
 951         PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
 952         PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
 953                 MSEL4CR_MSEL26_0), \
 954         PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
 955         PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
 956         PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
 957                 MSEL2CR_MSEL16_0),
 958         PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
 959         PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
 960                 MSEL2CR_MSEL16_0),
 961         PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
 962         PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
 963                 MSEL4CR_MSEL26_0), \
 964         PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
 965         PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
 966         PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
 967                 MSEL4CR_MSEL26_0), \
 968         PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
 969         PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
 970         PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
 971         PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
 972         PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
 973         PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
 974         PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
 975         PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
 976         PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
 977         PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
 978         PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
 979                 MSEL4CR_MSEL20_0), \
 980         PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
 981         PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
 982         PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
 983         PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
 984                 MSEL4CR_MSEL20_0), \
 985         PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
 986         PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
 987         PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
 988         PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
 989                 MSEL4CR_MSEL20_0), \
 990         PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
 991         PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
 992         PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
 993         PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
 994                 MSEL4CR_MSEL20_0), \
 995         PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
 996         PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
 997         PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
 998         PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
 999                 MSEL4CR_MSEL20_0), \
1000         PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
1001         PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
1002         PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
1003         PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
1004                 MSEL2CR_MSEL18_0), \
1005         PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
1006         PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
1007         PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
1008         PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
1009                 MSEL2CR_MSEL18_0), \
1010         PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
1011         PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
1012         PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
1013         PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
1014         PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
1015         PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
1016         PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
1017         PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
1018         PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
1019         PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
1020         PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
1021         PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
1022         PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
1023         PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
1024         PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
1025         PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
1026         PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
1027         PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
1028         PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
1029         PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
1030         PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
1031         PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
1032         PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
1033         PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
1034         PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
1035         PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
1036         PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
1037         PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
1038         PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
1039         PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
1040         PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
1041         PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
1042         PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
1043         PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
1044         PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
1045         PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
1046         PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
1047         PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
1048         PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
1049         PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
1050         PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
1051         PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
1052         PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
1053         PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
1054         PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
1055         PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
1056         PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
1057         PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
1058         PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
1059         PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
1060         PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
1061         PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
1062         PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
1063         PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
1064         PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
1065         PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
1066         PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
1067         PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
1068         PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
1069
1070         PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
1071         PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
1072         PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
1073         PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
1074         PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
1075         PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
1076         PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
1077         PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
1078         PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
1079         PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
1080         PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
1081         PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
1082         PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
1083         PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
1084         PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
1085         PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
1086         PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
1087
1088         /* MSEL2 special cases */
1089         PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1090                 MSEL2CR_MSEL12_0),
1091         PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
1092                 MSEL2CR_MSEL12_1),
1093         PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1094                 MSEL2CR_MSEL12_0),
1095         PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
1096                 MSEL2CR_MSEL12_1),
1097         PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
1098                 MSEL2CR_MSEL12_0),
1099         PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1100                 MSEL2CR_MSEL9_0),
1101         PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
1102                 MSEL2CR_MSEL9_1),
1103         PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1104                 MSEL2CR_MSEL9_0),
1105         PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
1106                 MSEL2CR_MSEL9_1),
1107         PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
1108                 MSEL2CR_MSEL9_0),
1109         PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1110                 MSEL2CR_MSEL6_0),
1111         PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
1112                 MSEL2CR_MSEL6_1),
1113         PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1114                 MSEL2CR_MSEL6_0),
1115         PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
1116                 MSEL2CR_MSEL6_1),
1117         PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
1118                 MSEL2CR_MSEL6_0),
1119         PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1120                 MSEL2CR_MSEL3_0),
1121         PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
1122                 MSEL2CR_MSEL3_1),
1123         PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1124                 MSEL2CR_MSEL3_0),
1125         PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
1126                 MSEL2CR_MSEL3_1),
1127         PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
1128                 MSEL2CR_MSEL3_0),
1129         PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1130                 MSEL2CR_MSEL0_0),
1131         PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
1132                 MSEL2CR_MSEL0_1),
1133         PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1134                 MSEL2CR_MSEL0_0),
1135         PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
1136                 MSEL2CR_MSEL0_1),
1137         PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
1138                 MSEL2CR_MSEL0_0),
1139
1140         /* MSEL3 special cases */
1141         PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
1142         PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
1143         PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
1144         PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
1145         PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
1146         PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
1147
1148         /* MSEL4 special cases */
1149         PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
1150         PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
1151         PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
1152         PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
1153         PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
1154         PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
1155         PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
1156         PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
1157         PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
1158 };
1159
1160 #define __I             (SH_PFC_PIN_CFG_INPUT)
1161 #define __O             (SH_PFC_PIN_CFG_OUTPUT)
1162 #define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1163 #define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
1164 #define __PU            (SH_PFC_PIN_CFG_PULL_UP)
1165 #define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1166
1167 #define SH73A0_PIN_I_PD(pin)            SH_PFC_PIN_CFG(pin, __I | __PD)
1168 #define SH73A0_PIN_I_PU(pin)            SH_PFC_PIN_CFG(pin, __I | __PU)
1169 #define SH73A0_PIN_I_PU_PD(pin)         SH_PFC_PIN_CFG(pin, __I | __PUD)
1170 #define SH73A0_PIN_IO(pin)              SH_PFC_PIN_CFG(pin, __IO)
1171 #define SH73A0_PIN_IO_PD(pin)           SH_PFC_PIN_CFG(pin, __IO | __PD)
1172 #define SH73A0_PIN_IO_PU(pin)           SH_PFC_PIN_CFG(pin, __IO | __PU)
1173 #define SH73A0_PIN_IO_PU_PD(pin)        SH_PFC_PIN_CFG(pin, __IO | __PUD)
1174 #define SH73A0_PIN_O(pin)               SH_PFC_PIN_CFG(pin, __O)
1175
1176 /* Pin numbers for pins without a corresponding GPIO port number are computed
1177  * from the row and column numbers with a 1000 offset to avoid collisions with
1178  * GPIO port numbers.
1179  */
1180 #define PIN_NUMBER(row, col)            (1000+((row)-1)*34+(col)-1)
1181
1182 static const struct sh_pfc_pin pinmux_pins[] = {
1183         /* Table 25-1 (I/O and Pull U/D) */
1184         SH73A0_PIN_I_PD(0),
1185         SH73A0_PIN_I_PU(1),
1186         SH73A0_PIN_I_PU(2),
1187         SH73A0_PIN_I_PU(3),
1188         SH73A0_PIN_I_PU(4),
1189         SH73A0_PIN_I_PU(5),
1190         SH73A0_PIN_I_PU(6),
1191         SH73A0_PIN_I_PU(7),
1192         SH73A0_PIN_I_PU(8),
1193         SH73A0_PIN_I_PD(9),
1194         SH73A0_PIN_I_PD(10),
1195         SH73A0_PIN_I_PU_PD(11),
1196         SH73A0_PIN_IO_PU_PD(12),
1197         SH73A0_PIN_IO_PU_PD(13),
1198         SH73A0_PIN_IO_PU_PD(14),
1199         SH73A0_PIN_IO_PU_PD(15),
1200         SH73A0_PIN_IO_PD(16),
1201         SH73A0_PIN_IO_PD(17),
1202         SH73A0_PIN_IO_PU(18),
1203         SH73A0_PIN_IO_PU(19),
1204         SH73A0_PIN_O(20),
1205         SH73A0_PIN_O(21),
1206         SH73A0_PIN_O(22),
1207         SH73A0_PIN_O(23),
1208         SH73A0_PIN_O(24),
1209         SH73A0_PIN_I_PD(25),
1210         SH73A0_PIN_I_PD(26),
1211         SH73A0_PIN_IO_PU(27),
1212         SH73A0_PIN_IO_PU(28),
1213         SH73A0_PIN_IO_PD(29),
1214         SH73A0_PIN_IO_PD(30),
1215         SH73A0_PIN_IO_PU(31),
1216         SH73A0_PIN_IO_PD(32),
1217         SH73A0_PIN_I_PU_PD(33),
1218         SH73A0_PIN_IO_PD(34),
1219         SH73A0_PIN_I_PU_PD(35),
1220         SH73A0_PIN_IO_PD(36),
1221         SH73A0_PIN_IO(37),
1222         SH73A0_PIN_O(38),
1223         SH73A0_PIN_I_PU(39),
1224         SH73A0_PIN_I_PU_PD(40),
1225         SH73A0_PIN_O(41),
1226         SH73A0_PIN_IO_PD(42),
1227         SH73A0_PIN_IO_PU_PD(43),
1228         SH73A0_PIN_IO_PU_PD(44),
1229         SH73A0_PIN_IO_PD(45),
1230         SH73A0_PIN_IO_PD(46),
1231         SH73A0_PIN_IO_PD(47),
1232         SH73A0_PIN_I_PD(48),
1233         SH73A0_PIN_IO_PU_PD(49),
1234         SH73A0_PIN_IO_PD(50),
1235         SH73A0_PIN_IO_PD(51),
1236         SH73A0_PIN_O(52),
1237         SH73A0_PIN_IO_PU_PD(53),
1238         SH73A0_PIN_IO_PU_PD(54),
1239         SH73A0_PIN_IO_PD(55),
1240         SH73A0_PIN_I_PU_PD(56),
1241         SH73A0_PIN_IO(57),
1242         SH73A0_PIN_IO(58),
1243         SH73A0_PIN_IO(59),
1244         SH73A0_PIN_IO(60),
1245         SH73A0_PIN_IO(61),
1246         SH73A0_PIN_IO_PD(62),
1247         SH73A0_PIN_IO_PD(63),
1248         SH73A0_PIN_IO_PU_PD(64),
1249         SH73A0_PIN_IO_PD(65),
1250         SH73A0_PIN_IO_PU_PD(66),
1251         SH73A0_PIN_IO_PU_PD(67),
1252         SH73A0_PIN_IO_PU_PD(68),
1253         SH73A0_PIN_IO_PU_PD(69),
1254         SH73A0_PIN_IO_PU_PD(70),
1255         SH73A0_PIN_IO_PU_PD(71),
1256         SH73A0_PIN_IO_PU_PD(72),
1257         SH73A0_PIN_I_PU_PD(73),
1258         SH73A0_PIN_IO_PU(74),
1259         SH73A0_PIN_IO_PU(75),
1260         SH73A0_PIN_IO_PU(76),
1261         SH73A0_PIN_IO_PU(77),
1262         SH73A0_PIN_IO_PU(78),
1263         SH73A0_PIN_IO_PU(79),
1264         SH73A0_PIN_IO_PU(80),
1265         SH73A0_PIN_IO_PU(81),
1266         SH73A0_PIN_IO_PU(82),
1267         SH73A0_PIN_IO_PU(83),
1268         SH73A0_PIN_IO_PU(84),
1269         SH73A0_PIN_IO_PU(85),
1270         SH73A0_PIN_IO_PU(86),
1271         SH73A0_PIN_IO_PU(87),
1272         SH73A0_PIN_IO_PU(88),
1273         SH73A0_PIN_IO_PU(89),
1274         SH73A0_PIN_O(90),
1275         SH73A0_PIN_IO_PU(91),
1276         SH73A0_PIN_O(92),
1277         SH73A0_PIN_IO_PU(93),
1278         SH73A0_PIN_O(94),
1279         SH73A0_PIN_I_PU_PD(95),
1280         SH73A0_PIN_IO(96),
1281         SH73A0_PIN_IO(97),
1282         SH73A0_PIN_IO(98),
1283         SH73A0_PIN_I_PU(99),
1284         SH73A0_PIN_O(100),
1285         SH73A0_PIN_O(101),
1286         SH73A0_PIN_I_PU(102),
1287         SH73A0_PIN_IO_PD(103),
1288         SH73A0_PIN_I_PU_PD(104),
1289         SH73A0_PIN_I_PD(105),
1290         SH73A0_PIN_I_PD(106),
1291         SH73A0_PIN_I_PU_PD(107),
1292         SH73A0_PIN_I_PU_PD(108),
1293         SH73A0_PIN_IO_PD(109),
1294         SH73A0_PIN_IO_PD(110),
1295         SH73A0_PIN_IO_PU_PD(111),
1296         SH73A0_PIN_IO_PU_PD(112),
1297         SH73A0_PIN_IO_PU_PD(113),
1298         SH73A0_PIN_IO_PD(114),
1299         SH73A0_PIN_IO_PU(115),
1300         SH73A0_PIN_IO_PU(116),
1301         SH73A0_PIN_IO_PU_PD(117),
1302         SH73A0_PIN_IO_PU_PD(118),
1303         SH73A0_PIN_IO_PD(128),
1304         SH73A0_PIN_IO_PD(129),
1305         SH73A0_PIN_IO_PU_PD(130),
1306         SH73A0_PIN_IO_PD(131),
1307         SH73A0_PIN_IO_PD(132),
1308         SH73A0_PIN_IO_PD(133),
1309         SH73A0_PIN_IO_PU_PD(134),
1310         SH73A0_PIN_IO_PU_PD(135),
1311         SH73A0_PIN_IO_PU_PD(136),
1312         SH73A0_PIN_IO_PU_PD(137),
1313         SH73A0_PIN_IO_PD(138),
1314         SH73A0_PIN_IO_PD(139),
1315         SH73A0_PIN_IO_PD(140),
1316         SH73A0_PIN_IO_PD(141),
1317         SH73A0_PIN_IO_PD(142),
1318         SH73A0_PIN_IO_PD(143),
1319         SH73A0_PIN_IO_PU_PD(144),
1320         SH73A0_PIN_IO_PD(145),
1321         SH73A0_PIN_IO_PU_PD(146),
1322         SH73A0_PIN_IO_PU_PD(147),
1323         SH73A0_PIN_IO_PU_PD(148),
1324         SH73A0_PIN_IO_PU_PD(149),
1325         SH73A0_PIN_I_PU_PD(150),
1326         SH73A0_PIN_IO_PU_PD(151),
1327         SH73A0_PIN_IO_PU_PD(152),
1328         SH73A0_PIN_IO_PD(153),
1329         SH73A0_PIN_IO_PD(154),
1330         SH73A0_PIN_I_PU_PD(155),
1331         SH73A0_PIN_IO_PU_PD(156),
1332         SH73A0_PIN_I_PD(157),
1333         SH73A0_PIN_IO_PD(158),
1334         SH73A0_PIN_IO_PU_PD(159),
1335         SH73A0_PIN_IO_PU_PD(160),
1336         SH73A0_PIN_I_PU_PD(161),
1337         SH73A0_PIN_I_PU_PD(162),
1338         SH73A0_PIN_IO_PU_PD(163),
1339         SH73A0_PIN_I_PU_PD(164),
1340         SH73A0_PIN_IO_PD(192),
1341         SH73A0_PIN_IO_PU_PD(193),
1342         SH73A0_PIN_IO_PD(194),
1343         SH73A0_PIN_IO_PU_PD(195),
1344         SH73A0_PIN_IO_PD(196),
1345         SH73A0_PIN_IO_PD(197),
1346         SH73A0_PIN_IO_PD(198),
1347         SH73A0_PIN_IO_PD(199),
1348         SH73A0_PIN_IO_PU_PD(200),
1349         SH73A0_PIN_IO_PU_PD(201),
1350         SH73A0_PIN_IO_PU_PD(202),
1351         SH73A0_PIN_IO_PU_PD(203),
1352         SH73A0_PIN_IO_PU_PD(204),
1353         SH73A0_PIN_IO_PU_PD(205),
1354         SH73A0_PIN_IO_PU_PD(206),
1355         SH73A0_PIN_IO_PD(207),
1356         SH73A0_PIN_IO_PD(208),
1357         SH73A0_PIN_IO_PD(209),
1358         SH73A0_PIN_IO_PD(210),
1359         SH73A0_PIN_IO_PD(211),
1360         SH73A0_PIN_IO_PD(212),
1361         SH73A0_PIN_IO_PD(213),
1362         SH73A0_PIN_IO_PU_PD(214),
1363         SH73A0_PIN_IO_PU_PD(215),
1364         SH73A0_PIN_IO_PD(216),
1365         SH73A0_PIN_IO_PD(217),
1366         SH73A0_PIN_O(218),
1367         SH73A0_PIN_IO_PD(219),
1368         SH73A0_PIN_IO_PD(220),
1369         SH73A0_PIN_IO_PU_PD(221),
1370         SH73A0_PIN_IO_PU_PD(222),
1371         SH73A0_PIN_I_PU_PD(223),
1372         SH73A0_PIN_I_PU_PD(224),
1373         SH73A0_PIN_IO_PU_PD(225),
1374         SH73A0_PIN_O(226),
1375         SH73A0_PIN_IO_PU_PD(227),
1376         SH73A0_PIN_I_PU_PD(228),
1377         SH73A0_PIN_I_PD(229),
1378         SH73A0_PIN_IO(230),
1379         SH73A0_PIN_IO_PU_PD(231),
1380         SH73A0_PIN_IO_PU_PD(232),
1381         SH73A0_PIN_I_PU_PD(233),
1382         SH73A0_PIN_IO_PU_PD(234),
1383         SH73A0_PIN_IO_PU_PD(235),
1384         SH73A0_PIN_IO_PU_PD(236),
1385         SH73A0_PIN_IO_PD(237),
1386         SH73A0_PIN_IO_PU_PD(238),
1387         SH73A0_PIN_IO_PU_PD(239),
1388         SH73A0_PIN_IO_PU_PD(240),
1389         SH73A0_PIN_O(241),
1390         SH73A0_PIN_I_PD(242),
1391         SH73A0_PIN_IO_PU_PD(243),
1392         SH73A0_PIN_IO_PU_PD(244),
1393         SH73A0_PIN_IO_PU_PD(245),
1394         SH73A0_PIN_IO_PU_PD(246),
1395         SH73A0_PIN_IO_PU_PD(247),
1396         SH73A0_PIN_IO_PU_PD(248),
1397         SH73A0_PIN_IO_PU_PD(249),
1398         SH73A0_PIN_IO_PU_PD(250),
1399         SH73A0_PIN_IO_PU_PD(251),
1400         SH73A0_PIN_IO_PU_PD(252),
1401         SH73A0_PIN_IO_PU_PD(253),
1402         SH73A0_PIN_IO_PU_PD(254),
1403         SH73A0_PIN_IO_PU_PD(255),
1404         SH73A0_PIN_IO_PU_PD(256),
1405         SH73A0_PIN_IO_PU_PD(257),
1406         SH73A0_PIN_IO_PU_PD(258),
1407         SH73A0_PIN_IO_PU_PD(259),
1408         SH73A0_PIN_IO_PU_PD(260),
1409         SH73A0_PIN_IO_PU_PD(261),
1410         SH73A0_PIN_IO_PU_PD(262),
1411         SH73A0_PIN_IO_PU_PD(263),
1412         SH73A0_PIN_IO_PU_PD(264),
1413         SH73A0_PIN_IO_PU_PD(265),
1414         SH73A0_PIN_IO_PU_PD(266),
1415         SH73A0_PIN_IO_PU_PD(267),
1416         SH73A0_PIN_IO_PU_PD(268),
1417         SH73A0_PIN_IO_PU_PD(269),
1418         SH73A0_PIN_IO_PU_PD(270),
1419         SH73A0_PIN_IO_PU_PD(271),
1420         SH73A0_PIN_IO_PU_PD(272),
1421         SH73A0_PIN_IO_PU_PD(273),
1422         SH73A0_PIN_IO_PU_PD(274),
1423         SH73A0_PIN_IO_PU_PD(275),
1424         SH73A0_PIN_IO_PU_PD(276),
1425         SH73A0_PIN_IO_PU_PD(277),
1426         SH73A0_PIN_IO_PU_PD(278),
1427         SH73A0_PIN_IO_PU_PD(279),
1428         SH73A0_PIN_IO_PU_PD(280),
1429         SH73A0_PIN_O(281),
1430         SH73A0_PIN_O(282),
1431         SH73A0_PIN_I_PU(288),
1432         SH73A0_PIN_IO_PU_PD(289),
1433         SH73A0_PIN_IO_PU_PD(290),
1434         SH73A0_PIN_IO_PU_PD(291),
1435         SH73A0_PIN_IO_PU_PD(292),
1436         SH73A0_PIN_IO_PU_PD(293),
1437         SH73A0_PIN_IO_PU_PD(294),
1438         SH73A0_PIN_IO_PU_PD(295),
1439         SH73A0_PIN_IO_PU_PD(296),
1440         SH73A0_PIN_IO_PU_PD(297),
1441         SH73A0_PIN_IO_PU_PD(298),
1442         SH73A0_PIN_IO_PU_PD(299),
1443         SH73A0_PIN_IO_PU_PD(300),
1444         SH73A0_PIN_IO_PU_PD(301),
1445         SH73A0_PIN_IO_PU_PD(302),
1446         SH73A0_PIN_IO_PU_PD(303),
1447         SH73A0_PIN_IO_PU_PD(304),
1448         SH73A0_PIN_IO_PU_PD(305),
1449         SH73A0_PIN_O(306),
1450         SH73A0_PIN_O(307),
1451         SH73A0_PIN_I_PU(308),
1452         SH73A0_PIN_O(309),
1453
1454         /* Pins not associated with a GPIO port */
1455         SH_PFC_PIN_NAMED(6, 26, F26),
1456 };
1457
1458 /* - BSC -------------------------------------------------------------------- */
1459 static const unsigned int bsc_data_0_7_pins[] = {
1460         /* D[0:7] */
1461         74, 75, 76, 77, 78, 79, 80, 81,
1462 };
1463 static const unsigned int bsc_data_0_7_mux[] = {
1464         D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1465         D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1466 };
1467 static const unsigned int bsc_data_8_15_pins[] = {
1468         /* D[8:15] */
1469         82, 83, 84, 85, 86, 87, 88, 89,
1470 };
1471 static const unsigned int bsc_data_8_15_mux[] = {
1472         D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1473         D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1474 };
1475 static const unsigned int bsc_cs4_pins[] = {
1476         /* CS */
1477         90,
1478 };
1479 static const unsigned int bsc_cs4_mux[] = {
1480         CS4__MARK,
1481 };
1482 static const unsigned int bsc_cs5_a_pins[] = {
1483         /* CS */
1484         91,
1485 };
1486 static const unsigned int bsc_cs5_a_mux[] = {
1487         CS5A__MARK,
1488 };
1489 static const unsigned int bsc_cs5_b_pins[] = {
1490         /* CS */
1491         92,
1492 };
1493 static const unsigned int bsc_cs5_b_mux[] = {
1494         CS5B__MARK,
1495 };
1496 static const unsigned int bsc_cs6_a_pins[] = {
1497         /* CS */
1498         94,
1499 };
1500 static const unsigned int bsc_cs6_a_mux[] = {
1501         CS6A__MARK,
1502 };
1503 static const unsigned int bsc_cs6_b_pins[] = {
1504         /* CS */
1505         93,
1506 };
1507 static const unsigned int bsc_cs6_b_mux[] = {
1508         CS6B__MARK,
1509 };
1510 static const unsigned int bsc_rd_pins[] = {
1511         /* RD */
1512         96,
1513 };
1514 static const unsigned int bsc_rd_mux[] = {
1515         RD__FSC_MARK,
1516 };
1517 static const unsigned int bsc_rdwr_0_pins[] = {
1518         /* RDWR */
1519         91,
1520 };
1521 static const unsigned int bsc_rdwr_0_mux[] = {
1522         PORT91_RDWR_MARK,
1523 };
1524 static const unsigned int bsc_rdwr_1_pins[] = {
1525         /* RDWR */
1526         97,
1527 };
1528 static const unsigned int bsc_rdwr_1_mux[] = {
1529         RDWR_FWE_MARK,
1530 };
1531 static const unsigned int bsc_rdwr_2_pins[] = {
1532         /* RDWR */
1533         149,
1534 };
1535 static const unsigned int bsc_rdwr_2_mux[] = {
1536         PORT149_RDWR_MARK,
1537 };
1538 static const unsigned int bsc_we0_pins[] = {
1539         /* WE0 */
1540         97,
1541 };
1542 static const unsigned int bsc_we0_mux[] = {
1543         WE0__FWE_MARK,
1544 };
1545 static const unsigned int bsc_we1_pins[] = {
1546         /* WE1 */
1547         98,
1548 };
1549 static const unsigned int bsc_we1_mux[] = {
1550         WE1__MARK,
1551 };
1552 /* - FSIA ------------------------------------------------------------------- */
1553 static const unsigned int fsia_mclk_in_pins[] = {
1554         /* CK */
1555         49,
1556 };
1557 static const unsigned int fsia_mclk_in_mux[] = {
1558         FSIACK_MARK,
1559 };
1560 static const unsigned int fsia_mclk_out_pins[] = {
1561         /* OMC */
1562         49,
1563 };
1564 static const unsigned int fsia_mclk_out_mux[] = {
1565         FSIAOMC_MARK,
1566 };
1567 static const unsigned int fsia_sclk_in_pins[] = {
1568         /* ILR, IBT */
1569         50, 51,
1570 };
1571 static const unsigned int fsia_sclk_in_mux[] = {
1572         FSIAILR_MARK, FSIAIBT_MARK,
1573 };
1574 static const unsigned int fsia_sclk_out_pins[] = {
1575         /* OLR, OBT */
1576         50, 51,
1577 };
1578 static const unsigned int fsia_sclk_out_mux[] = {
1579         FSIAOLR_MARK, FSIAOBT_MARK,
1580 };
1581 static const unsigned int fsia_data_in_pins[] = {
1582         /* ISLD */
1583         55,
1584 };
1585 static const unsigned int fsia_data_in_mux[] = {
1586         FSIAISLD_MARK,
1587 };
1588 static const unsigned int fsia_data_out_pins[] = {
1589         /* OSLD */
1590         52,
1591 };
1592 static const unsigned int fsia_data_out_mux[] = {
1593         FSIAOSLD_MARK,
1594 };
1595 static const unsigned int fsia_spdif_pins[] = {
1596         /* SPDIF */
1597         53,
1598 };
1599 static const unsigned int fsia_spdif_mux[] = {
1600         FSIASPDIF_MARK,
1601 };
1602 /* - FSIB ------------------------------------------------------------------- */
1603 static const unsigned int fsib_mclk_in_pins[] = {
1604         /* CK */
1605         54,
1606 };
1607 static const unsigned int fsib_mclk_in_mux[] = {
1608         FSIBCK_MARK,
1609 };
1610 static const unsigned int fsib_mclk_out_pins[] = {
1611         /* OMC */
1612         54,
1613 };
1614 static const unsigned int fsib_mclk_out_mux[] = {
1615         FSIBOMC_MARK,
1616 };
1617 static const unsigned int fsib_sclk_in_pins[] = {
1618         /* ILR, IBT */
1619         37, 36,
1620 };
1621 static const unsigned int fsib_sclk_in_mux[] = {
1622         FSIBILR_MARK, FSIBIBT_MARK,
1623 };
1624 static const unsigned int fsib_sclk_out_pins[] = {
1625         /* OLR, OBT */
1626         37, 36,
1627 };
1628 static const unsigned int fsib_sclk_out_mux[] = {
1629         FSIBOLR_MARK, FSIBOBT_MARK,
1630 };
1631 static const unsigned int fsib_data_in_pins[] = {
1632         /* ISLD */
1633         39,
1634 };
1635 static const unsigned int fsib_data_in_mux[] = {
1636         FSIBISLD_MARK,
1637 };
1638 static const unsigned int fsib_data_out_pins[] = {
1639         /* OSLD */
1640         38,
1641 };
1642 static const unsigned int fsib_data_out_mux[] = {
1643         FSIBOSLD_MARK,
1644 };
1645 static const unsigned int fsib_spdif_pins[] = {
1646         /* SPDIF */
1647         53,
1648 };
1649 static const unsigned int fsib_spdif_mux[] = {
1650         FSIBSPDIF_MARK,
1651 };
1652 /* - FSIC ------------------------------------------------------------------- */
1653 static const unsigned int fsic_mclk_in_pins[] = {
1654         /* CK */
1655         54,
1656 };
1657 static const unsigned int fsic_mclk_in_mux[] = {
1658         FSICCK_MARK,
1659 };
1660 static const unsigned int fsic_mclk_out_pins[] = {
1661         /* OMC */
1662         54,
1663 };
1664 static const unsigned int fsic_mclk_out_mux[] = {
1665         FSICOMC_MARK,
1666 };
1667 static const unsigned int fsic_sclk_in_pins[] = {
1668         /* ILR, IBT */
1669         46, 45,
1670 };
1671 static const unsigned int fsic_sclk_in_mux[] = {
1672         FSICILR_MARK, FSICIBT_MARK,
1673 };
1674 static const unsigned int fsic_sclk_out_pins[] = {
1675         /* OLR, OBT */
1676         46, 45,
1677 };
1678 static const unsigned int fsic_sclk_out_mux[] = {
1679         FSICOLR_MARK, FSICOBT_MARK,
1680 };
1681 static const unsigned int fsic_data_in_pins[] = {
1682         /* ISLD */
1683         48,
1684 };
1685 static const unsigned int fsic_data_in_mux[] = {
1686         FSICISLD_MARK,
1687 };
1688 static const unsigned int fsic_data_out_pins[] = {
1689         /* OSLD, OSLDT1, OSLDT2, OSLDT3 */
1690         47, 44, 42, 16,
1691 };
1692 static const unsigned int fsic_data_out_mux[] = {
1693         FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
1694 };
1695 static const unsigned int fsic_spdif_0_pins[] = {
1696         /* SPDIF */
1697         53,
1698 };
1699 static const unsigned int fsic_spdif_0_mux[] = {
1700         PORT53_FSICSPDIF_MARK,
1701 };
1702 static const unsigned int fsic_spdif_1_pins[] = {
1703         /* SPDIF */
1704         47,
1705 };
1706 static const unsigned int fsic_spdif_1_mux[] = {
1707         PORT47_FSICSPDIF_MARK,
1708 };
1709 /* - FSID ------------------------------------------------------------------- */
1710 static const unsigned int fsid_sclk_in_pins[] = {
1711         /* ILR, IBT */
1712         46, 45,
1713 };
1714 static const unsigned int fsid_sclk_in_mux[] = {
1715         FSIDILR_MARK, FSIDIBT_MARK,
1716 };
1717 static const unsigned int fsid_sclk_out_pins[] = {
1718         /* OLR, OBT */
1719         46, 45,
1720 };
1721 static const unsigned int fsid_sclk_out_mux[] = {
1722         FSIDOLR_MARK, FSIDOBT_MARK,
1723 };
1724 static const unsigned int fsid_data_in_pins[] = {
1725         /* ISLD */
1726         48,
1727 };
1728 static const unsigned int fsid_data_in_mux[] = {
1729         FSIDISLD_MARK,
1730 };
1731 /* - I2C2 ------------------------------------------------------------------- */
1732 static const unsigned int i2c2_0_pins[] = {
1733         /* SCL, SDA */
1734         237, 236,
1735 };
1736 static const unsigned int i2c2_0_mux[] = {
1737         PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
1738 };
1739 static const unsigned int i2c2_1_pins[] = {
1740         /* SCL, SDA */
1741         27, 28,
1742 };
1743 static const unsigned int i2c2_1_mux[] = {
1744         PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
1745 };
1746 static const unsigned int i2c2_2_pins[] = {
1747         /* SCL, SDA */
1748         115, 116,
1749 };
1750 static const unsigned int i2c2_2_mux[] = {
1751         PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
1752 };
1753 /* - I2C3 ------------------------------------------------------------------- */
1754 static const unsigned int i2c3_0_pins[] = {
1755         /* SCL, SDA */
1756         248, 249,
1757 };
1758 static const unsigned int i2c3_0_mux[] = {
1759         PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
1760 };
1761 static const unsigned int i2c3_1_pins[] = {
1762         /* SCL, SDA */
1763         27, 28,
1764 };
1765 static const unsigned int i2c3_1_mux[] = {
1766         PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
1767 };
1768 static const unsigned int i2c3_2_pins[] = {
1769         /* SCL, SDA */
1770         115, 116,
1771 };
1772 static const unsigned int i2c3_2_mux[] = {
1773         PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
1774 };
1775 /* - IrDA ------------------------------------------------------------------- */
1776 static const unsigned int irda_0_pins[] = {
1777         /* OUT, IN, FIRSEL */
1778         241, 242, 243,
1779 };
1780 static const unsigned int irda_0_mux[] = {
1781         PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
1782 };
1783 static const unsigned int irda_1_pins[] = {
1784         /* OUT, IN, FIRSEL */
1785         49, 53, 54,
1786 };
1787 static const unsigned int irda_1_mux[] = {
1788         PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
1789 };
1790 /* - KEYSC ------------------------------------------------------------------ */
1791 static const unsigned int keysc_in5_pins[] = {
1792         /* KEYIN[0:4] */
1793         66, 67, 68, 69, 70,
1794 };
1795 static const unsigned int keysc_in5_mux[] = {
1796         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1797         KEYIN4_MARK,
1798 };
1799 static const unsigned int keysc_in6_pins[] = {
1800         /* KEYIN[0:5] */
1801         66, 67, 68, 69, 70, 71,
1802 };
1803 static const unsigned int keysc_in6_mux[] = {
1804         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1805         KEYIN4_MARK, KEYIN5_MARK,
1806 };
1807 static const unsigned int keysc_in7_pins[] = {
1808         /* KEYIN[0:6] */
1809         66, 67, 68, 69, 70, 71, 72,
1810 };
1811 static const unsigned int keysc_in7_mux[] = {
1812         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1813         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
1814 };
1815 static const unsigned int keysc_in8_pins[] = {
1816         /* KEYIN[0:7] */
1817         66, 67, 68, 69, 70, 71, 72, 73,
1818 };
1819 static const unsigned int keysc_in8_mux[] = {
1820         KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
1821         KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
1822 };
1823 static const unsigned int keysc_out04_pins[] = {
1824         /* KEYOUT[0:4] */
1825         65, 64, 63, 62, 61,
1826 };
1827 static const unsigned int keysc_out04_mux[] = {
1828         KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
1829 };
1830 static const unsigned int keysc_out5_pins[] = {
1831         /* KEYOUT5 */
1832         60,
1833 };
1834 static const unsigned int keysc_out5_mux[] = {
1835         KEYOUT5_MARK,
1836 };
1837 static const unsigned int keysc_out6_0_pins[] = {
1838         /* KEYOUT6 */
1839         59,
1840 };
1841 static const unsigned int keysc_out6_0_mux[] = {
1842         PORT59_KEYOUT6_MARK,
1843 };
1844 static const unsigned int keysc_out6_1_pins[] = {
1845         /* KEYOUT6 */
1846         131,
1847 };
1848 static const unsigned int keysc_out6_1_mux[] = {
1849         PORT131_KEYOUT6_MARK,
1850 };
1851 static const unsigned int keysc_out6_2_pins[] = {
1852         /* KEYOUT6 */
1853         143,
1854 };
1855 static const unsigned int keysc_out6_2_mux[] = {
1856         PORT143_KEYOUT6_MARK,
1857 };
1858 static const unsigned int keysc_out7_0_pins[] = {
1859         /* KEYOUT7 */
1860         58,
1861 };
1862 static const unsigned int keysc_out7_0_mux[] = {
1863         PORT58_KEYOUT7_MARK,
1864 };
1865 static const unsigned int keysc_out7_1_pins[] = {
1866         /* KEYOUT7 */
1867         132,
1868 };
1869 static const unsigned int keysc_out7_1_mux[] = {
1870         PORT132_KEYOUT7_MARK,
1871 };
1872 static const unsigned int keysc_out7_2_pins[] = {
1873         /* KEYOUT7 */
1874         144,
1875 };
1876 static const unsigned int keysc_out7_2_mux[] = {
1877         PORT144_KEYOUT7_MARK,
1878 };
1879 static const unsigned int keysc_out8_0_pins[] = {
1880         /* KEYOUT8 */
1881         PIN_NUMBER(6, 26),
1882 };
1883 static const unsigned int keysc_out8_0_mux[] = {
1884         KEYOUT8_MARK,
1885 };
1886 static const unsigned int keysc_out8_1_pins[] = {
1887         /* KEYOUT8 */
1888         136,
1889 };
1890 static const unsigned int keysc_out8_1_mux[] = {
1891         PORT136_KEYOUT8_MARK,
1892 };
1893 static const unsigned int keysc_out8_2_pins[] = {
1894         /* KEYOUT8 */
1895         138,
1896 };
1897 static const unsigned int keysc_out8_2_mux[] = {
1898         PORT138_KEYOUT8_MARK,
1899 };
1900 static const unsigned int keysc_out9_0_pins[] = {
1901         /* KEYOUT9 */
1902         137,
1903 };
1904 static const unsigned int keysc_out9_0_mux[] = {
1905         PORT137_KEYOUT9_MARK,
1906 };
1907 static const unsigned int keysc_out9_1_pins[] = {
1908         /* KEYOUT9 */
1909         139,
1910 };
1911 static const unsigned int keysc_out9_1_mux[] = {
1912         PORT139_KEYOUT9_MARK,
1913 };
1914 static const unsigned int keysc_out9_2_pins[] = {
1915         /* KEYOUT9 */
1916         149,
1917 };
1918 static const unsigned int keysc_out9_2_mux[] = {
1919         PORT149_KEYOUT9_MARK,
1920 };
1921 static const unsigned int keysc_out10_0_pins[] = {
1922         /* KEYOUT10 */
1923         132,
1924 };
1925 static const unsigned int keysc_out10_0_mux[] = {
1926         PORT132_KEYOUT10_MARK,
1927 };
1928 static const unsigned int keysc_out10_1_pins[] = {
1929         /* KEYOUT10 */
1930         142,
1931 };
1932 static const unsigned int keysc_out10_1_mux[] = {
1933         PORT142_KEYOUT10_MARK,
1934 };
1935 static const unsigned int keysc_out11_0_pins[] = {
1936         /* KEYOUT11 */
1937         131,
1938 };
1939 static const unsigned int keysc_out11_0_mux[] = {
1940         PORT131_KEYOUT11_MARK,
1941 };
1942 static const unsigned int keysc_out11_1_pins[] = {
1943         /* KEYOUT11 */
1944         143,
1945 };
1946 static const unsigned int keysc_out11_1_mux[] = {
1947         PORT143_KEYOUT11_MARK,
1948 };
1949 /* - LCD -------------------------------------------------------------------- */
1950 static const unsigned int lcd_data8_pins[] = {
1951         /* D[0:7] */
1952         192, 193, 194, 195, 196, 197, 198, 199,
1953 };
1954 static const unsigned int lcd_data8_mux[] = {
1955         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1956         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1957 };
1958 static const unsigned int lcd_data9_pins[] = {
1959         /* D[0:8] */
1960         192, 193, 194, 195, 196, 197, 198, 199,
1961         200,
1962 };
1963 static const unsigned int lcd_data9_mux[] = {
1964         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1965         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1966         LCDD8_MARK,
1967 };
1968 static const unsigned int lcd_data12_pins[] = {
1969         /* D[0:11] */
1970         192, 193, 194, 195, 196, 197, 198, 199,
1971         200, 201, 202, 203,
1972 };
1973 static const unsigned int lcd_data12_mux[] = {
1974         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1975         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1976         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1977 };
1978 static const unsigned int lcd_data16_pins[] = {
1979         /* D[0:15] */
1980         192, 193, 194, 195, 196, 197, 198, 199,
1981         200, 201, 202, 203, 204, 205, 206, 207,
1982 };
1983 static const unsigned int lcd_data16_mux[] = {
1984         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1985         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1986         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1987         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
1988 };
1989 static const unsigned int lcd_data18_pins[] = {
1990         /* D[0:17] */
1991         192, 193, 194, 195, 196, 197, 198, 199,
1992         200, 201, 202, 203, 204, 205, 206, 207,
1993         208, 209,
1994 };
1995 static const unsigned int lcd_data18_mux[] = {
1996         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
1997         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
1998         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
1999         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2000         LCDD16_MARK, LCDD17_MARK,
2001 };
2002 static const unsigned int lcd_data24_pins[] = {
2003         /* D[0:23] */
2004         192, 193, 194, 195, 196, 197, 198, 199,
2005         200, 201, 202, 203, 204, 205, 206, 207,
2006         208, 209, 210, 211, 212, 213, 214, 215
2007 };
2008 static const unsigned int lcd_data24_mux[] = {
2009         LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
2010         LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
2011         LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
2012         LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
2013         LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
2014         LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
2015 };
2016 static const unsigned int lcd_display_pins[] = {
2017         /* DON */
2018         222,
2019 };
2020 static const unsigned int lcd_display_mux[] = {
2021         LCDDON_MARK,
2022 };
2023 static const unsigned int lcd_lclk_pins[] = {
2024         /* LCLK */
2025         221,
2026 };
2027 static const unsigned int lcd_lclk_mux[] = {
2028         LCDLCLK_MARK,
2029 };
2030 static const unsigned int lcd_sync_pins[] = {
2031         /* VSYN, HSYN, DCK, DISP */
2032         220, 218, 216, 219,
2033 };
2034 static const unsigned int lcd_sync_mux[] = {
2035         LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
2036 };
2037 static const unsigned int lcd_sys_pins[] = {
2038         /* CS, WR, RD, RS */
2039         218, 216, 217, 219,
2040 };
2041 static const unsigned int lcd_sys_mux[] = {
2042         LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
2043 };
2044 /* - LCD2 ------------------------------------------------------------------- */
2045 static const unsigned int lcd2_data8_pins[] = {
2046         /* D[0:7] */
2047         128, 129, 142, 143, 144, 145, 138, 139,
2048 };
2049 static const unsigned int lcd2_data8_mux[] = {
2050         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2051         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2052 };
2053 static const unsigned int lcd2_data9_pins[] = {
2054         /* D[0:8] */
2055         128, 129, 142, 143, 144, 145, 138, 139,
2056         140,
2057 };
2058 static const unsigned int lcd2_data9_mux[] = {
2059         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2060         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2061         LCD2D8_MARK,
2062 };
2063 static const unsigned int lcd2_data12_pins[] = {
2064         /* D[0:12] */
2065         128, 129, 142, 143, 144, 145, 138, 139,
2066         140, 141, 130, 131,
2067 };
2068 static const unsigned int lcd2_data12_mux[] = {
2069         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2070         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2071         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2072 };
2073 static const unsigned int lcd2_data16_pins[] = {
2074         /* D[0:15] */
2075         128, 129, 142, 143, 144, 145, 138, 139,
2076         140, 141, 130, 131, 132, 133, 134, 135,
2077 };
2078 static const unsigned int lcd2_data16_mux[] = {
2079         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2080         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2081         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2082         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2083 };
2084 static const unsigned int lcd2_data18_pins[] = {
2085         /* D[0:17] */
2086         128, 129, 142, 143, 144, 145, 138, 139,
2087         140, 141, 130, 131, 132, 133, 134, 135,
2088         136, 137,
2089 };
2090 static const unsigned int lcd2_data18_mux[] = {
2091         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2092         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2093         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2094         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2095         LCD2D16_MARK, LCD2D17_MARK,
2096 };
2097 static const unsigned int lcd2_data24_pins[] = {
2098         /* D[0:23] */
2099         128, 129, 142, 143, 144, 145, 138, 139,
2100         140, 141, 130, 131, 132, 133, 134, 135,
2101         136, 137, 146, 147, 234, 235, 238, 239
2102 };
2103 static const unsigned int lcd2_data24_mux[] = {
2104         LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
2105         LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
2106         LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
2107         LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
2108         LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
2109         LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
2110 };
2111 static const unsigned int lcd2_sync_0_pins[] = {
2112         /* VSYN, HSYN, DCK, DISP */
2113         128, 129, 146, 145,
2114 };
2115 static const unsigned int lcd2_sync_0_mux[] = {
2116         PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
2117         LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
2118 };
2119 static const unsigned int lcd2_sync_1_pins[] = {
2120         /* VSYN, HSYN, DCK, DISP */
2121         222, 221, 219, 217,
2122 };
2123 static const unsigned int lcd2_sync_1_mux[] = {
2124         PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
2125         LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
2126 };
2127 static const unsigned int lcd2_sys_0_pins[] = {
2128         /* CS, WR, RD, RS */
2129         129, 146, 147, 145,
2130 };
2131 static const unsigned int lcd2_sys_0_mux[] = {
2132         PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
2133         LCD2RD__MARK, PORT145_LCD2RS_MARK,
2134 };
2135 static const unsigned int lcd2_sys_1_pins[] = {
2136         /* CS, WR, RD, RS */
2137         221, 219, 147, 217,
2138 };
2139 static const unsigned int lcd2_sys_1_mux[] = {
2140         PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
2141         LCD2RD__MARK, PORT217_LCD2RS_MARK,
2142 };
2143 /* - MMCIF ------------------------------------------------------------------ */
2144 static const unsigned int mmc0_data1_0_pins[] = {
2145         /* D[0] */
2146         271,
2147 };
2148 static const unsigned int mmc0_data1_0_mux[] = {
2149         MMCD0_0_MARK,
2150 };
2151 static const unsigned int mmc0_data4_0_pins[] = {
2152         /* D[0:3] */
2153         271, 272, 273, 274,
2154 };
2155 static const unsigned int mmc0_data4_0_mux[] = {
2156         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2157 };
2158 static const unsigned int mmc0_data8_0_pins[] = {
2159         /* D[0:7] */
2160         271, 272, 273, 274, 275, 276, 277, 278,
2161 };
2162 static const unsigned int mmc0_data8_0_mux[] = {
2163         MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
2164         MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
2165 };
2166 static const unsigned int mmc0_ctrl_0_pins[] = {
2167         /* CMD, CLK */
2168         279, 270,
2169 };
2170 static const unsigned int mmc0_ctrl_0_mux[] = {
2171         MMCCMD0_MARK, MMCCLK0_MARK,
2172 };
2173
2174 static const unsigned int mmc0_data1_1_pins[] = {
2175         /* D[0] */
2176         305,
2177 };
2178 static const unsigned int mmc0_data1_1_mux[] = {
2179         MMCD1_0_MARK,
2180 };
2181 static const unsigned int mmc0_data4_1_pins[] = {
2182         /* D[0:3] */
2183         305, 304, 303, 302,
2184 };
2185 static const unsigned int mmc0_data4_1_mux[] = {
2186         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2187 };
2188 static const unsigned int mmc0_data8_1_pins[] = {
2189         /* D[0:7] */
2190         305, 304, 303, 302, 301, 300, 299, 298,
2191 };
2192 static const unsigned int mmc0_data8_1_mux[] = {
2193         MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
2194         MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
2195 };
2196 static const unsigned int mmc0_ctrl_1_pins[] = {
2197         /* CMD, CLK */
2198         297, 289,
2199 };
2200 static const unsigned int mmc0_ctrl_1_mux[] = {
2201         MMCCMD1_MARK, MMCCLK1_MARK,
2202 };
2203 /* - SCIFA0 ----------------------------------------------------------------- */
2204 static const unsigned int scifa0_data_pins[] = {
2205         /* RXD, TXD */
2206         43, 17,
2207 };
2208 static const unsigned int scifa0_data_mux[] = {
2209         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2210 };
2211 static const unsigned int scifa0_clk_pins[] = {
2212         /* SCK */
2213         16,
2214 };
2215 static const unsigned int scifa0_clk_mux[] = {
2216         SCIFA0_SCK_MARK,
2217 };
2218 static const unsigned int scifa0_ctrl_pins[] = {
2219         /* RTS, CTS */
2220         42, 44,
2221 };
2222 static const unsigned int scifa0_ctrl_mux[] = {
2223         SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
2224 };
2225 /* - SCIFA1 ----------------------------------------------------------------- */
2226 static const unsigned int scifa1_data_pins[] = {
2227         /* RXD, TXD */
2228         228, 225,
2229 };
2230 static const unsigned int scifa1_data_mux[] = {
2231         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2232 };
2233 static const unsigned int scifa1_clk_pins[] = {
2234         /* SCK */
2235         226,
2236 };
2237 static const unsigned int scifa1_clk_mux[] = {
2238         SCIFA1_SCK_MARK,
2239 };
2240 static const unsigned int scifa1_ctrl_pins[] = {
2241         /* RTS, CTS */
2242         227, 229,
2243 };
2244 static const unsigned int scifa1_ctrl_mux[] = {
2245         SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
2246 };
2247 /* - SCIFA2 ----------------------------------------------------------------- */
2248 static const unsigned int scifa2_data_0_pins[] = {
2249         /* RXD, TXD */
2250         155, 154,
2251 };
2252 static const unsigned int scifa2_data_0_mux[] = {
2253         SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
2254 };
2255 static const unsigned int scifa2_clk_0_pins[] = {
2256         /* SCK */
2257         158,
2258 };
2259 static const unsigned int scifa2_clk_0_mux[] = {
2260         SCIFA2_SCK1_MARK,
2261 };
2262 static const unsigned int scifa2_ctrl_0_pins[] = {
2263         /* RTS, CTS */
2264         156, 157,
2265 };
2266 static const unsigned int scifa2_ctrl_0_mux[] = {
2267         SCIFA2_RTS1__MARK, SCIFA2_CTS1__MARK,
2268 };
2269 static const unsigned int scifa2_data_1_pins[] = {
2270         /* RXD, TXD */
2271         233, 230,
2272 };
2273 static const unsigned int scifa2_data_1_mux[] = {
2274         SCIFA2_RXD2_MARK, SCIFA2_TXD2_MARK,
2275 };
2276 static const unsigned int scifa2_clk_1_pins[] = {
2277         /* SCK */
2278         232,
2279 };
2280 static const unsigned int scifa2_clk_1_mux[] = {
2281         SCIFA2_SCK2_MARK,
2282 };
2283 static const unsigned int scifa2_ctrl_1_pins[] = {
2284         /* RTS, CTS */
2285         234, 231,
2286 };
2287 static const unsigned int scifa2_ctrl_1_mux[] = {
2288         SCIFA2_RTS2__MARK, SCIFA2_CTS2__MARK,
2289 };
2290 /* - SCIFA3 ----------------------------------------------------------------- */
2291 static const unsigned int scifa3_data_pins[] = {
2292         /* RXD, TXD */
2293         108, 110,
2294 };
2295 static const unsigned int scifa3_data_mux[] = {
2296         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2297 };
2298 static const unsigned int scifa3_ctrl_pins[] = {
2299         /* RTS, CTS */
2300         109, 107,
2301 };
2302 static const unsigned int scifa3_ctrl_mux[] = {
2303         SCIFA3_RTS__MARK, SCIFA3_CTS__MARK,
2304 };
2305 /* - SCIFA4 ----------------------------------------------------------------- */
2306 static const unsigned int scifa4_data_pins[] = {
2307         /* RXD, TXD */
2308         33, 32,
2309 };
2310 static const unsigned int scifa4_data_mux[] = {
2311         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2312 };
2313 static const unsigned int scifa4_ctrl_pins[] = {
2314         /* RTS, CTS */
2315         34, 35,
2316 };
2317 static const unsigned int scifa4_ctrl_mux[] = {
2318         SCIFA4_RTS__MARK, SCIFA4_CTS__MARK,
2319 };
2320 /* - SCIFA5 ----------------------------------------------------------------- */
2321 static const unsigned int scifa5_data_0_pins[] = {
2322         /* RXD, TXD */
2323         246, 247,
2324 };
2325 static const unsigned int scifa5_data_0_mux[] = {
2326         PORT246_SCIFA5_RXD_MARK, PORT247_SCIFA5_TXD_MARK,
2327 };
2328 static const unsigned int scifa5_clk_0_pins[] = {
2329         /* SCK */
2330         248,
2331 };
2332 static const unsigned int scifa5_clk_0_mux[] = {
2333         PORT248_SCIFA5_SCK_MARK,
2334 };
2335 static const unsigned int scifa5_ctrl_0_pins[] = {
2336         /* RTS, CTS */
2337         245, 244,
2338 };
2339 static const unsigned int scifa5_ctrl_0_mux[] = {
2340         PORT245_SCIFA5_RTS__MARK, PORT244_SCIFA5_CTS__MARK,
2341 };
2342 static const unsigned int scifa5_data_1_pins[] = {
2343         /* RXD, TXD */
2344         195, 196,
2345 };
2346 static const unsigned int scifa5_data_1_mux[] = {
2347         PORT195_SCIFA5_RXD_MARK, PORT196_SCIFA5_TXD_MARK,
2348 };
2349 static const unsigned int scifa5_clk_1_pins[] = {
2350         /* SCK */
2351         197,
2352 };
2353 static const unsigned int scifa5_clk_1_mux[] = {
2354         PORT197_SCIFA5_SCK_MARK,
2355 };
2356 static const unsigned int scifa5_ctrl_1_pins[] = {
2357         /* RTS, CTS */
2358         194, 193,
2359 };
2360 static const unsigned int scifa5_ctrl_1_mux[] = {
2361         PORT194_SCIFA5_RTS__MARK, PORT193_SCIFA5_CTS__MARK,
2362 };
2363 static const unsigned int scifa5_data_2_pins[] = {
2364         /* RXD, TXD */
2365         162, 160,
2366 };
2367 static const unsigned int scifa5_data_2_mux[] = {
2368         PORT162_SCIFA5_RXD_MARK, PORT160_SCIFA5_TXD_MARK,
2369 };
2370 static const unsigned int scifa5_clk_2_pins[] = {
2371         /* SCK */
2372         159,
2373 };
2374 static const unsigned int scifa5_clk_2_mux[] = {
2375         PORT159_SCIFA5_SCK_MARK,
2376 };
2377 static const unsigned int scifa5_ctrl_2_pins[] = {
2378         /* RTS, CTS */
2379         163, 161,
2380 };
2381 static const unsigned int scifa5_ctrl_2_mux[] = {
2382         PORT163_SCIFA5_RTS__MARK, PORT161_SCIFA5_CTS__MARK,
2383 };
2384 /* - SCIFA6 ----------------------------------------------------------------- */
2385 static const unsigned int scifa6_pins[] = {
2386         /* TXD */
2387         240,
2388 };
2389 static const unsigned int scifa6_mux[] = {
2390         SCIFA6_TXD_MARK,
2391 };
2392 /* - SCIFA7 ----------------------------------------------------------------- */
2393 static const unsigned int scifa7_data_pins[] = {
2394         /* RXD, TXD */
2395         12, 18,
2396 };
2397 static const unsigned int scifa7_data_mux[] = {
2398         SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2399 };
2400 static const unsigned int scifa7_ctrl_pins[] = {
2401         /* RTS, CTS */
2402         19, 13,
2403 };
2404 static const unsigned int scifa7_ctrl_mux[] = {
2405         SCIFA7_RTS__MARK, SCIFA7_CTS__MARK,
2406 };
2407 /* - SCIFB ------------------------------------------------------------------ */
2408 static const unsigned int scifb_data_0_pins[] = {
2409         /* RXD, TXD */
2410         162, 160,
2411 };
2412 static const unsigned int scifb_data_0_mux[] = {
2413         PORT162_SCIFB_RXD_MARK, PORT160_SCIFB_TXD_MARK,
2414 };
2415 static const unsigned int scifb_clk_0_pins[] = {
2416         /* SCK */
2417         159,
2418 };
2419 static const unsigned int scifb_clk_0_mux[] = {
2420         PORT159_SCIFB_SCK_MARK,
2421 };
2422 static const unsigned int scifb_ctrl_0_pins[] = {
2423         /* RTS, CTS */
2424         163, 161,
2425 };
2426 static const unsigned int scifb_ctrl_0_mux[] = {
2427         PORT163_SCIFB_RTS__MARK, PORT161_SCIFB_CTS__MARK,
2428 };
2429 static const unsigned int scifb_data_1_pins[] = {
2430         /* RXD, TXD */
2431         246, 247,
2432 };
2433 static const unsigned int scifb_data_1_mux[] = {
2434         PORT246_SCIFB_RXD_MARK, PORT247_SCIFB_TXD_MARK,
2435 };
2436 static const unsigned int scifb_clk_1_pins[] = {
2437         /* SCK */
2438         248,
2439 };
2440 static const unsigned int scifb_clk_1_mux[] = {
2441         PORT248_SCIFB_SCK_MARK,
2442 };
2443 static const unsigned int scifb_ctrl_1_pins[] = {
2444         /* RTS, CTS */
2445         245, 244,
2446 };
2447 static const unsigned int scifb_ctrl_1_mux[] = {
2448         PORT245_SCIFB_RTS__MARK, PORT244_SCIFB_CTS__MARK,
2449 };
2450 /* - SDHI0 ------------------------------------------------------------------ */
2451 static const unsigned int sdhi0_data1_pins[] = {
2452         /* D0 */
2453         252,
2454 };
2455 static const unsigned int sdhi0_data1_mux[] = {
2456         SDHID0_0_MARK,
2457 };
2458 static const unsigned int sdhi0_data4_pins[] = {
2459         /* D[0:3] */
2460         252, 253, 254, 255,
2461 };
2462 static const unsigned int sdhi0_data4_mux[] = {
2463         SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
2464 };
2465 static const unsigned int sdhi0_ctrl_pins[] = {
2466         /* CMD, CLK */
2467         256, 250,
2468 };
2469 static const unsigned int sdhi0_ctrl_mux[] = {
2470         SDHICMD0_MARK, SDHICLK0_MARK,
2471 };
2472 static const unsigned int sdhi0_cd_pins[] = {
2473         /* CD */
2474         251,
2475 };
2476 static const unsigned int sdhi0_cd_mux[] = {
2477         SDHICD0_MARK,
2478 };
2479 static const unsigned int sdhi0_wp_pins[] = {
2480         /* WP */
2481         257,
2482 };
2483 static const unsigned int sdhi0_wp_mux[] = {
2484         SDHIWP0_MARK,
2485 };
2486 /* - SDHI1 ------------------------------------------------------------------ */
2487 static const unsigned int sdhi1_data1_pins[] = {
2488         /* D0 */
2489         259,
2490 };
2491 static const unsigned int sdhi1_data1_mux[] = {
2492         SDHID1_0_MARK,
2493 };
2494 static const unsigned int sdhi1_data4_pins[] = {
2495         /* D[0:3] */
2496         259, 260, 261, 262,
2497 };
2498 static const unsigned int sdhi1_data4_mux[] = {
2499         SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
2500 };
2501 static const unsigned int sdhi1_ctrl_pins[] = {
2502         /* CMD, CLK */
2503         263, 258,
2504 };
2505 static const unsigned int sdhi1_ctrl_mux[] = {
2506         SDHICMD1_MARK, SDHICLK1_MARK,
2507 };
2508 /* - SDHI2 ------------------------------------------------------------------ */
2509 static const unsigned int sdhi2_data1_pins[] = {
2510         /* D0 */
2511         265,
2512 };
2513 static const unsigned int sdhi2_data1_mux[] = {
2514         SDHID2_0_MARK,
2515 };
2516 static const unsigned int sdhi2_data4_pins[] = {
2517         /* D[0:3] */
2518         265, 266, 267, 268,
2519 };
2520 static const unsigned int sdhi2_data4_mux[] = {
2521         SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
2522 };
2523 static const unsigned int sdhi2_ctrl_pins[] = {
2524         /* CMD, CLK */
2525         269, 264,
2526 };
2527 static const unsigned int sdhi2_ctrl_mux[] = {
2528         SDHICMD2_MARK, SDHICLK2_MARK,
2529 };
2530 /* - TPU0 ------------------------------------------------------------------- */
2531 static const unsigned int tpu0_to0_pins[] = {
2532         /* TO */
2533         55,
2534 };
2535 static const unsigned int tpu0_to0_mux[] = {
2536         TPU0TO0_MARK,
2537 };
2538 static const unsigned int tpu0_to1_pins[] = {
2539         /* TO */
2540         59,
2541 };
2542 static const unsigned int tpu0_to1_mux[] = {
2543         TPU0TO1_MARK,
2544 };
2545 static const unsigned int tpu0_to2_pins[] = {
2546         /* TO */
2547         140,
2548 };
2549 static const unsigned int tpu0_to2_mux[] = {
2550         TPU0TO2_MARK,
2551 };
2552 static const unsigned int tpu0_to3_pins[] = {
2553         /* TO */
2554         141,
2555 };
2556 static const unsigned int tpu0_to3_mux[] = {
2557         TPU0TO3_MARK,
2558 };
2559 /* - TPU1 ------------------------------------------------------------------- */
2560 static const unsigned int tpu1_to0_pins[] = {
2561         /* TO */
2562         246,
2563 };
2564 static const unsigned int tpu1_to0_mux[] = {
2565         TPU1TO0_MARK,
2566 };
2567 static const unsigned int tpu1_to1_0_pins[] = {
2568         /* TO */
2569         28,
2570 };
2571 static const unsigned int tpu1_to1_0_mux[] = {
2572         PORT28_TPU1TO1_MARK,
2573 };
2574 static const unsigned int tpu1_to1_1_pins[] = {
2575         /* TO */
2576         29,
2577 };
2578 static const unsigned int tpu1_to1_1_mux[] = {
2579         PORT29_TPU1TO1_MARK,
2580 };
2581 static const unsigned int tpu1_to2_pins[] = {
2582         /* TO */
2583         153,
2584 };
2585 static const unsigned int tpu1_to2_mux[] = {
2586         TPU1TO2_MARK,
2587 };
2588 static const unsigned int tpu1_to3_pins[] = {
2589         /* TO */
2590         145,
2591 };
2592 static const unsigned int tpu1_to3_mux[] = {
2593         TPU1TO3_MARK,
2594 };
2595 /* - TPU2 ------------------------------------------------------------------- */
2596 static const unsigned int tpu2_to0_pins[] = {
2597         /* TO */
2598         248,
2599 };
2600 static const unsigned int tpu2_to0_mux[] = {
2601         TPU2TO0_MARK,
2602 };
2603 static const unsigned int tpu2_to1_pins[] = {
2604         /* TO */
2605         197,
2606 };
2607 static const unsigned int tpu2_to1_mux[] = {
2608         TPU2TO1_MARK,
2609 };
2610 static const unsigned int tpu2_to2_pins[] = {
2611         /* TO */
2612         50,
2613 };
2614 static const unsigned int tpu2_to2_mux[] = {
2615         TPU2TO2_MARK,
2616 };
2617 static const unsigned int tpu2_to3_pins[] = {
2618         /* TO */
2619         51,
2620 };
2621 static const unsigned int tpu2_to3_mux[] = {
2622         TPU2TO3_MARK,
2623 };
2624 /* - TPU3 ------------------------------------------------------------------- */
2625 static const unsigned int tpu3_to0_pins[] = {
2626         /* TO */
2627         163,
2628 };
2629 static const unsigned int tpu3_to0_mux[] = {
2630         TPU3TO0_MARK,
2631 };
2632 static const unsigned int tpu3_to1_pins[] = {
2633         /* TO */
2634         247,
2635 };
2636 static const unsigned int tpu3_to1_mux[] = {
2637         TPU3TO1_MARK,
2638 };
2639 static const unsigned int tpu3_to2_pins[] = {
2640         /* TO */
2641         54,
2642 };
2643 static const unsigned int tpu3_to2_mux[] = {
2644         TPU3TO2_MARK,
2645 };
2646 static const unsigned int tpu3_to3_pins[] = {
2647         /* TO */
2648         53,
2649 };
2650 static const unsigned int tpu3_to3_mux[] = {
2651         TPU3TO3_MARK,
2652 };
2653 /* - TPU4 ------------------------------------------------------------------- */
2654 static const unsigned int tpu4_to0_pins[] = {
2655         /* TO */
2656         241,
2657 };
2658 static const unsigned int tpu4_to0_mux[] = {
2659         TPU4TO0_MARK,
2660 };
2661 static const unsigned int tpu4_to1_pins[] = {
2662         /* TO */
2663         199,
2664 };
2665 static const unsigned int tpu4_to1_mux[] = {
2666         TPU4TO1_MARK,
2667 };
2668 static const unsigned int tpu4_to2_pins[] = {
2669         /* TO */
2670         58,
2671 };
2672 static const unsigned int tpu4_to2_mux[] = {
2673         TPU4TO2_MARK,
2674 };
2675 static const unsigned int tpu4_to3_pins[] = {
2676         /* TO */
2677 };
2678 static const unsigned int tpu4_to3_mux[] = {
2679         TPU4TO3_MARK,
2680 };
2681 /* - USB -------------------------------------------------------------------- */
2682 static const unsigned int usb_vbus_pins[] = {
2683         /* VBUS */
2684         0,
2685 };
2686 static const unsigned int usb_vbus_mux[] = {
2687         VBUS_0_MARK,
2688 };
2689
2690 static const struct sh_pfc_pin_group pinmux_groups[] = {
2691         SH_PFC_PIN_GROUP(bsc_data_0_7),
2692         SH_PFC_PIN_GROUP(bsc_data_8_15),
2693         SH_PFC_PIN_GROUP(bsc_cs4),
2694         SH_PFC_PIN_GROUP(bsc_cs5_a),
2695         SH_PFC_PIN_GROUP(bsc_cs5_b),
2696         SH_PFC_PIN_GROUP(bsc_cs6_a),
2697         SH_PFC_PIN_GROUP(bsc_cs6_b),
2698         SH_PFC_PIN_GROUP(bsc_rd),
2699         SH_PFC_PIN_GROUP(bsc_rdwr_0),
2700         SH_PFC_PIN_GROUP(bsc_rdwr_1),
2701         SH_PFC_PIN_GROUP(bsc_rdwr_2),
2702         SH_PFC_PIN_GROUP(bsc_we0),
2703         SH_PFC_PIN_GROUP(bsc_we1),
2704         SH_PFC_PIN_GROUP(fsia_mclk_in),
2705         SH_PFC_PIN_GROUP(fsia_mclk_out),
2706         SH_PFC_PIN_GROUP(fsia_sclk_in),
2707         SH_PFC_PIN_GROUP(fsia_sclk_out),
2708         SH_PFC_PIN_GROUP(fsia_data_in),
2709         SH_PFC_PIN_GROUP(fsia_data_out),
2710         SH_PFC_PIN_GROUP(fsia_spdif),
2711         SH_PFC_PIN_GROUP(fsib_mclk_in),
2712         SH_PFC_PIN_GROUP(fsib_mclk_out),
2713         SH_PFC_PIN_GROUP(fsib_sclk_in),
2714         SH_PFC_PIN_GROUP(fsib_sclk_out),
2715         SH_PFC_PIN_GROUP(fsib_data_in),
2716         SH_PFC_PIN_GROUP(fsib_data_out),
2717         SH_PFC_PIN_GROUP(fsib_spdif),
2718         SH_PFC_PIN_GROUP(fsic_mclk_in),
2719         SH_PFC_PIN_GROUP(fsic_mclk_out),
2720         SH_PFC_PIN_GROUP(fsic_sclk_in),
2721         SH_PFC_PIN_GROUP(fsic_sclk_out),
2722         SH_PFC_PIN_GROUP(fsic_data_in),
2723         SH_PFC_PIN_GROUP(fsic_data_out),
2724         SH_PFC_PIN_GROUP(fsic_spdif_0),
2725         SH_PFC_PIN_GROUP(fsic_spdif_1),
2726         SH_PFC_PIN_GROUP(fsid_sclk_in),
2727         SH_PFC_PIN_GROUP(fsid_sclk_out),
2728         SH_PFC_PIN_GROUP(fsid_data_in),
2729         SH_PFC_PIN_GROUP(i2c2_0),
2730         SH_PFC_PIN_GROUP(i2c2_1),
2731         SH_PFC_PIN_GROUP(i2c2_2),
2732         SH_PFC_PIN_GROUP(i2c3_0),
2733         SH_PFC_PIN_GROUP(i2c3_1),
2734         SH_PFC_PIN_GROUP(i2c3_2),
2735         SH_PFC_PIN_GROUP(irda_0),
2736         SH_PFC_PIN_GROUP(irda_1),
2737         SH_PFC_PIN_GROUP(keysc_in5),
2738         SH_PFC_PIN_GROUP(keysc_in6),
2739         SH_PFC_PIN_GROUP(keysc_in7),
2740         SH_PFC_PIN_GROUP(keysc_in8),
2741         SH_PFC_PIN_GROUP(keysc_out04),
2742         SH_PFC_PIN_GROUP(keysc_out5),
2743         SH_PFC_PIN_GROUP(keysc_out6_0),
2744         SH_PFC_PIN_GROUP(keysc_out6_1),
2745         SH_PFC_PIN_GROUP(keysc_out6_2),
2746         SH_PFC_PIN_GROUP(keysc_out7_0),
2747         SH_PFC_PIN_GROUP(keysc_out7_1),
2748         SH_PFC_PIN_GROUP(keysc_out7_2),
2749         SH_PFC_PIN_GROUP(keysc_out8_0),
2750         SH_PFC_PIN_GROUP(keysc_out8_1),
2751         SH_PFC_PIN_GROUP(keysc_out8_2),
2752         SH_PFC_PIN_GROUP(keysc_out9_0),
2753         SH_PFC_PIN_GROUP(keysc_out9_1),
2754         SH_PFC_PIN_GROUP(keysc_out9_2),
2755         SH_PFC_PIN_GROUP(keysc_out10_0),
2756         SH_PFC_PIN_GROUP(keysc_out10_1),
2757         SH_PFC_PIN_GROUP(keysc_out11_0),
2758         SH_PFC_PIN_GROUP(keysc_out11_1),
2759         SH_PFC_PIN_GROUP(lcd_data8),
2760         SH_PFC_PIN_GROUP(lcd_data9),
2761         SH_PFC_PIN_GROUP(lcd_data12),
2762         SH_PFC_PIN_GROUP(lcd_data16),
2763         SH_PFC_PIN_GROUP(lcd_data18),
2764         SH_PFC_PIN_GROUP(lcd_data24),
2765         SH_PFC_PIN_GROUP(lcd_display),
2766         SH_PFC_PIN_GROUP(lcd_lclk),
2767         SH_PFC_PIN_GROUP(lcd_sync),
2768         SH_PFC_PIN_GROUP(lcd_sys),
2769         SH_PFC_PIN_GROUP(lcd2_data8),
2770         SH_PFC_PIN_GROUP(lcd2_data9),
2771         SH_PFC_PIN_GROUP(lcd2_data12),
2772         SH_PFC_PIN_GROUP(lcd2_data16),
2773         SH_PFC_PIN_GROUP(lcd2_data18),
2774         SH_PFC_PIN_GROUP(lcd2_data24),
2775         SH_PFC_PIN_GROUP(lcd2_sync_0),
2776         SH_PFC_PIN_GROUP(lcd2_sync_1),
2777         SH_PFC_PIN_GROUP(lcd2_sys_0),
2778         SH_PFC_PIN_GROUP(lcd2_sys_1),
2779         SH_PFC_PIN_GROUP(mmc0_data1_0),
2780         SH_PFC_PIN_GROUP(mmc0_data4_0),
2781         SH_PFC_PIN_GROUP(mmc0_data8_0),
2782         SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2783         SH_PFC_PIN_GROUP(mmc0_data1_1),
2784         SH_PFC_PIN_GROUP(mmc0_data4_1),
2785         SH_PFC_PIN_GROUP(mmc0_data8_1),
2786         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2787         SH_PFC_PIN_GROUP(scifa0_data),
2788         SH_PFC_PIN_GROUP(scifa0_clk),
2789         SH_PFC_PIN_GROUP(scifa0_ctrl),
2790         SH_PFC_PIN_GROUP(scifa1_data),
2791         SH_PFC_PIN_GROUP(scifa1_clk),
2792         SH_PFC_PIN_GROUP(scifa1_ctrl),
2793         SH_PFC_PIN_GROUP(scifa2_data_0),
2794         SH_PFC_PIN_GROUP(scifa2_clk_0),
2795         SH_PFC_PIN_GROUP(scifa2_ctrl_0),
2796         SH_PFC_PIN_GROUP(scifa2_data_1),
2797         SH_PFC_PIN_GROUP(scifa2_clk_1),
2798         SH_PFC_PIN_GROUP(scifa2_ctrl_1),
2799         SH_PFC_PIN_GROUP(scifa3_data),
2800         SH_PFC_PIN_GROUP(scifa3_ctrl),
2801         SH_PFC_PIN_GROUP(scifa4_data),
2802         SH_PFC_PIN_GROUP(scifa4_ctrl),
2803         SH_PFC_PIN_GROUP(scifa5_data_0),
2804         SH_PFC_PIN_GROUP(scifa5_clk_0),
2805         SH_PFC_PIN_GROUP(scifa5_ctrl_0),
2806         SH_PFC_PIN_GROUP(scifa5_data_1),
2807         SH_PFC_PIN_GROUP(scifa5_clk_1),
2808         SH_PFC_PIN_GROUP(scifa5_ctrl_1),
2809         SH_PFC_PIN_GROUP(scifa5_data_2),
2810         SH_PFC_PIN_GROUP(scifa5_clk_2),
2811         SH_PFC_PIN_GROUP(scifa5_ctrl_2),
2812         SH_PFC_PIN_GROUP(scifa6),
2813         SH_PFC_PIN_GROUP(scifa7_data),
2814         SH_PFC_PIN_GROUP(scifa7_ctrl),
2815         SH_PFC_PIN_GROUP(scifb_data_0),
2816         SH_PFC_PIN_GROUP(scifb_clk_0),
2817         SH_PFC_PIN_GROUP(scifb_ctrl_0),
2818         SH_PFC_PIN_GROUP(scifb_data_1),
2819         SH_PFC_PIN_GROUP(scifb_clk_1),
2820         SH_PFC_PIN_GROUP(scifb_ctrl_1),
2821         SH_PFC_PIN_GROUP(sdhi0_data1),
2822         SH_PFC_PIN_GROUP(sdhi0_data4),
2823         SH_PFC_PIN_GROUP(sdhi0_ctrl),
2824         SH_PFC_PIN_GROUP(sdhi0_cd),
2825         SH_PFC_PIN_GROUP(sdhi0_wp),
2826         SH_PFC_PIN_GROUP(sdhi1_data1),
2827         SH_PFC_PIN_GROUP(sdhi1_data4),
2828         SH_PFC_PIN_GROUP(sdhi1_ctrl),
2829         SH_PFC_PIN_GROUP(sdhi2_data1),
2830         SH_PFC_PIN_GROUP(sdhi2_data4),
2831         SH_PFC_PIN_GROUP(sdhi2_ctrl),
2832         SH_PFC_PIN_GROUP(tpu0_to0),
2833         SH_PFC_PIN_GROUP(tpu0_to1),
2834         SH_PFC_PIN_GROUP(tpu0_to2),
2835         SH_PFC_PIN_GROUP(tpu0_to3),
2836         SH_PFC_PIN_GROUP(tpu1_to0),
2837         SH_PFC_PIN_GROUP(tpu1_to1_0),
2838         SH_PFC_PIN_GROUP(tpu1_to1_1),
2839         SH_PFC_PIN_GROUP(tpu1_to2),
2840         SH_PFC_PIN_GROUP(tpu1_to3),
2841         SH_PFC_PIN_GROUP(tpu2_to0),
2842         SH_PFC_PIN_GROUP(tpu2_to1),
2843         SH_PFC_PIN_GROUP(tpu2_to2),
2844         SH_PFC_PIN_GROUP(tpu2_to3),
2845         SH_PFC_PIN_GROUP(tpu3_to0),
2846         SH_PFC_PIN_GROUP(tpu3_to1),
2847         SH_PFC_PIN_GROUP(tpu3_to2),
2848         SH_PFC_PIN_GROUP(tpu3_to3),
2849         SH_PFC_PIN_GROUP(tpu4_to0),
2850         SH_PFC_PIN_GROUP(tpu4_to1),
2851         SH_PFC_PIN_GROUP(tpu4_to2),
2852         SH_PFC_PIN_GROUP(tpu4_to3),
2853         SH_PFC_PIN_GROUP(usb_vbus),
2854 };
2855
2856 static const char * const bsc_groups[] = {
2857         "bsc_data_0_7",
2858         "bsc_data_8_15",
2859         "bsc_cs4",
2860         "bsc_cs5_a",
2861         "bsc_cs5_b",
2862         "bsc_cs6_a",
2863         "bsc_cs6_b",
2864         "bsc_rd",
2865         "bsc_rdwr_0",
2866         "bsc_rdwr_1",
2867         "bsc_rdwr_2",
2868         "bsc_we0",
2869         "bsc_we1",
2870 };
2871
2872 static const char * const fsia_groups[] = {
2873         "fsia_mclk_in",
2874         "fsia_mclk_out",
2875         "fsia_sclk_in",
2876         "fsia_sclk_out",
2877         "fsia_data_in",
2878         "fsia_data_out",
2879         "fsia_spdif",
2880 };
2881
2882 static const char * const fsib_groups[] = {
2883         "fsib_mclk_in",
2884         "fsib_mclk_out",
2885         "fsib_sclk_in",
2886         "fsib_sclk_out",
2887         "fsib_data_in",
2888         "fsib_data_out",
2889         "fsib_spdif",
2890 };
2891
2892 static const char * const fsic_groups[] = {
2893         "fsic_mclk_in",
2894         "fsic_mclk_out",
2895         "fsic_sclk_in",
2896         "fsic_sclk_out",
2897         "fsic_data_in",
2898         "fsic_data_out",
2899         "fsic_spdif",
2900 };
2901
2902 static const char * const fsid_groups[] = {
2903         "fsid_sclk_in",
2904         "fsid_sclk_out",
2905         "fsid_data_in",
2906 };
2907
2908 static const char * const i2c2_groups[] = {
2909         "i2c2_0",
2910         "i2c2_1",
2911         "i2c2_2",
2912 };
2913
2914 static const char * const i2c3_groups[] = {
2915         "i2c3_0",
2916         "i2c3_1",
2917         "i2c3_2",
2918 };
2919
2920 static const char * const irda_groups[] = {
2921         "irda_0",
2922         "irda_1",
2923 };
2924
2925 static const char * const keysc_groups[] = {
2926         "keysc_in5",
2927         "keysc_in6",
2928         "keysc_in7",
2929         "keysc_in8",
2930         "keysc_out04",
2931         "keysc_out5",
2932         "keysc_out6_0",
2933         "keysc_out6_1",
2934         "keysc_out6_2",
2935         "keysc_out7_0",
2936         "keysc_out7_1",
2937         "keysc_out7_2",
2938         "keysc_out8_0",
2939         "keysc_out8_1",
2940         "keysc_out8_2",
2941         "keysc_out9_0",
2942         "keysc_out9_1",
2943         "keysc_out9_2",
2944         "keysc_out10_0",
2945         "keysc_out10_1",
2946         "keysc_out11_0",
2947         "keysc_out11_1",
2948 };
2949
2950 static const char * const lcd_groups[] = {
2951         "lcd_data8",
2952         "lcd_data9",
2953         "lcd_data12",
2954         "lcd_data16",
2955         "lcd_data18",
2956         "lcd_data24",
2957         "lcd_display",
2958         "lcd_lclk",
2959         "lcd_sync",
2960         "lcd_sys",
2961 };
2962
2963 static const char * const lcd2_groups[] = {
2964         "lcd2_data8",
2965         "lcd2_data9",
2966         "lcd2_data12",
2967         "lcd2_data16",
2968         "lcd2_data18",
2969         "lcd2_data24",
2970         "lcd2_sync_0",
2971         "lcd2_sync_1",
2972         "lcd2_sys_0",
2973         "lcd2_sys_1",
2974 };
2975
2976 static const char * const mmc0_groups[] = {
2977         "mmc0_data1_0",
2978         "mmc0_data4_0",
2979         "mmc0_data8_0",
2980         "mmc0_ctrl_0",
2981         "mmc0_data1_1",
2982         "mmc0_data4_1",
2983         "mmc0_data8_1",
2984         "mmc0_ctrl_1",
2985 };
2986
2987 static const char * const scifa0_groups[] = {
2988         "scifa0_data",
2989         "scifa0_clk",
2990         "scifa0_ctrl",
2991 };
2992
2993 static const char * const scifa1_groups[] = {
2994         "scifa1_data",
2995         "scifa1_clk",
2996         "scifa1_ctrl",
2997 };
2998
2999 static const char * const scifa2_groups[] = {
3000         "scifa2_data_0",
3001         "scifa2_clk_0",
3002         "scifa2_ctrl_0",
3003         "scifa2_data_1",
3004         "scifa2_clk_1",
3005         "scifa2_ctrl_1",
3006 };
3007
3008 static const char * const scifa3_groups[] = {
3009         "scifa3_data",
3010         "scifa3_ctrl",
3011 };
3012
3013 static const char * const scifa4_groups[] = {
3014         "scifa4_data",
3015         "scifa4_ctrl",
3016 };
3017
3018 static const char * const scifa5_groups[] = {
3019         "scifa5_data_0",
3020         "scifa5_clk_0",
3021         "scifa5_ctrl_0",
3022         "scifa5_data_1",
3023         "scifa5_clk_1",
3024         "scifa5_ctrl_1",
3025         "scifa5_data_2",
3026         "scifa5_clk_2",
3027         "scifa5_ctrl_2",
3028 };
3029
3030 static const char * const scifa6_groups[] = {
3031         "scifa6",
3032 };
3033
3034 static const char * const scifa7_groups[] = {
3035         "scifa7_data",
3036         "scifa7_ctrl",
3037 };
3038
3039 static const char * const scifb_groups[] = {
3040         "scifb_data_0",
3041         "scifb_clk_0",
3042         "scifb_ctrl_0",
3043         "scifb_data_1",
3044         "scifb_clk_1",
3045         "scifb_ctrl_1",
3046 };
3047
3048 static const char * const sdhi0_groups[] = {
3049         "sdhi0_data1",
3050         "sdhi0_data4",
3051         "sdhi0_ctrl",
3052         "sdhi0_cd",
3053         "sdhi0_wp",
3054 };
3055
3056 static const char * const sdhi1_groups[] = {
3057         "sdhi1_data1",
3058         "sdhi1_data4",
3059         "sdhi1_ctrl",
3060 };
3061
3062 static const char * const sdhi2_groups[] = {
3063         "sdhi2_data1",
3064         "sdhi2_data4",
3065         "sdhi2_ctrl",
3066 };
3067
3068 static const char * const usb_groups[] = {
3069         "usb_vbus",
3070 };
3071
3072 static const char * const tpu0_groups[] = {
3073         "tpu0_to0",
3074         "tpu0_to1",
3075         "tpu0_to2",
3076         "tpu0_to3",
3077 };
3078
3079 static const char * const tpu1_groups[] = {
3080         "tpu1_to0",
3081         "tpu1_to1_0",
3082         "tpu1_to1_1",
3083         "tpu1_to2",
3084         "tpu1_to3",
3085 };
3086
3087 static const char * const tpu2_groups[] = {
3088         "tpu2_to0",
3089         "tpu2_to1",
3090         "tpu2_to2",
3091         "tpu2_to3",
3092 };
3093
3094 static const char * const tpu3_groups[] = {
3095         "tpu3_to0",
3096         "tpu3_to1",
3097         "tpu3_to2",
3098         "tpu3_to3",
3099 };
3100
3101 static const char * const tpu4_groups[] = {
3102         "tpu4_to0",
3103         "tpu4_to1",
3104         "tpu4_to2",
3105         "tpu4_to3",
3106 };
3107
3108 static const struct sh_pfc_function pinmux_functions[] = {
3109         SH_PFC_FUNCTION(bsc),
3110         SH_PFC_FUNCTION(fsia),
3111         SH_PFC_FUNCTION(fsib),
3112         SH_PFC_FUNCTION(fsic),
3113         SH_PFC_FUNCTION(fsid),
3114         SH_PFC_FUNCTION(i2c2),
3115         SH_PFC_FUNCTION(i2c3),
3116         SH_PFC_FUNCTION(irda),
3117         SH_PFC_FUNCTION(keysc),
3118         SH_PFC_FUNCTION(lcd),
3119         SH_PFC_FUNCTION(lcd2),
3120         SH_PFC_FUNCTION(mmc0),
3121         SH_PFC_FUNCTION(scifa0),
3122         SH_PFC_FUNCTION(scifa1),
3123         SH_PFC_FUNCTION(scifa2),
3124         SH_PFC_FUNCTION(scifa3),
3125         SH_PFC_FUNCTION(scifa4),
3126         SH_PFC_FUNCTION(scifa5),
3127         SH_PFC_FUNCTION(scifa6),
3128         SH_PFC_FUNCTION(scifa7),
3129         SH_PFC_FUNCTION(scifb),
3130         SH_PFC_FUNCTION(sdhi0),
3131         SH_PFC_FUNCTION(sdhi1),
3132         SH_PFC_FUNCTION(sdhi2),
3133         SH_PFC_FUNCTION(tpu0),
3134         SH_PFC_FUNCTION(tpu1),
3135         SH_PFC_FUNCTION(tpu2),
3136         SH_PFC_FUNCTION(tpu3),
3137         SH_PFC_FUNCTION(tpu4),
3138         SH_PFC_FUNCTION(usb),
3139 };
3140
3141 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3142         PORTCR(0, 0xe6050000), /* PORT0CR */
3143         PORTCR(1, 0xe6050001), /* PORT1CR */
3144         PORTCR(2, 0xe6050002), /* PORT2CR */
3145         PORTCR(3, 0xe6050003), /* PORT3CR */
3146         PORTCR(4, 0xe6050004), /* PORT4CR */
3147         PORTCR(5, 0xe6050005), /* PORT5CR */
3148         PORTCR(6, 0xe6050006), /* PORT6CR */
3149         PORTCR(7, 0xe6050007), /* PORT7CR */
3150         PORTCR(8, 0xe6050008), /* PORT8CR */
3151         PORTCR(9, 0xe6050009), /* PORT9CR */
3152
3153         PORTCR(10, 0xe605000a), /* PORT10CR */
3154         PORTCR(11, 0xe605000b), /* PORT11CR */
3155         PORTCR(12, 0xe605000c), /* PORT12CR */
3156         PORTCR(13, 0xe605000d), /* PORT13CR */
3157         PORTCR(14, 0xe605000e), /* PORT14CR */
3158         PORTCR(15, 0xe605000f), /* PORT15CR */
3159         PORTCR(16, 0xe6050010), /* PORT16CR */
3160         PORTCR(17, 0xe6050011), /* PORT17CR */
3161         PORTCR(18, 0xe6050012), /* PORT18CR */
3162         PORTCR(19, 0xe6050013), /* PORT19CR */
3163
3164         PORTCR(20, 0xe6050014), /* PORT20CR */
3165         PORTCR(21, 0xe6050015), /* PORT21CR */
3166         PORTCR(22, 0xe6050016), /* PORT22CR */
3167         PORTCR(23, 0xe6050017), /* PORT23CR */
3168         PORTCR(24, 0xe6050018), /* PORT24CR */
3169         PORTCR(25, 0xe6050019), /* PORT25CR */
3170         PORTCR(26, 0xe605001a), /* PORT26CR */
3171         PORTCR(27, 0xe605001b), /* PORT27CR */
3172         PORTCR(28, 0xe605001c), /* PORT28CR */
3173         PORTCR(29, 0xe605001d), /* PORT29CR */
3174
3175         PORTCR(30, 0xe605001e), /* PORT30CR */
3176         PORTCR(31, 0xe605001f), /* PORT31CR */
3177         PORTCR(32, 0xe6051020), /* PORT32CR */
3178         PORTCR(33, 0xe6051021), /* PORT33CR */
3179         PORTCR(34, 0xe6051022), /* PORT34CR */
3180         PORTCR(35, 0xe6051023), /* PORT35CR */
3181         PORTCR(36, 0xe6051024), /* PORT36CR */
3182         PORTCR(37, 0xe6051025), /* PORT37CR */
3183         PORTCR(38, 0xe6051026), /* PORT38CR */
3184         PORTCR(39, 0xe6051027), /* PORT39CR */
3185
3186         PORTCR(40, 0xe6051028), /* PORT40CR */
3187         PORTCR(41, 0xe6051029), /* PORT41CR */
3188         PORTCR(42, 0xe605102a), /* PORT42CR */
3189         PORTCR(43, 0xe605102b), /* PORT43CR */
3190         PORTCR(44, 0xe605102c), /* PORT44CR */
3191         PORTCR(45, 0xe605102d), /* PORT45CR */
3192         PORTCR(46, 0xe605102e), /* PORT46CR */
3193         PORTCR(47, 0xe605102f), /* PORT47CR */
3194         PORTCR(48, 0xe6051030), /* PORT48CR */
3195         PORTCR(49, 0xe6051031), /* PORT49CR */
3196
3197         PORTCR(50, 0xe6051032), /* PORT50CR */
3198         PORTCR(51, 0xe6051033), /* PORT51CR */
3199         PORTCR(52, 0xe6051034), /* PORT52CR */
3200         PORTCR(53, 0xe6051035), /* PORT53CR */
3201         PORTCR(54, 0xe6051036), /* PORT54CR */
3202         PORTCR(55, 0xe6051037), /* PORT55CR */
3203         PORTCR(56, 0xe6051038), /* PORT56CR */
3204         PORTCR(57, 0xe6051039), /* PORT57CR */
3205         PORTCR(58, 0xe605103a), /* PORT58CR */
3206         PORTCR(59, 0xe605103b), /* PORT59CR */
3207
3208         PORTCR(60, 0xe605103c), /* PORT60CR */
3209         PORTCR(61, 0xe605103d), /* PORT61CR */
3210         PORTCR(62, 0xe605103e), /* PORT62CR */
3211         PORTCR(63, 0xe605103f), /* PORT63CR */
3212         PORTCR(64, 0xe6051040), /* PORT64CR */
3213         PORTCR(65, 0xe6051041), /* PORT65CR */
3214         PORTCR(66, 0xe6051042), /* PORT66CR */
3215         PORTCR(67, 0xe6051043), /* PORT67CR */
3216         PORTCR(68, 0xe6051044), /* PORT68CR */
3217         PORTCR(69, 0xe6051045), /* PORT69CR */
3218
3219         PORTCR(70, 0xe6051046), /* PORT70CR */
3220         PORTCR(71, 0xe6051047), /* PORT71CR */
3221         PORTCR(72, 0xe6051048), /* PORT72CR */
3222         PORTCR(73, 0xe6051049), /* PORT73CR */
3223         PORTCR(74, 0xe605104a), /* PORT74CR */
3224         PORTCR(75, 0xe605104b), /* PORT75CR */
3225         PORTCR(76, 0xe605104c), /* PORT76CR */
3226         PORTCR(77, 0xe605104d), /* PORT77CR */
3227         PORTCR(78, 0xe605104e), /* PORT78CR */
3228         PORTCR(79, 0xe605104f), /* PORT79CR */
3229
3230         PORTCR(80, 0xe6051050), /* PORT80CR */
3231         PORTCR(81, 0xe6051051), /* PORT81CR */
3232         PORTCR(82, 0xe6051052), /* PORT82CR */
3233         PORTCR(83, 0xe6051053), /* PORT83CR */
3234         PORTCR(84, 0xe6051054), /* PORT84CR */
3235         PORTCR(85, 0xe6051055), /* PORT85CR */
3236         PORTCR(86, 0xe6051056), /* PORT86CR */
3237         PORTCR(87, 0xe6051057), /* PORT87CR */
3238         PORTCR(88, 0xe6051058), /* PORT88CR */
3239         PORTCR(89, 0xe6051059), /* PORT89CR */
3240
3241         PORTCR(90, 0xe605105a), /* PORT90CR */
3242         PORTCR(91, 0xe605105b), /* PORT91CR */
3243         PORTCR(92, 0xe605105c), /* PORT92CR */
3244         PORTCR(93, 0xe605105d), /* PORT93CR */
3245         PORTCR(94, 0xe605105e), /* PORT94CR */
3246         PORTCR(95, 0xe605105f), /* PORT95CR */
3247         PORTCR(96, 0xe6052060), /* PORT96CR */
3248         PORTCR(97, 0xe6052061), /* PORT97CR */
3249         PORTCR(98, 0xe6052062), /* PORT98CR */
3250         PORTCR(99, 0xe6052063), /* PORT99CR */
3251
3252         PORTCR(100, 0xe6052064), /* PORT100CR */
3253         PORTCR(101, 0xe6052065), /* PORT101CR */
3254         PORTCR(102, 0xe6052066), /* PORT102CR */
3255         PORTCR(103, 0xe6052067), /* PORT103CR */
3256         PORTCR(104, 0xe6052068), /* PORT104CR */
3257         PORTCR(105, 0xe6052069), /* PORT105CR */
3258         PORTCR(106, 0xe605206a), /* PORT106CR */
3259         PORTCR(107, 0xe605206b), /* PORT107CR */
3260         PORTCR(108, 0xe605206c), /* PORT108CR */
3261         PORTCR(109, 0xe605206d), /* PORT109CR */
3262
3263         PORTCR(110, 0xe605206e), /* PORT110CR */
3264         PORTCR(111, 0xe605206f), /* PORT111CR */
3265         PORTCR(112, 0xe6052070), /* PORT112CR */
3266         PORTCR(113, 0xe6052071), /* PORT113CR */
3267         PORTCR(114, 0xe6052072), /* PORT114CR */
3268         PORTCR(115, 0xe6052073), /* PORT115CR */
3269         PORTCR(116, 0xe6052074), /* PORT116CR */
3270         PORTCR(117, 0xe6052075), /* PORT117CR */
3271         PORTCR(118, 0xe6052076), /* PORT118CR */
3272
3273         PORTCR(128, 0xe6052080), /* PORT128CR */
3274         PORTCR(129, 0xe6052081), /* PORT129CR */
3275
3276         PORTCR(130, 0xe6052082), /* PORT130CR */
3277         PORTCR(131, 0xe6052083), /* PORT131CR */
3278         PORTCR(132, 0xe6052084), /* PORT132CR */
3279         PORTCR(133, 0xe6052085), /* PORT133CR */
3280         PORTCR(134, 0xe6052086), /* PORT134CR */
3281         PORTCR(135, 0xe6052087), /* PORT135CR */
3282         PORTCR(136, 0xe6052088), /* PORT136CR */
3283         PORTCR(137, 0xe6052089), /* PORT137CR */
3284         PORTCR(138, 0xe605208a), /* PORT138CR */
3285         PORTCR(139, 0xe605208b), /* PORT139CR */
3286
3287         PORTCR(140, 0xe605208c), /* PORT140CR */
3288         PORTCR(141, 0xe605208d), /* PORT141CR */
3289         PORTCR(142, 0xe605208e), /* PORT142CR */
3290         PORTCR(143, 0xe605208f), /* PORT143CR */
3291         PORTCR(144, 0xe6052090), /* PORT144CR */
3292         PORTCR(145, 0xe6052091), /* PORT145CR */
3293         PORTCR(146, 0xe6052092), /* PORT146CR */
3294         PORTCR(147, 0xe6052093), /* PORT147CR */
3295         PORTCR(148, 0xe6052094), /* PORT148CR */
3296         PORTCR(149, 0xe6052095), /* PORT149CR */
3297
3298         PORTCR(150, 0xe6052096), /* PORT150CR */
3299         PORTCR(151, 0xe6052097), /* PORT151CR */
3300         PORTCR(152, 0xe6052098), /* PORT152CR */
3301         PORTCR(153, 0xe6052099), /* PORT153CR */
3302         PORTCR(154, 0xe605209a), /* PORT154CR */
3303         PORTCR(155, 0xe605209b), /* PORT155CR */
3304         PORTCR(156, 0xe605209c), /* PORT156CR */
3305         PORTCR(157, 0xe605209d), /* PORT157CR */
3306         PORTCR(158, 0xe605209e), /* PORT158CR */
3307         PORTCR(159, 0xe605209f), /* PORT159CR */
3308
3309         PORTCR(160, 0xe60520a0), /* PORT160CR */
3310         PORTCR(161, 0xe60520a1), /* PORT161CR */
3311         PORTCR(162, 0xe60520a2), /* PORT162CR */
3312         PORTCR(163, 0xe60520a3), /* PORT163CR */
3313         PORTCR(164, 0xe60520a4), /* PORT164CR */
3314
3315         PORTCR(192, 0xe60520c0), /* PORT192CR */
3316         PORTCR(193, 0xe60520c1), /* PORT193CR */
3317         PORTCR(194, 0xe60520c2), /* PORT194CR */
3318         PORTCR(195, 0xe60520c3), /* PORT195CR */
3319         PORTCR(196, 0xe60520c4), /* PORT196CR */
3320         PORTCR(197, 0xe60520c5), /* PORT197CR */
3321         PORTCR(198, 0xe60520c6), /* PORT198CR */
3322         PORTCR(199, 0xe60520c7), /* PORT199CR */
3323
3324         PORTCR(200, 0xe60520c8), /* PORT200CR */
3325         PORTCR(201, 0xe60520c9), /* PORT201CR */
3326         PORTCR(202, 0xe60520ca), /* PORT202CR */
3327         PORTCR(203, 0xe60520cb), /* PORT203CR */
3328         PORTCR(204, 0xe60520cc), /* PORT204CR */
3329         PORTCR(205, 0xe60520cd), /* PORT205CR */
3330         PORTCR(206, 0xe60520ce), /* PORT206CR */
3331         PORTCR(207, 0xe60520cf), /* PORT207CR */
3332         PORTCR(208, 0xe60520d0), /* PORT208CR */
3333         PORTCR(209, 0xe60520d1), /* PORT209CR */
3334
3335         PORTCR(210, 0xe60520d2), /* PORT210CR */
3336         PORTCR(211, 0xe60520d3), /* PORT211CR */
3337         PORTCR(212, 0xe60520d4), /* PORT212CR */
3338         PORTCR(213, 0xe60520d5), /* PORT213CR */
3339         PORTCR(214, 0xe60520d6), /* PORT214CR */
3340         PORTCR(215, 0xe60520d7), /* PORT215CR */
3341         PORTCR(216, 0xe60520d8), /* PORT216CR */
3342         PORTCR(217, 0xe60520d9), /* PORT217CR */
3343         PORTCR(218, 0xe60520da), /* PORT218CR */
3344         PORTCR(219, 0xe60520db), /* PORT219CR */
3345
3346         PORTCR(220, 0xe60520dc), /* PORT220CR */
3347         PORTCR(221, 0xe60520dd), /* PORT221CR */
3348         PORTCR(222, 0xe60520de), /* PORT222CR */
3349         PORTCR(223, 0xe60520df), /* PORT223CR */
3350         PORTCR(224, 0xe60530e0), /* PORT224CR */
3351         PORTCR(225, 0xe60530e1), /* PORT225CR */
3352         PORTCR(226, 0xe60530e2), /* PORT226CR */
3353         PORTCR(227, 0xe60530e3), /* PORT227CR */
3354         PORTCR(228, 0xe60530e4), /* PORT228CR */
3355         PORTCR(229, 0xe60530e5), /* PORT229CR */
3356
3357         PORTCR(230, 0xe60530e6), /* PORT230CR */
3358         PORTCR(231, 0xe60530e7), /* PORT231CR */
3359         PORTCR(232, 0xe60530e8), /* PORT232CR */
3360         PORTCR(233, 0xe60530e9), /* PORT233CR */
3361         PORTCR(234, 0xe60530ea), /* PORT234CR */
3362         PORTCR(235, 0xe60530eb), /* PORT235CR */
3363         PORTCR(236, 0xe60530ec), /* PORT236CR */
3364         PORTCR(237, 0xe60530ed), /* PORT237CR */
3365         PORTCR(238, 0xe60530ee), /* PORT238CR */
3366         PORTCR(239, 0xe60530ef), /* PORT239CR */
3367
3368         PORTCR(240, 0xe60530f0), /* PORT240CR */
3369         PORTCR(241, 0xe60530f1), /* PORT241CR */
3370         PORTCR(242, 0xe60530f2), /* PORT242CR */
3371         PORTCR(243, 0xe60530f3), /* PORT243CR */
3372         PORTCR(244, 0xe60530f4), /* PORT244CR */
3373         PORTCR(245, 0xe60530f5), /* PORT245CR */
3374         PORTCR(246, 0xe60530f6), /* PORT246CR */
3375         PORTCR(247, 0xe60530f7), /* PORT247CR */
3376         PORTCR(248, 0xe60530f8), /* PORT248CR */
3377         PORTCR(249, 0xe60530f9), /* PORT249CR */
3378
3379         PORTCR(250, 0xe60530fa), /* PORT250CR */
3380         PORTCR(251, 0xe60530fb), /* PORT251CR */
3381         PORTCR(252, 0xe60530fc), /* PORT252CR */
3382         PORTCR(253, 0xe60530fd), /* PORT253CR */
3383         PORTCR(254, 0xe60530fe), /* PORT254CR */
3384         PORTCR(255, 0xe60530ff), /* PORT255CR */
3385         PORTCR(256, 0xe6053100), /* PORT256CR */
3386         PORTCR(257, 0xe6053101), /* PORT257CR */
3387         PORTCR(258, 0xe6053102), /* PORT258CR */
3388         PORTCR(259, 0xe6053103), /* PORT259CR */
3389
3390         PORTCR(260, 0xe6053104), /* PORT260CR */
3391         PORTCR(261, 0xe6053105), /* PORT261CR */
3392         PORTCR(262, 0xe6053106), /* PORT262CR */
3393         PORTCR(263, 0xe6053107), /* PORT263CR */
3394         PORTCR(264, 0xe6053108), /* PORT264CR */
3395         PORTCR(265, 0xe6053109), /* PORT265CR */
3396         PORTCR(266, 0xe605310a), /* PORT266CR */
3397         PORTCR(267, 0xe605310b), /* PORT267CR */
3398         PORTCR(268, 0xe605310c), /* PORT268CR */
3399         PORTCR(269, 0xe605310d), /* PORT269CR */
3400
3401         PORTCR(270, 0xe605310e), /* PORT270CR */
3402         PORTCR(271, 0xe605310f), /* PORT271CR */
3403         PORTCR(272, 0xe6053110), /* PORT272CR */
3404         PORTCR(273, 0xe6053111), /* PORT273CR */
3405         PORTCR(274, 0xe6053112), /* PORT274CR */
3406         PORTCR(275, 0xe6053113), /* PORT275CR */
3407         PORTCR(276, 0xe6053114), /* PORT276CR */
3408         PORTCR(277, 0xe6053115), /* PORT277CR */
3409         PORTCR(278, 0xe6053116), /* PORT278CR */
3410         PORTCR(279, 0xe6053117), /* PORT279CR */
3411
3412         PORTCR(280, 0xe6053118), /* PORT280CR */
3413         PORTCR(281, 0xe6053119), /* PORT281CR */
3414         PORTCR(282, 0xe605311a), /* PORT282CR */
3415
3416         PORTCR(288, 0xe6052120), /* PORT288CR */
3417         PORTCR(289, 0xe6052121), /* PORT289CR */
3418
3419         PORTCR(290, 0xe6052122), /* PORT290CR */
3420         PORTCR(291, 0xe6052123), /* PORT291CR */
3421         PORTCR(292, 0xe6052124), /* PORT292CR */
3422         PORTCR(293, 0xe6052125), /* PORT293CR */
3423         PORTCR(294, 0xe6052126), /* PORT294CR */
3424         PORTCR(295, 0xe6052127), /* PORT295CR */
3425         PORTCR(296, 0xe6052128), /* PORT296CR */
3426         PORTCR(297, 0xe6052129), /* PORT297CR */
3427         PORTCR(298, 0xe605212a), /* PORT298CR */
3428         PORTCR(299, 0xe605212b), /* PORT299CR */
3429
3430         PORTCR(300, 0xe605212c), /* PORT300CR */
3431         PORTCR(301, 0xe605212d), /* PORT301CR */
3432         PORTCR(302, 0xe605212e), /* PORT302CR */
3433         PORTCR(303, 0xe605212f), /* PORT303CR */
3434         PORTCR(304, 0xe6052130), /* PORT304CR */
3435         PORTCR(305, 0xe6052131), /* PORT305CR */
3436         PORTCR(306, 0xe6052132), /* PORT306CR */
3437         PORTCR(307, 0xe6052133), /* PORT307CR */
3438         PORTCR(308, 0xe6052134), /* PORT308CR */
3439         PORTCR(309, 0xe6052135), /* PORT309CR */
3440
3441         { PINMUX_CFG_REG("MSEL2CR", 0xe605801c, 32, 1) {
3442                         0, 0,
3443                         0, 0,
3444                         0, 0,
3445                         0, 0,
3446                         0, 0,
3447                         0, 0,
3448                         0, 0,
3449                         0, 0,
3450                         0, 0,
3451                         0, 0,
3452                         0, 0,
3453                         0, 0,
3454                         MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
3455                         MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
3456                         MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
3457                         MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
3458                         0, 0,
3459                         MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
3460                         MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
3461                         MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
3462                         MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
3463                         MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
3464                         MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
3465                         MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
3466                         MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
3467                         MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
3468                         MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
3469                         MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
3470                         MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
3471                         MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
3472                         MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
3473                         MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
3474                 }
3475         },
3476         { PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
3477                         0, 0,
3478                         0, 0,
3479                         0, 0,
3480                         MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
3481                         0, 0,
3482                         0, 0,
3483                         0, 0,
3484                         0, 0,
3485                         0, 0,
3486                         0, 0,
3487                         0, 0,
3488                         0, 0,
3489                         0, 0,
3490                         0, 0,
3491                         0, 0,
3492                         0, 0,
3493                         MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
3494                         0, 0,
3495                         0, 0,
3496                         0, 0,
3497                         MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
3498                         0, 0,
3499                         MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
3500                         0, 0,
3501                         0, 0,
3502                         MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
3503                         0, 0,
3504                         0, 0,
3505                         0, 0,
3506                         MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
3507                         0, 0,
3508                         0, 0,
3509                 }
3510         },
3511         { PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
3512                         0, 0,
3513                         0, 0,
3514                         MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
3515                         0, 0,
3516                         MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
3517                         MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
3518                         0, 0,
3519                         0, 0,
3520                         0, 0,
3521                         MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
3522                         MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
3523                         MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
3524                         MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
3525                         0, 0,
3526                         0, 0,
3527                         0, 0,
3528                         MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
3529                         0, 0,
3530                         MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
3531                         MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
3532                         MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
3533                         MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
3534                         MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
3535                         MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
3536                         MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
3537                         0, 0,
3538                         0, 0,
3539                         MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
3540                         0, 0,
3541                         0, 0,
3542                         MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
3543                         0, 0,
3544                 }
3545         },
3546         { },
3547 };
3548
3549 static const struct pinmux_data_reg pinmux_data_regs[] = {
3550         { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
3551                         PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3552                         PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3553                         PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3554                         PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3555                         PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3556                         PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3557                         PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3558                         PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3559         },
3560         { PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
3561                         PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3562                         PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3563                         PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3564                         PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3565                         PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3566                         PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3567                         PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3568                         PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3569         },
3570         { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055004, 32) {
3571                         PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3572                         PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3573                         PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3574                         PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3575                         PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3576                         PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3577                         PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3578                         PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3579         },
3580         { PINMUX_DATA_REG("PORTR127_096DR", 0xe6056000, 32) {
3581                         0, 0, 0, 0,
3582                         0, 0, 0, 0,
3583                         0, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3584                         PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3585                         PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3586                         PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3587                         PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3588                         PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3589         },
3590         { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056004, 32) {
3591                         PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3592                         PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3593                         PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3594                         PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3595                         PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3596                         PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3597                         PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3598                         PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3599         },
3600         { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056008, 32) {
3601                         0, 0, 0, 0,
3602                         0, 0, 0, 0,
3603                         0, 0, 0, 0,
3604                         0, 0, 0, 0,
3605                         0, 0, 0, 0,
3606                         0, 0, 0, 0,
3607                         0, 0, 0, PORT164_DATA,
3608                         PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3609         },
3610         { PINMUX_DATA_REG("PORTR223_192DR", 0xe605600C, 32) {
3611                         PORT223_DATA, PORT222_DATA, PORT221_DATA, PORT220_DATA,
3612                         PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
3613                         PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
3614                         PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
3615                         PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3616                         PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3617                         PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3618                         PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3619         },
3620         { PINMUX_DATA_REG("PORTU255_224DR", 0xe6057000, 32) {
3621                         PORT255_DATA, PORT254_DATA, PORT253_DATA, PORT252_DATA,
3622                         PORT251_DATA, PORT250_DATA, PORT249_DATA, PORT248_DATA,
3623                         PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
3624                         PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
3625                         PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
3626                         PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
3627                         PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
3628                         PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA }
3629         },
3630         { PINMUX_DATA_REG("PORTU287_256DR", 0xe6057004, 32) {
3631                         0, 0, 0, 0,
3632                         0, PORT282_DATA, PORT281_DATA, PORT280_DATA,
3633                         PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
3634                         PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
3635                         PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
3636                         PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
3637                         PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
3638                         PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA }
3639         },
3640         { PINMUX_DATA_REG("PORTR319_288DR", 0xe6056010, 32) {
3641                         0, 0, 0, 0,
3642                         0, 0, 0, 0,
3643                         0, 0, PORT309_DATA, PORT308_DATA,
3644                         PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
3645                         PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
3646                         PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
3647                         PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
3648                         PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA }
3649         },
3650         { },
3651 };
3652
3653 static const struct pinmux_irq pinmux_irqs[] = {
3654         PINMUX_IRQ(irq_pin(0), 11),
3655         PINMUX_IRQ(irq_pin(1), 10),
3656         PINMUX_IRQ(irq_pin(2), 149),
3657         PINMUX_IRQ(irq_pin(3), 224),
3658         PINMUX_IRQ(irq_pin(4), 159),
3659         PINMUX_IRQ(irq_pin(5), 227),
3660         PINMUX_IRQ(irq_pin(6), 147),
3661         PINMUX_IRQ(irq_pin(7), 150),
3662         PINMUX_IRQ(irq_pin(8), 223),
3663         PINMUX_IRQ(irq_pin(9), 56, 308),
3664         PINMUX_IRQ(irq_pin(10), 54),
3665         PINMUX_IRQ(irq_pin(11), 238),
3666         PINMUX_IRQ(irq_pin(12), 156),
3667         PINMUX_IRQ(irq_pin(13), 239),
3668         PINMUX_IRQ(irq_pin(14), 251),
3669         PINMUX_IRQ(irq_pin(15), 0),
3670         PINMUX_IRQ(irq_pin(16), 249),
3671         PINMUX_IRQ(irq_pin(17), 234),
3672         PINMUX_IRQ(irq_pin(18), 13),
3673         PINMUX_IRQ(irq_pin(19), 9),
3674         PINMUX_IRQ(irq_pin(20), 14),
3675         PINMUX_IRQ(irq_pin(21), 15),
3676         PINMUX_IRQ(irq_pin(22), 40),
3677         PINMUX_IRQ(irq_pin(23), 53),
3678         PINMUX_IRQ(irq_pin(24), 118),
3679         PINMUX_IRQ(irq_pin(25), 164),
3680         PINMUX_IRQ(irq_pin(26), 115),
3681         PINMUX_IRQ(irq_pin(27), 116),
3682         PINMUX_IRQ(irq_pin(28), 117),
3683         PINMUX_IRQ(irq_pin(29), 28),
3684         PINMUX_IRQ(irq_pin(30), 27),
3685         PINMUX_IRQ(irq_pin(31), 26),
3686 };
3687
3688 /* -----------------------------------------------------------------------------
3689  * VCCQ MC0 regulator
3690  */
3691
3692 static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
3693 {
3694         struct sh_pfc *pfc = reg->reg_data;
3695         void __iomem *addr = pfc->windows[1].virt + 4;
3696         unsigned long flags;
3697         u32 value;
3698
3699         spin_lock_irqsave(&pfc->lock, flags);
3700
3701         value = ioread32(addr);
3702
3703         if (enable)
3704                 value |= BIT(28);
3705         else
3706                 value &= ~BIT(28);
3707
3708         iowrite32(value, addr);
3709
3710         spin_unlock_irqrestore(&pfc->lock, flags);
3711 }
3712
3713 static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
3714 {
3715         sh73a0_vccq_mc0_endisable(reg, true);
3716         return 0;
3717 }
3718
3719 static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
3720 {
3721         sh73a0_vccq_mc0_endisable(reg, false);
3722         return 0;
3723 }
3724
3725 static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
3726 {
3727         struct sh_pfc *pfc = reg->reg_data;
3728         void __iomem *addr = pfc->windows[1].virt + 4;
3729         unsigned long flags;
3730         u32 value;
3731
3732         spin_lock_irqsave(&pfc->lock, flags);
3733         value = ioread32(addr);
3734         spin_unlock_irqrestore(&pfc->lock, flags);
3735
3736         return !!(value & BIT(28));
3737 }
3738
3739 static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
3740 {
3741         return 3300000;
3742 }
3743
3744 static struct regulator_ops sh73a0_vccq_mc0_ops = {
3745         .enable = sh73a0_vccq_mc0_enable,
3746         .disable = sh73a0_vccq_mc0_disable,
3747         .is_enabled = sh73a0_vccq_mc0_is_enabled,
3748         .get_voltage = sh73a0_vccq_mc0_get_voltage,
3749 };
3750
3751 static const struct regulator_desc sh73a0_vccq_mc0_desc = {
3752         .owner = THIS_MODULE,
3753         .name = "vccq_mc0",
3754         .type = REGULATOR_VOLTAGE,
3755         .ops = &sh73a0_vccq_mc0_ops,
3756 };
3757
3758 static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
3759         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
3760         REGULATOR_SUPPLY("vqmmc", "ee100000.sdhi"),
3761 };
3762
3763 static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
3764         .constraints = {
3765                 .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3766         },
3767         .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
3768         .consumer_supplies = sh73a0_vccq_mc0_consumers,
3769 };
3770
3771 /* -----------------------------------------------------------------------------
3772  * Pin bias
3773  */
3774
3775 #define PORTnCR_PULMD_OFF       (0 << 6)
3776 #define PORTnCR_PULMD_DOWN      (2 << 6)
3777 #define PORTnCR_PULMD_UP        (3 << 6)
3778 #define PORTnCR_PULMD_MASK      (3 << 6)
3779
3780 static const unsigned int sh73a0_portcr_offsets[] = {
3781         0x00000000, 0x00001000, 0x00001000, 0x00002000, 0x00002000,
3782         0x00002000, 0x00002000, 0x00003000, 0x00003000, 0x00002000,
3783 };
3784
3785 static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3786 {
3787         void __iomem *addr = pfc->windows->virt
3788                            + sh73a0_portcr_offsets[pin >> 5] + pin;
3789         u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3790
3791         switch (value) {
3792         case PORTnCR_PULMD_UP:
3793                 return PIN_CONFIG_BIAS_PULL_UP;
3794         case PORTnCR_PULMD_DOWN:
3795                 return PIN_CONFIG_BIAS_PULL_DOWN;
3796         case PORTnCR_PULMD_OFF:
3797         default:
3798                 return PIN_CONFIG_BIAS_DISABLE;
3799         }
3800 }
3801
3802 static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3803                                    unsigned int bias)
3804 {
3805         void __iomem *addr = pfc->windows->virt
3806                            + sh73a0_portcr_offsets[pin >> 5] + pin;
3807         u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3808
3809         switch (bias) {
3810         case PIN_CONFIG_BIAS_PULL_UP:
3811                 value |= PORTnCR_PULMD_UP;
3812                 break;
3813         case PIN_CONFIG_BIAS_PULL_DOWN:
3814                 value |= PORTnCR_PULMD_DOWN;
3815                 break;
3816         }
3817
3818         iowrite8(value, addr);
3819 }
3820
3821 /* -----------------------------------------------------------------------------
3822  * SoC information
3823  */
3824
3825 struct sh73a0_pinmux_data {
3826         struct regulator_dev *vccq_mc0;
3827 };
3828
3829 static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
3830 {
3831         struct sh73a0_pinmux_data *data;
3832         struct regulator_config cfg = { };
3833         int ret;
3834
3835         data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
3836         if (data == NULL)
3837                 return -ENOMEM;
3838
3839         cfg.dev = pfc->dev;
3840         cfg.init_data = &sh73a0_vccq_mc0_init_data;
3841         cfg.driver_data = pfc;
3842
3843         data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
3844         if (IS_ERR(data->vccq_mc0)) {
3845                 ret = PTR_ERR(data->vccq_mc0);
3846                 dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
3847                         ret);
3848                 return ret;
3849         }
3850
3851         pfc->soc_data = data;
3852
3853         return 0;
3854 }
3855
3856 static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
3857 {
3858         struct sh73a0_pinmux_data *data = pfc->soc_data;
3859
3860         regulator_unregister(data->vccq_mc0);
3861 }
3862
3863 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
3864         .init = sh73a0_pinmux_soc_init,
3865         .exit = sh73a0_pinmux_soc_exit,
3866         .get_bias = sh73a0_pinmux_get_bias,
3867         .set_bias = sh73a0_pinmux_set_bias,
3868 };
3869
3870 const struct sh_pfc_soc_info sh73a0_pinmux_info = {
3871         .name = "sh73a0_pfc",
3872         .ops = &sh73a0_pinmux_ops,
3873
3874         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
3875         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
3876         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
3877
3878         .pins = pinmux_pins,
3879         .nr_pins = ARRAY_SIZE(pinmux_pins),
3880         .groups = pinmux_groups,
3881         .nr_groups = ARRAY_SIZE(pinmux_groups),
3882         .functions = pinmux_functions,
3883         .nr_functions = ARRAY_SIZE(pinmux_functions),
3884
3885         .cfg_regs = pinmux_config_regs,
3886         .data_regs = pinmux_data_regs,
3887
3888         .gpio_data = pinmux_data,
3889         .gpio_data_size = ARRAY_SIZE(pinmux_data),
3890
3891         .gpio_irq = pinmux_irqs,
3892         .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3893 };