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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / pinctrl / spear / pinctrl-spear1310.c
blob1a8bbfec60ca7748242701c687b22b8d93b43b99
1 /*
2 * Driver for the ST Microelectronics SPEAr1310 pinmux
3 *
4 * Copyright (C) 2012 ST Microelectronics
5 * Viresh Kumar <viresh.linux@gmail.com>
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12 #include <linux/err.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include "pinctrl-spear.h"
18
19 #define DRIVER_NAME "spear1310-pinmux"
20
21 /* pins */
22 static const struct pinctrl_pin_desc spear1310_pins[] = {
23 SPEAR_PIN_0_TO_101,
24 SPEAR_PIN_102_TO_245,
25 };
26
27 /* registers */
28 #define PERIP_CFG 0x3B0
29 #define MCIF_SEL_SHIFT 5
30 #define MCIF_SEL_SD (0x1 << MCIF_SEL_SHIFT)
31 #define MCIF_SEL_CF (0x2 << MCIF_SEL_SHIFT)
32 #define MCIF_SEL_XD (0x3 << MCIF_SEL_SHIFT)
33 #define MCIF_SEL_MASK (0x3 << MCIF_SEL_SHIFT)
34
35 #define PCIE_SATA_CFG 0x3A4
36 #define PCIE_SATA2_SEL_PCIE (0 << 31)
37 #define PCIE_SATA1_SEL_PCIE (0 << 30)
38 #define PCIE_SATA0_SEL_PCIE (0 << 29)
39 #define PCIE_SATA2_SEL_SATA (1 << 31)
40 #define PCIE_SATA1_SEL_SATA (1 << 30)
41 #define PCIE_SATA0_SEL_SATA (1 << 29)
42 #define SATA2_CFG_TX_CLK_EN (1 << 27)
43 #define SATA2_CFG_RX_CLK_EN (1 << 26)
44 #define SATA2_CFG_POWERUP_RESET (1 << 25)
45 #define SATA2_CFG_PM_CLK_EN (1 << 24)
46 #define SATA1_CFG_TX_CLK_EN (1 << 23)
47 #define SATA1_CFG_RX_CLK_EN (1 << 22)
48 #define SATA1_CFG_POWERUP_RESET (1 << 21)
49 #define SATA1_CFG_PM_CLK_EN (1 << 20)
50 #define SATA0_CFG_TX_CLK_EN (1 << 19)
51 #define SATA0_CFG_RX_CLK_EN (1 << 18)
52 #define SATA0_CFG_POWERUP_RESET (1 << 17)
53 #define SATA0_CFG_PM_CLK_EN (1 << 16)
54 #define PCIE2_CFG_DEVICE_PRESENT (1 << 11)
55 #define PCIE2_CFG_POWERUP_RESET (1 << 10)
56 #define PCIE2_CFG_CORE_CLK_EN (1 << 9)
57 #define PCIE2_CFG_AUX_CLK_EN (1 << 8)
58 #define PCIE1_CFG_DEVICE_PRESENT (1 << 7)
59 #define PCIE1_CFG_POWERUP_RESET (1 << 6)
60 #define PCIE1_CFG_CORE_CLK_EN (1 << 5)
61 #define PCIE1_CFG_AUX_CLK_EN (1 << 4)
62 #define PCIE0_CFG_DEVICE_PRESENT (1 << 3)
63 #define PCIE0_CFG_POWERUP_RESET (1 << 2)
64 #define PCIE0_CFG_CORE_CLK_EN (1 << 1)
65 #define PCIE0_CFG_AUX_CLK_EN (1 << 0)
66
67 #define PAD_FUNCTION_EN_0 0x650
68 #define PMX_UART0_MASK (1 << 1)
69 #define PMX_I2C0_MASK (1 << 2)
70 #define PMX_I2S0_MASK (1 << 3)
71 #define PMX_SSP0_MASK (1 << 4)
72 #define PMX_CLCD1_MASK (1 << 5)
73 #define PMX_EGPIO00_MASK (1 << 6)
74 #define PMX_EGPIO01_MASK (1 << 7)
75 #define PMX_EGPIO02_MASK (1 << 8)
76 #define PMX_EGPIO03_MASK (1 << 9)
77 #define PMX_EGPIO04_MASK (1 << 10)
78 #define PMX_EGPIO05_MASK (1 << 11)
79 #define PMX_EGPIO06_MASK (1 << 12)
80 #define PMX_EGPIO07_MASK (1 << 13)
81 #define PMX_EGPIO08_MASK (1 << 14)
82 #define PMX_EGPIO09_MASK (1 << 15)
83 #define PMX_SMI_MASK (1 << 16)
84 #define PMX_NAND8_MASK (1 << 17)
85 #define PMX_GMIICLK_MASK (1 << 18)
86 #define PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK (1 << 19)
87 #define PMX_RXCLK_RDV_TXEN_D03_MASK (1 << 20)
88 #define PMX_GMIID47_MASK (1 << 21)
89 #define PMX_MDC_MDIO_MASK (1 << 22)
90 #define PMX_MCI_DATA8_15_MASK (1 << 23)
91 #define PMX_NFAD23_MASK (1 << 24)
92 #define PMX_NFAD24_MASK (1 << 25)
93 #define PMX_NFAD25_MASK (1 << 26)
94 #define PMX_NFCE3_MASK (1 << 27)
95 #define PMX_NFWPRT3_MASK (1 << 28)
96 #define PMX_NFRSTPWDWN0_MASK (1 << 29)
97 #define PMX_NFRSTPWDWN1_MASK (1 << 30)
98 #define PMX_NFRSTPWDWN2_MASK (1 << 31)
99
100 #define PAD_FUNCTION_EN_1 0x654
101 #define PMX_NFRSTPWDWN3_MASK (1 << 0)
102 #define PMX_SMINCS2_MASK (1 << 1)
103 #define PMX_SMINCS3_MASK (1 << 2)
104 #define PMX_CLCD2_MASK (1 << 3)
105 #define PMX_KBD_ROWCOL68_MASK (1 << 4)
106 #define PMX_EGPIO10_MASK (1 << 5)
107 #define PMX_EGPIO11_MASK (1 << 6)
108 #define PMX_EGPIO12_MASK (1 << 7)
109 #define PMX_EGPIO13_MASK (1 << 8)
110 #define PMX_EGPIO14_MASK (1 << 9)
111 #define PMX_EGPIO15_MASK (1 << 10)
112 #define PMX_UART0_MODEM_MASK (1 << 11)
113 #define PMX_GPT0_TMR0_MASK (1 << 12)
114 #define PMX_GPT0_TMR1_MASK (1 << 13)
115 #define PMX_GPT1_TMR0_MASK (1 << 14)
116 #define PMX_GPT1_TMR1_MASK (1 << 15)
117 #define PMX_I2S1_MASK (1 << 16)
118 #define PMX_KBD_ROWCOL25_MASK (1 << 17)
119 #define PMX_NFIO8_15_MASK (1 << 18)
120 #define PMX_KBD_COL1_MASK (1 << 19)
121 #define PMX_NFCE1_MASK (1 << 20)
122 #define PMX_KBD_COL0_MASK (1 << 21)
123 #define PMX_NFCE2_MASK (1 << 22)
124 #define PMX_KBD_ROW1_MASK (1 << 23)
125 #define PMX_NFWPRT1_MASK (1 << 24)
126 #define PMX_KBD_ROW0_MASK (1 << 25)
127 #define PMX_NFWPRT2_MASK (1 << 26)
128 #define PMX_MCIDATA0_MASK (1 << 27)
129 #define PMX_MCIDATA1_MASK (1 << 28)
130 #define PMX_MCIDATA2_MASK (1 << 29)
131 #define PMX_MCIDATA3_MASK (1 << 30)
132 #define PMX_MCIDATA4_MASK (1 << 31)
133
134 #define PAD_FUNCTION_EN_2 0x658
135 #define PMX_MCIDATA5_MASK (1 << 0)
136 #define PMX_MCIDATA6_MASK (1 << 1)
137 #define PMX_MCIDATA7_MASK (1 << 2)
138 #define PMX_MCIDATA1SD_MASK (1 << 3)
139 #define PMX_MCIDATA2SD_MASK (1 << 4)
140 #define PMX_MCIDATA3SD_MASK (1 << 5)
141 #define PMX_MCIADDR0ALE_MASK (1 << 6)
142 #define PMX_MCIADDR1CLECLK_MASK (1 << 7)
143 #define PMX_MCIADDR2_MASK (1 << 8)
144 #define PMX_MCICECF_MASK (1 << 9)
145 #define PMX_MCICEXD_MASK (1 << 10)
146 #define PMX_MCICESDMMC_MASK (1 << 11)
147 #define PMX_MCICDCF1_MASK (1 << 12)
148 #define PMX_MCICDCF2_MASK (1 << 13)
149 #define PMX_MCICDXD_MASK (1 << 14)
150 #define PMX_MCICDSDMMC_MASK (1 << 15)
151 #define PMX_MCIDATADIR_MASK (1 << 16)
152 #define PMX_MCIDMARQWP_MASK (1 << 17)
153 #define PMX_MCIIORDRE_MASK (1 << 18)
154 #define PMX_MCIIOWRWE_MASK (1 << 19)
155 #define PMX_MCIRESETCF_MASK (1 << 20)
156 #define PMX_MCICS0CE_MASK (1 << 21)
157 #define PMX_MCICFINTR_MASK (1 << 22)
158 #define PMX_MCIIORDY_MASK (1 << 23)
159 #define PMX_MCICS1_MASK (1 << 24)
160 #define PMX_MCIDMAACK_MASK (1 << 25)
161 #define PMX_MCISDCMD_MASK (1 << 26)
162 #define PMX_MCILEDS_MASK (1 << 27)
163 #define PMX_TOUCH_XY_MASK (1 << 28)
164 #define PMX_SSP0_CS0_MASK (1 << 29)
165 #define PMX_SSP0_CS1_2_MASK (1 << 30)
166
167 #define PAD_DIRECTION_SEL_0 0x65C
168 #define PAD_DIRECTION_SEL_1 0x660
169 #define PAD_DIRECTION_SEL_2 0x664
170
171 /* combined macros */
172 #define PMX_GMII_MASK (PMX_GMIICLK_MASK | \
173 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
174 PMX_RXCLK_RDV_TXEN_D03_MASK | \
175 PMX_GMIID47_MASK | PMX_MDC_MDIO_MASK)
176
177 #define PMX_EGPIO_0_GRP_MASK (PMX_EGPIO00_MASK | PMX_EGPIO01_MASK | \
178 PMX_EGPIO02_MASK | \
179 PMX_EGPIO03_MASK | PMX_EGPIO04_MASK | \
180 PMX_EGPIO05_MASK | PMX_EGPIO06_MASK | \
181 PMX_EGPIO07_MASK | PMX_EGPIO08_MASK | \
182 PMX_EGPIO09_MASK)
183 #define PMX_EGPIO_1_GRP_MASK (PMX_EGPIO10_MASK | PMX_EGPIO11_MASK | \
184 PMX_EGPIO12_MASK | PMX_EGPIO13_MASK | \
185 PMX_EGPIO14_MASK | PMX_EGPIO15_MASK)
186
187 #define PMX_KEYBOARD_6X6_MASK (PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
188 PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL0_MASK | \
189 PMX_KBD_COL1_MASK)
190
191 #define PMX_NAND8BIT_0_MASK (PMX_NAND8_MASK | PMX_NFAD23_MASK | \
192 PMX_NFAD24_MASK | PMX_NFAD25_MASK | \
193 PMX_NFWPRT3_MASK | PMX_NFRSTPWDWN0_MASK | \
194 PMX_NFRSTPWDWN1_MASK | PMX_NFRSTPWDWN2_MASK | \
195 PMX_NFCE3_MASK)
196 #define PMX_NAND8BIT_1_MASK PMX_NFRSTPWDWN3_MASK
197
198 #define PMX_NAND16BIT_1_MASK (PMX_KBD_ROWCOL25_MASK | PMX_NFIO8_15_MASK)
199 #define PMX_NAND_4CHIPS_MASK (PMX_NFCE1_MASK | PMX_NFCE2_MASK | \
200 PMX_NFWPRT1_MASK | PMX_NFWPRT2_MASK | \
201 PMX_KBD_ROW0_MASK | PMX_KBD_ROW1_MASK | \
202 PMX_KBD_COL0_MASK | PMX_KBD_COL1_MASK)
203
204 #define PMX_MCIFALL_1_MASK 0xF8000000
205 #define PMX_MCIFALL_2_MASK 0x0FFFFFFF
206
207 #define PMX_PCI_REG1_MASK (PMX_SMINCS2_MASK | PMX_SMINCS3_MASK | \
208 PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK | \
209 PMX_EGPIO_1_GRP_MASK | PMX_GPT0_TMR0_MASK | \
210 PMX_GPT0_TMR1_MASK | PMX_GPT1_TMR0_MASK | \
211 PMX_GPT1_TMR1_MASK | PMX_I2S1_MASK | \
212 PMX_NFCE2_MASK)
213 #define PMX_PCI_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
214 PMX_SSP0_CS1_2_MASK)
215
216 #define PMX_SMII_0_1_2_MASK (PMX_CLCD2_MASK | PMX_KBD_ROWCOL68_MASK)
217 #define PMX_RGMII_REG0_MASK (PMX_MCI_DATA8_15_MASK | \
218 PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK | \
219 PMX_GMIID47_MASK)
220 #define PMX_RGMII_REG1_MASK (PMX_KBD_ROWCOL68_MASK | PMX_EGPIO_1_GRP_MASK |\
221 PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK | \
222 PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK)
223 #define PMX_RGMII_REG2_MASK (PMX_TOUCH_XY_MASK | PMX_SSP0_CS0_MASK | \
224 PMX_SSP0_CS1_2_MASK)
225
226 #define PCIE_CFG_VAL(x) (PCIE_SATA##x##_SEL_PCIE | \
227 PCIE##x##_CFG_AUX_CLK_EN | \
228 PCIE##x##_CFG_CORE_CLK_EN | \
229 PCIE##x##_CFG_POWERUP_RESET | \
230 PCIE##x##_CFG_DEVICE_PRESENT)
231 #define SATA_CFG_VAL(x) (PCIE_SATA##x##_SEL_SATA | \
232 SATA##x##_CFG_PM_CLK_EN | \
233 SATA##x##_CFG_POWERUP_RESET | \
234 SATA##x##_CFG_RX_CLK_EN | \
235 SATA##x##_CFG_TX_CLK_EN)
236
237 /* Pad multiplexing for i2c0 device */
238 static const unsigned i2c0_pins[] = { 102, 103 };
239 static struct spear_muxreg i2c0_muxreg[] = {
240 {
241 .reg = PAD_FUNCTION_EN_0,
242 .mask = PMX_I2C0_MASK,
243 .val = PMX_I2C0_MASK,
244 }, {
245 .reg = PAD_DIRECTION_SEL_0,
246 .mask = PMX_I2C0_MASK,
247 .val = PMX_I2C0_MASK,
248 },
249 };
250
251 static struct spear_modemux i2c0_modemux[] = {
252 {
253 .muxregs = i2c0_muxreg,
254 .nmuxregs = ARRAY_SIZE(i2c0_muxreg),
255 },
256 };
257
258 static struct spear_pingroup i2c0_pingroup = {
259 .name = "i2c0_grp",
260 .pins = i2c0_pins,
261 .npins = ARRAY_SIZE(i2c0_pins),
262 .modemuxs = i2c0_modemux,
263 .nmodemuxs = ARRAY_SIZE(i2c0_modemux),
264 };
265
266 static const char *const i2c0_grps[] = { "i2c0_grp" };
267 static struct spear_function i2c0_function = {
268 .name = "i2c0",
269 .groups = i2c0_grps,
270 .ngroups = ARRAY_SIZE(i2c0_grps),
271 };
272
273 /* Pad multiplexing for ssp0 device */
274 static const unsigned ssp0_pins[] = { 109, 110, 111, 112 };
275 static struct spear_muxreg ssp0_muxreg[] = {
276 {
277 .reg = PAD_FUNCTION_EN_0,
278 .mask = PMX_SSP0_MASK,
279 .val = PMX_SSP0_MASK,
280 }, {
281 .reg = PAD_DIRECTION_SEL_0,
282 .mask = PMX_SSP0_MASK,
283 .val = PMX_SSP0_MASK,
284 },
285 };
286
287 static struct spear_modemux ssp0_modemux[] = {
288 {
289 .muxregs = ssp0_muxreg,
290 .nmuxregs = ARRAY_SIZE(ssp0_muxreg),
291 },
292 };
293
294 static struct spear_pingroup ssp0_pingroup = {
295 .name = "ssp0_grp",
296 .pins = ssp0_pins,
297 .npins = ARRAY_SIZE(ssp0_pins),
298 .modemuxs = ssp0_modemux,
299 .nmodemuxs = ARRAY_SIZE(ssp0_modemux),
300 };
301
302 /* Pad multiplexing for ssp0_cs0 device */
303 static const unsigned ssp0_cs0_pins[] = { 96 };
304 static struct spear_muxreg ssp0_cs0_muxreg[] = {
305 {
306 .reg = PAD_FUNCTION_EN_2,
307 .mask = PMX_SSP0_CS0_MASK,
308 .val = PMX_SSP0_CS0_MASK,
309 }, {
310 .reg = PAD_DIRECTION_SEL_2,
311 .mask = PMX_SSP0_CS0_MASK,
312 .val = PMX_SSP0_CS0_MASK,
313 },
314 };
315
316 static struct spear_modemux ssp0_cs0_modemux[] = {
317 {
318 .muxregs = ssp0_cs0_muxreg,
319 .nmuxregs = ARRAY_SIZE(ssp0_cs0_muxreg),
320 },
321 };
322
323 static struct spear_pingroup ssp0_cs0_pingroup = {
324 .name = "ssp0_cs0_grp",
325 .pins = ssp0_cs0_pins,
326 .npins = ARRAY_SIZE(ssp0_cs0_pins),
327 .modemuxs = ssp0_cs0_modemux,
328 .nmodemuxs = ARRAY_SIZE(ssp0_cs0_modemux),
329 };
330
331 /* ssp0_cs1_2 device */
332 static const unsigned ssp0_cs1_2_pins[] = { 94, 95 };
333 static struct spear_muxreg ssp0_cs1_2_muxreg[] = {
334 {
335 .reg = PAD_FUNCTION_EN_2,
336 .mask = PMX_SSP0_CS1_2_MASK,
337 .val = PMX_SSP0_CS1_2_MASK,
338 }, {
339 .reg = PAD_DIRECTION_SEL_2,
340 .mask = PMX_SSP0_CS1_2_MASK,
341 .val = PMX_SSP0_CS1_2_MASK,
342 },
343 };
344
345 static struct spear_modemux ssp0_cs1_2_modemux[] = {
346 {
347 .muxregs = ssp0_cs1_2_muxreg,
348 .nmuxregs = ARRAY_SIZE(ssp0_cs1_2_muxreg),
349 },
350 };
351
352 static struct spear_pingroup ssp0_cs1_2_pingroup = {
353 .name = "ssp0_cs1_2_grp",
354 .pins = ssp0_cs1_2_pins,
355 .npins = ARRAY_SIZE(ssp0_cs1_2_pins),
356 .modemuxs = ssp0_cs1_2_modemux,
357 .nmodemuxs = ARRAY_SIZE(ssp0_cs1_2_modemux),
358 };
359
360 static const char *const ssp0_grps[] = { "ssp0_grp", "ssp0_cs0_grp",
361 "ssp0_cs1_2_grp" };
362 static struct spear_function ssp0_function = {
363 .name = "ssp0",
364 .groups = ssp0_grps,
365 .ngroups = ARRAY_SIZE(ssp0_grps),
366 };
367
368 /* Pad multiplexing for i2s0 device */
369 static const unsigned i2s0_pins[] = { 104, 105, 106, 107, 108 };
370 static struct spear_muxreg i2s0_muxreg[] = {
371 {
372 .reg = PAD_FUNCTION_EN_0,
373 .mask = PMX_I2S0_MASK,
374 .val = PMX_I2S0_MASK,
375 }, {
376 .reg = PAD_DIRECTION_SEL_0,
377 .mask = PMX_I2S0_MASK,
378 .val = PMX_I2S0_MASK,
379 },
380 };
381
382 static struct spear_modemux i2s0_modemux[] = {
383 {
384 .muxregs = i2s0_muxreg,
385 .nmuxregs = ARRAY_SIZE(i2s0_muxreg),
386 },
387 };
388
389 static struct spear_pingroup i2s0_pingroup = {
390 .name = "i2s0_grp",
391 .pins = i2s0_pins,
392 .npins = ARRAY_SIZE(i2s0_pins),
393 .modemuxs = i2s0_modemux,
394 .nmodemuxs = ARRAY_SIZE(i2s0_modemux),
395 };
396
397 static const char *const i2s0_grps[] = { "i2s0_grp" };
398 static struct spear_function i2s0_function = {
399 .name = "i2s0",
400 .groups = i2s0_grps,
401 .ngroups = ARRAY_SIZE(i2s0_grps),
402 };
403
404 /* Pad multiplexing for i2s1 device */
405 static const unsigned i2s1_pins[] = { 0, 1, 2, 3 };
406 static struct spear_muxreg i2s1_muxreg[] = {
407 {
408 .reg = PAD_FUNCTION_EN_1,
409 .mask = PMX_I2S1_MASK,
410 .val = PMX_I2S1_MASK,
411 }, {
412 .reg = PAD_DIRECTION_SEL_1,
413 .mask = PMX_I2S1_MASK,
414 .val = PMX_I2S1_MASK,
415 },
416 };
417
418 static struct spear_modemux i2s1_modemux[] = {
419 {
420 .muxregs = i2s1_muxreg,
421 .nmuxregs = ARRAY_SIZE(i2s1_muxreg),
422 },
423 };
424
425 static struct spear_pingroup i2s1_pingroup = {
426 .name = "i2s1_grp",
427 .pins = i2s1_pins,
428 .npins = ARRAY_SIZE(i2s1_pins),
429 .modemuxs = i2s1_modemux,
430 .nmodemuxs = ARRAY_SIZE(i2s1_modemux),
431 };
432
433 static const char *const i2s1_grps[] = { "i2s1_grp" };
434 static struct spear_function i2s1_function = {
435 .name = "i2s1",
436 .groups = i2s1_grps,
437 .ngroups = ARRAY_SIZE(i2s1_grps),
438 };
439
440 /* Pad multiplexing for clcd device */
441 static const unsigned clcd_pins[] = { 113, 114, 115, 116, 117, 118, 119, 120,
442 121, 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134,
443 135, 136, 137, 138, 139, 140, 141, 142 };
444 static struct spear_muxreg clcd_muxreg[] = {
445 {
446 .reg = PAD_FUNCTION_EN_0,
447 .mask = PMX_CLCD1_MASK,
448 .val = PMX_CLCD1_MASK,
449 }, {
450 .reg = PAD_DIRECTION_SEL_0,
451 .mask = PMX_CLCD1_MASK,
452 .val = PMX_CLCD1_MASK,
453 },
454 };
455
456 static struct spear_modemux clcd_modemux[] = {
457 {
458 .muxregs = clcd_muxreg,
459 .nmuxregs = ARRAY_SIZE(clcd_muxreg),
460 },
461 };
462
463 static struct spear_pingroup clcd_pingroup = {
464 .name = "clcd_grp",
465 .pins = clcd_pins,
466 .npins = ARRAY_SIZE(clcd_pins),
467 .modemuxs = clcd_modemux,
468 .nmodemuxs = ARRAY_SIZE(clcd_modemux),
469 };
470
471 static const unsigned clcd_high_res_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37,
472 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53 };
473 static struct spear_muxreg clcd_high_res_muxreg[] = {
474 {
475 .reg = PAD_FUNCTION_EN_1,
476 .mask = PMX_CLCD2_MASK,
477 .val = PMX_CLCD2_MASK,
478 }, {
479 .reg = PAD_DIRECTION_SEL_1,
480 .mask = PMX_CLCD2_MASK,
481 .val = PMX_CLCD2_MASK,
482 },
483 };
484
485 static struct spear_modemux clcd_high_res_modemux[] = {
486 {
487 .muxregs = clcd_high_res_muxreg,
488 .nmuxregs = ARRAY_SIZE(clcd_high_res_muxreg),
489 },
490 };
491
492 static struct spear_pingroup clcd_high_res_pingroup = {
493 .name = "clcd_high_res_grp",
494 .pins = clcd_high_res_pins,
495 .npins = ARRAY_SIZE(clcd_high_res_pins),
496 .modemuxs = clcd_high_res_modemux,
497 .nmodemuxs = ARRAY_SIZE(clcd_high_res_modemux),
498 };
499
500 static const char *const clcd_grps[] = { "clcd_grp", "clcd_high_res_grp" };
501 static struct spear_function clcd_function = {
502 .name = "clcd",
503 .groups = clcd_grps,
504 .ngroups = ARRAY_SIZE(clcd_grps),
505 };
506
507 static const unsigned arm_gpio_pins[] = { 18, 19, 20, 21, 22, 23, 143, 144, 145,
508 146, 147, 148, 149, 150, 151, 152 };
509 static struct spear_muxreg arm_gpio_muxreg[] = {
510 {
511 .reg = PAD_FUNCTION_EN_0,
512 .mask = PMX_EGPIO_0_GRP_MASK,
513 .val = PMX_EGPIO_0_GRP_MASK,
514 }, {
515 .reg = PAD_FUNCTION_EN_1,
516 .mask = PMX_EGPIO_1_GRP_MASK,
517 .val = PMX_EGPIO_1_GRP_MASK,
518 }, {
519 .reg = PAD_DIRECTION_SEL_0,
520 .mask = PMX_EGPIO_0_GRP_MASK,
521 .val = PMX_EGPIO_0_GRP_MASK,
522 }, {
523 .reg = PAD_DIRECTION_SEL_1,
524 .mask = PMX_EGPIO_1_GRP_MASK,
525 .val = PMX_EGPIO_1_GRP_MASK,
526 },
527 };
528
529 static struct spear_modemux arm_gpio_modemux[] = {
530 {
531 .muxregs = arm_gpio_muxreg,
532 .nmuxregs = ARRAY_SIZE(arm_gpio_muxreg),
533 },
534 };
535
536 static struct spear_pingroup arm_gpio_pingroup = {
537 .name = "arm_gpio_grp",
538 .pins = arm_gpio_pins,
539 .npins = ARRAY_SIZE(arm_gpio_pins),
540 .modemuxs = arm_gpio_modemux,
541 .nmodemuxs = ARRAY_SIZE(arm_gpio_modemux),
542 };
543
544 static const char *const arm_gpio_grps[] = { "arm_gpio_grp" };
545 static struct spear_function arm_gpio_function = {
546 .name = "arm_gpio",
547 .groups = arm_gpio_grps,
548 .ngroups = ARRAY_SIZE(arm_gpio_grps),
549 };
550
551 /* Pad multiplexing for smi 2 chips device */
552 static const unsigned smi_2_chips_pins[] = { 153, 154, 155, 156, 157 };
553 static struct spear_muxreg smi_2_chips_muxreg[] = {
554 {
555 .reg = PAD_FUNCTION_EN_0,
556 .mask = PMX_SMI_MASK,
557 .val = PMX_SMI_MASK,
558 }, {
559 .reg = PAD_DIRECTION_SEL_0,
560 .mask = PMX_SMI_MASK,
561 .val = PMX_SMI_MASK,
562 },
563 };
564
565 static struct spear_modemux smi_2_chips_modemux[] = {
566 {
567 .muxregs = smi_2_chips_muxreg,
568 .nmuxregs = ARRAY_SIZE(smi_2_chips_muxreg),
569 },
570 };
571
572 static struct spear_pingroup smi_2_chips_pingroup = {
573 .name = "smi_2_chips_grp",
574 .pins = smi_2_chips_pins,
575 .npins = ARRAY_SIZE(smi_2_chips_pins),
576 .modemuxs = smi_2_chips_modemux,
577 .nmodemuxs = ARRAY_SIZE(smi_2_chips_modemux),
578 };
579
580 static const unsigned smi_4_chips_pins[] = { 54, 55 };
581 static struct spear_muxreg smi_4_chips_muxreg[] = {
582 {
583 .reg = PAD_FUNCTION_EN_0,
584 .mask = PMX_SMI_MASK,
585 .val = PMX_SMI_MASK,
586 }, {
587 .reg = PAD_FUNCTION_EN_1,
588 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
589 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
590 }, {
591 .reg = PAD_DIRECTION_SEL_0,
592 .mask = PMX_SMI_MASK,
593 .val = PMX_SMI_MASK,
594 }, {
595 .reg = PAD_DIRECTION_SEL_1,
596 .mask = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
597 .val = PMX_SMINCS2_MASK | PMX_SMINCS3_MASK,
598 },
599 };
600
601 static struct spear_modemux smi_4_chips_modemux[] = {
602 {
603 .muxregs = smi_4_chips_muxreg,
604 .nmuxregs = ARRAY_SIZE(smi_4_chips_muxreg),
605 },
606 };
607
608 static struct spear_pingroup smi_4_chips_pingroup = {
609 .name = "smi_4_chips_grp",
610 .pins = smi_4_chips_pins,
611 .npins = ARRAY_SIZE(smi_4_chips_pins),
612 .modemuxs = smi_4_chips_modemux,
613 .nmodemuxs = ARRAY_SIZE(smi_4_chips_modemux),
614 };
615
616 static const char *const smi_grps[] = { "smi_2_chips_grp", "smi_4_chips_grp" };
617 static struct spear_function smi_function = {
618 .name = "smi",
619 .groups = smi_grps,
620 .ngroups = ARRAY_SIZE(smi_grps),
621 };
622
623 /* Pad multiplexing for gmii device */
624 static const unsigned gmii_pins[] = { 173, 174, 175, 176, 177, 178, 179, 180,
625 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194,
626 195, 196, 197, 198, 199, 200 };
627 static struct spear_muxreg gmii_muxreg[] = {
628 {
629 .reg = PAD_FUNCTION_EN_0,
630 .mask = PMX_GMII_MASK,
631 .val = PMX_GMII_MASK,
632 }, {
633 .reg = PAD_DIRECTION_SEL_0,
634 .mask = PMX_GMII_MASK,
635 .val = PMX_GMII_MASK,
636 },
637 };
638
639 static struct spear_modemux gmii_modemux[] = {
640 {
641 .muxregs = gmii_muxreg,
642 .nmuxregs = ARRAY_SIZE(gmii_muxreg),
643 },
644 };
645
646 static struct spear_pingroup gmii_pingroup = {
647 .name = "gmii_grp",
648 .pins = gmii_pins,
649 .npins = ARRAY_SIZE(gmii_pins),
650 .modemuxs = gmii_modemux,
651 .nmodemuxs = ARRAY_SIZE(gmii_modemux),
652 };
653
654 static const char *const gmii_grps[] = { "gmii_grp" };
655 static struct spear_function gmii_function = {
656 .name = "gmii",
657 .groups = gmii_grps,
658 .ngroups = ARRAY_SIZE(gmii_grps),
659 };
660
661 /* Pad multiplexing for rgmii device */
662 static const unsigned rgmii_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27,
663 28, 29, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 175,
664 180, 181, 182, 183, 185, 188, 193, 194, 195, 196, 197, 198, 211, 212 };
665 static struct spear_muxreg rgmii_muxreg[] = {
666 {
667 .reg = PAD_FUNCTION_EN_0,
668 .mask = PMX_RGMII_REG0_MASK,
669 .val = 0,
670 }, {
671 .reg = PAD_FUNCTION_EN_1,
672 .mask = PMX_RGMII_REG1_MASK,
673 .val = 0,
674 }, {
675 .reg = PAD_FUNCTION_EN_2,
676 .mask = PMX_RGMII_REG2_MASK,
677 .val = 0,
678 }, {
679 .reg = PAD_DIRECTION_SEL_0,
680 .mask = PMX_RGMII_REG0_MASK,
681 .val = PMX_RGMII_REG0_MASK,
682 }, {
683 .reg = PAD_DIRECTION_SEL_1,
684 .mask = PMX_RGMII_REG1_MASK,
685 .val = PMX_RGMII_REG1_MASK,
686 }, {
687 .reg = PAD_DIRECTION_SEL_2,
688 .mask = PMX_RGMII_REG2_MASK,
689 .val = PMX_RGMII_REG2_MASK,
690 },
691 };
692
693 static struct spear_modemux rgmii_modemux[] = {
694 {
695 .muxregs = rgmii_muxreg,
696 .nmuxregs = ARRAY_SIZE(rgmii_muxreg),
697 },
698 };
699
700 static struct spear_pingroup rgmii_pingroup = {
701 .name = "rgmii_grp",
702 .pins = rgmii_pins,
703 .npins = ARRAY_SIZE(rgmii_pins),
704 .modemuxs = rgmii_modemux,
705 .nmodemuxs = ARRAY_SIZE(rgmii_modemux),
706 };
707
708 static const char *const rgmii_grps[] = { "rgmii_grp" };
709 static struct spear_function rgmii_function = {
710 .name = "rgmii",
711 .groups = rgmii_grps,
712 .ngroups = ARRAY_SIZE(rgmii_grps),
713 };
714
715 /* Pad multiplexing for smii_0_1_2 device */
716 static const unsigned smii_0_1_2_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32,
717 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,
718 51, 52, 53, 54, 55 };
719 static struct spear_muxreg smii_0_1_2_muxreg[] = {
720 {
721 .reg = PAD_FUNCTION_EN_1,
722 .mask = PMX_SMII_0_1_2_MASK,
723 .val = 0,
724 }, {
725 .reg = PAD_DIRECTION_SEL_1,
726 .mask = PMX_SMII_0_1_2_MASK,
727 .val = PMX_SMII_0_1_2_MASK,
728 },
729 };
730
731 static struct spear_modemux smii_0_1_2_modemux[] = {
732 {
733 .muxregs = smii_0_1_2_muxreg,
734 .nmuxregs = ARRAY_SIZE(smii_0_1_2_muxreg),
735 },
736 };
737
738 static struct spear_pingroup smii_0_1_2_pingroup = {
739 .name = "smii_0_1_2_grp",
740 .pins = smii_0_1_2_pins,
741 .npins = ARRAY_SIZE(smii_0_1_2_pins),
742 .modemuxs = smii_0_1_2_modemux,
743 .nmodemuxs = ARRAY_SIZE(smii_0_1_2_modemux),
744 };
745
746 static const char *const smii_0_1_2_grps[] = { "smii_0_1_2_grp" };
747 static struct spear_function smii_0_1_2_function = {
748 .name = "smii_0_1_2",
749 .groups = smii_0_1_2_grps,
750 .ngroups = ARRAY_SIZE(smii_0_1_2_grps),
751 };
752
753 /* Pad multiplexing for ras_mii_txclk device */
754 static const unsigned ras_mii_txclk_pins[] = { 98, 99 };
755 static struct spear_muxreg ras_mii_txclk_muxreg[] = {
756 {
757 .reg = PAD_FUNCTION_EN_1,
758 .mask = PMX_NFCE2_MASK,
759 .val = 0,
760 }, {
761 .reg = PAD_DIRECTION_SEL_1,
762 .mask = PMX_NFCE2_MASK,
763 .val = PMX_NFCE2_MASK,
764 },
765 };
766
767 static struct spear_modemux ras_mii_txclk_modemux[] = {
768 {
769 .muxregs = ras_mii_txclk_muxreg,
770 .nmuxregs = ARRAY_SIZE(ras_mii_txclk_muxreg),
771 },
772 };
773
774 static struct spear_pingroup ras_mii_txclk_pingroup = {
775 .name = "ras_mii_txclk_grp",
776 .pins = ras_mii_txclk_pins,
777 .npins = ARRAY_SIZE(ras_mii_txclk_pins),
778 .modemuxs = ras_mii_txclk_modemux,
779 .nmodemuxs = ARRAY_SIZE(ras_mii_txclk_modemux),
780 };
781
782 static const char *const ras_mii_txclk_grps[] = { "ras_mii_txclk_grp" };
783 static struct spear_function ras_mii_txclk_function = {
784 .name = "ras_mii_txclk",
785 .groups = ras_mii_txclk_grps,
786 .ngroups = ARRAY_SIZE(ras_mii_txclk_grps),
787 };
788
789 /* Pad multiplexing for nand 8bit device (cs0 only) */
790 static const unsigned nand_8bit_pins[] = { 56, 57, 58, 59, 60, 61, 62, 63, 64,
791 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82,
792 83, 84, 85, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169,
793 170, 171, 172, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
794 212 };
795 static struct spear_muxreg nand_8bit_muxreg[] = {
796 {
797 .reg = PAD_FUNCTION_EN_0,
798 .mask = PMX_NAND8BIT_0_MASK,
799 .val = PMX_NAND8BIT_0_MASK,
800 }, {
801 .reg = PAD_FUNCTION_EN_1,
802 .mask = PMX_NAND8BIT_1_MASK,
803 .val = PMX_NAND8BIT_1_MASK,
804 }, {
805 .reg = PAD_DIRECTION_SEL_0,
806 .mask = PMX_NAND8BIT_0_MASK,
807 .val = PMX_NAND8BIT_0_MASK,
808 }, {
809 .reg = PAD_DIRECTION_SEL_1,
810 .mask = PMX_NAND8BIT_1_MASK,
811 .val = PMX_NAND8BIT_1_MASK,
812 },
813 };
814
815 static struct spear_modemux nand_8bit_modemux[] = {
816 {
817 .muxregs = nand_8bit_muxreg,
818 .nmuxregs = ARRAY_SIZE(nand_8bit_muxreg),
819 },
820 };
821
822 static struct spear_pingroup nand_8bit_pingroup = {
823 .name = "nand_8bit_grp",
824 .pins = nand_8bit_pins,
825 .npins = ARRAY_SIZE(nand_8bit_pins),
826 .modemuxs = nand_8bit_modemux,
827 .nmodemuxs = ARRAY_SIZE(nand_8bit_modemux),
828 };
829
830 /* Pad multiplexing for nand 16bit device */
831 static const unsigned nand_16bit_pins[] = { 201, 202, 203, 204, 207, 208, 209,
832 210 };
833 static struct spear_muxreg nand_16bit_muxreg[] = {
834 {
835 .reg = PAD_FUNCTION_EN_1,
836 .mask = PMX_NAND16BIT_1_MASK,
837 .val = PMX_NAND16BIT_1_MASK,
838 }, {
839 .reg = PAD_DIRECTION_SEL_1,
840 .mask = PMX_NAND16BIT_1_MASK,
841 .val = PMX_NAND16BIT_1_MASK,
842 },
843 };
844
845 static struct spear_modemux nand_16bit_modemux[] = {
846 {
847 .muxregs = nand_16bit_muxreg,
848 .nmuxregs = ARRAY_SIZE(nand_16bit_muxreg),
849 },
850 };
851
852 static struct spear_pingroup nand_16bit_pingroup = {
853 .name = "nand_16bit_grp",
854 .pins = nand_16bit_pins,
855 .npins = ARRAY_SIZE(nand_16bit_pins),
856 .modemuxs = nand_16bit_modemux,
857 .nmodemuxs = ARRAY_SIZE(nand_16bit_modemux),
858 };
859
860 /* Pad multiplexing for nand 4 chips */
861 static const unsigned nand_4_chips_pins[] = { 205, 206, 211, 212 };
862 static struct spear_muxreg nand_4_chips_muxreg[] = {
863 {
864 .reg = PAD_FUNCTION_EN_1,
865 .mask = PMX_NAND_4CHIPS_MASK,
866 .val = PMX_NAND_4CHIPS_MASK,
867 }, {
868 .reg = PAD_DIRECTION_SEL_1,
869 .mask = PMX_NAND_4CHIPS_MASK,
870 .val = PMX_NAND_4CHIPS_MASK,
871 },
872 };
873
874 static struct spear_modemux nand_4_chips_modemux[] = {
875 {
876 .muxregs = nand_4_chips_muxreg,
877 .nmuxregs = ARRAY_SIZE(nand_4_chips_muxreg),
878 },
879 };
880
881 static struct spear_pingroup nand_4_chips_pingroup = {
882 .name = "nand_4_chips_grp",
883 .pins = nand_4_chips_pins,
884 .npins = ARRAY_SIZE(nand_4_chips_pins),
885 .modemuxs = nand_4_chips_modemux,
886 .nmodemuxs = ARRAY_SIZE(nand_4_chips_modemux),
887 };
888
889 static const char *const nand_grps[] = { "nand_8bit_grp", "nand_16bit_grp",
890 "nand_4_chips_grp" };
891 static struct spear_function nand_function = {
892 .name = "nand",
893 .groups = nand_grps,
894 .ngroups = ARRAY_SIZE(nand_grps),
895 };
896
897 /* Pad multiplexing for keyboard_6x6 device */
898 static const unsigned keyboard_6x6_pins[] = { 201, 202, 203, 204, 205, 206, 207,
899 208, 209, 210, 211, 212 };
900 static struct spear_muxreg keyboard_6x6_muxreg[] = {
901 {
902 .reg = PAD_FUNCTION_EN_1,
903 .mask = PMX_KEYBOARD_6X6_MASK | PMX_NFIO8_15_MASK |
904 PMX_NFCE1_MASK | PMX_NFCE2_MASK | PMX_NFWPRT1_MASK |
905 PMX_NFWPRT2_MASK,
906 .val = PMX_KEYBOARD_6X6_MASK,
907 },
908 };
909
910 static struct spear_modemux keyboard_6x6_modemux[] = {
911 {
912 .muxregs = keyboard_6x6_muxreg,
913 .nmuxregs = ARRAY_SIZE(keyboard_6x6_muxreg),
914 },
915 };
916
917 static struct spear_pingroup keyboard_6x6_pingroup = {
918 .name = "keyboard_6x6_grp",
919 .pins = keyboard_6x6_pins,
920 .npins = ARRAY_SIZE(keyboard_6x6_pins),
921 .modemuxs = keyboard_6x6_modemux,
922 .nmodemuxs = ARRAY_SIZE(keyboard_6x6_modemux),
923 };
924
925 /* Pad multiplexing for keyboard_rowcol6_8 device */
926 static const unsigned keyboard_rowcol6_8_pins[] = { 24, 25, 26, 27, 28, 29 };
927 static struct spear_muxreg keyboard_rowcol6_8_muxreg[] = {
928 {
929 .reg = PAD_FUNCTION_EN_1,
930 .mask = PMX_KBD_ROWCOL68_MASK,
931 .val = PMX_KBD_ROWCOL68_MASK,
932 }, {
933 .reg = PAD_DIRECTION_SEL_1,
934 .mask = PMX_KBD_ROWCOL68_MASK,
935 .val = PMX_KBD_ROWCOL68_MASK,
936 },
937 };
938
939 static struct spear_modemux keyboard_rowcol6_8_modemux[] = {
940 {
941 .muxregs = keyboard_rowcol6_8_muxreg,
942 .nmuxregs = ARRAY_SIZE(keyboard_rowcol6_8_muxreg),
943 },
944 };
945
946 static struct spear_pingroup keyboard_rowcol6_8_pingroup = {
947 .name = "keyboard_rowcol6_8_grp",
948 .pins = keyboard_rowcol6_8_pins,
949 .npins = ARRAY_SIZE(keyboard_rowcol6_8_pins),
950 .modemuxs = keyboard_rowcol6_8_modemux,
951 .nmodemuxs = ARRAY_SIZE(keyboard_rowcol6_8_modemux),
952 };
953
954 static const char *const keyboard_grps[] = { "keyboard_6x6_grp",
955 "keyboard_rowcol6_8_grp" };
956 static struct spear_function keyboard_function = {
957 .name = "keyboard",
958 .groups = keyboard_grps,
959 .ngroups = ARRAY_SIZE(keyboard_grps),
960 };
961
962 /* Pad multiplexing for uart0 device */
963 static const unsigned uart0_pins[] = { 100, 101 };
964 static struct spear_muxreg uart0_muxreg[] = {
965 {
966 .reg = PAD_FUNCTION_EN_0,
967 .mask = PMX_UART0_MASK,
968 .val = PMX_UART0_MASK,
969 }, {
970 .reg = PAD_DIRECTION_SEL_0,
971 .mask = PMX_UART0_MASK,
972 .val = PMX_UART0_MASK,
973 },
974 };
975
976 static struct spear_modemux uart0_modemux[] = {
977 {
978 .muxregs = uart0_muxreg,
979 .nmuxregs = ARRAY_SIZE(uart0_muxreg),
980 },
981 };
982
983 static struct spear_pingroup uart0_pingroup = {
984 .name = "uart0_grp",
985 .pins = uart0_pins,
986 .npins = ARRAY_SIZE(uart0_pins),
987 .modemuxs = uart0_modemux,
988 .nmodemuxs = ARRAY_SIZE(uart0_modemux),
989 };
990
991 /* Pad multiplexing for uart0_modem device */
992 static const unsigned uart0_modem_pins[] = { 12, 13, 14, 15, 16, 17 };
993 static struct spear_muxreg uart0_modem_muxreg[] = {
994 {
995 .reg = PAD_FUNCTION_EN_1,
996 .mask = PMX_UART0_MODEM_MASK,
997 .val = PMX_UART0_MODEM_MASK,
998 }, {
999 .reg = PAD_DIRECTION_SEL_1,
1000 .mask = PMX_UART0_MODEM_MASK,
1001 .val = PMX_UART0_MODEM_MASK,
1002 },
1003 };
1004
1005 static struct spear_modemux uart0_modem_modemux[] = {
1006 {
1007 .muxregs = uart0_modem_muxreg,
1008 .nmuxregs = ARRAY_SIZE(uart0_modem_muxreg),
1009 },
1010 };
1011
1012 static struct spear_pingroup uart0_modem_pingroup = {
1013 .name = "uart0_modem_grp",
1014 .pins = uart0_modem_pins,
1015 .npins = ARRAY_SIZE(uart0_modem_pins),
1016 .modemuxs = uart0_modem_modemux,
1017 .nmodemuxs = ARRAY_SIZE(uart0_modem_modemux),
1018 };
1019
1020 static const char *const uart0_grps[] = { "uart0_grp", "uart0_modem_grp" };
1021 static struct spear_function uart0_function = {
1022 .name = "uart0",
1023 .groups = uart0_grps,
1024 .ngroups = ARRAY_SIZE(uart0_grps),
1025 };
1026
1027 /* Pad multiplexing for gpt0_tmr0 device */
1028 static const unsigned gpt0_tmr0_pins[] = { 10, 11 };
1029 static struct spear_muxreg gpt0_tmr0_muxreg[] = {
1030 {
1031 .reg = PAD_FUNCTION_EN_1,
1032 .mask = PMX_GPT0_TMR0_MASK,
1033 .val = PMX_GPT0_TMR0_MASK,
1034 }, {
1035 .reg = PAD_DIRECTION_SEL_1,
1036 .mask = PMX_GPT0_TMR0_MASK,
1037 .val = PMX_GPT0_TMR0_MASK,
1038 },
1039 };
1040
1041 static struct spear_modemux gpt0_tmr0_modemux[] = {
1042 {
1043 .muxregs = gpt0_tmr0_muxreg,
1044 .nmuxregs = ARRAY_SIZE(gpt0_tmr0_muxreg),
1045 },
1046 };
1047
1048 static struct spear_pingroup gpt0_tmr0_pingroup = {
1049 .name = "gpt0_tmr0_grp",
1050 .pins = gpt0_tmr0_pins,
1051 .npins = ARRAY_SIZE(gpt0_tmr0_pins),
1052 .modemuxs = gpt0_tmr0_modemux,
1053 .nmodemuxs = ARRAY_SIZE(gpt0_tmr0_modemux),
1054 };
1055
1056 /* Pad multiplexing for gpt0_tmr1 device */
1057 static const unsigned gpt0_tmr1_pins[] = { 8, 9 };
1058 static struct spear_muxreg gpt0_tmr1_muxreg[] = {
1059 {
1060 .reg = PAD_FUNCTION_EN_1,
1061 .mask = PMX_GPT0_TMR1_MASK,
1062 .val = PMX_GPT0_TMR1_MASK,
1063 }, {
1064 .reg = PAD_DIRECTION_SEL_1,
1065 .mask = PMX_GPT0_TMR1_MASK,
1066 .val = PMX_GPT0_TMR1_MASK,
1067 },
1068 };
1069
1070 static struct spear_modemux gpt0_tmr1_modemux[] = {
1071 {
1072 .muxregs = gpt0_tmr1_muxreg,
1073 .nmuxregs = ARRAY_SIZE(gpt0_tmr1_muxreg),
1074 },
1075 };
1076
1077 static struct spear_pingroup gpt0_tmr1_pingroup = {
1078 .name = "gpt0_tmr1_grp",
1079 .pins = gpt0_tmr1_pins,
1080 .npins = ARRAY_SIZE(gpt0_tmr1_pins),
1081 .modemuxs = gpt0_tmr1_modemux,
1082 .nmodemuxs = ARRAY_SIZE(gpt0_tmr1_modemux),
1083 };
1084
1085 static const char *const gpt0_grps[] = { "gpt0_tmr0_grp", "gpt0_tmr1_grp" };
1086 static struct spear_function gpt0_function = {
1087 .name = "gpt0",
1088 .groups = gpt0_grps,
1089 .ngroups = ARRAY_SIZE(gpt0_grps),
1090 };
1091
1092 /* Pad multiplexing for gpt1_tmr0 device */
1093 static const unsigned gpt1_tmr0_pins[] = { 6, 7 };
1094 static struct spear_muxreg gpt1_tmr0_muxreg[] = {
1095 {
1096 .reg = PAD_FUNCTION_EN_1,
1097 .mask = PMX_GPT1_TMR0_MASK,
1098 .val = PMX_GPT1_TMR0_MASK,
1099 }, {
1100 .reg = PAD_DIRECTION_SEL_1,
1101 .mask = PMX_GPT1_TMR0_MASK,
1102 .val = PMX_GPT1_TMR0_MASK,
1103 },
1104 };
1105
1106 static struct spear_modemux gpt1_tmr0_modemux[] = {
1107 {
1108 .muxregs = gpt1_tmr0_muxreg,
1109 .nmuxregs = ARRAY_SIZE(gpt1_tmr0_muxreg),
1110 },
1111 };
1112
1113 static struct spear_pingroup gpt1_tmr0_pingroup = {
1114 .name = "gpt1_tmr0_grp",
1115 .pins = gpt1_tmr0_pins,
1116 .npins = ARRAY_SIZE(gpt1_tmr0_pins),
1117 .modemuxs = gpt1_tmr0_modemux,
1118 .nmodemuxs = ARRAY_SIZE(gpt1_tmr0_modemux),
1119 };
1120
1121 /* Pad multiplexing for gpt1_tmr1 device */
1122 static const unsigned gpt1_tmr1_pins[] = { 4, 5 };
1123 static struct spear_muxreg gpt1_tmr1_muxreg[] = {
1124 {
1125 .reg = PAD_FUNCTION_EN_1,
1126 .mask = PMX_GPT1_TMR1_MASK,
1127 .val = PMX_GPT1_TMR1_MASK,
1128 }, {
1129 .reg = PAD_DIRECTION_SEL_1,
1130 .mask = PMX_GPT1_TMR1_MASK,
1131 .val = PMX_GPT1_TMR1_MASK,
1132 },
1133 };
1134
1135 static struct spear_modemux gpt1_tmr1_modemux[] = {
1136 {
1137 .muxregs = gpt1_tmr1_muxreg,
1138 .nmuxregs = ARRAY_SIZE(gpt1_tmr1_muxreg),
1139 },
1140 };
1141
1142 static struct spear_pingroup gpt1_tmr1_pingroup = {
1143 .name = "gpt1_tmr1_grp",
1144 .pins = gpt1_tmr1_pins,
1145 .npins = ARRAY_SIZE(gpt1_tmr1_pins),
1146 .modemuxs = gpt1_tmr1_modemux,
1147 .nmodemuxs = ARRAY_SIZE(gpt1_tmr1_modemux),
1148 };
1149
1150 static const char *const gpt1_grps[] = { "gpt1_tmr1_grp", "gpt1_tmr0_grp" };
1151 static struct spear_function gpt1_function = {
1152 .name = "gpt1",
1153 .groups = gpt1_grps,
1154 .ngroups = ARRAY_SIZE(gpt1_grps),
1155 };
1156
1157 /* Pad multiplexing for mcif device */
1158 static const unsigned mcif_pins[] = { 86, 87, 88, 89, 90, 91, 92, 93, 213, 214,
1159 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228,
1160 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242,
1161 243, 244, 245 };
1162 #define MCIF_MUXREG \
1163 { \
1164 .reg = PAD_FUNCTION_EN_0, \
1165 .mask = PMX_MCI_DATA8_15_MASK, \
1166 .val = PMX_MCI_DATA8_15_MASK, \
1167 }, { \
1168 .reg = PAD_FUNCTION_EN_1, \
1169 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1170 PMX_NFWPRT2_MASK, \
1171 .val = PMX_MCIFALL_1_MASK, \
1172 }, { \
1173 .reg = PAD_FUNCTION_EN_2, \
1174 .mask = PMX_MCIFALL_2_MASK, \
1175 .val = PMX_MCIFALL_2_MASK, \
1176 }, { \
1177 .reg = PAD_DIRECTION_SEL_0, \
1178 .mask = PMX_MCI_DATA8_15_MASK, \
1179 .val = PMX_MCI_DATA8_15_MASK, \
1180 }, { \
1181 .reg = PAD_DIRECTION_SEL_1, \
1182 .mask = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1183 PMX_NFWPRT2_MASK, \
1184 .val = PMX_MCIFALL_1_MASK | PMX_NFWPRT1_MASK | \
1185 PMX_NFWPRT2_MASK, \
1186 }, { \
1187 .reg = PAD_DIRECTION_SEL_2, \
1188 .mask = PMX_MCIFALL_2_MASK, \
1189 .val = PMX_MCIFALL_2_MASK, \
1190 }
1191
1192 /* sdhci device */
1193 static struct spear_muxreg sdhci_muxreg[] = {
1194 MCIF_MUXREG,
1195 {
1196 .reg = PERIP_CFG,
1197 .mask = MCIF_SEL_MASK,
1198 .val = MCIF_SEL_SD,
1199 },
1200 };
1201
1202 static struct spear_modemux sdhci_modemux[] = {
1203 {
1204 .muxregs = sdhci_muxreg,
1205 .nmuxregs = ARRAY_SIZE(sdhci_muxreg),
1206 },
1207 };
1208
1209 static struct spear_pingroup sdhci_pingroup = {
1210 .name = "sdhci_grp",
1211 .pins = mcif_pins,
1212 .npins = ARRAY_SIZE(mcif_pins),
1213 .modemuxs = sdhci_modemux,
1214 .nmodemuxs = ARRAY_SIZE(sdhci_modemux),
1215 };
1216
1217 static const char *const sdhci_grps[] = { "sdhci_grp" };
1218 static struct spear_function sdhci_function = {
1219 .name = "sdhci",
1220 .groups = sdhci_grps,
1221 .ngroups = ARRAY_SIZE(sdhci_grps),
1222 };
1223
1224 /* cf device */
1225 static struct spear_muxreg cf_muxreg[] = {
1226 MCIF_MUXREG,
1227 {
1228 .reg = PERIP_CFG,
1229 .mask = MCIF_SEL_MASK,
1230 .val = MCIF_SEL_CF,
1231 },
1232 };
1233
1234 static struct spear_modemux cf_modemux[] = {
1235 {
1236 .muxregs = cf_muxreg,
1237 .nmuxregs = ARRAY_SIZE(cf_muxreg),
1238 },
1239 };
1240
1241 static struct spear_pingroup cf_pingroup = {
1242 .name = "cf_grp",
1243 .pins = mcif_pins,
1244 .npins = ARRAY_SIZE(mcif_pins),
1245 .modemuxs = cf_modemux,
1246 .nmodemuxs = ARRAY_SIZE(cf_modemux),
1247 };
1248
1249 static const char *const cf_grps[] = { "cf_grp" };
1250 static struct spear_function cf_function = {
1251 .name = "cf",
1252 .groups = cf_grps,
1253 .ngroups = ARRAY_SIZE(cf_grps),
1254 };
1255
1256 /* xd device */
1257 static struct spear_muxreg xd_muxreg[] = {
1258 MCIF_MUXREG,
1259 {
1260 .reg = PERIP_CFG,
1261 .mask = MCIF_SEL_MASK,
1262 .val = MCIF_SEL_XD,
1263 },
1264 };
1265
1266 static struct spear_modemux xd_modemux[] = {
1267 {
1268 .muxregs = xd_muxreg,
1269 .nmuxregs = ARRAY_SIZE(xd_muxreg),
1270 },
1271 };
1272
1273 static struct spear_pingroup xd_pingroup = {
1274 .name = "xd_grp",
1275 .pins = mcif_pins,
1276 .npins = ARRAY_SIZE(mcif_pins),
1277 .modemuxs = xd_modemux,
1278 .nmodemuxs = ARRAY_SIZE(xd_modemux),
1279 };
1280
1281 static const char *const xd_grps[] = { "xd_grp" };
1282 static struct spear_function xd_function = {
1283 .name = "xd",
1284 .groups = xd_grps,
1285 .ngroups = ARRAY_SIZE(xd_grps),
1286 };
1287
1288 /* Pad multiplexing for touch_xy device */
1289 static const unsigned touch_xy_pins[] = { 97 };
1290 static struct spear_muxreg touch_xy_muxreg[] = {
1291 {
1292 .reg = PAD_FUNCTION_EN_2,
1293 .mask = PMX_TOUCH_XY_MASK,
1294 .val = PMX_TOUCH_XY_MASK,
1295 }, {
1296 .reg = PAD_DIRECTION_SEL_2,
1297 .mask = PMX_TOUCH_XY_MASK,
1298 .val = PMX_TOUCH_XY_MASK,
1299 },
1300 };
1301
1302 static struct spear_modemux touch_xy_modemux[] = {
1303 {
1304 .muxregs = touch_xy_muxreg,
1305 .nmuxregs = ARRAY_SIZE(touch_xy_muxreg),
1306 },
1307 };
1308
1309 static struct spear_pingroup touch_xy_pingroup = {
1310 .name = "touch_xy_grp",
1311 .pins = touch_xy_pins,
1312 .npins = ARRAY_SIZE(touch_xy_pins),
1313 .modemuxs = touch_xy_modemux,
1314 .nmodemuxs = ARRAY_SIZE(touch_xy_modemux),
1315 };
1316
1317 static const char *const touch_xy_grps[] = { "touch_xy_grp" };
1318 static struct spear_function touch_xy_function = {
1319 .name = "touchscreen",
1320 .groups = touch_xy_grps,
1321 .ngroups = ARRAY_SIZE(touch_xy_grps),
1322 };
1323
1324 /* Pad multiplexing for uart1 device */
1325 /* Muxed with I2C */
1326 static const unsigned uart1_dis_i2c_pins[] = { 102, 103 };
1327 static struct spear_muxreg uart1_dis_i2c_muxreg[] = {
1328 {
1329 .reg = PAD_FUNCTION_EN_0,
1330 .mask = PMX_I2C0_MASK,
1331 .val = 0,
1332 }, {
1333 .reg = PAD_DIRECTION_SEL_0,
1334 .mask = PMX_I2C0_MASK,
1335 .val = PMX_I2C0_MASK,
1336 },
1337 };
1338
1339 static struct spear_modemux uart1_dis_i2c_modemux[] = {
1340 {
1341 .muxregs = uart1_dis_i2c_muxreg,
1342 .nmuxregs = ARRAY_SIZE(uart1_dis_i2c_muxreg),
1343 },
1344 };
1345
1346 static struct spear_pingroup uart_1_dis_i2c_pingroup = {
1347 .name = "uart1_disable_i2c_grp",
1348 .pins = uart1_dis_i2c_pins,
1349 .npins = ARRAY_SIZE(uart1_dis_i2c_pins),
1350 .modemuxs = uart1_dis_i2c_modemux,
1351 .nmodemuxs = ARRAY_SIZE(uart1_dis_i2c_modemux),
1352 };
1353
1354 /* Muxed with SD/MMC */
1355 static const unsigned uart1_dis_sd_pins[] = { 214, 215 };
1356 static struct spear_muxreg uart1_dis_sd_muxreg[] = {
1357 {
1358 .reg = PAD_FUNCTION_EN_1,
1359 .mask = PMX_MCIDATA1_MASK |
1360 PMX_MCIDATA2_MASK,
1361 .val = 0,
1362 }, {
1363 .reg = PAD_DIRECTION_SEL_1,
1364 .mask = PMX_MCIDATA1_MASK |
1365 PMX_MCIDATA2_MASK,
1366 .val = PMX_MCIDATA1_MASK |
1367 PMX_MCIDATA2_MASK,
1368 },
1369 };
1370
1371 static struct spear_modemux uart1_dis_sd_modemux[] = {
1372 {
1373 .muxregs = uart1_dis_sd_muxreg,
1374 .nmuxregs = ARRAY_SIZE(uart1_dis_sd_muxreg),
1375 },
1376 };
1377
1378 static struct spear_pingroup uart_1_dis_sd_pingroup = {
1379 .name = "uart1_disable_sd_grp",
1380 .pins = uart1_dis_sd_pins,
1381 .npins = ARRAY_SIZE(uart1_dis_sd_pins),
1382 .modemuxs = uart1_dis_sd_modemux,
1383 .nmodemuxs = ARRAY_SIZE(uart1_dis_sd_modemux),
1384 };
1385
1386 static const char *const uart1_grps[] = { "uart1_disable_i2c_grp",
1387 "uart1_disable_sd_grp" };
1388 static struct spear_function uart1_function = {
1389 .name = "uart1",
1390 .groups = uart1_grps,
1391 .ngroups = ARRAY_SIZE(uart1_grps),
1392 };
1393
1394 /* Pad multiplexing for uart2_3 device */
1395 static const unsigned uart2_3_pins[] = { 104, 105, 106, 107 };
1396 static struct spear_muxreg uart2_3_muxreg[] = {
1397 {
1398 .reg = PAD_FUNCTION_EN_0,
1399 .mask = PMX_I2S0_MASK,
1400 .val = 0,
1401 }, {
1402 .reg = PAD_DIRECTION_SEL_0,
1403 .mask = PMX_I2S0_MASK,
1404 .val = PMX_I2S0_MASK,
1405 },
1406 };
1407
1408 static struct spear_modemux uart2_3_modemux[] = {
1409 {
1410 .muxregs = uart2_3_muxreg,
1411 .nmuxregs = ARRAY_SIZE(uart2_3_muxreg),
1412 },
1413 };
1414
1415 static struct spear_pingroup uart_2_3_pingroup = {
1416 .name = "uart2_3_grp",
1417 .pins = uart2_3_pins,
1418 .npins = ARRAY_SIZE(uart2_3_pins),
1419 .modemuxs = uart2_3_modemux,
1420 .nmodemuxs = ARRAY_SIZE(uart2_3_modemux),
1421 };
1422
1423 static const char *const uart2_3_grps[] = { "uart2_3_grp" };
1424 static struct spear_function uart2_3_function = {
1425 .name = "uart2_3",
1426 .groups = uart2_3_grps,
1427 .ngroups = ARRAY_SIZE(uart2_3_grps),
1428 };
1429
1430 /* Pad multiplexing for uart4 device */
1431 static const unsigned uart4_pins[] = { 108, 113 };
1432 static struct spear_muxreg uart4_muxreg[] = {
1433 {
1434 .reg = PAD_FUNCTION_EN_0,
1435 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1436 .val = 0,
1437 }, {
1438 .reg = PAD_DIRECTION_SEL_0,
1439 .mask = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1440 .val = PMX_I2S0_MASK | PMX_CLCD1_MASK,
1441 },
1442 };
1443
1444 static struct spear_modemux uart4_modemux[] = {
1445 {
1446 .muxregs = uart4_muxreg,
1447 .nmuxregs = ARRAY_SIZE(uart4_muxreg),
1448 },
1449 };
1450
1451 static struct spear_pingroup uart_4_pingroup = {
1452 .name = "uart4_grp",
1453 .pins = uart4_pins,
1454 .npins = ARRAY_SIZE(uart4_pins),
1455 .modemuxs = uart4_modemux,
1456 .nmodemuxs = ARRAY_SIZE(uart4_modemux),
1457 };
1458
1459 static const char *const uart4_grps[] = { "uart4_grp" };
1460 static struct spear_function uart4_function = {
1461 .name = "uart4",
1462 .groups = uart4_grps,
1463 .ngroups = ARRAY_SIZE(uart4_grps),
1464 };
1465
1466 /* Pad multiplexing for uart5 device */
1467 static const unsigned uart5_pins[] = { 114, 115 };
1468 static struct spear_muxreg uart5_muxreg[] = {
1469 {
1470 .reg = PAD_FUNCTION_EN_0,
1471 .mask = PMX_CLCD1_MASK,
1472 .val = 0,
1473 }, {
1474 .reg = PAD_DIRECTION_SEL_0,
1475 .mask = PMX_CLCD1_MASK,
1476 .val = PMX_CLCD1_MASK,
1477 },
1478 };
1479
1480 static struct spear_modemux uart5_modemux[] = {
1481 {
1482 .muxregs = uart5_muxreg,
1483 .nmuxregs = ARRAY_SIZE(uart5_muxreg),
1484 },
1485 };
1486
1487 static struct spear_pingroup uart_5_pingroup = {
1488 .name = "uart5_grp",
1489 .pins = uart5_pins,
1490 .npins = ARRAY_SIZE(uart5_pins),
1491 .modemuxs = uart5_modemux,
1492 .nmodemuxs = ARRAY_SIZE(uart5_modemux),
1493 };
1494
1495 static const char *const uart5_grps[] = { "uart5_grp" };
1496 static struct spear_function uart5_function = {
1497 .name = "uart5",
1498 .groups = uart5_grps,
1499 .ngroups = ARRAY_SIZE(uart5_grps),
1500 };
1501
1502 /* Pad multiplexing for rs485_0_1_tdm_0_1 device */
1503 static const unsigned rs485_0_1_tdm_0_1_pins[] = { 116, 117, 118, 119, 120, 121,
1504 122, 123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135,
1505 136, 137 };
1506 static struct spear_muxreg rs485_0_1_tdm_0_1_muxreg[] = {
1507 {
1508 .reg = PAD_FUNCTION_EN_0,
1509 .mask = PMX_CLCD1_MASK,
1510 .val = 0,
1511 }, {
1512 .reg = PAD_DIRECTION_SEL_0,
1513 .mask = PMX_CLCD1_MASK,
1514 .val = PMX_CLCD1_MASK,
1515 },
1516 };
1517
1518 static struct spear_modemux rs485_0_1_tdm_0_1_modemux[] = {
1519 {
1520 .muxregs = rs485_0_1_tdm_0_1_muxreg,
1521 .nmuxregs = ARRAY_SIZE(rs485_0_1_tdm_0_1_muxreg),
1522 },
1523 };
1524
1525 static struct spear_pingroup rs485_0_1_tdm_0_1_pingroup = {
1526 .name = "rs485_0_1_tdm_0_1_grp",
1527 .pins = rs485_0_1_tdm_0_1_pins,
1528 .npins = ARRAY_SIZE(rs485_0_1_tdm_0_1_pins),
1529 .modemuxs = rs485_0_1_tdm_0_1_modemux,
1530 .nmodemuxs = ARRAY_SIZE(rs485_0_1_tdm_0_1_modemux),
1531 };
1532
1533 static const char *const rs485_0_1_tdm_0_1_grps[] = { "rs485_0_1_tdm_0_1_grp" };
1534 static struct spear_function rs485_0_1_tdm_0_1_function = {
1535 .name = "rs485_0_1_tdm_0_1",
1536 .groups = rs485_0_1_tdm_0_1_grps,
1537 .ngroups = ARRAY_SIZE(rs485_0_1_tdm_0_1_grps),
1538 };
1539
1540 /* Pad multiplexing for i2c_1_2 device */
1541 static const unsigned i2c_1_2_pins[] = { 138, 139, 140, 141 };
1542 static struct spear_muxreg i2c_1_2_muxreg[] = {
1543 {
1544 .reg = PAD_FUNCTION_EN_0,
1545 .mask = PMX_CLCD1_MASK,
1546 .val = 0,
1547 }, {
1548 .reg = PAD_DIRECTION_SEL_0,
1549 .mask = PMX_CLCD1_MASK,
1550 .val = PMX_CLCD1_MASK,
1551 },
1552 };
1553
1554 static struct spear_modemux i2c_1_2_modemux[] = {
1555 {
1556 .muxregs = i2c_1_2_muxreg,
1557 .nmuxregs = ARRAY_SIZE(i2c_1_2_muxreg),
1558 },
1559 };
1560
1561 static struct spear_pingroup i2c_1_2_pingroup = {
1562 .name = "i2c_1_2_grp",
1563 .pins = i2c_1_2_pins,
1564 .npins = ARRAY_SIZE(i2c_1_2_pins),
1565 .modemuxs = i2c_1_2_modemux,
1566 .nmodemuxs = ARRAY_SIZE(i2c_1_2_modemux),
1567 };
1568
1569 static const char *const i2c_1_2_grps[] = { "i2c_1_2_grp" };
1570 static struct spear_function i2c_1_2_function = {
1571 .name = "i2c_1_2",
1572 .groups = i2c_1_2_grps,
1573 .ngroups = ARRAY_SIZE(i2c_1_2_grps),
1574 };
1575
1576 /* Pad multiplexing for i2c3_dis_smi_clcd device */
1577 /* Muxed with SMI & CLCD */
1578 static const unsigned i2c3_dis_smi_clcd_pins[] = { 142, 153 };
1579 static struct spear_muxreg i2c3_dis_smi_clcd_muxreg[] = {
1580 {
1581 .reg = PAD_FUNCTION_EN_0,
1582 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1583 .val = 0,
1584 }, {
1585 .reg = PAD_DIRECTION_SEL_0,
1586 .mask = PMX_CLCD1_MASK | PMX_SMI_MASK,
1587 .val = PMX_CLCD1_MASK | PMX_SMI_MASK,
1588 },
1589 };
1590
1591 static struct spear_modemux i2c3_dis_smi_clcd_modemux[] = {
1592 {
1593 .muxregs = i2c3_dis_smi_clcd_muxreg,
1594 .nmuxregs = ARRAY_SIZE(i2c3_dis_smi_clcd_muxreg),
1595 },
1596 };
1597
1598 static struct spear_pingroup i2c3_dis_smi_clcd_pingroup = {
1599 .name = "i2c3_dis_smi_clcd_grp",
1600 .pins = i2c3_dis_smi_clcd_pins,
1601 .npins = ARRAY_SIZE(i2c3_dis_smi_clcd_pins),
1602 .modemuxs = i2c3_dis_smi_clcd_modemux,
1603 .nmodemuxs = ARRAY_SIZE(i2c3_dis_smi_clcd_modemux),
1604 };
1605
1606 /* Pad multiplexing for i2c3_dis_sd_i2s0 device */
1607 /* Muxed with SD/MMC & I2S1 */
1608 static const unsigned i2c3_dis_sd_i2s0_pins[] = { 0, 216 };
1609 static struct spear_muxreg i2c3_dis_sd_i2s0_muxreg[] = {
1610 {
1611 .reg = PAD_FUNCTION_EN_1,
1612 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1613 .val = 0,
1614 }, {
1615 .reg = PAD_DIRECTION_SEL_1,
1616 .mask = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1617 .val = PMX_I2S1_MASK | PMX_MCIDATA3_MASK,
1618 },
1619 };
1620
1621 static struct spear_modemux i2c3_dis_sd_i2s0_modemux[] = {
1622 {
1623 .muxregs = i2c3_dis_sd_i2s0_muxreg,
1624 .nmuxregs = ARRAY_SIZE(i2c3_dis_sd_i2s0_muxreg),
1625 },
1626 };
1627
1628 static struct spear_pingroup i2c3_dis_sd_i2s0_pingroup = {
1629 .name = "i2c3_dis_sd_i2s0_grp",
1630 .pins = i2c3_dis_sd_i2s0_pins,
1631 .npins = ARRAY_SIZE(i2c3_dis_sd_i2s0_pins),
1632 .modemuxs = i2c3_dis_sd_i2s0_modemux,
1633 .nmodemuxs = ARRAY_SIZE(i2c3_dis_sd_i2s0_modemux),
1634 };
1635
1636 static const char *const i2c3_grps[] = { "i2c3_dis_smi_clcd_grp",
1637 "i2c3_dis_sd_i2s0_grp" };
1638 static struct spear_function i2c3_unction = {
1639 .name = "i2c3_i2s1",
1640 .groups = i2c3_grps,
1641 .ngroups = ARRAY_SIZE(i2c3_grps),
1642 };
1643
1644 /* Pad multiplexing for i2c_4_5_dis_smi device */
1645 /* Muxed with SMI */
1646 static const unsigned i2c_4_5_dis_smi_pins[] = { 154, 155, 156, 157 };
1647 static struct spear_muxreg i2c_4_5_dis_smi_muxreg[] = {
1648 {
1649 .reg = PAD_FUNCTION_EN_0,
1650 .mask = PMX_SMI_MASK,
1651 .val = 0,
1652 }, {
1653 .reg = PAD_DIRECTION_SEL_0,
1654 .mask = PMX_SMI_MASK,
1655 .val = PMX_SMI_MASK,
1656 },
1657 };
1658
1659 static struct spear_modemux i2c_4_5_dis_smi_modemux[] = {
1660 {
1661 .muxregs = i2c_4_5_dis_smi_muxreg,
1662 .nmuxregs = ARRAY_SIZE(i2c_4_5_dis_smi_muxreg),
1663 },
1664 };
1665
1666 static struct spear_pingroup i2c_4_5_dis_smi_pingroup = {
1667 .name = "i2c_4_5_dis_smi_grp",
1668 .pins = i2c_4_5_dis_smi_pins,
1669 .npins = ARRAY_SIZE(i2c_4_5_dis_smi_pins),
1670 .modemuxs = i2c_4_5_dis_smi_modemux,
1671 .nmodemuxs = ARRAY_SIZE(i2c_4_5_dis_smi_modemux),
1672 };
1673
1674 /* Pad multiplexing for i2c4_dis_sd device */
1675 /* Muxed with SD/MMC */
1676 static const unsigned i2c4_dis_sd_pins[] = { 217, 218 };
1677 static struct spear_muxreg i2c4_dis_sd_muxreg[] = {
1678 {
1679 .reg = PAD_FUNCTION_EN_1,
1680 .mask = PMX_MCIDATA4_MASK,
1681 .val = 0,
1682 }, {
1683 .reg = PAD_FUNCTION_EN_2,
1684 .mask = PMX_MCIDATA5_MASK,
1685 .val = 0,
1686 }, {
1687 .reg = PAD_DIRECTION_SEL_1,
1688 .mask = PMX_MCIDATA4_MASK,
1689 .val = PMX_MCIDATA4_MASK,
1690 }, {
1691 .reg = PAD_DIRECTION_SEL_2,
1692 .mask = PMX_MCIDATA5_MASK,
1693 .val = PMX_MCIDATA5_MASK,
1694 },
1695 };
1696
1697 static struct spear_modemux i2c4_dis_sd_modemux[] = {
1698 {
1699 .muxregs = i2c4_dis_sd_muxreg,
1700 .nmuxregs = ARRAY_SIZE(i2c4_dis_sd_muxreg),
1701 },
1702 };
1703
1704 static struct spear_pingroup i2c4_dis_sd_pingroup = {
1705 .name = "i2c4_dis_sd_grp",
1706 .pins = i2c4_dis_sd_pins,
1707 .npins = ARRAY_SIZE(i2c4_dis_sd_pins),
1708 .modemuxs = i2c4_dis_sd_modemux,
1709 .nmodemuxs = ARRAY_SIZE(i2c4_dis_sd_modemux),
1710 };
1711
1712 /* Pad multiplexing for i2c5_dis_sd device */
1713 /* Muxed with SD/MMC */
1714 static const unsigned i2c5_dis_sd_pins[] = { 219, 220 };
1715 static struct spear_muxreg i2c5_dis_sd_muxreg[] = {
1716 {
1717 .reg = PAD_FUNCTION_EN_2,
1718 .mask = PMX_MCIDATA6_MASK |
1719 PMX_MCIDATA7_MASK,
1720 .val = 0,
1721 }, {
1722 .reg = PAD_DIRECTION_SEL_2,
1723 .mask = PMX_MCIDATA6_MASK |
1724 PMX_MCIDATA7_MASK,
1725 .val = PMX_MCIDATA6_MASK |
1726 PMX_MCIDATA7_MASK,
1727 },
1728 };
1729
1730 static struct spear_modemux i2c5_dis_sd_modemux[] = {
1731 {
1732 .muxregs = i2c5_dis_sd_muxreg,
1733 .nmuxregs = ARRAY_SIZE(i2c5_dis_sd_muxreg),
1734 },
1735 };
1736
1737 static struct spear_pingroup i2c5_dis_sd_pingroup = {
1738 .name = "i2c5_dis_sd_grp",
1739 .pins = i2c5_dis_sd_pins,
1740 .npins = ARRAY_SIZE(i2c5_dis_sd_pins),
1741 .modemuxs = i2c5_dis_sd_modemux,
1742 .nmodemuxs = ARRAY_SIZE(i2c5_dis_sd_modemux),
1743 };
1744
1745 static const char *const i2c_4_5_grps[] = { "i2c5_dis_sd_grp",
1746 "i2c4_dis_sd_grp", "i2c_4_5_dis_smi_grp" };
1747 static struct spear_function i2c_4_5_function = {
1748 .name = "i2c_4_5",
1749 .groups = i2c_4_5_grps,
1750 .ngroups = ARRAY_SIZE(i2c_4_5_grps),
1751 };
1752
1753 /* Pad multiplexing for i2c_6_7_dis_kbd device */
1754 /* Muxed with KBD */
1755 static const unsigned i2c_6_7_dis_kbd_pins[] = { 207, 208, 209, 210 };
1756 static struct spear_muxreg i2c_6_7_dis_kbd_muxreg[] = {
1757 {
1758 .reg = PAD_FUNCTION_EN_1,
1759 .mask = PMX_KBD_ROWCOL25_MASK,
1760 .val = 0,
1761 }, {
1762 .reg = PAD_DIRECTION_SEL_1,
1763 .mask = PMX_KBD_ROWCOL25_MASK,
1764 .val = PMX_KBD_ROWCOL25_MASK,
1765 },
1766 };
1767
1768 static struct spear_modemux i2c_6_7_dis_kbd_modemux[] = {
1769 {
1770 .muxregs = i2c_6_7_dis_kbd_muxreg,
1771 .nmuxregs = ARRAY_SIZE(i2c_6_7_dis_kbd_muxreg),
1772 },
1773 };
1774
1775 static struct spear_pingroup i2c_6_7_dis_kbd_pingroup = {
1776 .name = "i2c_6_7_dis_kbd_grp",
1777 .pins = i2c_6_7_dis_kbd_pins,
1778 .npins = ARRAY_SIZE(i2c_6_7_dis_kbd_pins),
1779 .modemuxs = i2c_6_7_dis_kbd_modemux,
1780 .nmodemuxs = ARRAY_SIZE(i2c_6_7_dis_kbd_modemux),
1781 };
1782
1783 /* Pad multiplexing for i2c6_dis_sd device */
1784 /* Muxed with SD/MMC */
1785 static const unsigned i2c6_dis_sd_pins[] = { 236, 237 };
1786 static struct spear_muxreg i2c6_dis_sd_muxreg[] = {
1787 {
1788 .reg = PAD_FUNCTION_EN_2,
1789 .mask = PMX_MCIIORDRE_MASK |
1790 PMX_MCIIOWRWE_MASK,
1791 .val = 0,
1792 }, {
1793 .reg = PAD_DIRECTION_SEL_2,
1794 .mask = PMX_MCIIORDRE_MASK |
1795 PMX_MCIIOWRWE_MASK,
1796 .val = PMX_MCIIORDRE_MASK |
1797 PMX_MCIIOWRWE_MASK,
1798 },
1799 };
1800
1801 static struct spear_modemux i2c6_dis_sd_modemux[] = {
1802 {
1803 .muxregs = i2c6_dis_sd_muxreg,
1804 .nmuxregs = ARRAY_SIZE(i2c6_dis_sd_muxreg),
1805 },
1806 };
1807
1808 static struct spear_pingroup i2c6_dis_sd_pingroup = {
1809 .name = "i2c6_dis_sd_grp",
1810 .pins = i2c6_dis_sd_pins,
1811 .npins = ARRAY_SIZE(i2c6_dis_sd_pins),
1812 .modemuxs = i2c6_dis_sd_modemux,
1813 .nmodemuxs = ARRAY_SIZE(i2c6_dis_sd_modemux),
1814 };
1815
1816 /* Pad multiplexing for i2c7_dis_sd device */
1817 static const unsigned i2c7_dis_sd_pins[] = { 238, 239 };
1818 static struct spear_muxreg i2c7_dis_sd_muxreg[] = {
1819 {
1820 .reg = PAD_FUNCTION_EN_2,
1821 .mask = PMX_MCIRESETCF_MASK |
1822 PMX_MCICS0CE_MASK,
1823 .val = 0,
1824 }, {
1825 .reg = PAD_DIRECTION_SEL_2,
1826 .mask = PMX_MCIRESETCF_MASK |
1827 PMX_MCICS0CE_MASK,
1828 .val = PMX_MCIRESETCF_MASK |
1829 PMX_MCICS0CE_MASK,
1830 },
1831 };
1832
1833 static struct spear_modemux i2c7_dis_sd_modemux[] = {
1834 {
1835 .muxregs = i2c7_dis_sd_muxreg,
1836 .nmuxregs = ARRAY_SIZE(i2c7_dis_sd_muxreg),
1837 },
1838 };
1839
1840 static struct spear_pingroup i2c7_dis_sd_pingroup = {
1841 .name = "i2c7_dis_sd_grp",
1842 .pins = i2c7_dis_sd_pins,
1843 .npins = ARRAY_SIZE(i2c7_dis_sd_pins),
1844 .modemuxs = i2c7_dis_sd_modemux,
1845 .nmodemuxs = ARRAY_SIZE(i2c7_dis_sd_modemux),
1846 };
1847
1848 static const char *const i2c_6_7_grps[] = { "i2c6_dis_sd_grp",
1849 "i2c7_dis_sd_grp", "i2c_6_7_dis_kbd_grp" };
1850 static struct spear_function i2c_6_7_function = {
1851 .name = "i2c_6_7",
1852 .groups = i2c_6_7_grps,
1853 .ngroups = ARRAY_SIZE(i2c_6_7_grps),
1854 };
1855
1856 /* Pad multiplexing for can0_dis_nor device */
1857 /* Muxed with NOR */
1858 static const unsigned can0_dis_nor_pins[] = { 56, 57 };
1859 static struct spear_muxreg can0_dis_nor_muxreg[] = {
1860 {
1861 .reg = PAD_FUNCTION_EN_0,
1862 .mask = PMX_NFRSTPWDWN2_MASK,
1863 .val = 0,
1864 }, {
1865 .reg = PAD_FUNCTION_EN_1,
1866 .mask = PMX_NFRSTPWDWN3_MASK,
1867 .val = 0,
1868 }, {
1869 .reg = PAD_DIRECTION_SEL_0,
1870 .mask = PMX_NFRSTPWDWN2_MASK,
1871 .val = PMX_NFRSTPWDWN2_MASK,
1872 }, {
1873 .reg = PAD_DIRECTION_SEL_1,
1874 .mask = PMX_NFRSTPWDWN3_MASK,
1875 .val = PMX_NFRSTPWDWN3_MASK,
1876 },
1877 };
1878
1879 static struct spear_modemux can0_dis_nor_modemux[] = {
1880 {
1881 .muxregs = can0_dis_nor_muxreg,
1882 .nmuxregs = ARRAY_SIZE(can0_dis_nor_muxreg),
1883 },
1884 };
1885
1886 static struct spear_pingroup can0_dis_nor_pingroup = {
1887 .name = "can0_dis_nor_grp",
1888 .pins = can0_dis_nor_pins,
1889 .npins = ARRAY_SIZE(can0_dis_nor_pins),
1890 .modemuxs = can0_dis_nor_modemux,
1891 .nmodemuxs = ARRAY_SIZE(can0_dis_nor_modemux),
1892 };
1893
1894 /* Pad multiplexing for can0_dis_sd device */
1895 /* Muxed with SD/MMC */
1896 static const unsigned can0_dis_sd_pins[] = { 240, 241 };
1897 static struct spear_muxreg can0_dis_sd_muxreg[] = {
1898 {
1899 .reg = PAD_FUNCTION_EN_2,
1900 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1901 .val = 0,
1902 }, {
1903 .reg = PAD_DIRECTION_SEL_2,
1904 .mask = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1905 .val = PMX_MCICFINTR_MASK | PMX_MCIIORDY_MASK,
1906 },
1907 };
1908
1909 static struct spear_modemux can0_dis_sd_modemux[] = {
1910 {
1911 .muxregs = can0_dis_sd_muxreg,
1912 .nmuxregs = ARRAY_SIZE(can0_dis_sd_muxreg),
1913 },
1914 };
1915
1916 static struct spear_pingroup can0_dis_sd_pingroup = {
1917 .name = "can0_dis_sd_grp",
1918 .pins = can0_dis_sd_pins,
1919 .npins = ARRAY_SIZE(can0_dis_sd_pins),
1920 .modemuxs = can0_dis_sd_modemux,
1921 .nmodemuxs = ARRAY_SIZE(can0_dis_sd_modemux),
1922 };
1923
1924 static const char *const can0_grps[] = { "can0_dis_nor_grp", "can0_dis_sd_grp"
1925 };
1926 static struct spear_function can0_function = {
1927 .name = "can0",
1928 .groups = can0_grps,
1929 .ngroups = ARRAY_SIZE(can0_grps),
1930 };
1931
1932 /* Pad multiplexing for can1_dis_sd device */
1933 /* Muxed with SD/MMC */
1934 static const unsigned can1_dis_sd_pins[] = { 242, 243 };
1935 static struct spear_muxreg can1_dis_sd_muxreg[] = {
1936 {
1937 .reg = PAD_FUNCTION_EN_2,
1938 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1939 .val = 0,
1940 }, {
1941 .reg = PAD_DIRECTION_SEL_2,
1942 .mask = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1943 .val = PMX_MCICS1_MASK | PMX_MCIDMAACK_MASK,
1944 },
1945 };
1946
1947 static struct spear_modemux can1_dis_sd_modemux[] = {
1948 {
1949 .muxregs = can1_dis_sd_muxreg,
1950 .nmuxregs = ARRAY_SIZE(can1_dis_sd_muxreg),
1951 },
1952 };
1953
1954 static struct spear_pingroup can1_dis_sd_pingroup = {
1955 .name = "can1_dis_sd_grp",
1956 .pins = can1_dis_sd_pins,
1957 .npins = ARRAY_SIZE(can1_dis_sd_pins),
1958 .modemuxs = can1_dis_sd_modemux,
1959 .nmodemuxs = ARRAY_SIZE(can1_dis_sd_modemux),
1960 };
1961
1962 /* Pad multiplexing for can1_dis_kbd device */
1963 /* Muxed with KBD */
1964 static const unsigned can1_dis_kbd_pins[] = { 201, 202 };
1965 static struct spear_muxreg can1_dis_kbd_muxreg[] = {
1966 {
1967 .reg = PAD_FUNCTION_EN_1,
1968 .mask = PMX_KBD_ROWCOL25_MASK,
1969 .val = 0,
1970 }, {
1971 .reg = PAD_DIRECTION_SEL_1,
1972 .mask = PMX_KBD_ROWCOL25_MASK,
1973 .val = PMX_KBD_ROWCOL25_MASK,
1974 },
1975 };
1976
1977 static struct spear_modemux can1_dis_kbd_modemux[] = {
1978 {
1979 .muxregs = can1_dis_kbd_muxreg,
1980 .nmuxregs = ARRAY_SIZE(can1_dis_kbd_muxreg),
1981 },
1982 };
1983
1984 static struct spear_pingroup can1_dis_kbd_pingroup = {
1985 .name = "can1_dis_kbd_grp",
1986 .pins = can1_dis_kbd_pins,
1987 .npins = ARRAY_SIZE(can1_dis_kbd_pins),
1988 .modemuxs = can1_dis_kbd_modemux,
1989 .nmodemuxs = ARRAY_SIZE(can1_dis_kbd_modemux),
1990 };
1991
1992 static const char *const can1_grps[] = { "can1_dis_sd_grp", "can1_dis_kbd_grp"
1993 };
1994 static struct spear_function can1_function = {
1995 .name = "can1",
1996 .groups = can1_grps,
1997 .ngroups = ARRAY_SIZE(can1_grps),
1998 };
1999
2000 /* Pad multiplexing for (ras-ip) pci device */
2001 static const unsigned pci_pins[] = { 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 18,
2002 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36,
2003 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54,
2004 55, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99 };
2005
2006 static struct spear_muxreg pci_muxreg[] = {
2007 {
2008 .reg = PAD_FUNCTION_EN_0,
2009 .mask = PMX_MCI_DATA8_15_MASK,
2010 .val = 0,
2011 }, {
2012 .reg = PAD_FUNCTION_EN_1,
2013 .mask = PMX_PCI_REG1_MASK,
2014 .val = 0,
2015 }, {
2016 .reg = PAD_FUNCTION_EN_2,
2017 .mask = PMX_PCI_REG2_MASK,
2018 .val = 0,
2019 }, {
2020 .reg = PAD_DIRECTION_SEL_0,
2021 .mask = PMX_MCI_DATA8_15_MASK,
2022 .val = PMX_MCI_DATA8_15_MASK,
2023 }, {
2024 .reg = PAD_DIRECTION_SEL_1,
2025 .mask = PMX_PCI_REG1_MASK,
2026 .val = PMX_PCI_REG1_MASK,
2027 }, {
2028 .reg = PAD_DIRECTION_SEL_2,
2029 .mask = PMX_PCI_REG2_MASK,
2030 .val = PMX_PCI_REG2_MASK,
2031 },
2032 };
2033
2034 static struct spear_modemux pci_modemux[] = {
2035 {
2036 .muxregs = pci_muxreg,
2037 .nmuxregs = ARRAY_SIZE(pci_muxreg),
2038 },
2039 };
2040
2041 static struct spear_pingroup pci_pingroup = {
2042 .name = "pci_grp",
2043 .pins = pci_pins,
2044 .npins = ARRAY_SIZE(pci_pins),
2045 .modemuxs = pci_modemux,
2046 .nmodemuxs = ARRAY_SIZE(pci_modemux),
2047 };
2048
2049 static const char *const pci_grps[] = { "pci_grp" };
2050 static struct spear_function pci_function = {
2051 .name = "pci",
2052 .groups = pci_grps,
2053 .ngroups = ARRAY_SIZE(pci_grps),
2054 };
2055
2056 /* pad multiplexing for (fix-part) pcie0 device */
2057 static struct spear_muxreg pcie0_muxreg[] = {
2058 {
2059 .reg = PCIE_SATA_CFG,
2060 .mask = PCIE_CFG_VAL(0),
2061 .val = PCIE_CFG_VAL(0),
2062 },
2063 };
2064
2065 static struct spear_modemux pcie0_modemux[] = {
2066 {
2067 .muxregs = pcie0_muxreg,
2068 .nmuxregs = ARRAY_SIZE(pcie0_muxreg),
2069 },
2070 };
2071
2072 static struct spear_pingroup pcie0_pingroup = {
2073 .name = "pcie0_grp",
2074 .modemuxs = pcie0_modemux,
2075 .nmodemuxs = ARRAY_SIZE(pcie0_modemux),
2076 };
2077
2078 /* pad multiplexing for (fix-part) pcie1 device */
2079 static struct spear_muxreg pcie1_muxreg[] = {
2080 {
2081 .reg = PCIE_SATA_CFG,
2082 .mask = PCIE_CFG_VAL(1),
2083 .val = PCIE_CFG_VAL(1),
2084 },
2085 };
2086
2087 static struct spear_modemux pcie1_modemux[] = {
2088 {
2089 .muxregs = pcie1_muxreg,
2090 .nmuxregs = ARRAY_SIZE(pcie1_muxreg),
2091 },
2092 };
2093
2094 static struct spear_pingroup pcie1_pingroup = {
2095 .name = "pcie1_grp",
2096 .modemuxs = pcie1_modemux,
2097 .nmodemuxs = ARRAY_SIZE(pcie1_modemux),
2098 };
2099
2100 /* pad multiplexing for (fix-part) pcie2 device */
2101 static struct spear_muxreg pcie2_muxreg[] = {
2102 {
2103 .reg = PCIE_SATA_CFG,
2104 .mask = PCIE_CFG_VAL(2),
2105 .val = PCIE_CFG_VAL(2),
2106 },
2107 };
2108
2109 static struct spear_modemux pcie2_modemux[] = {
2110 {
2111 .muxregs = pcie2_muxreg,
2112 .nmuxregs = ARRAY_SIZE(pcie2_muxreg),
2113 },
2114 };
2115
2116 static struct spear_pingroup pcie2_pingroup = {
2117 .name = "pcie2_grp",
2118 .modemuxs = pcie2_modemux,
2119 .nmodemuxs = ARRAY_SIZE(pcie2_modemux),
2120 };
2121
2122 static const char *const pcie_grps[] = { "pcie0_grp", "pcie1_grp", "pcie2_grp"
2123 };
2124 static struct spear_function pcie_function = {
2125 .name = "pci_express",
2126 .groups = pcie_grps,
2127 .ngroups = ARRAY_SIZE(pcie_grps),
2128 };
2129
2130 /* pad multiplexing for sata0 device */
2131 static struct spear_muxreg sata0_muxreg[] = {
2132 {
2133 .reg = PCIE_SATA_CFG,
2134 .mask = SATA_CFG_VAL(0),
2135 .val = SATA_CFG_VAL(0),
2136 },
2137 };
2138
2139 static struct spear_modemux sata0_modemux[] = {
2140 {
2141 .muxregs = sata0_muxreg,
2142 .nmuxregs = ARRAY_SIZE(sata0_muxreg),
2143 },
2144 };
2145
2146 static struct spear_pingroup sata0_pingroup = {
2147 .name = "sata0_grp",
2148 .modemuxs = sata0_modemux,
2149 .nmodemuxs = ARRAY_SIZE(sata0_modemux),
2150 };
2151
2152 /* pad multiplexing for sata1 device */
2153 static struct spear_muxreg sata1_muxreg[] = {
2154 {
2155 .reg = PCIE_SATA_CFG,
2156 .mask = SATA_CFG_VAL(1),
2157 .val = SATA_CFG_VAL(1),
2158 },
2159 };
2160
2161 static struct spear_modemux sata1_modemux[] = {
2162 {
2163 .muxregs = sata1_muxreg,
2164 .nmuxregs = ARRAY_SIZE(sata1_muxreg),
2165 },
2166 };
2167
2168 static struct spear_pingroup sata1_pingroup = {
2169 .name = "sata1_grp",
2170 .modemuxs = sata1_modemux,
2171 .nmodemuxs = ARRAY_SIZE(sata1_modemux),
2172 };
2173
2174 /* pad multiplexing for sata2 device */
2175 static struct spear_muxreg sata2_muxreg[] = {
2176 {
2177 .reg = PCIE_SATA_CFG,
2178 .mask = SATA_CFG_VAL(2),
2179 .val = SATA_CFG_VAL(2),
2180 },
2181 };
2182
2183 static struct spear_modemux sata2_modemux[] = {
2184 {
2185 .muxregs = sata2_muxreg,
2186 .nmuxregs = ARRAY_SIZE(sata2_muxreg),
2187 },
2188 };
2189
2190 static struct spear_pingroup sata2_pingroup = {
2191 .name = "sata2_grp",
2192 .modemuxs = sata2_modemux,
2193 .nmodemuxs = ARRAY_SIZE(sata2_modemux),
2194 };
2195
2196 static const char *const sata_grps[] = { "sata0_grp", "sata1_grp", "sata2_grp"
2197 };
2198 static struct spear_function sata_function = {
2199 .name = "sata",
2200 .groups = sata_grps,
2201 .ngroups = ARRAY_SIZE(sata_grps),
2202 };
2203
2204 /* Pad multiplexing for ssp1_dis_kbd device */
2205 static const unsigned ssp1_dis_kbd_pins[] = { 203, 204, 205, 206 };
2206 static struct spear_muxreg ssp1_dis_kbd_muxreg[] = {
2207 {
2208 .reg = PAD_FUNCTION_EN_1,
2209 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2210 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2211 PMX_NFCE2_MASK,
2212 .val = 0,
2213 }, {
2214 .reg = PAD_DIRECTION_SEL_1,
2215 .mask = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2216 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2217 PMX_NFCE2_MASK,
2218 .val = PMX_KBD_ROWCOL25_MASK | PMX_KBD_COL1_MASK |
2219 PMX_KBD_COL0_MASK | PMX_NFIO8_15_MASK | PMX_NFCE1_MASK |
2220 PMX_NFCE2_MASK,
2221 },
2222 };
2223
2224 static struct spear_modemux ssp1_dis_kbd_modemux[] = {
2225 {
2226 .muxregs = ssp1_dis_kbd_muxreg,
2227 .nmuxregs = ARRAY_SIZE(ssp1_dis_kbd_muxreg),
2228 },
2229 };
2230
2231 static struct spear_pingroup ssp1_dis_kbd_pingroup = {
2232 .name = "ssp1_dis_kbd_grp",
2233 .pins = ssp1_dis_kbd_pins,
2234 .npins = ARRAY_SIZE(ssp1_dis_kbd_pins),
2235 .modemuxs = ssp1_dis_kbd_modemux,
2236 .nmodemuxs = ARRAY_SIZE(ssp1_dis_kbd_modemux),
2237 };
2238
2239 /* Pad multiplexing for ssp1_dis_sd device */
2240 static const unsigned ssp1_dis_sd_pins[] = { 224, 226, 227, 228 };
2241 static struct spear_muxreg ssp1_dis_sd_muxreg[] = {
2242 {
2243 .reg = PAD_FUNCTION_EN_2,
2244 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2245 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2246 .val = 0,
2247 }, {
2248 .reg = PAD_DIRECTION_SEL_2,
2249 .mask = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2250 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2251 .val = PMX_MCIADDR0ALE_MASK | PMX_MCIADDR2_MASK |
2252 PMX_MCICECF_MASK | PMX_MCICEXD_MASK,
2253 },
2254 };
2255
2256 static struct spear_modemux ssp1_dis_sd_modemux[] = {
2257 {
2258 .muxregs = ssp1_dis_sd_muxreg,
2259 .nmuxregs = ARRAY_SIZE(ssp1_dis_sd_muxreg),
2260 },
2261 };
2262
2263 static struct spear_pingroup ssp1_dis_sd_pingroup = {
2264 .name = "ssp1_dis_sd_grp",
2265 .pins = ssp1_dis_sd_pins,
2266 .npins = ARRAY_SIZE(ssp1_dis_sd_pins),
2267 .modemuxs = ssp1_dis_sd_modemux,
2268 .nmodemuxs = ARRAY_SIZE(ssp1_dis_sd_modemux),
2269 };
2270
2271 static const char *const ssp1_grps[] = { "ssp1_dis_kbd_grp",
2272 "ssp1_dis_sd_grp" };
2273 static struct spear_function ssp1_function = {
2274 .name = "ssp1",
2275 .groups = ssp1_grps,
2276 .ngroups = ARRAY_SIZE(ssp1_grps),
2277 };
2278
2279 /* Pad multiplexing for gpt64 device */
2280 static const unsigned gpt64_pins[] = { 230, 231, 232, 245 };
2281 static struct spear_muxreg gpt64_muxreg[] = {
2282 {
2283 .reg = PAD_FUNCTION_EN_2,
2284 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2285 | PMX_MCILEDS_MASK,
2286 .val = 0,
2287 }, {
2288 .reg = PAD_DIRECTION_SEL_2,
2289 .mask = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2290 | PMX_MCILEDS_MASK,
2291 .val = PMX_MCICDCF1_MASK | PMX_MCICDCF2_MASK | PMX_MCICDXD_MASK
2292 | PMX_MCILEDS_MASK,
2293 },
2294 };
2295
2296 static struct spear_modemux gpt64_modemux[] = {
2297 {
2298 .muxregs = gpt64_muxreg,
2299 .nmuxregs = ARRAY_SIZE(gpt64_muxreg),
2300 },
2301 };
2302
2303 static struct spear_pingroup gpt64_pingroup = {
2304 .name = "gpt64_grp",
2305 .pins = gpt64_pins,
2306 .npins = ARRAY_SIZE(gpt64_pins),
2307 .modemuxs = gpt64_modemux,
2308 .nmodemuxs = ARRAY_SIZE(gpt64_modemux),
2309 };
2310
2311 static const char *const gpt64_grps[] = { "gpt64_grp" };
2312 static struct spear_function gpt64_function = {
2313 .name = "gpt64",
2314 .groups = gpt64_grps,
2315 .ngroups = ARRAY_SIZE(gpt64_grps),
2316 };
2317
2318 /* pingroups */
2319 static struct spear_pingroup *spear1310_pingroups[] = {
2320 &i2c0_pingroup,
2321 &ssp0_pingroup,
2322 &i2s0_pingroup,
2323 &i2s1_pingroup,
2324 &clcd_pingroup,
2325 &clcd_high_res_pingroup,
2326 &arm_gpio_pingroup,
2327 &smi_2_chips_pingroup,
2328 &smi_4_chips_pingroup,
2329 &gmii_pingroup,
2330 &rgmii_pingroup,
2331 &smii_0_1_2_pingroup,
2332 &ras_mii_txclk_pingroup,
2333 &nand_8bit_pingroup,
2334 &nand_16bit_pingroup,
2335 &nand_4_chips_pingroup,
2336 &keyboard_6x6_pingroup,
2337 &keyboard_rowcol6_8_pingroup,
2338 &uart0_pingroup,
2339 &uart0_modem_pingroup,
2340 &gpt0_tmr0_pingroup,
2341 &gpt0_tmr1_pingroup,
2342 &gpt1_tmr0_pingroup,
2343 &gpt1_tmr1_pingroup,
2344 &sdhci_pingroup,
2345 &cf_pingroup,
2346 &xd_pingroup,
2347 &touch_xy_pingroup,
2348 &ssp0_cs0_pingroup,
2349 &ssp0_cs1_2_pingroup,
2350 &uart_1_dis_i2c_pingroup,
2351 &uart_1_dis_sd_pingroup,
2352 &uart_2_3_pingroup,
2353 &uart_4_pingroup,
2354 &uart_5_pingroup,
2355 &rs485_0_1_tdm_0_1_pingroup,
2356 &i2c_1_2_pingroup,
2357 &i2c3_dis_smi_clcd_pingroup,
2358 &i2c3_dis_sd_i2s0_pingroup,
2359 &i2c_4_5_dis_smi_pingroup,
2360 &i2c4_dis_sd_pingroup,
2361 &i2c5_dis_sd_pingroup,
2362 &i2c_6_7_dis_kbd_pingroup,
2363 &i2c6_dis_sd_pingroup,
2364 &i2c7_dis_sd_pingroup,
2365 &can0_dis_nor_pingroup,
2366 &can0_dis_sd_pingroup,
2367 &can1_dis_sd_pingroup,
2368 &can1_dis_kbd_pingroup,
2369 &pci_pingroup,
2370 &pcie0_pingroup,
2371 &pcie1_pingroup,
2372 &pcie2_pingroup,
2373 &sata0_pingroup,
2374 &sata1_pingroup,
2375 &sata2_pingroup,
2376 &ssp1_dis_kbd_pingroup,
2377 &ssp1_dis_sd_pingroup,
2378 &gpt64_pingroup,
2379 };
2380
2381 /* functions */
2382 static struct spear_function *spear1310_functions[] = {
2383 &i2c0_function,
2384 &ssp0_function,
2385 &i2s0_function,
2386 &i2s1_function,
2387 &clcd_function,
2388 &arm_gpio_function,
2389 &smi_function,
2390 &gmii_function,
2391 &rgmii_function,
2392 &smii_0_1_2_function,
2393 &ras_mii_txclk_function,
2394 &nand_function,
2395 &keyboard_function,
2396 &uart0_function,
2397 &gpt0_function,
2398 &gpt1_function,
2399 &sdhci_function,
2400 &cf_function,
2401 &xd_function,
2402 &touch_xy_function,
2403 &uart1_function,
2404 &uart2_3_function,
2405 &uart4_function,
2406 &uart5_function,
2407 &rs485_0_1_tdm_0_1_function,
2408 &i2c_1_2_function,
2409 &i2c3_unction,
2410 &i2c_4_5_function,
2411 &i2c_6_7_function,
2412 &can0_function,
2413 &can1_function,
2414 &pci_function,
2415 &pcie_function,
2416 &sata_function,
2417 &ssp1_function,
2418 &gpt64_function,
2419 };
2420
2421 static const unsigned pin18[] = { 18, };
2422 static const unsigned pin19[] = { 19, };
2423 static const unsigned pin20[] = { 20, };
2424 static const unsigned pin21[] = { 21, };
2425 static const unsigned pin22[] = { 22, };
2426 static const unsigned pin23[] = { 23, };
2427 static const unsigned pin54[] = { 54, };
2428 static const unsigned pin55[] = { 55, };
2429 static const unsigned pin56[] = { 56, };
2430 static const unsigned pin57[] = { 57, };
2431 static const unsigned pin58[] = { 58, };
2432 static const unsigned pin59[] = { 59, };
2433 static const unsigned pin60[] = { 60, };
2434 static const unsigned pin61[] = { 61, };
2435 static const unsigned pin62[] = { 62, };
2436 static const unsigned pin63[] = { 63, };
2437 static const unsigned pin143[] = { 143, };
2438 static const unsigned pin144[] = { 144, };
2439 static const unsigned pin145[] = { 145, };
2440 static const unsigned pin146[] = { 146, };
2441 static const unsigned pin147[] = { 147, };
2442 static const unsigned pin148[] = { 148, };
2443 static const unsigned pin149[] = { 149, };
2444 static const unsigned pin150[] = { 150, };
2445 static const unsigned pin151[] = { 151, };
2446 static const unsigned pin152[] = { 152, };
2447 static const unsigned pin205[] = { 205, };
2448 static const unsigned pin206[] = { 206, };
2449 static const unsigned pin211[] = { 211, };
2450 static const unsigned pin212[] = { 212, };
2451 static const unsigned pin213[] = { 213, };
2452 static const unsigned pin214[] = { 214, };
2453 static const unsigned pin215[] = { 215, };
2454 static const unsigned pin216[] = { 216, };
2455 static const unsigned pin217[] = { 217, };
2456 static const unsigned pin218[] = { 218, };
2457 static const unsigned pin219[] = { 219, };
2458 static const unsigned pin220[] = { 220, };
2459 static const unsigned pin221[] = { 221, };
2460 static const unsigned pin222[] = { 222, };
2461 static const unsigned pin223[] = { 223, };
2462 static const unsigned pin224[] = { 224, };
2463 static const unsigned pin225[] = { 225, };
2464 static const unsigned pin226[] = { 226, };
2465 static const unsigned pin227[] = { 227, };
2466 static const unsigned pin228[] = { 228, };
2467 static const unsigned pin229[] = { 229, };
2468 static const unsigned pin230[] = { 230, };
2469 static const unsigned pin231[] = { 231, };
2470 static const unsigned pin232[] = { 232, };
2471 static const unsigned pin233[] = { 233, };
2472 static const unsigned pin234[] = { 234, };
2473 static const unsigned pin235[] = { 235, };
2474 static const unsigned pin236[] = { 236, };
2475 static const unsigned pin237[] = { 237, };
2476 static const unsigned pin238[] = { 238, };
2477 static const unsigned pin239[] = { 239, };
2478 static const unsigned pin240[] = { 240, };
2479 static const unsigned pin241[] = { 241, };
2480 static const unsigned pin242[] = { 242, };
2481 static const unsigned pin243[] = { 243, };
2482 static const unsigned pin244[] = { 244, };
2483 static const unsigned pin245[] = { 245, };
2484
2485 static const unsigned pin_grp0[] = { 173, 174, };
2486 static const unsigned pin_grp1[] = { 175, 185, 188, 197, 198, };
2487 static const unsigned pin_grp2[] = { 176, 177, 178, 179, 184, 186, 187, 189,
2488 190, 191, 192, };
2489 static const unsigned pin_grp3[] = { 180, 181, 182, 183, 193, 194, 195, 196, };
2490 static const unsigned pin_grp4[] = { 199, 200, };
2491 static const unsigned pin_grp5[] = { 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74,
2492 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, };
2493 static const unsigned pin_grp6[] = { 86, 87, 88, 89, 90, 91, 92, 93, };
2494 static const unsigned pin_grp7[] = { 98, 99, };
2495 static const unsigned pin_grp8[] = { 158, 159, 160, 161, 162, 163, 164, 165,
2496 166, 167, 168, 169, 170, 171, 172, };
2497
2498 /* Define muxreg arrays */
2499 DEFINE_2_MUXREG(i2c0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2C0_MASK, 0, 1);
2500 DEFINE_2_MUXREG(ssp0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SSP0_MASK, 0, 1);
2501 DEFINE_2_MUXREG(ssp0_cs0_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS0_MASK, 0, 1);
2502 DEFINE_2_MUXREG(ssp0_cs1_2_pins, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_SSP0_CS1_2_MASK, 0, 1);
2503 DEFINE_2_MUXREG(i2s0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_I2S0_MASK, 0, 1);
2504 DEFINE_2_MUXREG(i2s1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_I2S1_MASK, 0, 1);
2505 DEFINE_2_MUXREG(clcd_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_CLCD1_MASK, 0, 1);
2506 DEFINE_2_MUXREG(clcd_high_res_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_CLCD2_MASK, 0, 1);
2507 DEFINE_2_MUXREG(pin18, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO15_MASK, 0, 1);
2508 DEFINE_2_MUXREG(pin19, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO14_MASK, 0, 1);
2509 DEFINE_2_MUXREG(pin20, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO13_MASK, 0, 1);
2510 DEFINE_2_MUXREG(pin21, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO12_MASK, 0, 1);
2511 DEFINE_2_MUXREG(pin22, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO11_MASK, 0, 1);
2512 DEFINE_2_MUXREG(pin23, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO10_MASK, 0, 1);
2513 DEFINE_2_MUXREG(pin143, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO00_MASK, 0, 1);
2514 DEFINE_2_MUXREG(pin144, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO01_MASK, 0, 1);
2515 DEFINE_2_MUXREG(pin145, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO02_MASK, 0, 1);
2516 DEFINE_2_MUXREG(pin146, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO03_MASK, 0, 1);
2517 DEFINE_2_MUXREG(pin147, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO04_MASK, 0, 1);
2518 DEFINE_2_MUXREG(pin148, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO05_MASK, 0, 1);
2519 DEFINE_2_MUXREG(pin149, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO06_MASK, 0, 1);
2520 DEFINE_2_MUXREG(pin150, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO07_MASK, 0, 1);
2521 DEFINE_2_MUXREG(pin151, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO08_MASK, 0, 1);
2522 DEFINE_2_MUXREG(pin152, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_EGPIO09_MASK, 0, 1);
2523 DEFINE_2_MUXREG(smi_2_chips_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_SMI_MASK, 0, 1);
2524 DEFINE_2_MUXREG(pin54, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS3_MASK, 0, 1);
2525 DEFINE_2_MUXREG(pin55, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_SMINCS2_MASK, 0, 1);
2526 DEFINE_2_MUXREG(pin56, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFRSTPWDWN3_MASK, 0, 1);
2527 DEFINE_2_MUXREG(pin57, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN2_MASK, 0, 1);
2528 DEFINE_2_MUXREG(pin58, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN1_MASK, 0, 1);
2529 DEFINE_2_MUXREG(pin59, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFRSTPWDWN0_MASK, 0, 1);
2530 DEFINE_2_MUXREG(pin60, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFWPRT3_MASK, 0, 1);
2531 DEFINE_2_MUXREG(pin61, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFCE3_MASK, 0, 1);
2532 DEFINE_2_MUXREG(pin62, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD25_MASK, 0, 1);
2533 DEFINE_2_MUXREG(pin63, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD24_MASK, 0, 1);
2534 DEFINE_2_MUXREG(pin_grp0, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICLK_MASK, 0, 1);
2535 DEFINE_2_MUXREG(pin_grp1, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIICOL_CRS_XFERER_MIITXCLK_MASK, 0, 1);
2536 DEFINE_2_MUXREG(pin_grp2, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_RXCLK_RDV_TXEN_D03_MASK, 0, 1);
2537 DEFINE_2_MUXREG(pin_grp3, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_GMIID47_MASK, 0, 1);
2538 DEFINE_2_MUXREG(pin_grp4, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MDC_MDIO_MASK, 0, 1);
2539 DEFINE_2_MUXREG(pin_grp5, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_NFAD23_MASK, 0, 1);
2540 DEFINE_2_MUXREG(pin_grp6, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_MCI_DATA8_15_MASK, 0, 1);
2541 DEFINE_2_MUXREG(pin_grp7, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NFCE2_MASK, 0, 1);
2542 DEFINE_2_MUXREG(pin_grp8, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND8_MASK, 0, 1);
2543 DEFINE_2_MUXREG(nand_16bit_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_NAND16BIT_1_MASK, 0, 1);
2544 DEFINE_2_MUXREG(pin205, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL1_MASK | PMX_NFCE1_MASK, 0, 1);
2545 DEFINE_2_MUXREG(pin206, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_COL0_MASK | PMX_NFCE2_MASK, 0, 1);
2546 DEFINE_2_MUXREG(pin211, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW1_MASK | PMX_NFWPRT1_MASK, 0, 1);
2547 DEFINE_2_MUXREG(pin212, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROW0_MASK | PMX_NFWPRT2_MASK, 0, 1);
2548 DEFINE_2_MUXREG(pin213, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA0_MASK, 0, 1);
2549 DEFINE_2_MUXREG(pin214, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA1_MASK, 0, 1);
2550 DEFINE_2_MUXREG(pin215, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA2_MASK, 0, 1);
2551 DEFINE_2_MUXREG(pin216, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA3_MASK, 0, 1);
2552 DEFINE_2_MUXREG(pin217, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_MCIDATA4_MASK, 0, 1);
2553 DEFINE_2_MUXREG(pin218, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA5_MASK, 0, 1);
2554 DEFINE_2_MUXREG(pin219, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA6_MASK, 0, 1);
2555 DEFINE_2_MUXREG(pin220, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA7_MASK, 0, 1);
2556 DEFINE_2_MUXREG(pin221, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA1SD_MASK, 0, 1);
2557 DEFINE_2_MUXREG(pin222, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA2SD_MASK, 0, 1);
2558 DEFINE_2_MUXREG(pin223, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATA3SD_MASK, 0, 1);
2559 DEFINE_2_MUXREG(pin224, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR0ALE_MASK, 0, 1);
2560 DEFINE_2_MUXREG(pin225, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR1CLECLK_MASK, 0, 1);
2561 DEFINE_2_MUXREG(pin226, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIADDR2_MASK, 0, 1);
2562 DEFINE_2_MUXREG(pin227, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICECF_MASK, 0, 1);
2563 DEFINE_2_MUXREG(pin228, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICEXD_MASK, 0, 1);
2564 DEFINE_2_MUXREG(pin229, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICESDMMC_MASK, 0, 1);
2565 DEFINE_2_MUXREG(pin230, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF1_MASK, 0, 1);
2566 DEFINE_2_MUXREG(pin231, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDCF2_MASK, 0, 1);
2567 DEFINE_2_MUXREG(pin232, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDXD_MASK, 0, 1);
2568 DEFINE_2_MUXREG(pin233, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICDSDMMC_MASK, 0, 1);
2569 DEFINE_2_MUXREG(pin234, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDATADIR_MASK, 0, 1);
2570 DEFINE_2_MUXREG(pin235, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMARQWP_MASK, 0, 1);
2571 DEFINE_2_MUXREG(pin236, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDRE_MASK, 0, 1);
2572 DEFINE_2_MUXREG(pin237, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIOWRWE_MASK, 0, 1);
2573 DEFINE_2_MUXREG(pin238, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIRESETCF_MASK, 0, 1);
2574 DEFINE_2_MUXREG(pin239, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS0CE_MASK, 0, 1);
2575 DEFINE_2_MUXREG(pin240, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICFINTR_MASK, 0, 1);
2576 DEFINE_2_MUXREG(pin241, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIIORDY_MASK, 0, 1);
2577 DEFINE_2_MUXREG(pin242, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCICS1_MASK, 0, 1);
2578 DEFINE_2_MUXREG(pin243, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCIDMAACK_MASK, 0, 1);
2579 DEFINE_2_MUXREG(pin244, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCISDCMD_MASK, 0, 1);
2580 DEFINE_2_MUXREG(pin245, PAD_FUNCTION_EN_2, PAD_DIRECTION_SEL_2, PMX_MCILEDS_MASK, 0, 1);
2581 DEFINE_2_MUXREG(keyboard_rowcol6_8_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_KBD_ROWCOL68_MASK, 0, 1);
2582 DEFINE_2_MUXREG(uart0_pins, PAD_FUNCTION_EN_0, PAD_DIRECTION_SEL_0, PMX_UART0_MASK, 0, 1);
2583 DEFINE_2_MUXREG(uart0_modem_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_UART0_MODEM_MASK, 0, 1);
2584 DEFINE_2_MUXREG(gpt0_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR0_MASK, 0, 1);
2585 DEFINE_2_MUXREG(gpt0_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT0_TMR1_MASK, 0, 1);
2586 DEFINE_2_MUXREG(gpt1_tmr0_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR0_MASK, 0, 1);
2587 DEFINE_2_MUXREG(gpt1_tmr1_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_GPT1_TMR1_MASK, 0, 1);
2588 DEFINE_2_MUXREG(touch_xy_pins, PAD_FUNCTION_EN_1, PAD_DIRECTION_SEL_1, PMX_TOUCH_XY_MASK, 0, 1);
2589
2590 static struct spear_gpio_pingroup spear1310_gpio_pingroup[] = {
2591 GPIO_PINGROUP(i2c0_pins),
2592 GPIO_PINGROUP(ssp0_pins),
2593 GPIO_PINGROUP(ssp0_cs0_pins),
2594 GPIO_PINGROUP(ssp0_cs1_2_pins),
2595 GPIO_PINGROUP(i2s0_pins),
2596 GPIO_PINGROUP(i2s1_pins),
2597 GPIO_PINGROUP(clcd_pins),
2598 GPIO_PINGROUP(clcd_high_res_pins),
2599 GPIO_PINGROUP(pin18),
2600 GPIO_PINGROUP(pin19),
2601 GPIO_PINGROUP(pin20),
2602 GPIO_PINGROUP(pin21),
2603 GPIO_PINGROUP(pin22),
2604 GPIO_PINGROUP(pin23),
2605 GPIO_PINGROUP(pin143),
2606 GPIO_PINGROUP(pin144),
2607 GPIO_PINGROUP(pin145),
2608 GPIO_PINGROUP(pin146),
2609 GPIO_PINGROUP(pin147),
2610 GPIO_PINGROUP(pin148),
2611 GPIO_PINGROUP(pin149),
2612 GPIO_PINGROUP(pin150),
2613 GPIO_PINGROUP(pin151),
2614 GPIO_PINGROUP(pin152),
2615 GPIO_PINGROUP(smi_2_chips_pins),
2616 GPIO_PINGROUP(pin54),
2617 GPIO_PINGROUP(pin55),
2618 GPIO_PINGROUP(pin56),
2619 GPIO_PINGROUP(pin57),
2620 GPIO_PINGROUP(pin58),
2621 GPIO_PINGROUP(pin59),
2622 GPIO_PINGROUP(pin60),
2623 GPIO_PINGROUP(pin61),
2624 GPIO_PINGROUP(pin62),
2625 GPIO_PINGROUP(pin63),
2626 GPIO_PINGROUP(pin_grp0),
2627 GPIO_PINGROUP(pin_grp1),
2628 GPIO_PINGROUP(pin_grp2),
2629 GPIO_PINGROUP(pin_grp3),
2630 GPIO_PINGROUP(pin_grp4),
2631 GPIO_PINGROUP(pin_grp5),
2632 GPIO_PINGROUP(pin_grp6),
2633 GPIO_PINGROUP(pin_grp7),
2634 GPIO_PINGROUP(pin_grp8),
2635 GPIO_PINGROUP(nand_16bit_pins),
2636 GPIO_PINGROUP(pin205),
2637 GPIO_PINGROUP(pin206),
2638 GPIO_PINGROUP(pin211),
2639 GPIO_PINGROUP(pin212),
2640 GPIO_PINGROUP(pin213),
2641 GPIO_PINGROUP(pin214),
2642 GPIO_PINGROUP(pin215),
2643 GPIO_PINGROUP(pin216),
2644 GPIO_PINGROUP(pin217),
2645 GPIO_PINGROUP(pin218),
2646 GPIO_PINGROUP(pin219),
2647 GPIO_PINGROUP(pin220),
2648 GPIO_PINGROUP(pin221),
2649 GPIO_PINGROUP(pin222),
2650 GPIO_PINGROUP(pin223),
2651 GPIO_PINGROUP(pin224),
2652 GPIO_PINGROUP(pin225),
2653 GPIO_PINGROUP(pin226),
2654 GPIO_PINGROUP(pin227),
2655 GPIO_PINGROUP(pin228),
2656 GPIO_PINGROUP(pin229),
2657 GPIO_PINGROUP(pin230),
2658 GPIO_PINGROUP(pin231),
2659 GPIO_PINGROUP(pin232),
2660 GPIO_PINGROUP(pin233),
2661 GPIO_PINGROUP(pin234),
2662 GPIO_PINGROUP(pin235),
2663 GPIO_PINGROUP(pin236),
2664 GPIO_PINGROUP(pin237),
2665 GPIO_PINGROUP(pin238),
2666 GPIO_PINGROUP(pin239),
2667 GPIO_PINGROUP(pin240),
2668 GPIO_PINGROUP(pin241),
2669 GPIO_PINGROUP(pin242),
2670 GPIO_PINGROUP(pin243),
2671 GPIO_PINGROUP(pin244),
2672 GPIO_PINGROUP(pin245),
2673 GPIO_PINGROUP(keyboard_rowcol6_8_pins),
2674 GPIO_PINGROUP(uart0_pins),
2675 GPIO_PINGROUP(uart0_modem_pins),
2676 GPIO_PINGROUP(gpt0_tmr0_pins),
2677 GPIO_PINGROUP(gpt0_tmr1_pins),
2678 GPIO_PINGROUP(gpt1_tmr0_pins),
2679 GPIO_PINGROUP(gpt1_tmr1_pins),
2680 GPIO_PINGROUP(touch_xy_pins),
2681 };
2682
2683 static struct spear_pinctrl_machdata spear1310_machdata = {
2684 .pins = spear1310_pins,
2685 .npins = ARRAY_SIZE(spear1310_pins),
2686 .groups = spear1310_pingroups,
2687 .ngroups = ARRAY_SIZE(spear1310_pingroups),
2688 .functions = spear1310_functions,
2689 .nfunctions = ARRAY_SIZE(spear1310_functions),
2690 .gpio_pingroups = spear1310_gpio_pingroup,
2691 .ngpio_pingroups = ARRAY_SIZE(spear1310_gpio_pingroup),
2692 .modes_supported = false,
2693 };
2694
2695 static struct of_device_id spear1310_pinctrl_of_match[] = {
2696 {
2697 .compatible = "st,spear1310-pinmux",
2698 },
2699 {},
2700 };
2701
2702 static int spear1310_pinctrl_probe(struct platform_device *pdev)
2703 {
2704 return spear_pinctrl_probe(pdev, &spear1310_machdata);
2705 }
2706
2707 static int spear1310_pinctrl_remove(struct platform_device *pdev)
2708 {
2709 return spear_pinctrl_remove(pdev);
2710 }
2711
2712 static struct platform_driver spear1310_pinctrl_driver = {
2713 .driver = {
2714 .name = DRIVER_NAME,
2715 .owner = THIS_MODULE,
2716 .of_match_table = spear1310_pinctrl_of_match,
2717 },
2718 .probe = spear1310_pinctrl_probe,
2719 .remove = spear1310_pinctrl_remove,
2720 };
2721
2722 static int __init spear1310_pinctrl_init(void)
2723 {
2724 return platform_driver_register(&spear1310_pinctrl_driver);
2725 }
2726 arch_initcall(spear1310_pinctrl_init);
2727
2728 static void __exit spear1310_pinctrl_exit(void)
2729 {
2730 platform_driver_unregister(&spear1310_pinctrl_driver);
2731 }
2732 module_exit(spear1310_pinctrl_exit);
2733
2734 MODULE_AUTHOR("Viresh Kumar <viresh.linux@gmail.com>");
2735 MODULE_DESCRIPTION("ST Microelectronics SPEAr1310 pinctrl driver");
2736 MODULE_LICENSE("GPL v2");
2737 MODULE_DEVICE_TABLE(of, spear1310_pinctrl_of_match);
Linux with added FPC-III support