drivers/scsi/be2iscsi/be_main.h

   1 /**
   2  * Copyright (C) 2005 - 2013 Emulex
   3  * All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License version 2
   7  * as published by the Free Software Foundation.  The full GNU General
   8  * Public License is included in this distribution in the file called COPYING.
   9  *
  10  * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11  *
  12  * Contact Information:
  13  * linux-drivers@emulex.com
  14  *
  15  * Emulex
  16  * 3333 Susan Street
  17  * Costa Mesa, CA 92626
  18  */
  19
  20 #ifndef _BEISCSI_MAIN_
  21 #define _BEISCSI_MAIN_
  22
  23 #include <linux/kernel.h>
  24 #include <linux/pci.h>
  25 #include <linux/if_ether.h>
  26 #include <linux/in.h>
  27 #include <linux/ctype.h>
  28 #include <linux/module.h>
  29 #include <linux/aer.h>
  30 #include <scsi/scsi.h>
  31 #include <scsi/scsi_cmnd.h>
  32 #include <scsi/scsi_device.h>
  33 #include <scsi/scsi_host.h>
  34 #include <scsi/iscsi_proto.h>
  35 #include <scsi/libiscsi.h>
  36 #include <scsi/scsi_transport_iscsi.h>
  37
  38 #define DRV_NAME                "be2iscsi"
  39 #define BUILD_STR               "10.0.659.0"
  40 #define BE_NAME                 "Emulex OneConnect" \
  41                                 "Open-iSCSI Driver version" BUILD_STR
  42 #define DRV_DESC                BE_NAME " " "Driver"
  43
  44 #define BE_VENDOR_ID            0x19A2
  45 #define ELX_VENDOR_ID           0x10DF
  46 /* DEVICE ID's for BE2 */
  47 #define BE_DEVICE_ID1           0x212
  48 #define OC_DEVICE_ID1           0x702
  49 #define OC_DEVICE_ID2           0x703
  50
  51 /* DEVICE ID's for BE3 */
  52 #define BE_DEVICE_ID2           0x222
  53 #define OC_DEVICE_ID3           0x712
  54
  55 /* DEVICE ID for SKH */
  56 #define OC_SKH_ID1              0x722
  57
  58 #define BE2_IO_DEPTH            1024
  59 #define BE2_MAX_SESSIONS        256
  60 #define BE2_CMDS_PER_CXN        128
  61 #define BE2_TMFS                16
  62 #define BE2_NOPOUT_REQ          16
  63 #define BE2_SGE                 32
  64 #define BE2_DEFPDU_HDR_SZ       64
  65 #define BE2_DEFPDU_DATA_SZ      8192
  66
  67 #define MAX_CPUS                64
  68 #define BEISCSI_MAX_NUM_CPUS    7
  69
  70 #define BEISCSI_VER_STRLEN 32
  71
  72 #define BEISCSI_SGLIST_ELEMENTS 30
  73
  74 #define BEISCSI_CMD_PER_LUN     128     /* scsi_host->cmd_per_lun */
  75 #define BEISCSI_MAX_SECTORS     2048    /* scsi_host->max_sectors */
  76 #define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
  77
  78 #define BEISCSI_MAX_CMD_LEN     16      /* scsi_host->max_cmd_len */
  79 #define BEISCSI_NUM_MAX_LUN     256     /* scsi_host->max_lun */
  80 #define BEISCSI_NUM_DEVICES_SUPPORTED   0x01
  81 #define BEISCSI_MAX_FRAGS_INIT  192
  82 #define BE_NUM_MSIX_ENTRIES     1
  83
  84 #define MPU_EP_CONTROL          0
  85 #define MPU_EP_SEMAPHORE        0xac
  86 #define BE2_SOFT_RESET          0x5c
  87 #define BE2_PCI_ONLINE0         0xb0
  88 #define BE2_PCI_ONLINE1         0xb4
  89 #define BE2_SET_RESET           0x80
  90 #define BE2_MPU_IRAM_ONLINE     0x00000080
  91
  92 #define BE_SENSE_INFO_SIZE              258
  93 #define BE_ISCSI_PDU_HEADER_SIZE        64
  94 #define BE_MIN_MEM_SIZE                 16384
  95 #define MAX_CMD_SZ                      65536
  96 #define IIOC_SCSI_DATA                  0x05    /* Write Operation */
  97
  98 #define INVALID_SESS_HANDLE     0xFFFFFFFF
  99
 100 #define BE_ADAPTER_LINK_UP      0x001
 101 #define BE_ADAPTER_LINK_DOWN    0x002
 102 #define BE_ADAPTER_PCI_ERR      0x004
 103
 104 #define BEISCSI_CLEAN_UNLOAD    0x01
 105 #define BEISCSI_EEH_UNLOAD      0x02
 106 /**
 107  * hardware needs the async PDU buffers to be posted in multiples of 8
 108  * So have atleast 8 of them by default
 109  */
 110
 111 #define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num)    \
 112         (phwi->phwi_ctxt->pasync_ctx[ulp_num])
 113
 114 /********* Memory BAR register ************/
 115 #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET      0xfc
 116 /**
 117  * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
 118  * Disable" may still globally block interrupts in addition to individual
 119  * interrupt masks; a mechanism for the device driver to block all interrupts
 120  * atomically without having to arbitrate for the PCI Interrupt Disable bit
 121  * with the OS.
 122  */
 123 #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK      (1 << 29)       /* bit 29 */
 124
 125 /********* ISR0 Register offset **********/
 126 #define CEV_ISR0_OFFSET                         0xC18
 127 #define CEV_ISR_SIZE                            4
 128
 129 /**
 130  * Macros for reading/writing a protection domain or CSR registers
 131  * in BladeEngine.
 132  */
 133
 134 #define DB_TXULP0_OFFSET 0x40
 135 #define DB_RXULP0_OFFSET 0xA0
 136 /********* Event Q door bell *************/
 137 #define DB_EQ_OFFSET                    DB_CQ_OFFSET
 138 #define DB_EQ_RING_ID_MASK              0x1FF   /* bits 0 - 8 */
 139 /* Clear the interrupt for this eq */
 140 #define DB_EQ_CLR_SHIFT                 (9)     /* bit 9 */
 141 /* Must be 1 */
 142 #define DB_EQ_EVNT_SHIFT                (10)    /* bit 10 */
 143 /* Number of event entries processed */
 144 #define DB_EQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 145 /* Rearm bit */
 146 #define DB_EQ_REARM_SHIFT               (29)    /* bit 29 */
 147
 148 /********* Compl Q door bell *************/
 149 #define DB_CQ_OFFSET                    0x120
 150 #define DB_CQ_RING_ID_MASK              0x3FF   /* bits 0 - 9 */
 151 /* Number of event entries processed */
 152 #define DB_CQ_NUM_POPPED_SHIFT          (16)    /* bits 16 - 28 */
 153 /* Rearm bit */
 154 #define DB_CQ_REARM_SHIFT               (29)    /* bit 29 */
 155
 156 #define GET_HWI_CONTROLLER_WS(pc)       (pc->phwi_ctrlr)
 157 #define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 158                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
 159 #define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
 160                 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
 161
 162 #define PAGES_REQUIRED(x) \
 163         ((x < PAGE_SIZE) ? 1 :  ((x + PAGE_SIZE - 1) / PAGE_SIZE))
 164
 165 #define BEISCSI_MSI_NAME 20 /* size of msi_name string */
 166
 167 #define MEM_DESCR_OFFSET 8
 168 #define BEISCSI_DEFQ_HDR 1
 169 #define BEISCSI_DEFQ_DATA 0
 170 enum be_mem_enum {
 171         HWI_MEM_ADDN_CONTEXT,
 172         HWI_MEM_WRB,
 173         HWI_MEM_WRBH,
 174         HWI_MEM_SGLH,
 175         HWI_MEM_SGE,
 176         HWI_MEM_TEMPLATE_HDR_ULP0,
 177         HWI_MEM_ASYNC_HEADER_BUF_ULP0,  /* 6 */
 178         HWI_MEM_ASYNC_DATA_BUF_ULP0,
 179         HWI_MEM_ASYNC_HEADER_RING_ULP0,
 180         HWI_MEM_ASYNC_DATA_RING_ULP0,
 181         HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
 182         HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
 183         HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
 184         HWI_MEM_TEMPLATE_HDR_ULP1,
 185         HWI_MEM_ASYNC_HEADER_BUF_ULP1,  /* 14 */
 186         HWI_MEM_ASYNC_DATA_BUF_ULP1,
 187         HWI_MEM_ASYNC_HEADER_RING_ULP1,
 188         HWI_MEM_ASYNC_DATA_RING_ULP1,
 189         HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
 190         HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
 191         HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
 192         ISCSI_MEM_GLOBAL_HEADER,
 193         SE_MEM_MAX
 194 };
 195
 196 struct be_bus_address32 {
 197         unsigned int address_lo;
 198         unsigned int address_hi;
 199 };
 200
 201 struct be_bus_address64 {
 202         unsigned long long address;
 203 };
 204
 205 struct be_bus_address {
 206         union {
 207                 struct be_bus_address32 a32;
 208                 struct be_bus_address64 a64;
 209         } u;
 210 };
 211
 212 struct mem_array {
 213         struct be_bus_address bus_address;      /* Bus address of location */
 214         void *virtual_address;          /* virtual address to the location */
 215         unsigned int size;              /* Size required by memory block */
 216 };
 217
 218 struct be_mem_descriptor {
 219         unsigned int index;     /* Index of this memory parameter */
 220         unsigned int category;  /* type indicates cached/non-cached */
 221         unsigned int num_elements;      /* number of elements in this
 222                                          * descriptor
 223                                          */
 224         unsigned int alignment_mask;    /* Alignment mask for this block */
 225         unsigned int size_in_bytes;     /* Size required by memory block */
 226         struct mem_array *mem_array;
 227 };
 228
 229 struct sgl_handle {
 230         unsigned int sgl_index;
 231         unsigned int type;
 232         unsigned int cid;
 233         struct iscsi_task *task;
 234         struct iscsi_sge *pfrag;
 235 };
 236
 237 struct hba_parameters {
 238         unsigned int ios_per_ctrl;
 239         unsigned int cxns_per_ctrl;
 240         unsigned int asyncpdus_per_ctrl;
 241         unsigned int icds_per_ctrl;
 242         unsigned int num_sge_per_io;
 243         unsigned int defpdu_hdr_sz;
 244         unsigned int defpdu_data_sz;
 245         unsigned int num_cq_entries;
 246         unsigned int num_eq_entries;
 247         unsigned int wrbs_per_cxn;
 248         unsigned int crashmode;
 249         unsigned int hba_num;
 250
 251         unsigned int mgmt_ws_sz;
 252         unsigned int hwi_ws_sz;
 253
 254         unsigned int eto;
 255         unsigned int ldto;
 256
 257         unsigned int dbg_flags;
 258         unsigned int num_cxn;
 259
 260         unsigned int eq_timer;
 261         /**
 262          * These are calculated from other params. They're here
 263          * for debug purposes
 264          */
 265         unsigned int num_mcc_pages;
 266         unsigned int num_mcc_cq_pages;
 267         unsigned int num_cq_pages;
 268         unsigned int num_eq_pages;
 269
 270         unsigned int num_async_pdu_buf_pages;
 271         unsigned int num_async_pdu_buf_sgl_pages;
 272         unsigned int num_async_pdu_buf_cq_pages;
 273
 274         unsigned int num_async_pdu_hdr_pages;
 275         unsigned int num_async_pdu_hdr_sgl_pages;
 276         unsigned int num_async_pdu_hdr_cq_pages;
 277
 278         unsigned int num_sge;
 279 };
 280
 281 struct invalidate_command_table {
 282         unsigned short icd;
 283         unsigned short cid;
 284 } __packed;
 285
 286 #define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
 287         (phwi_ctrlr->wrb_context[cri].ulp_num)
 288 struct hwi_wrb_context {
 289         struct list_head wrb_handle_list;
 290         struct list_head wrb_handle_drvr_list;
 291         struct wrb_handle **pwrb_handle_base;
 292         struct wrb_handle **pwrb_handle_basestd;
 293         struct iscsi_wrb *plast_wrb;
 294         unsigned short alloc_index;
 295         unsigned short free_index;
 296         unsigned short wrb_handles_available;
 297         unsigned short cid;
 298         uint8_t ulp_num;        /* ULP to which CID binded */
 299         uint16_t register_set;
 300         uint16_t doorbell_format;
 301         uint32_t doorbell_offset;
 302 };
 303
 304 struct ulp_cid_info {
 305         unsigned short *cid_array;
 306         unsigned short avlbl_cids;
 307         unsigned short cid_alloc;
 308         unsigned short cid_free;
 309 };
 310
 311 #include "be.h"
 312 #define chip_be2(phba)      (phba->generation == BE_GEN2)
 313 #define chip_be3_r(phba)    (phba->generation == BE_GEN3)
 314 #define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
 315
 316 #define BEISCSI_ULP0    0
 317 #define BEISCSI_ULP1    1
 318 #define BEISCSI_ULP_COUNT   2
 319 #define BEISCSI_ULP0_LOADED 0x01
 320 #define BEISCSI_ULP1_LOADED 0x02
 321
 322 #define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
 323         (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
 324 #define BEISCSI_ULP0_AVLBL_CID(phba) \
 325         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
 326 #define BEISCSI_ULP1_AVLBL_CID(phba) \
 327         BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
 328
 329 struct beiscsi_hba {
 330         struct hba_parameters params;
 331         struct hwi_controller *phwi_ctrlr;
 332         unsigned int mem_req[SE_MEM_MAX];
 333         /* PCI BAR mapped addresses */
 334         u8 __iomem *csr_va;     /* CSR */
 335         u8 __iomem *db_va;      /* Door  Bell  */
 336         u8 __iomem *pci_va;     /* PCI Config */
 337         struct be_bus_address csr_pa;   /* CSR */
 338         struct be_bus_address db_pa;    /* CSR */
 339         struct be_bus_address pci_pa;   /* CSR */
 340         /* PCI representation of our HBA */
 341         struct pci_dev *pcidev;
 342         unsigned short asic_revision;
 343         unsigned int num_cpus;
 344         unsigned int nxt_cqid;
 345         struct msix_entry msix_entries[MAX_CPUS];
 346         char *msi_name[MAX_CPUS];
 347         bool msix_enabled;
 348         struct be_mem_descriptor *init_mem;
 349
 350         unsigned short io_sgl_alloc_index;
 351         unsigned short io_sgl_free_index;
 352         unsigned short io_sgl_hndl_avbl;
 353         struct sgl_handle **io_sgl_hndl_base;
 354         struct sgl_handle **sgl_hndl_array;
 355
 356         unsigned short eh_sgl_alloc_index;
 357         unsigned short eh_sgl_free_index;
 358         unsigned short eh_sgl_hndl_avbl;
 359         struct sgl_handle **eh_sgl_hndl_base;
 360         spinlock_t io_sgl_lock;
 361         spinlock_t mgmt_sgl_lock;
 362         spinlock_t isr_lock;
 363         spinlock_t async_pdu_lock;
 364         unsigned int age;
 365         struct list_head hba_queue;
 366 #define BE_MAX_SESSION 2048
 367 #define BE_SET_CID_TO_CRI(cri_index, cid) \
 368                           (phba->cid_to_cri_map[cid] = cri_index)
 369 #define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
 370         unsigned short cid_to_cri_map[BE_MAX_SESSION];
 371         struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
 372         struct iscsi_endpoint **ep_array;
 373         struct beiscsi_conn **conn_table;
 374         struct iscsi_boot_kset *boot_kset;
 375         struct Scsi_Host *shost;
 376         struct iscsi_iface *ipv4_iface;
 377         struct iscsi_iface *ipv6_iface;
 378         struct {
 379                 /**
 380                  * group together since they are used most frequently
 381                  * for cid to cri conversion
 382                  */
 383                 unsigned int phys_port;
 384                 unsigned int eqid_count;
 385                 unsigned int cqid_count;
 386                 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
 387 #define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
 388                 (phba->fw_config.iscsi_cid_count[ulp_num])
 389                 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
 390                 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
 391                 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
 392                 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
 393                 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
 394
 395                 unsigned short iscsi_features;
 396                 uint16_t dual_ulp_aware;
 397                 unsigned long ulp_supported;
 398         } fw_config;
 399
 400         unsigned int state;
 401         bool fw_timeout;
 402         bool ue_detected;
 403         struct delayed_work beiscsi_hw_check_task;
 404
 405         bool mac_addr_set;
 406         u8 mac_address[ETH_ALEN];
 407         char fw_ver_str[BEISCSI_VER_STRLEN];
 408         char wq_name[20];
 409         struct workqueue_struct *wq;    /* The actuak work queue */
 410         struct be_ctrl_info ctrl;
 411         unsigned int generation;
 412         unsigned int interface_handle;
 413         struct mgmt_session_info boot_sess;
 414         struct invalidate_command_table inv_tbl[128];
 415
 416         unsigned int attr_log_enable;
 417         int (*iotask_fn)(struct iscsi_task *,
 418                         struct scatterlist *sg,
 419                         uint32_t num_sg, uint32_t xferlen,
 420                         uint32_t writedir);
 421 };
 422
 423 struct beiscsi_session {
 424         struct pci_pool *bhs_pool;
 425 };
 426
 427 /**
 428  * struct beiscsi_conn - iscsi connection structure
 429  */
 430 struct beiscsi_conn {
 431         struct iscsi_conn *conn;
 432         struct beiscsi_hba *phba;
 433         u32 exp_statsn;
 434         u32 doorbell_offset;
 435         u32 beiscsi_conn_cid;
 436         struct beiscsi_endpoint *ep;
 437         unsigned short login_in_progress;
 438         struct wrb_handle *plogin_wrb_handle;
 439         struct sgl_handle *plogin_sgl_handle;
 440         struct beiscsi_session *beiscsi_sess;
 441         struct iscsi_task *task;
 442 };
 443
 444 /* This structure is used by the chip */
 445 struct pdu_data_out {
 446         u32 dw[12];
 447 };
 448 /**
 449  * Pseudo amap definition in which each bit of the actual structure is defined
 450  * as a byte: used to calculate offset/shift/mask of each field
 451  */
 452 struct amap_pdu_data_out {
 453         u8 opcode[6];           /* opcode */
 454         u8 rsvd0[2];            /* should be 0 */
 455         u8 rsvd1[7];
 456         u8 final_bit;           /* F bit */
 457         u8 rsvd2[16];
 458         u8 ahs_length[8];       /* no AHS */
 459         u8 data_len_hi[8];
 460         u8 data_len_lo[16];     /* DataSegmentLength */
 461         u8 lun[64];
 462         u8 itt[32];             /* ITT; initiator task tag */
 463         u8 ttt[32];             /* TTT; valid for R2T or 0xffffffff */
 464         u8 rsvd3[32];
 465         u8 exp_stat_sn[32];
 466         u8 rsvd4[32];
 467         u8 data_sn[32];
 468         u8 buffer_offset[32];
 469         u8 rsvd5[32];
 470 };
 471
 472 struct be_cmd_bhs {
 473         struct iscsi_scsi_req iscsi_hdr;
 474         unsigned char pad1[16];
 475         struct pdu_data_out iscsi_data_pdu;
 476         unsigned char pad2[BE_SENSE_INFO_SIZE -
 477                         sizeof(struct pdu_data_out)];
 478 };
 479
 480 struct beiscsi_io_task {
 481         struct wrb_handle *pwrb_handle;
 482         struct sgl_handle *psgl_handle;
 483         struct beiscsi_conn *conn;
 484         struct scsi_cmnd *scsi_cmnd;
 485         unsigned int cmd_sn;
 486         unsigned int flags;
 487         unsigned short cid;
 488         unsigned short header_len;
 489         itt_t libiscsi_itt;
 490         struct be_cmd_bhs *cmd_bhs;
 491         struct be_bus_address bhs_pa;
 492         unsigned short bhs_len;
 493         dma_addr_t mtask_addr;
 494         uint32_t mtask_data_count;
 495         uint8_t wrb_type;
 496 };
 497
 498 struct be_nonio_bhs {
 499         struct iscsi_hdr iscsi_hdr;
 500         unsigned char pad1[16];
 501         struct pdu_data_out iscsi_data_pdu;
 502         unsigned char pad2[BE_SENSE_INFO_SIZE -
 503                         sizeof(struct pdu_data_out)];
 504 };
 505
 506 struct be_status_bhs {
 507         struct iscsi_scsi_req iscsi_hdr;
 508         unsigned char pad1[16];
 509         /**
 510          * The plus 2 below is to hold the sense info length that gets
 511          * DMA'ed by RxULP
 512          */
 513         unsigned char sense_info[BE_SENSE_INFO_SIZE];
 514 };
 515
 516 struct iscsi_sge {
 517         u32 dw[4];
 518 };
 519
 520 /**
 521  * Pseudo amap definition in which each bit of the actual structure is defined
 522  * as a byte: used to calculate offset/shift/mask of each field
 523  */
 524 struct amap_iscsi_sge {
 525         u8 addr_hi[32];
 526         u8 addr_lo[32];
 527         u8 sge_offset[22];      /* DWORD 2 */
 528         u8 rsvd0[9];            /* DWORD 2 */
 529         u8 last_sge;            /* DWORD 2 */
 530         u8 len[17];             /* DWORD 3 */
 531         u8 rsvd1[15];           /* DWORD 3 */
 532 };
 533
 534 struct beiscsi_offload_params {
 535         u32 dw[6];
 536 };
 537
 538 #define OFFLD_PARAMS_ERL        0x00000003
 539 #define OFFLD_PARAMS_DDE        0x00000004
 540 #define OFFLD_PARAMS_HDE        0x00000008
 541 #define OFFLD_PARAMS_IR2T       0x00000010
 542 #define OFFLD_PARAMS_IMD        0x00000020
 543 #define OFFLD_PARAMS_DATA_SEQ_INORDER   0x00000040
 544 #define OFFLD_PARAMS_PDU_SEQ_INORDER    0x00000080
 545 #define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
 546
 547 /**
 548  * Pseudo amap definition in which each bit of the actual structure is defined
 549  * as a byte: used to calculate offset/shift/mask of each field
 550  */
 551 struct amap_beiscsi_offload_params {
 552         u8 max_burst_length[32];
 553         u8 max_send_data_segment_length[32];
 554         u8 first_burst_length[32];
 555         u8 erl[2];
 556         u8 dde[1];
 557         u8 hde[1];
 558         u8 ir2t[1];
 559         u8 imd[1];
 560         u8 data_seq_inorder[1];
 561         u8 pdu_seq_inorder[1];
 562         u8 max_r2t[16];
 563         u8 pad[8];
 564         u8 exp_statsn[32];
 565         u8 max_recv_data_segment_length[32];
 566 };
 567
 568 /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
 569                 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
 570
 571 struct async_pdu_handle {
 572         struct list_head link;
 573         struct be_bus_address pa;
 574         void *pbuffer;
 575         unsigned int consumed;
 576         unsigned char index;
 577         unsigned char is_header;
 578         unsigned short cri;
 579         unsigned long buffer_len;
 580 };
 581
 582 struct hwi_async_entry {
 583         struct {
 584                 unsigned char hdr_received;
 585                 unsigned char hdr_len;
 586                 unsigned short bytes_received;
 587                 unsigned int bytes_needed;
 588                 struct list_head list;
 589         } wait_queue;
 590
 591         struct list_head header_busy_list;
 592         struct list_head data_busy_list;
 593 };
 594
 595 struct hwi_async_pdu_context {
 596         struct {
 597                 struct be_bus_address pa_base;
 598                 void *va_base;
 599                 void *ring_base;
 600                 struct async_pdu_handle *handle_base;
 601
 602                 unsigned int host_write_ptr;
 603                 unsigned int ep_read_ptr;
 604                 unsigned int writables;
 605
 606                 unsigned int free_entries;
 607                 unsigned int busy_entries;
 608
 609                 struct list_head free_list;
 610         } async_header;
 611
 612         struct {
 613                 struct be_bus_address pa_base;
 614                 void *va_base;
 615                 void *ring_base;
 616                 struct async_pdu_handle *handle_base;
 617
 618                 unsigned int host_write_ptr;
 619                 unsigned int ep_read_ptr;
 620                 unsigned int writables;
 621
 622                 unsigned int free_entries;
 623                 unsigned int busy_entries;
 624                 struct list_head free_list;
 625         } async_data;
 626
 627         unsigned int buffer_size;
 628         unsigned int num_entries;
 629 #define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
 630         unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
 631         /**
 632          * This is a varying size list! Do not add anything
 633          * after this entry!!
 634          */
 635         struct hwi_async_entry *async_entry;
 636 };
 637
 638 #define PDUCQE_CODE_MASK        0x0000003F
 639 #define PDUCQE_DPL_MASK         0xFFFF0000
 640 #define PDUCQE_INDEX_MASK       0x0000FFFF
 641
 642 struct i_t_dpdu_cqe {
 643         u32 dw[4];
 644 } __packed;
 645
 646 /**
 647  * Pseudo amap definition in which each bit of the actual structure is defined
 648  * as a byte: used to calculate offset/shift/mask of each field
 649  */
 650 struct amap_i_t_dpdu_cqe {
 651         u8 db_addr_hi[32];
 652         u8 db_addr_lo[32];
 653         u8 code[6];
 654         u8 cid[10];
 655         u8 dpl[16];
 656         u8 index[16];
 657         u8 num_cons[10];
 658         u8 rsvd0[4];
 659         u8 final;
 660         u8 valid;
 661 } __packed;
 662
 663 struct amap_i_t_dpdu_cqe_v2 {
 664         u8 db_addr_hi[32];  /* DWORD 0 */
 665         u8 db_addr_lo[32];  /* DWORD 1 */
 666         u8 code[6]; /* DWORD 2 */
 667         u8 num_cons; /* DWORD 2*/
 668         u8 rsvd0[8]; /* DWORD 2 */
 669         u8 dpl[17]; /* DWORD 2 */
 670         u8 index[16]; /* DWORD 3 */
 671         u8 cid[13]; /* DWORD 3 */
 672         u8 rsvd1; /* DWORD 3 */
 673         u8 final; /* DWORD 3 */
 674         u8 valid; /* DWORD 3 */
 675 } __packed;
 676
 677 #define CQE_VALID_MASK  0x80000000
 678 #define CQE_CODE_MASK   0x0000003F
 679 #define CQE_CID_MASK    0x0000FFC0
 680
 681 #define EQE_VALID_MASK          0x00000001
 682 #define EQE_MAJORCODE_MASK      0x0000000E
 683 #define EQE_RESID_MASK          0xFFFF0000
 684
 685 struct be_eq_entry {
 686         u32 dw[1];
 687 } __packed;
 688
 689 /**
 690  * Pseudo amap definition in which each bit of the actual structure is defined
 691  * as a byte: used to calculate offset/shift/mask of each field
 692  */
 693 struct amap_eq_entry {
 694         u8 valid;               /* DWORD 0 */
 695         u8 major_code[3];       /* DWORD 0 */
 696         u8 minor_code[12];      /* DWORD 0 */
 697         u8 resource_id[16];     /* DWORD 0 */
 698
 699 } __packed;
 700
 701 struct cq_db {
 702         u32 dw[1];
 703 } __packed;
 704
 705 /**
 706  * Pseudo amap definition in which each bit of the actual structure is defined
 707  * as a byte: used to calculate offset/shift/mask of each field
 708  */
 709 struct amap_cq_db {
 710         u8 qid[10];
 711         u8 event[1];
 712         u8 rsvd0[5];
 713         u8 num_popped[13];
 714         u8 rearm[1];
 715         u8 rsvd1[2];
 716 } __packed;
 717
 718 void beiscsi_process_eq(struct beiscsi_hba *phba);
 719
 720 struct iscsi_wrb {
 721         u32 dw[16];
 722 } __packed;
 723
 724 #define WRB_TYPE_MASK 0xF0000000
 725 #define SKH_WRB_TYPE_OFFSET 27
 726 #define BE_WRB_TYPE_OFFSET  28
 727
 728 #define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
 729                 (pwrb->dw[0] |= (wrb_type << type_offset))
 730
 731 /**
 732  * Pseudo amap definition in which each bit of the actual structure is defined
 733  * as a byte: used to calculate offset/shift/mask of each field
 734  */
 735 struct amap_iscsi_wrb {
 736         u8 lun[14];             /* DWORD 0 */
 737         u8 lt;                  /* DWORD 0 */
 738         u8 invld;               /* DWORD 0 */
 739         u8 wrb_idx[8];          /* DWORD 0 */
 740         u8 dsp;                 /* DWORD 0 */
 741         u8 dmsg;                /* DWORD 0 */
 742         u8 undr_run;            /* DWORD 0 */
 743         u8 over_run;            /* DWORD 0 */
 744         u8 type[4];             /* DWORD 0 */
 745         u8 ptr2nextwrb[8];      /* DWORD 1 */
 746         u8 r2t_exp_dtl[24];     /* DWORD 1 */
 747         u8 sgl_icd_idx[12];     /* DWORD 2 */
 748         u8 rsvd0[20];           /* DWORD 2 */
 749         u8 exp_data_sn[32];     /* DWORD 3 */
 750         u8 iscsi_bhs_addr_hi[32];       /* DWORD 4 */
 751         u8 iscsi_bhs_addr_lo[32];       /* DWORD 5 */
 752         u8 cmdsn_itt[32];       /* DWORD 6 */
 753         u8 dif_ref_tag[32];     /* DWORD 7 */
 754         u8 sge0_addr_hi[32];    /* DWORD 8 */
 755         u8 sge0_addr_lo[32];    /* DWORD 9  */
 756         u8 sge0_offset[22];     /* DWORD 10 */
 757         u8 pbs;                 /* DWORD 10 */
 758         u8 dif_mode[2];         /* DWORD 10 */
 759         u8 rsvd1[6];            /* DWORD 10 */
 760         u8 sge0_last;           /* DWORD 10 */
 761         u8 sge0_len[17];        /* DWORD 11 */
 762         u8 dif_meta_tag[14];    /* DWORD 11 */
 763         u8 sge0_in_ddr;         /* DWORD 11 */
 764         u8 sge1_addr_hi[32];    /* DWORD 12 */
 765         u8 sge1_addr_lo[32];    /* DWORD 13 */
 766         u8 sge1_r2t_offset[22]; /* DWORD 14 */
 767         u8 rsvd2[9];            /* DWORD 14 */
 768         u8 sge1_last;           /* DWORD 14 */
 769         u8 sge1_len[17];        /* DWORD 15 */
 770         u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
 771         u8 rsvd3[2];            /* DWORD 15 */
 772         u8 sge1_in_ddr;         /* DWORD 15 */
 773
 774 } __packed;
 775
 776 struct amap_iscsi_wrb_v2 {
 777         u8 r2t_exp_dtl[25]; /* DWORD 0 */
 778         u8 rsvd0[2];    /* DWORD 0*/
 779         u8 type[5];     /* DWORD 0 */
 780         u8 ptr2nextwrb[8];  /* DWORD 1 */
 781         u8 wrb_idx[8];      /* DWORD 1 */
 782         u8 lun[16];     /* DWORD 1 */
 783         u8 sgl_idx[16]; /* DWORD 2 */
 784         u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
 785         u8 exp_data_sn[32]; /* DWORD 3 */
 786         u8 iscsi_bhs_addr_hi[32];   /* DWORD 4 */
 787         u8 iscsi_bhs_addr_lo[32];   /* DWORD 5 */
 788         u8 cq_id[16];   /* DWORD 6 */
 789         u8 rsvd1[16];   /* DWORD 6 */
 790         u8 cmdsn_itt[32];   /* DWORD 7 */
 791         u8 sge0_addr_hi[32];    /* DWORD 8 */
 792         u8 sge0_addr_lo[32];    /* DWORD 9 */
 793         u8 sge0_offset[24]; /* DWORD 10 */
 794         u8 rsvd2[7];    /* DWORD 10 */
 795         u8 sge0_last;   /* DWORD 10 */
 796         u8 sge0_len[17];    /* DWORD 11 */
 797         u8 rsvd3[7];    /* DWORD 11 */
 798         u8 diff_enbl;   /* DWORD 11 */
 799         u8 u_run;       /* DWORD 11 */
 800         u8 o_run;       /* DWORD 11 */
 801         u8 invalid;     /* DWORD 11 */
 802         u8 dsp;         /* DWORD 11 */
 803         u8 dmsg;        /* DWORD 11 */
 804         u8 rsvd4;       /* DWORD 11 */
 805         u8 lt;          /* DWORD 11 */
 806         u8 sge1_addr_hi[32];    /* DWORD 12 */
 807         u8 sge1_addr_lo[32];    /* DWORD 13 */
 808         u8 sge1_r2t_offset[24]; /* DWORD 14 */
 809         u8 rsvd5[7];    /* DWORD 14 */
 810         u8 sge1_last;   /* DWORD 14 */
 811         u8 sge1_len[17];    /* DWORD 15 */
 812         u8 rsvd6[15];   /* DWORD 15 */
 813 } __packed;
 814
 815
 816 struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
 817 void
 818 free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
 819
 820 void beiscsi_process_all_cqs(struct work_struct *work);
 821 void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
 822                                      struct iscsi_task *task);
 823
 824 static inline bool beiscsi_error(struct beiscsi_hba *phba)
 825 {
 826         return phba->ue_detected || phba->fw_timeout;
 827 }
 828
 829 struct pdu_nop_out {
 830         u32 dw[12];
 831 };
 832
 833 /**
 834  * Pseudo amap definition in which each bit of the actual structure is defined
 835  * as a byte: used to calculate offset/shift/mask of each field
 836  */
 837 struct amap_pdu_nop_out {
 838         u8 opcode[6];           /* opcode 0x00 */
 839         u8 i_bit;               /* I Bit */
 840         u8 x_bit;               /* reserved; should be 0 */
 841         u8 fp_bit_filler1[7];
 842         u8 f_bit;               /* always 1 */
 843         u8 reserved1[16];
 844         u8 ahs_length[8];       /* no AHS */
 845         u8 data_len_hi[8];
 846         u8 data_len_lo[16];     /* DataSegmentLength */
 847         u8 lun[64];
 848         u8 itt[32];             /* initiator id for ping or 0xffffffff */
 849         u8 ttt[32];             /* target id for ping or 0xffffffff */
 850         u8 cmd_sn[32];
 851         u8 exp_stat_sn[32];
 852         u8 reserved5[128];
 853 };
 854
 855 #define PDUBASE_OPCODE_MASK     0x0000003F
 856 #define PDUBASE_DATALENHI_MASK  0x0000FF00
 857 #define PDUBASE_DATALENLO_MASK  0xFFFF0000
 858
 859 struct pdu_base {
 860         u32 dw[16];
 861 } __packed;
 862
 863 /**
 864  * Pseudo amap definition in which each bit of the actual structure is defined
 865  * as a byte: used to calculate offset/shift/mask of each field
 866  */
 867 struct amap_pdu_base {
 868         u8 opcode[6];
 869         u8 i_bit;               /* immediate bit */
 870         u8 x_bit;               /* reserved, always 0 */
 871         u8 reserved1[24];       /* opcode-specific fields */
 872         u8 ahs_length[8];       /* length units is 4 byte words */
 873         u8 data_len_hi[8];
 874         u8 data_len_lo[16];     /* DatasegmentLength */
 875         u8 lun[64];             /* lun or opcode-specific fields */
 876         u8 itt[32];             /* initiator task tag */
 877         u8 reserved4[224];
 878 };
 879
 880 struct iscsi_target_context_update_wrb {
 881         u32 dw[16];
 882 } __packed;
 883
 884 /**
 885  * Pseudo amap definition in which each bit of the actual structure is defined
 886  * as a byte: used to calculate offset/shift/mask of each field
 887  */
 888 #define BE_TGT_CTX_UPDT_CMD 0x07
 889 struct amap_iscsi_target_context_update_wrb {
 890         u8 lun[14];             /* DWORD 0 */
 891         u8 lt;                  /* DWORD 0 */
 892         u8 invld;               /* DWORD 0 */
 893         u8 wrb_idx[8];          /* DWORD 0 */
 894         u8 dsp;                 /* DWORD 0 */
 895         u8 dmsg;                /* DWORD 0 */
 896         u8 undr_run;            /* DWORD 0 */
 897         u8 over_run;            /* DWORD 0 */
 898         u8 type[4];             /* DWORD 0 */
 899         u8 ptr2nextwrb[8];      /* DWORD 1 */
 900         u8 max_burst_length[19];        /* DWORD 1 */
 901         u8 rsvd0[5];            /* DWORD 1 */
 902         u8 rsvd1[15];           /* DWORD 2 */
 903         u8 max_send_data_segment_length[17];    /* DWORD 2 */
 904         u8 first_burst_length[14];      /* DWORD 3 */
 905         u8 rsvd2[2];            /* DWORD 3 */
 906         u8 tx_wrbindex_drv_msg[8];      /* DWORD 3 */
 907         u8 rsvd3[5];            /* DWORD 3 */
 908         u8 session_state[3];    /* DWORD 3 */
 909         u8 rsvd4[16];           /* DWORD 4 */
 910         u8 tx_jumbo;            /* DWORD 4 */
 911         u8 hde;                 /* DWORD 4 */
 912         u8 dde;                 /* DWORD 4 */
 913         u8 erl[2];              /* DWORD 4 */
 914         u8 domain_id[5];                /* DWORD 4 */
 915         u8 mode;                /* DWORD 4 */
 916         u8 imd;                 /* DWORD 4 */
 917         u8 ir2t;                /* DWORD 4 */
 918         u8 notpredblq[2];       /* DWORD 4 */
 919         u8 compltonack;         /* DWORD 4 */
 920         u8 stat_sn[32];         /* DWORD 5 */
 921         u8 pad_buffer_addr_hi[32];      /* DWORD 6 */
 922         u8 pad_buffer_addr_lo[32];      /* DWORD 7 */
 923         u8 pad_addr_hi[32];     /* DWORD 8 */
 924         u8 pad_addr_lo[32];     /* DWORD 9 */
 925         u8 rsvd5[32];           /* DWORD 10 */
 926         u8 rsvd6[32];           /* DWORD 11 */
 927         u8 rsvd7[32];           /* DWORD 12 */
 928         u8 rsvd8[32];           /* DWORD 13 */
 929         u8 rsvd9[32];           /* DWORD 14 */
 930         u8 rsvd10[32];          /* DWORD 15 */
 931
 932 } __packed;
 933
 934 #define BEISCSI_MAX_RECV_DATASEG_LEN    (64 * 1024)
 935 #define BEISCSI_MAX_CXNS    1
 936 struct amap_iscsi_target_context_update_wrb_v2 {
 937         u8 max_burst_length[24];    /* DWORD 0 */
 938         u8 rsvd0[3];    /* DWORD 0 */
 939         u8 type[5];     /* DWORD 0 */
 940         u8 ptr2nextwrb[8];  /* DWORD 1 */
 941         u8 wrb_idx[8];      /* DWORD 1 */
 942         u8 rsvd1[16];       /* DWORD 1 */
 943         u8 max_send_data_segment_length[24];    /* DWORD 2 */
 944         u8 rsvd2[8];    /* DWORD 2 */
 945         u8 first_burst_length[24]; /* DWORD 3 */
 946         u8 rsvd3[8]; /* DOWRD 3 */
 947         u8 max_r2t[16]; /* DWORD 4 */
 948         u8 rsvd4;       /* DWORD 4 */
 949         u8 hde;         /* DWORD 4 */
 950         u8 dde;         /* DWORD 4 */
 951         u8 erl[2];      /* DWORD 4 */
 952         u8 rsvd5[6];    /* DWORD 4 */
 953         u8 imd;         /* DWORD 4 */
 954         u8 ir2t;        /* DWORD 4 */
 955         u8 rsvd6[3];    /* DWORD 4 */
 956         u8 stat_sn[32];     /* DWORD 5 */
 957         u8 rsvd7[32];   /* DWORD 6 */
 958         u8 rsvd8[32];   /* DWORD 7 */
 959         u8 max_recv_dataseg_len[24];    /* DWORD 8 */
 960         u8 rsvd9[8]; /* DWORD 8 */
 961         u8 rsvd10[32];   /* DWORD 9 */
 962         u8 rsvd11[32];   /* DWORD 10 */
 963         u8 max_cxns[16]; /* DWORD 11 */
 964         u8 rsvd12[11]; /* DWORD  11*/
 965         u8 invld; /* DWORD 11 */
 966         u8 rsvd13;/* DWORD 11*/
 967         u8 dmsg; /* DWORD 11 */
 968         u8 data_seq_inorder; /* DWORD 11 */
 969         u8 pdu_seq_inorder; /* DWORD 11 */
 970         u8 rsvd14[32]; /*DWORD 12 */
 971         u8 rsvd15[32]; /* DWORD 13 */
 972         u8 rsvd16[32]; /* DWORD 14 */
 973         u8 rsvd17[32]; /* DWORD 15 */
 974 } __packed;
 975
 976
 977 struct be_ring {
 978         u32 pages;              /* queue size in pages */
 979         u32 id;                 /* queue id assigned by beklib */
 980         u32 num;                /* number of elements in queue */
 981         u32 cidx;               /* consumer index */
 982         u32 pidx;               /* producer index -- not used by most rings */
 983         u32 item_size;          /* size in bytes of one object */
 984         u8 ulp_num;     /* ULP to which CID binded */
 985         u16 register_set;
 986         u16 doorbell_format;
 987         u32 doorbell_offset;
 988
 989         void *va;               /* The virtual address of the ring.  This
 990                                  * should be last to allow 32 & 64 bit debugger
 991                                  * extensions to work.
 992                                  */
 993 };
 994
 995 struct hwi_controller {
 996         struct list_head io_sgl_list;
 997         struct list_head eh_sgl_list;
 998         struct sgl_handle *psgl_handle_base;
 999         unsigned int wrb_mem_index;
1000
1001         struct hwi_wrb_context *wrb_context;
1002         struct mcc_wrb *pmcc_wrb_base;
1003         struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1004         struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
1005         struct hwi_context_memory *phwi_ctxt;
1006 };
1007
1008 enum hwh_type_enum {
1009         HWH_TYPE_IO = 1,
1010         HWH_TYPE_LOGOUT = 2,
1011         HWH_TYPE_TMF = 3,
1012         HWH_TYPE_NOP = 4,
1013         HWH_TYPE_IO_RD = 5,
1014         HWH_TYPE_LOGIN = 11,
1015         HWH_TYPE_INVALID = 0xFFFFFFFF
1016 };
1017
1018 struct wrb_handle {
1019         enum hwh_type_enum type;
1020         unsigned short wrb_index;
1021         unsigned short nxt_wrb_index;
1022
1023         struct iscsi_task *pio_handle;
1024         struct iscsi_wrb *pwrb;
1025 };
1026
1027 struct hwi_context_memory {
1028         /* Adaptive interrupt coalescing (AIC) info */
1029         u16 min_eqd;            /* in usecs */
1030         u16 max_eqd;            /* in usecs */
1031         u16 cur_eqd;            /* in usecs */
1032         struct be_eq_obj be_eq[MAX_CPUS];
1033         struct be_queue_info be_cq[MAX_CPUS - 1];
1034
1035         struct be_queue_info *be_wrbq;
1036         struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1037         struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1038         struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
1039 };
1040
1041 /* Logging related definitions */
1042 #define BEISCSI_LOG_INIT        0x0001  /* Initialization events */
1043 #define BEISCSI_LOG_MBOX        0x0002  /* Mailbox Events */
1044 #define BEISCSI_LOG_MISC        0x0004  /* Miscllaneous Events */
1045 #define BEISCSI_LOG_EH          0x0008  /* Error Handler */
1046 #define BEISCSI_LOG_IO          0x0010  /* IO Code Path */
1047 #define BEISCSI_LOG_CONFIG      0x0020  /* CONFIG Code Path */
1048 #define BEISCSI_LOG_ISCSI       0x0040  /* SCSI/iSCSI Protocol related Logs */
1049
1050 #define beiscsi_log(phba, level, mask, fmt, arg...) \
1051 do { \
1052         uint32_t log_value = phba->attr_log_enable; \
1053                 if (((mask) & log_value) || (level[1] <= '3')) \
1054                         shost_printk(level, phba->shost, \
1055                                      fmt, __LINE__, ##arg); \
1056 } while (0)
1057
1058 #endif