drivers/scsi/hpsa.h

   1 /*
   2  *    Disk Array driver for HP Smart Array SAS controllers
   3  *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
   4  *
   5  *    This program is free software; you can redistribute it and/or modify
   6  *    it under the terms of the GNU General Public License as published by
   7  *    the Free Software Foundation; version 2 of the License.
   8  *
   9  *    This program is distributed in the hope that it will be useful,
  10  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  12  *    NON INFRINGEMENT.  See the GNU General Public License for more details.
  13  *
  14  *    You should have received a copy of the GNU General Public License
  15  *    along with this program; if not, write to the Free Software
  16  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  *
  18  *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
  19  *
  20  */
  21 #ifndef HPSA_H
  22 #define HPSA_H
  23
  24 #include <scsi/scsicam.h>
  25
  26 #define IO_OK           0
  27 #define IO_ERROR        1
  28
  29 struct ctlr_info;
  30
  31 struct access_method {
  32         void (*submit_command)(struct ctlr_info *h,
  33                 struct CommandList *c);
  34         void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
  35         unsigned long (*fifo_full)(struct ctlr_info *h);
  36         bool (*intr_pending)(struct ctlr_info *h);
  37         unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
  38 };
  39
  40 struct hpsa_scsi_dev_t {
  41         int devtype;
  42         int bus, target, lun;           /* as presented to the OS */
  43         unsigned char scsi3addr[8];     /* as presented to the HW */
  44 #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
  45         unsigned char device_id[16];    /* from inquiry pg. 0x83 */
  46         unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
  47         unsigned char model[16];        /* bytes 16-31 of inquiry data */
  48         unsigned char raid_level;       /* from inquiry page 0xC1 */
  49 };
  50
  51 struct reply_pool {
  52         u64 *head;
  53         size_t size;
  54         u8 wraparound;
  55         u32 current_entry;
  56 };
  57
  58 struct ctlr_info {
  59         int     ctlr;
  60         char    devname[8];
  61         char    *product_name;
  62         struct pci_dev *pdev;
  63         u32     board_id;
  64         void __iomem *vaddr;
  65         unsigned long paddr;
  66         int     nr_cmds; /* Number of commands allowed on this controller */
  67         struct CfgTable __iomem *cfgtable;
  68         int     interrupts_enabled;
  69         int     major;
  70         int     max_commands;
  71         int     commands_outstanding;
  72         int     max_outstanding; /* Debug */
  73         int     usage_count;  /* number of opens all all minor devices */
  74 #       define PERF_MODE_INT    0
  75 #       define DOORBELL_INT     1
  76 #       define SIMPLE_MODE_INT  2
  77 #       define MEMQ_MODE_INT    3
  78         unsigned int intr[MAX_REPLY_QUEUES];
  79         unsigned int msix_vector;
  80         unsigned int msi_vector;
  81         int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
  82         struct access_method access;
  83
  84         /* queue and queue Info */
  85         struct list_head reqQ;
  86         struct list_head cmpQ;
  87         unsigned int Qdepth;
  88         unsigned int maxSG;
  89         spinlock_t lock;
  90         int maxsgentries;
  91         u8 max_cmd_sg_entries;
  92         int chainsize;
  93         struct SGDescriptor **cmd_sg_list;
  94
  95         /* pointers to command and error info pool */
  96         struct CommandList      *cmd_pool;
  97         dma_addr_t              cmd_pool_dhandle;
  98         struct ErrorInfo        *errinfo_pool;
  99         dma_addr_t              errinfo_pool_dhandle;
 100         unsigned long           *cmd_pool_bits;
 101         int                     scan_finished;
 102         spinlock_t              scan_lock;
 103         wait_queue_head_t       scan_wait_queue;
 104
 105         struct Scsi_Host *scsi_host;
 106         spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
 107         int ndevices; /* number of used elements in .dev[] array. */
 108         struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
 109         /*
 110          * Performant mode tables.
 111          */
 112         u32 trans_support;
 113         u32 trans_offset;
 114         struct TransTable_struct *transtable;
 115         unsigned long transMethod;
 116
 117         /* cap concurrent passthrus at some reasonable maximum */
 118 #define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
 119         spinlock_t passthru_count_lock; /* protects passthru_count */
 120         int passthru_count;
 121
 122         /*
 123          * Performant mode completion buffers
 124          */
 125         u64 *reply_pool;
 126         size_t reply_pool_size;
 127         struct reply_pool reply_queue[MAX_REPLY_QUEUES];
 128         u8 nreply_queues;
 129         dma_addr_t reply_pool_dhandle;
 130         u32 *blockFetchTable;
 131         unsigned char *hba_inquiry_data;
 132         u64 last_intr_timestamp;
 133         u32 last_heartbeat;
 134         u64 last_heartbeat_timestamp;
 135         u32 heartbeat_sample_interval;
 136         atomic_t firmware_flash_in_progress;
 137         u32 lockup_detected;
 138         struct delayed_work monitor_ctlr_work;
 139         int remove_in_progress;
 140         u32 fifo_recently_full;
 141         /* Address of h->q[x] is passed to intr handler to know which queue */
 142         u8 q[MAX_REPLY_QUEUES];
 143         u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
 144 #define HPSATMF_BITS_SUPPORTED  (1 << 0)
 145 #define HPSATMF_PHYS_LUN_RESET  (1 << 1)
 146 #define HPSATMF_PHYS_NEX_RESET  (1 << 2)
 147 #define HPSATMF_PHYS_TASK_ABORT (1 << 3)
 148 #define HPSATMF_PHYS_TSET_ABORT (1 << 4)
 149 #define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
 150 #define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
 151 #define HPSATMF_PHYS_QRY_TASK   (1 << 7)
 152 #define HPSATMF_PHYS_QRY_TSET   (1 << 8)
 153 #define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
 154 #define HPSATMF_MASK_SUPPORTED  (1 << 16)
 155 #define HPSATMF_LOG_LUN_RESET   (1 << 17)
 156 #define HPSATMF_LOG_NEX_RESET   (1 << 18)
 157 #define HPSATMF_LOG_TASK_ABORT  (1 << 19)
 158 #define HPSATMF_LOG_TSET_ABORT  (1 << 20)
 159 #define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
 160 #define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
 161 #define HPSATMF_LOG_QRY_TASK    (1 << 23)
 162 #define HPSATMF_LOG_QRY_TSET    (1 << 24)
 163 #define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
 164 };
 165 #define HPSA_ABORT_MSG 0
 166 #define HPSA_DEVICE_RESET_MSG 1
 167 #define HPSA_RESET_TYPE_CONTROLLER 0x00
 168 #define HPSA_RESET_TYPE_BUS 0x01
 169 #define HPSA_RESET_TYPE_TARGET 0x03
 170 #define HPSA_RESET_TYPE_LUN 0x04
 171 #define HPSA_MSG_SEND_RETRY_LIMIT 10
 172 #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
 173
 174 /* Maximum time in seconds driver will wait for command completions
 175  * when polling before giving up.
 176  */
 177 #define HPSA_MAX_POLL_TIME_SECS (20)
 178
 179 /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 180  * how many times to retry TEST UNIT READY on a device
 181  * while waiting for it to become ready before giving up.
 182  * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 183  * between sending TURs while waiting for a device
 184  * to become ready.
 185  */
 186 #define HPSA_TUR_RETRY_LIMIT (20)
 187 #define HPSA_MAX_WAIT_INTERVAL_SECS (30)
 188
 189 /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 190  * to become ready, in seconds, before giving up on it.
 191  * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 192  * between polling the board to see if it is ready, in
 193  * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 194  * HPSA_BOARD_READY_ITERATIONS are derived from those.
 195  */
 196 #define HPSA_BOARD_READY_WAIT_SECS (120)
 197 #define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
 198 #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
 199 #define HPSA_BOARD_READY_POLL_INTERVAL \
 200         ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
 201 #define HPSA_BOARD_READY_ITERATIONS \
 202         ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
 203                 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
 204 #define HPSA_BOARD_NOT_READY_ITERATIONS \
 205         ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
 206                 HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
 207 #define HPSA_POST_RESET_PAUSE_MSECS (3000)
 208 #define HPSA_POST_RESET_NOOP_RETRIES (12)
 209
 210 /*  Defining the diffent access_menthods */
 211 /*
 212  * Memory mapped FIFO interface (SMART 53xx cards)
 213  */
 214 #define SA5_DOORBELL    0x20
 215 #define SA5_REQUEST_PORT_OFFSET 0x40
 216 #define SA5_REPLY_INTR_MASK_OFFSET      0x34
 217 #define SA5_REPLY_PORT_OFFSET           0x44
 218 #define SA5_INTR_STATUS         0x30
 219 #define SA5_SCRATCHPAD_OFFSET   0xB0
 220
 221 #define SA5_CTCFG_OFFSET        0xB4
 222 #define SA5_CTMEM_OFFSET        0xB8
 223
 224 #define SA5_INTR_OFF            0x08
 225 #define SA5B_INTR_OFF           0x04
 226 #define SA5_INTR_PENDING        0x08
 227 #define SA5B_INTR_PENDING       0x04
 228 #define FIFO_EMPTY              0xffffffff
 229 #define HPSA_FIRMWARE_READY     0xffff0000 /* value in scratchpad register */
 230
 231 #define HPSA_ERROR_BIT          0x02
 232
 233 /* Performant mode flags */
 234 #define SA5_PERF_INTR_PENDING   0x04
 235 #define SA5_PERF_INTR_OFF       0x05
 236 #define SA5_OUTDB_STATUS_PERF_BIT       0x01
 237 #define SA5_OUTDB_CLEAR_PERF_BIT        0x01
 238 #define SA5_OUTDB_CLEAR         0xA0
 239 #define SA5_OUTDB_CLEAR_PERF_BIT        0x01
 240 #define SA5_OUTDB_STATUS        0x9C
 241
 242
 243 #define HPSA_INTR_ON    1
 244 #define HPSA_INTR_OFF   0
 245 /*
 246         Send the command to the hardware
 247 */
 248 static void SA5_submit_command(struct ctlr_info *h,
 249         struct CommandList *c)
 250 {
 251         dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
 252                 c->Header.Tag.lower);
 253         writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
 254         (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
 255 }
 256
 257 /*
 258  *  This card is the opposite of the other cards.
 259  *   0 turns interrupts on...
 260  *   0x08 turns them off...
 261  */
 262 static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
 263 {
 264         if (val) { /* Turn interrupts on */
 265                 h->interrupts_enabled = 1;
 266                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 267                 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 268         } else { /* Turn them off */
 269                 h->interrupts_enabled = 0;
 270                 writel(SA5_INTR_OFF,
 271                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 272                 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 273         }
 274 }
 275
 276 static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
 277 {
 278         if (val) { /* turn on interrupts */
 279                 h->interrupts_enabled = 1;
 280                 writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 281                 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 282         } else {
 283                 h->interrupts_enabled = 0;
 284                 writel(SA5_PERF_INTR_OFF,
 285                         h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 286                 (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
 287         }
 288 }
 289
 290 static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
 291 {
 292         struct reply_pool *rq = &h->reply_queue[q];
 293         unsigned long flags, register_value = FIFO_EMPTY;
 294
 295         /* msi auto clears the interrupt pending bit. */
 296         if (!(h->msi_vector || h->msix_vector)) {
 297                 /* flush the controller write of the reply queue by reading
 298                  * outbound doorbell status register.
 299                  */
 300                 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
 301                 writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
 302                 /* Do a read in order to flush the write to the controller
 303                  * (as per spec.)
 304                  */
 305                 register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
 306         }
 307
 308         if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
 309                 register_value = rq->head[rq->current_entry];
 310                 rq->current_entry++;
 311                 spin_lock_irqsave(&h->lock, flags);
 312                 h->commands_outstanding--;
 313                 spin_unlock_irqrestore(&h->lock, flags);
 314         } else {
 315                 register_value = FIFO_EMPTY;
 316         }
 317         /* Check for wraparound */
 318         if (rq->current_entry == h->max_commands) {
 319                 rq->current_entry = 0;
 320                 rq->wraparound ^= 1;
 321         }
 322         return register_value;
 323 }
 324
 325 /*
 326  *  Returns true if fifo is full.
 327  *
 328  */
 329 static unsigned long SA5_fifo_full(struct ctlr_info *h)
 330 {
 331         if (h->commands_outstanding >= h->max_commands)
 332                 return 1;
 333         else
 334                 return 0;
 335
 336 }
 337 /*
 338  *   returns value read from hardware.
 339  *     returns FIFO_EMPTY if there is nothing to read
 340  */
 341 static unsigned long SA5_completed(struct ctlr_info *h,
 342         __attribute__((unused)) u8 q)
 343 {
 344         unsigned long register_value
 345                 = readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
 346         unsigned long flags;
 347
 348         if (register_value != FIFO_EMPTY) {
 349                 spin_lock_irqsave(&h->lock, flags);
 350                 h->commands_outstanding--;
 351                 spin_unlock_irqrestore(&h->lock, flags);
 352         }
 353
 354 #ifdef HPSA_DEBUG
 355         if (register_value != FIFO_EMPTY)
 356                 dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
 357                         register_value);
 358         else
 359                 dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
 360 #endif
 361
 362         return register_value;
 363 }
 364 /*
 365  *      Returns true if an interrupt is pending..
 366  */
 367 static bool SA5_intr_pending(struct ctlr_info *h)
 368 {
 369         unsigned long register_value  =
 370                 readl(h->vaddr + SA5_INTR_STATUS);
 371         dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
 372         return register_value & SA5_INTR_PENDING;
 373 }
 374
 375 static bool SA5_performant_intr_pending(struct ctlr_info *h)
 376 {
 377         unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
 378
 379         if (!register_value)
 380                 return false;
 381
 382         if (h->msi_vector || h->msix_vector)
 383                 return true;
 384
 385         /* Read outbound doorbell to flush */
 386         register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
 387         return register_value & SA5_OUTDB_STATUS_PERF_BIT;
 388 }
 389
 390 static struct access_method SA5_access = {
 391         SA5_submit_command,
 392         SA5_intr_mask,
 393         SA5_fifo_full,
 394         SA5_intr_pending,
 395         SA5_completed,
 396 };
 397
 398 static struct access_method SA5_performant_access = {
 399         SA5_submit_command,
 400         SA5_performant_intr_mask,
 401         SA5_fifo_full,
 402         SA5_performant_intr_pending,
 403         SA5_performant_completed,
 404 };
 405
 406 struct board_type {
 407         u32     board_id;
 408         char    *product_name;
 409         struct access_method *access;
 410 };
 411
 412 #endif /* HPSA_H */
 413