?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / scsi / mpt2sas / mpi / mpi2_cnfg.h
blob88cb7f828bbd3c133bee3318534c50d0ca23edf1
1 /*
2 * Copyright (c) 2000-2013 LSI Corporation.
3 *
4 *
5 * Name: mpi2_cnfg.h
6 * Title: MPI Configuration messages and pages
7 * Creation Date: November 10, 2006
8 *
9 * mpi2_cnfg.h Version: 02.00.23
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A.
17 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags.
18 * Added Manufacturing Page 11.
19 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE
20 * define.
21 * 06-26-07 02.00.02 Adding generic structure for product-specific
22 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS.
23 * Rework of BIOS Page 2 configuration page.
24 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the
25 * forms.
26 * Added configuration pages IOC Page 8 and Driver
27 * Persistent Mapping Page 0.
28 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated
29 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1,
30 * RAID Physical Disk Pages 0 and 1, RAID Configuration
31 * Page 0).
32 * Added new value for AccessStatus field of SAS Device
33 * Page 0 (_SATA_NEEDS_INITIALIZATION).
34 * 10-31-07 02.00.04 Added missing SEPDevHandle field to
35 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0.
36 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for
37 * NVDATA.
38 * Modified IOC Page 7 to use masks and added field for
39 * SASBroadcastPrimitiveMasks.
40 * Added MPI2_CONFIG_PAGE_BIOS_4.
41 * Added MPI2_CONFIG_PAGE_LOG_0.
42 * 02-29-08 02.00.06 Modified various names to make them 32-character unique.
43 * Added SAS Device IDs.
44 * Updated Integrated RAID configuration pages including
45 * Manufacturing Page 4, IOC Page 6, and RAID Configuration
46 * Page 0.
47 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA.
48 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION.
49 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING.
50 * Added missing MaxNumRoutedSasAddresses field to
51 * MPI2_CONFIG_PAGE_EXPANDER_0.
52 * Added SAS Port Page 0.
53 * Modified structure layout for
54 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0.
55 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use
56 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array.
57 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF
58 * to 0x000000FF.
59 * Added two new values for the Physical Disk Coercion Size
60 * bits in the Flags field of Manufacturing Page 4.
61 * Added product-specific Manufacturing pages 16 to 31.
62 * Modified Flags bits for controlling write cache on SATA
63 * drives in IO Unit Page 1.
64 * Added new bit to AdditionalControlFlags of SAS IO Unit
65 * Page 1 to control Invalid Topology Correction.
66 * Added additional defines for RAID Volume Page 0
67 * VolumeStatusFlags field.
68 * Modified meaning of RAID Volume Page 0 VolumeSettings
69 * define for auto-configure of hot-swap drives.
70 * Added SupportedPhysDisks field to RAID Volume Page 1 and
71 * added related defines.
72 * Added PhysDiskAttributes field (and related defines) to
73 * RAID Physical Disk Page 0.
74 * Added MPI2_SAS_PHYINFO_PHY_VACANT define.
75 * Added three new DiscoveryStatus bits for SAS IO Unit
76 * Page 0 and SAS Expander Page 0.
77 * Removed multiplexing information from SAS IO Unit pages.
78 * Added BootDeviceWaitTime field to SAS IO Unit Page 4.
79 * Removed Zone Address Resolved bit from PhyInfo and from
80 * Expander Page 0 Flags field.
81 * Added two new AccessStatus values to SAS Device Page 0
82 * for indicating routing problems. Added 3 reserved words
83 * to this page.
84 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3.
85 * Inserted missing reserved field into structure for IOC
86 * Page 6.
87 * Added more pending task bits to RAID Volume Page 0
88 * VolumeStatusFlags defines.
89 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define.
90 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0
91 * and SAS Expander Page 0 to flag a downstream initiator
92 * when in simplified routing mode.
93 * Removed SATA Init Failure defines for DiscoveryStatus
94 * fields of SAS IO Unit Page 0 and SAS Expander Page 0.
95 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define.
96 * Added PortGroups, DmaGroup, and ControlGroup fields to
97 * SAS Device Page 0.
98 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO
99 * Unit Page 6.
100 * Added expander reduced functionality data to SAS
101 * Expander Page 0.
102 * Added SAS PHY Page 2 and SAS PHY Page 3.
103 * 07-30-09 02.00.12 Added IO Unit Page 7.
104 * Added new device ids.
105 * Added SAS IO Unit Page 5.
106 * Added partial and slumber power management capable flags
107 * to SAS Device Page 0 Flags field.
108 * Added PhyInfo defines for power condition.
109 * Added Ethernet configuration pages.
110 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY.
111 * Added SAS PHY Page 4 structure and defines.
112 * 02-10-10 02.00.14 Modified the comments for the configuration page
113 * structures that contain an array of data. The host
114 * should use the "count" field in the page data (e.g. the
115 * NumPhys field) to determine the number of valid elements
116 * in the array.
117 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines.
118 * Added PowerManagementCapabilities to IO Unit Page 7.
119 * Added PortWidthModGroup field to
120 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS.
121 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines.
122 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines.
123 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines.
124 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT
125 * define.
126 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define.
127 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define.
128 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing)
129 * defines.
130 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to
131 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for
132 * the Pinout field.
133 * Added BoardTemperature and BoardTemperatureUnits fields
134 * to MPI2_CONFIG_PAGE_IO_UNIT_7.
135 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define
136 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure.
137 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST.
138 * Added IO Unit Page 8, IO Unit Page 9,
139 * and IO Unit Page 10.
140 * Added SASNotifyPrimitiveMasks field to
141 * MPI2_CONFIG_PAGE_IOC_7.
142 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec).
143 * 05-25-11 02.00.20 Cleaned up a few comments.
144 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities
145 * for PCIe link as obsolete.
146 * Added SpinupFlags field containing a Disable Spin-up
147 * bit to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of
148 * SAS IO Unit Page 4.
149 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT.
150 * Added UEFIVersion field to BIOS Page 1 and defined new
151 * BiosOptions bits.
152 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER.
153 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID.
154 * --------------------------------------------------------------------------
155 */
156
157 #ifndef MPI2_CNFG_H
158 #define MPI2_CNFG_H
159
160 /*****************************************************************************
161 * Configuration Page Header and defines
162 *****************************************************************************/
163
164 /* Config Page Header */
165 typedef struct _MPI2_CONFIG_PAGE_HEADER
166 {
167 U8 PageVersion; /* 0x00 */
168 U8 PageLength; /* 0x01 */
169 U8 PageNumber; /* 0x02 */
170 U8 PageType; /* 0x03 */
171 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER,
172 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t;
173
174 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION
175 {
176 MPI2_CONFIG_PAGE_HEADER Struct;
177 U8 Bytes[4];
178 U16 Word16[2];
179 U32 Word32;
180 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION,
181 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion;
182
183 /* Extended Config Page Header */
184 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER
185 {
186 U8 PageVersion; /* 0x00 */
187 U8 Reserved1; /* 0x01 */
188 U8 PageNumber; /* 0x02 */
189 U8 PageType; /* 0x03 */
190 U16 ExtPageLength; /* 0x04 */
191 U8 ExtPageType; /* 0x06 */
192 U8 Reserved2; /* 0x07 */
193 } MPI2_CONFIG_EXTENDED_PAGE_HEADER,
194 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER,
195 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t;
196
197 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION
198 {
199 MPI2_CONFIG_PAGE_HEADER Struct;
200 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext;
201 U8 Bytes[8];
202 U16 Word16[4];
203 U32 Word32[2];
204 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION,
205 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion;
206
207
208 /* PageType field values */
209 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00)
210 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10)
211 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20)
212 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0)
213
214 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00)
215 #define MPI2_CONFIG_PAGETYPE_IOC (0x01)
216 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02)
217 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
218 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09)
219 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
220 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F)
221 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F)
222
223 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF)
224
225
226 /* ExtPageType field values */
227 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
228 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
229 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
230 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
231 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14)
232 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
233 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16)
234 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17)
235 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18)
236 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19)
237 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A)
238
239
240 /*****************************************************************************
241 * PageAddress defines
242 *****************************************************************************/
243
244 /* RAID Volume PageAddress format */
245 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000)
246 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
247 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000)
248
249 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF)
250
251
252 /* RAID Physical Disk PageAddress format */
253 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000)
254 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000)
255 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000)
256 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000)
257
258 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
259 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF)
260
261
262 /* SAS Expander PageAddress format */
263 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
264 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000)
265 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000)
266 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000)
267
268 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF)
269 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000)
270 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16)
271
272
273 /* SAS Device PageAddress format */
274 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
275 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
276 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000)
277
278 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF)
279
280
281 /* SAS PHY PageAddress format */
282 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
283 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000)
284 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000)
285
286 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
287 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
288
289
290 /* SAS Port PageAddress format */
291 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000)
292 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000)
293 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000)
294
295 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF)
296
297
298 /* SAS Enclosure PageAddress format */
299 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
300 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
301 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000)
302
303 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF)
304
305
306 /* RAID Configuration PageAddress format */
307 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000)
308 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000)
309 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000)
310 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000)
311
312 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF)
313
314
315 /* Driver Persistent Mapping PageAddress format */
316 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000)
317 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000)
318
319 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000)
320 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16)
321 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF)
322
323
324 /* Ethernet PageAddress format */
325 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000)
326 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000)
327
328 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF)
329
330
331
332 /****************************************************************************
333 * Configuration messages
334 ****************************************************************************/
335
336 /* Configuration Request Message */
337 typedef struct _MPI2_CONFIG_REQUEST
338 {
339 U8 Action; /* 0x00 */
340 U8 SGLFlags; /* 0x01 */
341 U8 ChainOffset; /* 0x02 */
342 U8 Function; /* 0x03 */
343 U16 ExtPageLength; /* 0x04 */
344 U8 ExtPageType; /* 0x06 */
345 U8 MsgFlags; /* 0x07 */
346 U8 VP_ID; /* 0x08 */
347 U8 VF_ID; /* 0x09 */
348 U16 Reserved1; /* 0x0A */
349 U8 Reserved2; /* 0x0C */
350 U8 ProxyVF_ID; /* 0x0D */
351 U16 Reserved4; /* 0x0E */
352 U32 Reserved3; /* 0x10 */
353 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
354 U32 PageAddress; /* 0x18 */
355 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */
356 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST,
357 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t;
358
359 /* values for the Action field */
360 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00)
361 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
362 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
363 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03)
364 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
365 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
366 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
367 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07)
368
369 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */
370
371
372 /* Config Reply Message */
373 typedef struct _MPI2_CONFIG_REPLY
374 {
375 U8 Action; /* 0x00 */
376 U8 SGLFlags; /* 0x01 */
377 U8 MsgLength; /* 0x02 */
378 U8 Function; /* 0x03 */
379 U16 ExtPageLength; /* 0x04 */
380 U8 ExtPageType; /* 0x06 */
381 U8 MsgFlags; /* 0x07 */
382 U8 VP_ID; /* 0x08 */
383 U8 VF_ID; /* 0x09 */
384 U16 Reserved1; /* 0x0A */
385 U16 Reserved2; /* 0x0C */
386 U16 IOCStatus; /* 0x0E */
387 U32 IOCLogInfo; /* 0x10 */
388 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */
389 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY,
390 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t;
391
392
393
394 /*****************************************************************************
395 *
396 * C o n f i g u r a t i o n P a g e s
397 *
398 *****************************************************************************/
399
400 /****************************************************************************
401 * Manufacturing Config pages
402 ****************************************************************************/
403
404 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000)
405
406 /* SAS */
407 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070)
408 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072)
409 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074)
410 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076)
411 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077)
412 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064)
413 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065)
414
415 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E)
416
417 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080)
418 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081)
419 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082)
420 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083)
421 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084)
422 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085)
423 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086)
424 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087)
425 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E)
426
427
428
429
430 /* Manufacturing Page 0 */
431
432 typedef struct _MPI2_CONFIG_PAGE_MAN_0
433 {
434 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
435 U8 ChipName[16]; /* 0x04 */
436 U8 ChipRevision[8]; /* 0x14 */
437 U8 BoardName[16]; /* 0x1C */
438 U8 BoardAssembly[16]; /* 0x2C */
439 U8 BoardTracerNumber[16]; /* 0x3C */
440 } MPI2_CONFIG_PAGE_MAN_0,
441 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0,
442 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t;
443
444 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00)
445
446
447 /* Manufacturing Page 1 */
448
449 typedef struct _MPI2_CONFIG_PAGE_MAN_1
450 {
451 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
452 U8 VPD[256]; /* 0x04 */
453 } MPI2_CONFIG_PAGE_MAN_1,
454 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1,
455 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t;
456
457 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00)
458
459
460 typedef struct _MPI2_CHIP_REVISION_ID
461 {
462 U16 DeviceID; /* 0x00 */
463 U8 PCIRevisionID; /* 0x02 */
464 U8 Reserved; /* 0x03 */
465 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID,
466 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t;
467
468
469 /* Manufacturing Page 2 */
470
471 /*
472 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
473 * one and check Header.PageLength at runtime.
474 */
475 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS
476 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
477 #endif
478
479 typedef struct _MPI2_CONFIG_PAGE_MAN_2
480 {
481 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
482 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
483 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */
484 } MPI2_CONFIG_PAGE_MAN_2,
485 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2,
486 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t;
487
488 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00)
489
490
491 /* Manufacturing Page 3 */
492
493 /*
494 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
495 * one and check Header.PageLength at runtime.
496 */
497 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS
498 #define MPI2_MAN_PAGE_3_INFO_WORDS (1)
499 #endif
500
501 typedef struct _MPI2_CONFIG_PAGE_MAN_3
502 {
503 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
504 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */
505 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */
506 } MPI2_CONFIG_PAGE_MAN_3,
507 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3,
508 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t;
509
510 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00)
511
512
513 /* Manufacturing Page 4 */
514
515 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS
516 {
517 U8 PowerSaveFlags; /* 0x00 */
518 U8 InternalOperationsSleepTime; /* 0x01 */
519 U8 InternalOperationsRunTime; /* 0x02 */
520 U8 HostIdleTime; /* 0x03 */
521 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
522 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS,
523 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t;
524
525 /* defines for the PowerSaveFlags field */
526 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03)
527 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00)
528 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01)
529 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02)
530
531 typedef struct _MPI2_CONFIG_PAGE_MAN_4
532 {
533 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
534 U32 Reserved1; /* 0x04 */
535 U32 Flags; /* 0x08 */
536 U8 InquirySize; /* 0x0C */
537 U8 Reserved2; /* 0x0D */
538 U16 Reserved3; /* 0x0E */
539 U8 InquiryData[56]; /* 0x10 */
540 U32 RAID0VolumeSettings; /* 0x48 */
541 U32 RAID1EVolumeSettings; /* 0x4C */
542 U32 RAID1VolumeSettings; /* 0x50 */
543 U32 RAID10VolumeSettings; /* 0x54 */
544 U32 Reserved4; /* 0x58 */
545 U32 Reserved5; /* 0x5C */
546 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */
547 U8 MaxOCEDisks; /* 0x64 */
548 U8 ResyncRate; /* 0x65 */
549 U16 DataScrubDuration; /* 0x66 */
550 U8 MaxHotSpares; /* 0x68 */
551 U8 MaxPhysDisksPerVol; /* 0x69 */
552 U8 MaxPhysDisks; /* 0x6A */
553 U8 MaxVolumes; /* 0x6B */
554 } MPI2_CONFIG_PAGE_MAN_4,
555 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4,
556 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t;
557
558 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A)
559
560 /* Manufacturing Page 4 Flags field */
561 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000)
562 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000)
563
564 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000)
565 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000)
566 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000)
567
568 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00)
569 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000)
570 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400)
571 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800)
572 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00)
573
574 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300)
575 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000)
576 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100)
577 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200)
578
579 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080)
580 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040)
581 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020)
582 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010)
583 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008)
584 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004)
585 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002)
586 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001)
587
588
589 /* Manufacturing Page 5 */
590
591 /*
592 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
593 * one and check the value returned for NumPhys at runtime.
594 */
595 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES
596 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1)
597 #endif
598
599 typedef struct _MPI2_MANUFACTURING5_ENTRY
600 {
601 U64 WWID; /* 0x00 */
602 U64 DeviceName; /* 0x08 */
603 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY,
604 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t;
605
606 typedef struct _MPI2_CONFIG_PAGE_MAN_5
607 {
608 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
609 U8 NumPhys; /* 0x04 */
610 U8 Reserved1; /* 0x05 */
611 U16 Reserved2; /* 0x06 */
612 U32 Reserved3; /* 0x08 */
613 U32 Reserved4; /* 0x0C */
614 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */
615 } MPI2_CONFIG_PAGE_MAN_5,
616 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5,
617 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t;
618
619 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03)
620
621
622 /* Manufacturing Page 6 */
623
624 typedef struct _MPI2_CONFIG_PAGE_MAN_6
625 {
626 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
627 U32 ProductSpecificInfo;/* 0x04 */
628 } MPI2_CONFIG_PAGE_MAN_6,
629 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6,
630 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t;
631
632 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00)
633
634
635 /* Manufacturing Page 7 */
636
637 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO
638 {
639 U32 Pinout; /* 0x00 */
640 U8 Connector[16]; /* 0x04 */
641 U8 Location; /* 0x14 */
642 U8 ReceptacleID; /* 0x15 */
643 U16 Slot; /* 0x16 */
644 U32 Reserved2; /* 0x18 */
645 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO,
646 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t;
647
648 /* defines for the Pinout field */
649 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00)
650 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8)
651
652 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF)
653 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00)
654 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01)
655 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02)
656 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03)
657 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04)
658 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05)
659 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06)
660 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07)
661 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08)
662 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09)
663 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A)
664 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B)
665 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C)
666 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D)
667
668 /* defines for the Location field */
669 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01)
670 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02)
671 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04)
672 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08)
673 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10)
674 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20)
675 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80)
676
677 /*
678 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
679 * one and check the value returned for NumPhys at runtime.
680 */
681 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX
682 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1)
683 #endif
684
685 typedef struct _MPI2_CONFIG_PAGE_MAN_7
686 {
687 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
688 U32 Reserved1; /* 0x04 */
689 U32 Reserved2; /* 0x08 */
690 U32 Flags; /* 0x0C */
691 U8 EnclosureName[16]; /* 0x10 */
692 U8 NumPhys; /* 0x20 */
693 U8 Reserved3; /* 0x21 */
694 U16 Reserved4; /* 0x22 */
695 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */
696 } MPI2_CONFIG_PAGE_MAN_7,
697 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7,
698 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t;
699
700 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01)
701
702 /* defines for the Flags field */
703 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002)
704 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001)
705
706
707 /*
708 * Generic structure to use for product-specific manufacturing pages
709 * (currently Manufacturing Page 8 through Manufacturing Page 31).
710 */
711
712 typedef struct _MPI2_CONFIG_PAGE_MAN_PS
713 {
714 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
715 U32 ProductSpecificInfo;/* 0x04 */
716 } MPI2_CONFIG_PAGE_MAN_PS,
717 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS,
718 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t;
719
720 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00)
721 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00)
722 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00)
723 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00)
724 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00)
725 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00)
726 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00)
727 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00)
728 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00)
729 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00)
730 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00)
731 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00)
732 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00)
733 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00)
734 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00)
735 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00)
736 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00)
737 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00)
738 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00)
739 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00)
740 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00)
741 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00)
742 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00)
743 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00)
744
745
746 /****************************************************************************
747 * IO Unit Config Pages
748 ****************************************************************************/
749
750 /* IO Unit Page 0 */
751
752 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0
753 {
754 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
755 U64 UniqueValue; /* 0x04 */
756 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */
757 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */
758 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0,
759 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t;
760
761 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02)
762
763
764 /* IO Unit Page 1 */
765
766 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1
767 {
768 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
769 U32 Flags; /* 0x04 */
770 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1,
771 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t;
772
773 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04)
774
775 /* IO Unit Page 1 Flags defines */
776 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800)
777 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600)
778 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9)
779 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000)
780 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200)
781 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400)
782 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
783 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040)
784 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020)
785 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
786
787
788 /* IO Unit Page 3 */
789
790 /*
791 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
792 * one and check the value returned for GPIOCount at runtime.
793 */
794 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX
795 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
796 #endif
797
798 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3
799 {
800 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
801 U8 GPIOCount; /* 0x04 */
802 U8 Reserved1; /* 0x05 */
803 U16 Reserved2; /* 0x06 */
804 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */
805 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3,
806 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t;
807
808 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01)
809
810 /* defines for IO Unit Page 3 GPIOVal field */
811 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC)
812 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
813 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000)
814 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001)
815
816
817 /* IO Unit Page 5 */
818
819 /*
820 * Upper layer code (drivers, utilities, etc.) should leave this define set to
821 * one and check the value returned for NumDmaEngines at runtime.
822 */
823 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES
824 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1)
825 #endif
826
827 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 {
828 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
829 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */
830 U64 RaidAcceleratorBufferSize; /* 0x0C */
831 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */
832 U8 RAControlSize; /* 0x1C */
833 U8 NumDmaEngines; /* 0x1D */
834 U8 RAMinControlSize; /* 0x1E */
835 U8 RAMaxControlSize; /* 0x1F */
836 U32 Reserved1; /* 0x20 */
837 U32 Reserved2; /* 0x24 */
838 U32 Reserved3; /* 0x28 */
839 U32 DmaEngineCapabilities
840 [MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */
841 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5,
842 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t;
843
844 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00)
845
846 /* defines for IO Unit Page 5 DmaEngineCapabilities field */
847 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00)
848 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16)
849
850 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008)
851 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004)
852 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002)
853 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001)
854
855
856 /* IO Unit Page 6 */
857
858 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 {
859 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
860 U16 Flags; /* 0x04 */
861 U8 RAHostControlSize; /* 0x06 */
862 U8 Reserved0; /* 0x07 */
863 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */
864 U32 Reserved1; /* 0x10 */
865 U32 Reserved2; /* 0x14 */
866 U32 Reserved3; /* 0x18 */
867 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6,
868 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t;
869
870 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00)
871
872 /* defines for IO Unit Page 6 Flags field */
873 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001)
874
875
876 /* IO Unit Page 7 */
877
878 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 {
879 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
880 U16 Reserved1; /* 0x04 */
881 U8 PCIeWidth; /* 0x06 */
882 U8 PCIeSpeed; /* 0x07 */
883 U32 ProcessorState; /* 0x08 */
884 U32 PowerManagementCapabilities; /* 0x0C */
885 U16 IOCTemperature; /* 0x10 */
886 U8 IOCTemperatureUnits; /* 0x12 */
887 U8 IOCSpeed; /* 0x13 */
888 U16 BoardTemperature; /* 0x14 */
889 U8 BoardTemperatureUnits; /* 0x16 */
890 U8 Reserved3; /* 0x17 */
891 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7,
892 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t;
893
894 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02)
895
896 /* defines for IO Unit Page 7 PCIeWidth field */
897 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01)
898 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02)
899 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04)
900 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08)
901
902 /* defines for IO Unit Page 7 PCIeSpeed field */
903 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00)
904 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01)
905 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02)
906
907 /* defines for IO Unit Page 7 ProcessorState field */
908 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F)
909 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0)
910
911 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00)
912 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01)
913 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02)
914
915 /* defines for IO Unit Page 7 PowerManagementCapabilities field */
916 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400)
917 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200)
918 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100)
919 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */
920 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */
921
922 /* defines for IO Unit Page 7 IOCTemperatureUnits field */
923 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00)
924 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01)
925 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02)
926
927 /* defines for IO Unit Page 7 IOCSpeed field */
928 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01)
929 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02)
930 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04)
931 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08)
932
933 /* defines for IO Unit Page 7 BoardTemperatureUnits field */
934 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00)
935 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01)
936 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02)
937
938 /* IO Unit Page 8 */
939
940 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4)
941
942 typedef struct _MPI2_IOUNIT8_SENSOR {
943 U16 Flags; /* 0x00 */
944 U16 Reserved1; /* 0x02 */
945 U16
946 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */
947 U32 Reserved2; /* 0x0C */
948 U32 Reserved3; /* 0x10 */
949 U32 Reserved4; /* 0x14 */
950 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR,
951 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t;
952
953 /* defines for IO Unit Page 8 Sensor Flags field */
954 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008)
955 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004)
956 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002)
957 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001)
958
959 /*
960 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
961 * one and check the value returned for NumSensors at runtime.
962 */
963 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES
964 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1)
965 #endif
966
967 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 {
968 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
969 U32 Reserved1; /* 0x04 */
970 U32 Reserved2; /* 0x08 */
971 U8 NumSensors; /* 0x0C */
972 U8 PollingInterval; /* 0x0D */
973 U16 Reserved3; /* 0x0E */
974 MPI2_IOUNIT8_SENSOR
975 Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */
976 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8,
977 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t;
978
979 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00)
980
981
982 /* IO Unit Page 9 */
983
984 typedef struct _MPI2_IOUNIT9_SENSOR {
985 U16 CurrentTemperature; /* 0x00 */
986 U16 Reserved1; /* 0x02 */
987 U8 Flags; /* 0x04 */
988 U8 Reserved2; /* 0x05 */
989 U16 Reserved3; /* 0x06 */
990 U32 Reserved4; /* 0x08 */
991 U32 Reserved5; /* 0x0C */
992 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR,
993 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t;
994
995 /* defines for IO Unit Page 9 Sensor Flags field */
996 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01)
997
998 /*
999 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1000 * one and check the value returned for NumSensors at runtime.
1001 */
1002 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES
1003 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1)
1004 #endif
1005
1006 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 {
1007 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1008 U32 Reserved1; /* 0x04 */
1009 U32 Reserved2; /* 0x08 */
1010 U8 NumSensors; /* 0x0C */
1011 U8 Reserved4; /* 0x0D */
1012 U16 Reserved3; /* 0x0E */
1013 MPI2_IOUNIT9_SENSOR
1014 Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */
1015 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9,
1016 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t;
1017
1018 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00)
1019
1020
1021 /* IO Unit Page 10 */
1022
1023 typedef struct _MPI2_IOUNIT10_FUNCTION {
1024 U8 CreditPercent; /* 0x00 */
1025 U8 Reserved1; /* 0x01 */
1026 U16 Reserved2; /* 0x02 */
1027 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION,
1028 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t;
1029
1030 /*
1031 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1032 * one and check the value returned for NumFunctions at runtime.
1033 */
1034 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES
1035 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1)
1036 #endif
1037
1038 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 {
1039 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1040 U8 NumFunctions; /* 0x04 */
1041 U8 Reserved1; /* 0x05 */
1042 U16 Reserved2; /* 0x06 */
1043 U32 Reserved3; /* 0x08 */
1044 U32 Reserved4; /* 0x0C */
1045 MPI2_IOUNIT10_FUNCTION
1046 Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES];/* 0x10 */
1047 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10,
1048 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t;
1049
1050 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01)
1051
1052
1053
1054 /****************************************************************************
1055 * IOC Config Pages
1056 ****************************************************************************/
1057
1058 /* IOC Page 0 */
1059
1060 typedef struct _MPI2_CONFIG_PAGE_IOC_0
1061 {
1062 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1063 U32 Reserved1; /* 0x04 */
1064 U32 Reserved2; /* 0x08 */
1065 U16 VendorID; /* 0x0C */
1066 U16 DeviceID; /* 0x0E */
1067 U8 RevisionID; /* 0x10 */
1068 U8 Reserved3; /* 0x11 */
1069 U16 Reserved4; /* 0x12 */
1070 U32 ClassCode; /* 0x14 */
1071 U16 SubsystemVendorID; /* 0x18 */
1072 U16 SubsystemID; /* 0x1A */
1073 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0,
1074 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t;
1075
1076 #define MPI2_IOCPAGE0_PAGEVERSION (0x02)
1077
1078
1079 /* IOC Page 1 */
1080
1081 typedef struct _MPI2_CONFIG_PAGE_IOC_1
1082 {
1083 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1084 U32 Flags; /* 0x04 */
1085 U32 CoalescingTimeout; /* 0x08 */
1086 U8 CoalescingDepth; /* 0x0C */
1087 U8 PCISlotNum; /* 0x0D */
1088 U8 PCIBusNum; /* 0x0E */
1089 U8 PCIDomainSegment; /* 0x0F */
1090 U32 Reserved1; /* 0x10 */
1091 U32 Reserved2; /* 0x14 */
1092 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1,
1093 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t;
1094
1095 #define MPI2_IOCPAGE1_PAGEVERSION (0x05)
1096
1097 /* defines for IOC Page 1 Flags field */
1098 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001)
1099
1100 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
1101 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF)
1102 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF)
1103
1104 /* IOC Page 6 */
1105
1106 typedef struct _MPI2_CONFIG_PAGE_IOC_6
1107 {
1108 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1109 U32 CapabilitiesFlags; /* 0x04 */
1110 U8 MaxDrivesRAID0; /* 0x08 */
1111 U8 MaxDrivesRAID1; /* 0x09 */
1112 U8 MaxDrivesRAID1E; /* 0x0A */
1113 U8 MaxDrivesRAID10; /* 0x0B */
1114 U8 MinDrivesRAID0; /* 0x0C */
1115 U8 MinDrivesRAID1; /* 0x0D */
1116 U8 MinDrivesRAID1E; /* 0x0E */
1117 U8 MinDrivesRAID10; /* 0x0F */
1118 U32 Reserved1; /* 0x10 */
1119 U8 MaxGlobalHotSpares; /* 0x14 */
1120 U8 MaxPhysDisks; /* 0x15 */
1121 U8 MaxVolumes; /* 0x16 */
1122 U8 MaxConfigs; /* 0x17 */
1123 U8 MaxOCEDisks; /* 0x18 */
1124 U8 Reserved2; /* 0x19 */
1125 U16 Reserved3; /* 0x1A */
1126 U32 SupportedStripeSizeMapRAID0; /* 0x1C */
1127 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */
1128 U32 SupportedStripeSizeMapRAID10; /* 0x24 */
1129 U32 Reserved4; /* 0x28 */
1130 U32 Reserved5; /* 0x2C */
1131 U16 DefaultMetadataSize; /* 0x30 */
1132 U16 Reserved6; /* 0x32 */
1133 U16 MaxBadBlockTableEntries; /* 0x34 */
1134 U16 Reserved7; /* 0x36 */
1135 U32 IRNvsramVersion; /* 0x38 */
1136 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6,
1137 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t;
1138
1139 #define MPI2_IOCPAGE6_PAGEVERSION (0x05)
1140
1141 /* defines for IOC Page 6 CapabilitiesFlags */
1142 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020)
1143 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010)
1144 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008)
1145 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004)
1146 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002)
1147 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001)
1148
1149
1150 /* IOC Page 7 */
1151
1152 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4)
1153
1154 typedef struct _MPI2_CONFIG_PAGE_IOC_7
1155 {
1156 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1157 U32 Reserved1; /* 0x04 */
1158 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */
1159 U16 SASBroadcastPrimitiveMasks; /* 0x18 */
1160 U16 SASNotifyPrimitiveMasks; /* 0x1A */
1161 U32 Reserved3; /* 0x1C */
1162 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7,
1163 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t;
1164
1165 #define MPI2_IOCPAGE7_PAGEVERSION (0x02)
1166
1167
1168 /* IOC Page 8 */
1169
1170 typedef struct _MPI2_CONFIG_PAGE_IOC_8
1171 {
1172 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1173 U8 NumDevsPerEnclosure; /* 0x04 */
1174 U8 Reserved1; /* 0x05 */
1175 U16 Reserved2; /* 0x06 */
1176 U16 MaxPersistentEntries; /* 0x08 */
1177 U16 MaxNumPhysicalMappedIDs; /* 0x0A */
1178 U16 Flags; /* 0x0C */
1179 U16 Reserved3; /* 0x0E */
1180 U16 IRVolumeMappingFlags; /* 0x10 */
1181 U16 Reserved4; /* 0x12 */
1182 U32 Reserved5; /* 0x14 */
1183 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8,
1184 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t;
1185
1186 #define MPI2_IOCPAGE8_PAGEVERSION (0x00)
1187
1188 /* defines for IOC Page 8 Flags field */
1189 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020)
1190 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010)
1191
1192 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E)
1193 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000)
1194 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002)
1195
1196 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001)
1197 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000)
1198
1199 /* defines for IOC Page 8 IRVolumeMappingFlags */
1200 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003)
1201 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000)
1202 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001)
1203
1204
1205 /****************************************************************************
1206 * BIOS Config Pages
1207 ****************************************************************************/
1208
1209 /* BIOS Page 1 */
1210
1211 typedef struct _MPI2_CONFIG_PAGE_BIOS_1
1212 {
1213 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1214 U32 BiosOptions; /* 0x04 */
1215 U32 IOCSettings; /* 0x08 */
1216 U32 Reserved1; /* 0x0C */
1217 U32 DeviceSettings; /* 0x10 */
1218 U16 NumberOfDevices; /* 0x14 */
1219 U16 UEFIVersion; /* 0x16 */
1220 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */
1221 U16 IOTimeoutSequential; /* 0x1A */
1222 U16 IOTimeoutOther; /* 0x1C */
1223 U16 IOTimeoutBlockDevicesRM; /* 0x1E */
1224 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1,
1225 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t;
1226
1227 #define MPI2_BIOSPAGE1_PAGEVERSION (0x05)
1228
1229 /* values for BIOS Page 1 BiosOptions field */
1230 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0)
1231 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000)
1232
1233 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006)
1234 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000)
1235 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002)
1236 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004)
1237
1238 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
1239
1240 /* values for BIOS Page 1 IOCSettings field */
1241 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
1242 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
1243 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
1244
1245 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1246 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1247 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1248 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1249
1250 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1251 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1252 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1253 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1254 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1255
1256 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1257
1258 /* values for BIOS Page 1 DeviceSettings field */
1259 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010)
1260 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1261 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1262 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1263 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1264
1265 /* defines for BIOS Page 1 UEFIVersion field */
1266 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00)
1267 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8)
1268 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF)
1269 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0)
1270
1271
1272
1273 /* BIOS Page 2 */
1274
1275 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER
1276 {
1277 U32 Reserved1; /* 0x00 */
1278 U32 Reserved2; /* 0x04 */
1279 U32 Reserved3; /* 0x08 */
1280 U32 Reserved4; /* 0x0C */
1281 U32 Reserved5; /* 0x10 */
1282 U32 Reserved6; /* 0x14 */
1283 } MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1284 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER,
1285 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t;
1286
1287 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID
1288 {
1289 U64 SASAddress; /* 0x00 */
1290 U8 LUN[8]; /* 0x08 */
1291 U32 Reserved1; /* 0x10 */
1292 U32 Reserved2; /* 0x14 */
1293 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID,
1294 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t;
1295
1296 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT
1297 {
1298 U64 EnclosureLogicalID; /* 0x00 */
1299 U32 Reserved1; /* 0x08 */
1300 U32 Reserved2; /* 0x0C */
1301 U16 SlotNumber; /* 0x10 */
1302 U16 Reserved3; /* 0x12 */
1303 U32 Reserved4; /* 0x14 */
1304 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1305 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT,
1306 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t;
1307
1308 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME
1309 {
1310 U64 DeviceName; /* 0x00 */
1311 U8 LUN[8]; /* 0x08 */
1312 U32 Reserved1; /* 0x10 */
1313 U32 Reserved2; /* 0x14 */
1314 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME,
1315 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t;
1316
1317 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE
1318 {
1319 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1320 MPI2_BOOT_DEVICE_SAS_WWID SasWwid;
1321 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1322 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName;
1323 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE,
1324 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t;
1325
1326 typedef struct _MPI2_CONFIG_PAGE_BIOS_2
1327 {
1328 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1329 U32 Reserved1; /* 0x04 */
1330 U32 Reserved2; /* 0x08 */
1331 U32 Reserved3; /* 0x0C */
1332 U32 Reserved4; /* 0x10 */
1333 U32 Reserved5; /* 0x14 */
1334 U32 Reserved6; /* 0x18 */
1335 U8 ReqBootDeviceForm; /* 0x1C */
1336 U8 Reserved7; /* 0x1D */
1337 U16 Reserved8; /* 0x1E */
1338 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */
1339 U8 ReqAltBootDeviceForm; /* 0x38 */
1340 U8 Reserved9; /* 0x39 */
1341 U16 Reserved10; /* 0x3A */
1342 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */
1343 U8 CurrentBootDeviceForm; /* 0x58 */
1344 U8 Reserved11; /* 0x59 */
1345 U16 Reserved12; /* 0x5A */
1346 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */
1347 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2,
1348 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t;
1349
1350 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04)
1351
1352 /* values for BIOS Page 2 BootDeviceForm fields */
1353 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F)
1354 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00)
1355 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05)
1356 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1357 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07)
1358
1359
1360 /* BIOS Page 3 */
1361
1362 typedef struct _MPI2_ADAPTER_INFO
1363 {
1364 U8 PciBusNumber; /* 0x00 */
1365 U8 PciDeviceAndFunctionNumber; /* 0x01 */
1366 U16 AdapterFlags; /* 0x02 */
1367 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO,
1368 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t;
1369
1370 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
1371 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
1372
1373 typedef struct _MPI2_CONFIG_PAGE_BIOS_3
1374 {
1375 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1376 U32 GlobalFlags; /* 0x04 */
1377 U32 BiosVersion; /* 0x08 */
1378 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */
1379 U32 Reserved1; /* 0x1C */
1380 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3,
1381 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t;
1382
1383 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00)
1384
1385 /* values for BIOS Page 3 GlobalFlags */
1386 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002)
1387 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004)
1388 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010)
1389
1390 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
1391 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
1392 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020)
1393 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
1394
1395
1396 /* BIOS Page 4 */
1397
1398 /*
1399 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1400 * one and check the value returned for NumPhys at runtime.
1401 */
1402 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES
1403 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1)
1404 #endif
1405
1406 typedef struct _MPI2_BIOS4_ENTRY
1407 {
1408 U64 ReassignmentWWID; /* 0x00 */
1409 U64 ReassignmentDeviceName; /* 0x08 */
1410 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY,
1411 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t;
1412
1413 typedef struct _MPI2_CONFIG_PAGE_BIOS_4
1414 {
1415 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1416 U8 NumPhys; /* 0x04 */
1417 U8 Reserved1; /* 0x05 */
1418 U16 Reserved2; /* 0x06 */
1419 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */
1420 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4,
1421 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t;
1422
1423 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01)
1424
1425
1426 /****************************************************************************
1427 * RAID Volume Config Pages
1428 ****************************************************************************/
1429
1430 /* RAID Volume Page 0 */
1431
1432 typedef struct _MPI2_RAIDVOL0_PHYS_DISK
1433 {
1434 U8 RAIDSetNum; /* 0x00 */
1435 U8 PhysDiskMap; /* 0x01 */
1436 U8 PhysDiskNum; /* 0x02 */
1437 U8 Reserved; /* 0x03 */
1438 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK,
1439 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t;
1440
1441 /* defines for the PhysDiskMap field */
1442 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1443 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1444
1445 typedef struct _MPI2_RAIDVOL0_SETTINGS
1446 {
1447 U16 Settings; /* 0x00 */
1448 U8 HotSparePool; /* 0x01 */
1449 U8 Reserved; /* 0x02 */
1450 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS,
1451 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t;
1452
1453 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
1454 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01)
1455 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02)
1456 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04)
1457 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08)
1458 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10)
1459 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20)
1460 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40)
1461 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80)
1462
1463 /* RAID Volume Page 0 VolumeSettings defines */
1464 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008)
1465 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004)
1466
1467 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003)
1468 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000)
1469 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001)
1470 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002)
1471
1472 /*
1473 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1474 * one and check the value returned for NumPhysDisks at runtime.
1475 */
1476 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX
1477 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
1478 #endif
1479
1480 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0
1481 {
1482 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1483 U16 DevHandle; /* 0x04 */
1484 U8 VolumeState; /* 0x06 */
1485 U8 VolumeType; /* 0x07 */
1486 U32 VolumeStatusFlags; /* 0x08 */
1487 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */
1488 U64 MaxLBA; /* 0x10 */
1489 U32 StripeSize; /* 0x18 */
1490 U16 BlockSize; /* 0x1C */
1491 U16 Reserved1; /* 0x1E */
1492 U8 SupportedPhysDisks; /* 0x20 */
1493 U8 ResyncRate; /* 0x21 */
1494 U16 DataScrubDuration; /* 0x22 */
1495 U8 NumPhysDisks; /* 0x24 */
1496 U8 Reserved2; /* 0x25 */
1497 U8 Reserved3; /* 0x26 */
1498 U8 InactiveStatus; /* 0x27 */
1499 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */
1500 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0,
1501 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t;
1502
1503 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A)
1504
1505 /* values for RAID VolumeState */
1506 #define MPI2_RAID_VOL_STATE_MISSING (0x00)
1507 #define MPI2_RAID_VOL_STATE_FAILED (0x01)
1508 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02)
1509 #define MPI2_RAID_VOL_STATE_ONLINE (0x03)
1510 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04)
1511 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05)
1512
1513 /* values for RAID VolumeType */
1514 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00)
1515 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01)
1516 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02)
1517 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05)
1518 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF)
1519
1520 /* values for RAID Volume Page 0 VolumeStatusFlags field */
1521 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000)
1522 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000)
1523 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000)
1524 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000)
1525 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000)
1526 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000)
1527 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000)
1528 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000)
1529 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000)
1530 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000)
1531 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080)
1532 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040)
1533 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020)
1534 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000)
1535 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010)
1536 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008)
1537 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004)
1538 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002)
1539 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001)
1540
1541 /* values for RAID Volume Page 0 SupportedPhysDisks field */
1542 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08)
1543 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04)
1544 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02)
1545 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01)
1546
1547 /* values for RAID Volume Page 0 InactiveStatus field */
1548 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
1549 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
1550 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
1551 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
1552 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
1553 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
1554 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
1555
1556
1557 /* RAID Volume Page 1 */
1558
1559 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1
1560 {
1561 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1562 U16 DevHandle; /* 0x04 */
1563 U16 Reserved0; /* 0x06 */
1564 U8 GUID[24]; /* 0x08 */
1565 U8 Name[16]; /* 0x20 */
1566 U64 WWID; /* 0x30 */
1567 U32 Reserved1; /* 0x38 */
1568 U32 Reserved2; /* 0x3C */
1569 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1,
1570 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t;
1571
1572 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03)
1573
1574
1575 /****************************************************************************
1576 * RAID Physical Disk Config Pages
1577 ****************************************************************************/
1578
1579 /* RAID Physical Disk Page 0 */
1580
1581 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS
1582 {
1583 U16 Reserved1; /* 0x00 */
1584 U8 HotSparePool; /* 0x02 */
1585 U8 Reserved2; /* 0x03 */
1586 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS,
1587 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t;
1588
1589 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */
1590
1591 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA
1592 {
1593 U8 VendorID[8]; /* 0x00 */
1594 U8 ProductID[16]; /* 0x08 */
1595 U8 ProductRevLevel[4]; /* 0x18 */
1596 U8 SerialNum[32]; /* 0x1C */
1597 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1598 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA,
1599 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t;
1600
1601 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0
1602 {
1603 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1604 U16 DevHandle; /* 0x04 */
1605 U8 Reserved1; /* 0x06 */
1606 U8 PhysDiskNum; /* 0x07 */
1607 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */
1608 U32 Reserved2; /* 0x0C */
1609 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */
1610 U32 Reserved3; /* 0x4C */
1611 U8 PhysDiskState; /* 0x50 */
1612 U8 OfflineReason; /* 0x51 */
1613 U8 IncompatibleReason; /* 0x52 */
1614 U8 PhysDiskAttributes; /* 0x53 */
1615 U32 PhysDiskStatusFlags; /* 0x54 */
1616 U64 DeviceMaxLBA; /* 0x58 */
1617 U64 HostMaxLBA; /* 0x60 */
1618 U64 CoercedMaxLBA; /* 0x68 */
1619 U16 BlockSize; /* 0x70 */
1620 U16 Reserved5; /* 0x72 */
1621 U32 Reserved6; /* 0x74 */
1622 } MPI2_CONFIG_PAGE_RD_PDISK_0,
1623 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0,
1624 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t;
1625
1626 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05)
1627
1628 /* PhysDiskState defines */
1629 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00)
1630 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01)
1631 #define MPI2_RAID_PD_STATE_OFFLINE (0x02)
1632 #define MPI2_RAID_PD_STATE_ONLINE (0x03)
1633 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04)
1634 #define MPI2_RAID_PD_STATE_DEGRADED (0x05)
1635 #define MPI2_RAID_PD_STATE_REBUILDING (0x06)
1636 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07)
1637
1638 /* OfflineReason defines */
1639 #define MPI2_PHYSDISK0_ONLINE (0x00)
1640 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01)
1641 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03)
1642 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04)
1643 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05)
1644 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06)
1645 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF)
1646
1647 /* IncompatibleReason defines */
1648 #define MPI2_PHYSDISK0_COMPATIBLE (0x00)
1649 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01)
1650 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02)
1651 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03)
1652 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04)
1653 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05)
1654 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06)
1655 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF)
1656
1657 /* PhysDiskAttributes defines */
1658 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C)
1659 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08)
1660 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04)
1661
1662 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03)
1663 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02)
1664 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01)
1665
1666 /* PhysDiskStatusFlags defines */
1667 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040)
1668 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020)
1669 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010)
1670 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000)
1671 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008)
1672 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004)
1673 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002)
1674 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001)
1675
1676
1677 /* RAID Physical Disk Page 1 */
1678
1679 /*
1680 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1681 * one and check the value returned for NumPhysDiskPaths at runtime.
1682 */
1683 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX
1684 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1)
1685 #endif
1686
1687 typedef struct _MPI2_RAIDPHYSDISK1_PATH
1688 {
1689 U16 DevHandle; /* 0x00 */
1690 U16 Reserved1; /* 0x02 */
1691 U64 WWID; /* 0x04 */
1692 U64 OwnerWWID; /* 0x0C */
1693 U8 OwnerIdentifier; /* 0x14 */
1694 U8 Reserved2; /* 0x15 */
1695 U16 Flags; /* 0x16 */
1696 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH,
1697 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t;
1698
1699 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */
1700 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004)
1701 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
1702 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
1703
1704 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1
1705 {
1706 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */
1707 U8 NumPhysDiskPaths; /* 0x04 */
1708 U8 PhysDiskNum; /* 0x05 */
1709 U16 Reserved1; /* 0x06 */
1710 U32 Reserved2; /* 0x08 */
1711 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */
1712 } MPI2_CONFIG_PAGE_RD_PDISK_1,
1713 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1,
1714 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t;
1715
1716 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02)
1717
1718
1719 /****************************************************************************
1720 * values for fields used by several types of SAS Config Pages
1721 ****************************************************************************/
1722
1723 /* values for NegotiatedLinkRates fields */
1724 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0)
1725 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4)
1726 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F)
1727 /* link rates used for Negotiated Physical and Logical Link Rate */
1728 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00)
1729 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01)
1730 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02)
1731 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03)
1732 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04)
1733 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05)
1734 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06)
1735 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08)
1736 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09)
1737 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A)
1738
1739
1740 /* values for AttachedPhyInfo fields */
1741 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040)
1742 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020)
1743 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010)
1744
1745 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F)
1746 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000)
1747 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001)
1748 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002)
1749 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003)
1750 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004)
1751 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005)
1752 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006)
1753 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007)
1754 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008)
1755
1756
1757 /* values for PhyInfo fields */
1758 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000)
1759
1760 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000)
1761 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27)
1762 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000)
1763 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000)
1764 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000)
1765
1766 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000)
1767 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000)
1768 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000)
1769 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000)
1770 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000)
1771 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000)
1772
1773 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000)
1774 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000)
1775 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000)
1776 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000)
1777 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000)
1778 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000)
1779 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000)
1780 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000)
1781 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000)
1782 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000)
1783
1784 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000)
1785 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
1786 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000)
1787 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000)
1788
1789 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
1790 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
1791
1792 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
1793 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000)
1794 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
1795 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020)
1796
1797
1798 /* values for SAS ProgrammedLinkRate fields */
1799 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0)
1800 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
1801 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80)
1802 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90)
1803 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0)
1804 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F)
1805 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
1806 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08)
1807 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09)
1808 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A)
1809
1810
1811 /* values for SAS HwLinkRate fields */
1812 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0)
1813 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80)
1814 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90)
1815 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0)
1816 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F)
1817 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08)
1818 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09)
1819 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A)
1820
1821
1822
1823 /****************************************************************************
1824 * SAS IO Unit Config Pages
1825 ****************************************************************************/
1826
1827 /* SAS IO Unit Page 0 */
1828
1829 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA
1830 {
1831 U8 Port; /* 0x00 */
1832 U8 PortFlags; /* 0x01 */
1833 U8 PhyFlags; /* 0x02 */
1834 U8 NegotiatedLinkRate; /* 0x03 */
1835 U32 ControllerPhyDeviceInfo;/* 0x04 */
1836 U16 AttachedDevHandle; /* 0x08 */
1837 U16 ControllerDevHandle; /* 0x0A */
1838 U32 DiscoveryStatus; /* 0x0C */
1839 U32 Reserved; /* 0x10 */
1840 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA,
1841 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t;
1842
1843 /*
1844 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1845 * one and check the value returned for NumPhys at runtime.
1846 */
1847 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX
1848 #define MPI2_SAS_IOUNIT0_PHY_MAX (1)
1849 #endif
1850
1851 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0
1852 {
1853 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1854 U32 Reserved1; /* 0x08 */
1855 U8 NumPhys; /* 0x0C */
1856 U8 Reserved2; /* 0x0D */
1857 U16 Reserved3; /* 0x0E */
1858 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */
1859 } MPI2_CONFIG_PAGE_SASIOUNIT_0,
1860 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0,
1861 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t;
1862
1863 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05)
1864
1865 /* values for SAS IO Unit Page 0 PortFlags */
1866 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08)
1867 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01)
1868
1869 /* values for SAS IO Unit Page 0 PhyFlags */
1870 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10)
1871 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08)
1872
1873 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
1874
1875 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
1876
1877 /* values for SAS IO Unit Page 0 DiscoveryStatus */
1878 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
1879 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
1880 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000)
1881 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
1882 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000)
1883 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
1884 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
1885 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000)
1886 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
1887 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
1888 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400)
1889 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
1890 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
1891 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
1892 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
1893 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
1894 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010)
1895 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
1896 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
1897 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001)
1898
1899
1900 /* SAS IO Unit Page 1 */
1901
1902 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA
1903 {
1904 U8 Port; /* 0x00 */
1905 U8 PortFlags; /* 0x01 */
1906 U8 PhyFlags; /* 0x02 */
1907 U8 MaxMinLinkRate; /* 0x03 */
1908 U32 ControllerPhyDeviceInfo; /* 0x04 */
1909 U16 MaxTargetPortConnectTime; /* 0x08 */
1910 U16 Reserved1; /* 0x0A */
1911 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA,
1912 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t;
1913
1914 /*
1915 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1916 * one and check the value returned for NumPhys at runtime.
1917 */
1918 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX
1919 #define MPI2_SAS_IOUNIT1_PHY_MAX (1)
1920 #endif
1921
1922 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1
1923 {
1924 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
1925 U16 ControlFlags; /* 0x08 */
1926 U16 SASNarrowMaxQueueDepth; /* 0x0A */
1927 U16 AdditionalControlFlags; /* 0x0C */
1928 U16 SASWideMaxQueueDepth; /* 0x0E */
1929 U8 NumPhys; /* 0x10 */
1930 U8 SATAMaxQDepth; /* 0x11 */
1931 U8 ReportDeviceMissingDelay; /* 0x12 */
1932 U8 IODeviceMissingDelay; /* 0x13 */
1933 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */
1934 } MPI2_CONFIG_PAGE_SASIOUNIT_1,
1935 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1,
1936 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t;
1937
1938 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09)
1939
1940 /* values for SAS IO Unit Page 1 ControlFlags */
1941 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
1942 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
1943 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
1944 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
1945
1946 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
1947 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
1948 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0)
1949 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1)
1950 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2)
1951
1952 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
1953 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
1954 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
1955 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
1956 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008)
1957 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
1958 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
1959 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
1960
1961 /* values for SAS IO Unit Page 1 AdditionalControlFlags */
1962 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080)
1963 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040)
1964 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020)
1965 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010)
1966 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008)
1967 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004)
1968 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002)
1969 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001)
1970
1971 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */
1972 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F)
1973 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80)
1974
1975 /* values for SAS IO Unit Page 1 PortFlags */
1976 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
1977
1978 /* values for SAS IO Unit Page 1 PhyFlags */
1979 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10)
1980 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08)
1981
1982 /* values for SAS IO Unit Page 1 MaxMinLinkRate */
1983 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0)
1984 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80)
1985 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90)
1986 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0)
1987 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F)
1988 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08)
1989 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09)
1990 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A)
1991
1992 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
1993
1994
1995 /* SAS IO Unit Page 4 */
1996
1997 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP
1998 {
1999 U8 MaxTargetSpinup; /* 0x00 */
2000 U8 SpinupDelay; /* 0x01 */
2001 U8 SpinupFlags; /* 0x02 */
2002 U8 Reserved1; /* 0x03 */
2003 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP,
2004 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t;
2005
2006 /* defines for SAS IO Unit Page 4 SpinupFlags */
2007 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01)
2008
2009 /*
2010 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2011 * one and check the value returned for NumPhys at runtime.
2012 */
2013 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX
2014 #define MPI2_SAS_IOUNIT4_PHY_MAX (4)
2015 #endif
2016
2017 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4
2018 {
2019 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2020 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */
2021 U32 Reserved1; /* 0x18 */
2022 U32 Reserved2; /* 0x1C */
2023 U32 Reserved3; /* 0x20 */
2024 U8 BootDeviceWaitTime; /* 0x24 */
2025 U8 Reserved4; /* 0x25 */
2026 U16 Reserved5; /* 0x26 */
2027 U8 NumPhys; /* 0x28 */
2028 U8 PEInitialSpinupDelay; /* 0x29 */
2029 U8 PEReplyDelay; /* 0x2A */
2030 U8 Flags; /* 0x2B */
2031 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */
2032 } MPI2_CONFIG_PAGE_SASIOUNIT_4,
2033 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4,
2034 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t;
2035
2036 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02)
2037
2038 /* defines for Flags field */
2039 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01)
2040
2041 /* defines for PHY field */
2042 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03)
2043
2044
2045 /* SAS IO Unit Page 5 */
2046
2047 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS {
2048 U8 ControlFlags; /* 0x00 */
2049 U8 PortWidthModGroup; /* 0x01 */
2050 U16 InactivityTimerExponent; /* 0x02 */
2051 U8 SATAPartialTimeout; /* 0x04 */
2052 U8 Reserved2; /* 0x05 */
2053 U8 SATASlumberTimeout; /* 0x06 */
2054 U8 Reserved3; /* 0x07 */
2055 U8 SASPartialTimeout; /* 0x08 */
2056 U8 Reserved4; /* 0x09 */
2057 U8 SASSlumberTimeout; /* 0x0A */
2058 U8 Reserved5; /* 0x0B */
2059 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2060 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS,
2061 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t;
2062
2063 /* defines for ControlFlags field */
2064 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08)
2065 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04)
2066 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02)
2067 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01)
2068
2069 /* defines for PortWidthModeGroup field */
2070 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF)
2071
2072 /* defines for InactivityTimerExponent field */
2073 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000)
2074 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12)
2075 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700)
2076 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8)
2077 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070)
2078 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4)
2079 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007)
2080 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0)
2081
2082 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7)
2083 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6)
2084 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5)
2085 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4)
2086 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3)
2087 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2)
2088 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1)
2089 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0)
2090
2091 /*
2092 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2093 * one and check the value returned for NumPhys at runtime.
2094 */
2095 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX
2096 #define MPI2_SAS_IOUNIT5_PHY_MAX (1)
2097 #endif
2098
2099 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 {
2100 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2101 U8 NumPhys; /* 0x08 */
2102 U8 Reserved1; /* 0x09 */
2103 U16 Reserved2; /* 0x0A */
2104 U32 Reserved3; /* 0x0C */
2105 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings
2106 [MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */
2107 } MPI2_CONFIG_PAGE_SASIOUNIT_5,
2108 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5,
2109 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t;
2110
2111 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01)
2112
2113
2114 /* SAS IO Unit Page 6 */
2115
2116 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS {
2117 U8 CurrentStatus; /* 0x00 */
2118 U8 CurrentModulation; /* 0x01 */
2119 U8 CurrentUtilization; /* 0x02 */
2120 U8 Reserved1; /* 0x03 */
2121 U32 Reserved2; /* 0x04 */
2122 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2123 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS,
2124 Mpi2SasIOUnit6PortWidthModGroupStatus_t,
2125 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t;
2126
2127 /* defines for CurrentStatus field */
2128 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00)
2129 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01)
2130 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02)
2131 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03)
2132 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04)
2133 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05)
2134 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06)
2135 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07)
2136
2137 /* defines for CurrentModulation field */
2138 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00)
2139 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01)
2140 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02)
2141 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03)
2142
2143 /*
2144 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2145 * one and check the value returned for NumGroups at runtime.
2146 */
2147 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX
2148 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1)
2149 #endif
2150
2151 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 {
2152 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2153 U32 Reserved1; /* 0x08 */
2154 U32 Reserved2; /* 0x0C */
2155 U8 NumGroups; /* 0x10 */
2156 U8 Reserved3; /* 0x11 */
2157 U16 Reserved4; /* 0x12 */
2158 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS
2159 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */
2160 } MPI2_CONFIG_PAGE_SASIOUNIT_6,
2161 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6,
2162 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t;
2163
2164 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00)
2165
2166
2167 /* SAS IO Unit Page 7 */
2168
2169 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS {
2170 U8 Flags; /* 0x00 */
2171 U8 Reserved1; /* 0x01 */
2172 U16 Reserved2; /* 0x02 */
2173 U8 Threshold75Pct; /* 0x04 */
2174 U8 Threshold50Pct; /* 0x05 */
2175 U8 Threshold25Pct; /* 0x06 */
2176 U8 Reserved3; /* 0x07 */
2177 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2178 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS,
2179 Mpi2SasIOUnit7PortWidthModGroupSettings_t,
2180 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t;
2181
2182 /* defines for Flags field */
2183 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01)
2184
2185
2186 /*
2187 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2188 * one and check the value returned for NumGroups at runtime.
2189 */
2190 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX
2191 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1)
2192 #endif
2193
2194 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 {
2195 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2196 U8 SamplingInterval; /* 0x08 */
2197 U8 WindowLength; /* 0x09 */
2198 U16 Reserved1; /* 0x0A */
2199 U32 Reserved2; /* 0x0C */
2200 U32 Reserved3; /* 0x10 */
2201 U8 NumGroups; /* 0x14 */
2202 U8 Reserved4; /* 0x15 */
2203 U16 Reserved5; /* 0x16 */
2204 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS
2205 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */
2206 } MPI2_CONFIG_PAGE_SASIOUNIT_7,
2207 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7,
2208 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t;
2209
2210 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00)
2211
2212
2213 /* SAS IO Unit Page 8 */
2214
2215 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 {
2216 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2217 U32 Reserved1; /* 0x08 */
2218 U32 PowerManagementCapabilities;/* 0x0C */
2219 U32 Reserved2; /* 0x10 */
2220 } MPI2_CONFIG_PAGE_SASIOUNIT_8,
2221 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8,
2222 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t;
2223
2224 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00)
2225
2226 /* defines for PowerManagementCapabilities field */
2227 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000)
2228 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800)
2229 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400)
2230 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200)
2231 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100)
2232 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010)
2233 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008)
2234 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004)
2235 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002)
2236 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001)
2237
2238
2239
2240 /* SAS IO Unit Page 16 */
2241
2242 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 {
2243 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2244 U64 TimeStamp; /* 0x08 */
2245 U32 Reserved1; /* 0x10 */
2246 U32 Reserved2; /* 0x14 */
2247 U32 FastPathPendedRequests; /* 0x18 */
2248 U32 FastPathUnPendedRequests; /* 0x1C */
2249 U32 FastPathHostRequestStarts; /* 0x20 */
2250 U32 FastPathFirmwareRequestStarts; /* 0x24 */
2251 U32 FastPathHostCompletions; /* 0x28 */
2252 U32 FastPathFirmwareCompletions; /* 0x2C */
2253 U32 NonFastPathRequestStarts; /* 0x30 */
2254 U32 NonFastPathHostCompletions; /* 0x30 */
2255 } MPI2_CONFIG_PAGE_SASIOUNIT16,
2256 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16,
2257 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t;
2258
2259 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00)
2260
2261
2262 /****************************************************************************
2263 * SAS Expander Config Pages
2264 ****************************************************************************/
2265
2266 /* SAS Expander Page 0 */
2267
2268 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0
2269 {
2270 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2271 U8 PhysicalPort; /* 0x08 */
2272 U8 ReportGenLength; /* 0x09 */
2273 U16 EnclosureHandle; /* 0x0A */
2274 U64 SASAddress; /* 0x0C */
2275 U32 DiscoveryStatus; /* 0x14 */
2276 U16 DevHandle; /* 0x18 */
2277 U16 ParentDevHandle; /* 0x1A */
2278 U16 ExpanderChangeCount; /* 0x1C */
2279 U16 ExpanderRouteIndexes; /* 0x1E */
2280 U8 NumPhys; /* 0x20 */
2281 U8 SASLevel; /* 0x21 */
2282 U16 Flags; /* 0x22 */
2283 U16 STPBusInactivityTimeLimit; /* 0x24 */
2284 U16 STPMaxConnectTimeLimit; /* 0x26 */
2285 U16 STP_SMP_NexusLossTime; /* 0x28 */
2286 U16 MaxNumRoutedSasAddresses; /* 0x2A */
2287 U64 ActiveZoneManagerSASAddress;/* 0x2C */
2288 U16 ZoneLockInactivityLimit; /* 0x34 */
2289 U16 Reserved1; /* 0x36 */
2290 U8 TimeToReducedFunc; /* 0x38 */
2291 U8 InitialTimeToReducedFunc; /* 0x39 */
2292 U8 MaxReducedFuncTime; /* 0x3A */
2293 U8 Reserved2; /* 0x3B */
2294 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0,
2295 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t;
2296
2297 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06)
2298
2299 /* values for SAS Expander Page 0 DiscoveryStatus field */
2300 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000)
2301 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000)
2302 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000)
2303 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000)
2304 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000)
2305 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000)
2306 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000)
2307 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000)
2308 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000)
2309 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2310 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2311 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2312 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2313 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2314 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2315 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2316 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2317 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2318 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2319 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2320
2321 /* values for SAS Expander Page 0 Flags field */
2322 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000)
2323 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000)
2324 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800)
2325 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400)
2326 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200)
2327 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100)
2328 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080)
2329 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010)
2330 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004)
2331 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002)
2332 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001)
2333
2334
2335 /* SAS Expander Page 1 */
2336
2337 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1
2338 {
2339 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2340 U8 PhysicalPort; /* 0x08 */
2341 U8 Reserved1; /* 0x09 */
2342 U16 Reserved2; /* 0x0A */
2343 U8 NumPhys; /* 0x0C */
2344 U8 Phy; /* 0x0D */
2345 U16 NumTableEntriesProgrammed; /* 0x0E */
2346 U8 ProgrammedLinkRate; /* 0x10 */
2347 U8 HwLinkRate; /* 0x11 */
2348 U16 AttachedDevHandle; /* 0x12 */
2349 U32 PhyInfo; /* 0x14 */
2350 U32 AttachedDeviceInfo; /* 0x18 */
2351 U16 ExpanderDevHandle; /* 0x1C */
2352 U8 ChangeCount; /* 0x1E */
2353 U8 NegotiatedLinkRate; /* 0x1F */
2354 U8 PhyIdentifier; /* 0x20 */
2355 U8 AttachedPhyIdentifier; /* 0x21 */
2356 U8 Reserved3; /* 0x22 */
2357 U8 DiscoveryInfo; /* 0x23 */
2358 U32 AttachedPhyInfo; /* 0x24 */
2359 U8 ZoneGroup; /* 0x28 */
2360 U8 SelfConfigStatus; /* 0x29 */
2361 U16 Reserved4; /* 0x2A */
2362 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1,
2363 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t;
2364
2365 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02)
2366
2367 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2368
2369 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2370
2371 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2372
2373 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */
2374
2375 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2376
2377 /* values for SAS Expander Page 1 DiscoveryInfo field */
2378 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04)
2379 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2380 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2381
2382 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2383
2384 /****************************************************************************
2385 * SAS Device Config Pages
2386 ****************************************************************************/
2387
2388 /* SAS Device Page 0 */
2389
2390 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0
2391 {
2392 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2393 U16 Slot; /* 0x08 */
2394 U16 EnclosureHandle; /* 0x0A */
2395 U64 SASAddress; /* 0x0C */
2396 U16 ParentDevHandle; /* 0x14 */
2397 U8 PhyNum; /* 0x16 */
2398 U8 AccessStatus; /* 0x17 */
2399 U16 DevHandle; /* 0x18 */
2400 U8 AttachedPhyIdentifier; /* 0x1A */
2401 U8 ZoneGroup; /* 0x1B */
2402 U32 DeviceInfo; /* 0x1C */
2403 U16 Flags; /* 0x20 */
2404 U8 PhysicalPort; /* 0x22 */
2405 U8 MaxPortConnections; /* 0x23 */
2406 U64 DeviceName; /* 0x24 */
2407 U8 PortGroups; /* 0x2C */
2408 U8 DmaGroup; /* 0x2D */
2409 U8 ControlGroup; /* 0x2E */
2410 U8 Reserved1; /* 0x2F */
2411 U32 Reserved2; /* 0x30 */
2412 U32 Reserved3; /* 0x34 */
2413 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0,
2414 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t;
2415
2416 #define MPI2_SASDEVICE0_PAGEVERSION (0x08)
2417
2418 /* values for SAS Device Page 0 AccessStatus field */
2419 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2420 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2421 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2422 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03)
2423 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04)
2424 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05)
2425 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06)
2426 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07)
2427 /* specific values for SATA Init failures */
2428 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10)
2429 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11)
2430 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12)
2431 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13)
2432 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14)
2433 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15)
2434 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16)
2435 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17)
2436 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18)
2437 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19)
2438 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F)
2439
2440 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */
2441
2442 /* values for SAS Device Page 0 Flags field */
2443 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000)
2444 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000)
2445 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800)
2446 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400)
2447 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2448 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2449 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2450 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2451 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2452 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2453 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2454 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2455
2456
2457 /* SAS Device Page 1 */
2458
2459 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1
2460 {
2461 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2462 U32 Reserved1; /* 0x08 */
2463 U64 SASAddress; /* 0x0C */
2464 U32 Reserved2; /* 0x14 */
2465 U16 DevHandle; /* 0x18 */
2466 U16 Reserved3; /* 0x1A */
2467 U8 InitialRegDeviceFIS[20];/* 0x1C */
2468 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1,
2469 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t;
2470
2471 #define MPI2_SASDEVICE1_PAGEVERSION (0x01)
2472
2473
2474 /****************************************************************************
2475 * SAS PHY Config Pages
2476 ****************************************************************************/
2477
2478 /* SAS PHY Page 0 */
2479
2480 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0
2481 {
2482 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2483 U16 OwnerDevHandle; /* 0x08 */
2484 U16 Reserved1; /* 0x0A */
2485 U16 AttachedDevHandle; /* 0x0C */
2486 U8 AttachedPhyIdentifier; /* 0x0E */
2487 U8 Reserved2; /* 0x0F */
2488 U32 AttachedPhyInfo; /* 0x10 */
2489 U8 ProgrammedLinkRate; /* 0x14 */
2490 U8 HwLinkRate; /* 0x15 */
2491 U8 ChangeCount; /* 0x16 */
2492 U8 Flags; /* 0x17 */
2493 U32 PhyInfo; /* 0x18 */
2494 U8 NegotiatedLinkRate; /* 0x1C */
2495 U8 Reserved3; /* 0x1D */
2496 U16 Reserved4; /* 0x1E */
2497 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0,
2498 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t;
2499
2500 #define MPI2_SASPHY0_PAGEVERSION (0x03)
2501
2502 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */
2503
2504 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */
2505
2506 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */
2507
2508 /* values for SAS PHY Page 0 Flags field */
2509 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2510
2511 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */
2512
2513 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */
2514
2515
2516 /* SAS PHY Page 1 */
2517
2518 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1
2519 {
2520 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2521 U32 Reserved1; /* 0x08 */
2522 U32 InvalidDwordCount; /* 0x0C */
2523 U32 RunningDisparityErrorCount; /* 0x10 */
2524 U32 LossDwordSynchCount; /* 0x14 */
2525 U32 PhyResetProblemCount; /* 0x18 */
2526 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1,
2527 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t;
2528
2529 #define MPI2_SASPHY1_PAGEVERSION (0x01)
2530
2531
2532 /* SAS PHY Page 2 */
2533
2534 typedef struct _MPI2_SASPHY2_PHY_EVENT {
2535 U8 PhyEventCode; /* 0x00 */
2536 U8 Reserved1; /* 0x01 */
2537 U16 Reserved2; /* 0x02 */
2538 U32 PhyEventInfo; /* 0x04 */
2539 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT,
2540 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t;
2541
2542 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */
2543
2544
2545 /*
2546 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2547 * one and check the value returned for NumPhyEvents at runtime.
2548 */
2549 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX
2550 #define MPI2_SASPHY2_PHY_EVENT_MAX (1)
2551 #endif
2552
2553 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 {
2554 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2555 U32 Reserved1; /* 0x08 */
2556 U8 NumPhyEvents; /* 0x0C */
2557 U8 Reserved2; /* 0x0D */
2558 U16 Reserved3; /* 0x0E */
2559 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX];
2560 /* 0x10 */
2561 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2,
2562 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t;
2563
2564 #define MPI2_SASPHY2_PAGEVERSION (0x00)
2565
2566
2567 /* SAS PHY Page 3 */
2568
2569 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG {
2570 U8 PhyEventCode; /* 0x00 */
2571 U8 Reserved1; /* 0x01 */
2572 U16 Reserved2; /* 0x02 */
2573 U8 CounterType; /* 0x04 */
2574 U8 ThresholdWindow; /* 0x05 */
2575 U8 TimeUnits; /* 0x06 */
2576 U8 Reserved3; /* 0x07 */
2577 U32 EventThreshold; /* 0x08 */
2578 U16 ThresholdFlags; /* 0x0C */
2579 U16 Reserved4; /* 0x0E */
2580 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG,
2581 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t;
2582
2583 /* values for PhyEventCode field */
2584 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00)
2585 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01)
2586 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02)
2587 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03)
2588 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04)
2589 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05)
2590 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06)
2591 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20)
2592 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21)
2593 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22)
2594 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23)
2595 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24)
2596 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25)
2597 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26)
2598 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27)
2599 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28)
2600 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29)
2601 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A)
2602 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B)
2603 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C)
2604 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D)
2605 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E)
2606 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40)
2607 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41)
2608 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42)
2609 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43)
2610 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44)
2611 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45)
2612 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50)
2613 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51)
2614 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52)
2615 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60)
2616 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61)
2617 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63)
2618 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0)
2619 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1)
2620 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2)
2621
2622 /* values for the CounterType field */
2623 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00)
2624 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01)
2625 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02)
2626
2627 /* values for the TimeUnits field */
2628 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00)
2629 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01)
2630 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02)
2631 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03)
2632
2633 /* values for the ThresholdFlags field */
2634 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002)
2635 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001)
2636
2637 /*
2638 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2639 * one and check the value returned for NumPhyEvents at runtime.
2640 */
2641 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX
2642 #define MPI2_SASPHY3_PHY_EVENT_MAX (1)
2643 #endif
2644
2645 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 {
2646 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2647 U32 Reserved1; /* 0x08 */
2648 U8 NumPhyEvents; /* 0x0C */
2649 U8 Reserved2; /* 0x0D */
2650 U16 Reserved3; /* 0x0E */
2651 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig
2652 [MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */
2653 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3,
2654 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t;
2655
2656 #define MPI2_SASPHY3_PAGEVERSION (0x00)
2657
2658
2659 /* SAS PHY Page 4 */
2660
2661 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 {
2662 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2663 U16 Reserved1; /* 0x08 */
2664 U8 Reserved2; /* 0x0A */
2665 U8 Flags; /* 0x0B */
2666 U8 InitialFrame[28]; /* 0x0C */
2667 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4,
2668 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t;
2669
2670 #define MPI2_SASPHY4_PAGEVERSION (0x00)
2671
2672 /* values for the Flags field */
2673 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02)
2674 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01)
2675
2676
2677
2678
2679 /****************************************************************************
2680 * SAS Port Config Pages
2681 ****************************************************************************/
2682
2683 /* SAS Port Page 0 */
2684
2685 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0
2686 {
2687 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2688 U8 PortNumber; /* 0x08 */
2689 U8 PhysicalPort; /* 0x09 */
2690 U8 PortWidth; /* 0x0A */
2691 U8 PhysicalPortWidth; /* 0x0B */
2692 U8 ZoneGroup; /* 0x0C */
2693 U8 Reserved1; /* 0x0D */
2694 U16 Reserved2; /* 0x0E */
2695 U64 SASAddress; /* 0x10 */
2696 U32 DeviceInfo; /* 0x18 */
2697 U32 Reserved3; /* 0x1C */
2698 U32 Reserved4; /* 0x20 */
2699 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0,
2700 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t;
2701
2702 #define MPI2_SASPORT0_PAGEVERSION (0x00)
2703
2704 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */
2705
2706
2707 /****************************************************************************
2708 * SAS Enclosure Config Pages
2709 ****************************************************************************/
2710
2711 /* SAS Enclosure Page 0 */
2712
2713 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0
2714 {
2715 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2716 U32 Reserved1; /* 0x08 */
2717 U64 EnclosureLogicalID; /* 0x0C */
2718 U16 Flags; /* 0x14 */
2719 U16 EnclosureHandle; /* 0x16 */
2720 U16 NumSlots; /* 0x18 */
2721 U16 StartSlot; /* 0x1A */
2722 U16 Reserved2; /* 0x1C */
2723 U16 SEPDevHandle; /* 0x1E */
2724 U32 Reserved3; /* 0x20 */
2725 U32 Reserved4; /* 0x24 */
2726 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2727 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0,
2728 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t;
2729
2730 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03)
2731
2732 /* values for SAS Enclosure Page 0 Flags field */
2733 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2734 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2735 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2736 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2737 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2738 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2739 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2740
2741
2742 /****************************************************************************
2743 * Log Config Page
2744 ****************************************************************************/
2745
2746 /* Log Page 0 */
2747
2748 /*
2749 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2750 * one and check the value returned for NumLogEntries at runtime.
2751 */
2752 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES
2753 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1)
2754 #endif
2755
2756 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C)
2757
2758 typedef struct _MPI2_LOG_0_ENTRY
2759 {
2760 U64 TimeStamp; /* 0x00 */
2761 U32 Reserved1; /* 0x08 */
2762 U16 LogSequence; /* 0x0C */
2763 U16 LogEntryQualifier; /* 0x0E */
2764 U8 VP_ID; /* 0x10 */
2765 U8 VF_ID; /* 0x11 */
2766 U16 Reserved2; /* 0x12 */
2767 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */
2768 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY,
2769 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t;
2770
2771 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2772 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2773 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2774 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002)
2775 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000)
2776 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF)
2777
2778 typedef struct _MPI2_CONFIG_PAGE_LOG_0
2779 {
2780 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2781 U32 Reserved1; /* 0x08 */
2782 U32 Reserved2; /* 0x0C */
2783 U16 NumLogEntries; /* 0x10 */
2784 U16 Reserved3; /* 0x12 */
2785 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */
2786 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0,
2787 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t;
2788
2789 #define MPI2_LOG_0_PAGEVERSION (0x02)
2790
2791
2792 /****************************************************************************
2793 * RAID Config Page
2794 ****************************************************************************/
2795
2796 /* RAID Page 0 */
2797
2798 /*
2799 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2800 * one and check the value returned for NumElements at runtime.
2801 */
2802 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS
2803 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1)
2804 #endif
2805
2806 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT
2807 {
2808 U16 ElementFlags; /* 0x00 */
2809 U16 VolDevHandle; /* 0x02 */
2810 U8 HotSparePool; /* 0x04 */
2811 U8 PhysDiskNum; /* 0x05 */
2812 U16 PhysDiskDevHandle; /* 0x06 */
2813 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2814 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT,
2815 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t;
2816
2817 /* values for the ElementFlags field */
2818 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F)
2819 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000)
2820 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001)
2821 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002)
2822 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003)
2823
2824
2825 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0
2826 {
2827 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2828 U8 NumHotSpares; /* 0x08 */
2829 U8 NumPhysDisks; /* 0x09 */
2830 U8 NumVolumes; /* 0x0A */
2831 U8 ConfigNum; /* 0x0B */
2832 U32 Flags; /* 0x0C */
2833 U8 ConfigGUID[24]; /* 0x10 */
2834 U32 Reserved1; /* 0x28 */
2835 U8 NumElements; /* 0x2C */
2836 U8 Reserved2; /* 0x2D */
2837 U16 Reserved3; /* 0x2E */
2838 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */
2839 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2840 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0,
2841 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t;
2842
2843 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00)
2844
2845 /* values for RAID Configuration Page 0 Flags field */
2846 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001)
2847
2848
2849 /****************************************************************************
2850 * Driver Persistent Mapping Config Pages
2851 ****************************************************************************/
2852
2853 /* Driver Persistent Mapping Page 0 */
2854
2855 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY
2856 {
2857 U64 PhysicalIdentifier; /* 0x00 */
2858 U16 MappingInformation; /* 0x08 */
2859 U16 DeviceIndex; /* 0x0A */
2860 U32 PhysicalBitsMapping; /* 0x0C */
2861 U32 Reserved1; /* 0x10 */
2862 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2863 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY,
2864 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t;
2865
2866 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0
2867 {
2868 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2869 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */
2870 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2871 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0,
2872 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t;
2873
2874 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00)
2875
2876 /* values for Driver Persistent Mapping Page 0 MappingInformation field */
2877 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0)
2878 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4)
2879 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F)
2880
2881
2882 /****************************************************************************
2883 * Ethernet Config Pages
2884 ****************************************************************************/
2885
2886 /* Ethernet Page 0 */
2887
2888 /* IP address (union of IPv4 and IPv6) */
2889 typedef union _MPI2_ETHERNET_IP_ADDR {
2890 U32 IPv4Addr;
2891 U32 IPv6Addr[4];
2892 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR,
2893 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t;
2894
2895 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32)
2896
2897 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 {
2898 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2899 U8 NumInterfaces; /* 0x08 */
2900 U8 Reserved0; /* 0x09 */
2901 U16 Reserved1; /* 0x0A */
2902 U32 Status; /* 0x0C */
2903 U8 MediaState; /* 0x10 */
2904 U8 Reserved2; /* 0x11 */
2905 U16 Reserved3; /* 0x12 */
2906 U8 MacAddress[6]; /* 0x14 */
2907 U8 Reserved4; /* 0x1A */
2908 U8 Reserved5; /* 0x1B */
2909 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */
2910 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */
2911 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */
2912 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */
2913 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */
2914 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */
2915 U8 HostName
2916 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2917 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0,
2918 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t;
2919
2920 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00)
2921
2922 /* values for Ethernet Page 0 Status field */
2923 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000)
2924 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000)
2925 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000)
2926 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100)
2927 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080)
2928 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040)
2929 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020)
2930 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010)
2931 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008)
2932 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004)
2933 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002)
2934 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001)
2935
2936 /* values for Ethernet Page 0 MediaState field */
2937 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80)
2938 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00)
2939 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80)
2940
2941 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07)
2942 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00)
2943 #define MPI2_ETHPG0_MS_10MBIT (0x01)
2944 #define MPI2_ETHPG0_MS_100MBIT (0x02)
2945 #define MPI2_ETHPG0_MS_1GBIT (0x03)
2946
2947
2948 /* Ethernet Page 1 */
2949
2950 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 {
2951 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
2952 U32 Reserved0; /* 0x08 */
2953 U32 Flags; /* 0x0C */
2954 U8 MediaState; /* 0x10 */
2955 U8 Reserved1; /* 0x11 */
2956 U16 Reserved2; /* 0x12 */
2957 U8 MacAddress[6]; /* 0x14 */
2958 U8 Reserved3; /* 0x1A */
2959 U8 Reserved4; /* 0x1B */
2960 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */
2961 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */
2962 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */
2963 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */
2964 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */
2965 U32 Reserved5; /* 0x6C */
2966 U32 Reserved6; /* 0x70 */
2967 U32 Reserved7; /* 0x74 */
2968 U32 Reserved8; /* 0x78 */
2969 U8 HostName
2970 [MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */
2971 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1,
2972 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t;
2973
2974 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00)
2975
2976 /* values for Ethernet Page 1 Flags field */
2977 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100)
2978 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080)
2979 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040)
2980 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020)
2981 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010)
2982 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008)
2983 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004)
2984 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002)
2985 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001)
2986
2987 /* values for Ethernet Page 1 MediaState field */
2988 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80)
2989 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00)
2990 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80)
2991
2992 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07)
2993 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00)
2994 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01)
2995 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02)
2996 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03)
2997
2998
2999 /****************************************************************************
3000 * Extended Manufacturing Config Pages
3001 ****************************************************************************/
3002
3003 /*
3004 * Generic structure to use for product-specific extended manufacturing pages
3005 * (currently Extended Manufacturing Page 40 through Extended Manufacturing
3006 * Page 60).
3007 */
3008
3009 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS {
3010 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */
3011 U32 ProductSpecificInfo; /* 0x08 */
3012 } MPI2_CONFIG_PAGE_EXT_MAN_PS,
3013 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS,
3014 Mpi2ExtManufacturingPagePS_t,
3015 MPI2_POINTER pMpi2ExtManufacturingPagePS_t;
3016
3017 /* PageVersion should be provided by product-specific code */
3018
3019 #endif
3020
Linux with added FPC-III support