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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / scsi / pm8001 / pm80xx_hwi.c
blobc950dc5c99432967891c093d7bddb0bb24186e7e
1 /*
2 * PMC-Sierra SPCv/ve 8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 PMC-Sierra, Inc.,
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40 #include <linux/slab.h>
41 #include "pm8001_sas.h"
42 #include "pm80xx_hwi.h"
43 #include "pm8001_chips.h"
44 #include "pm8001_ctl.h"
45
46 #define SMP_DIRECT 1
47 #define SMP_INDIRECT 2
48
49
50 int pm80xx_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shift_value)
51 {
52 u32 reg_val;
53 unsigned long start;
54 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER, shift_value);
55 /* confirm the setting is written */
56 start = jiffies + HZ; /* 1 sec */
57 do {
58 reg_val = pm8001_cr32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER);
59 } while ((reg_val != shift_value) && time_before(jiffies, start));
60 if (reg_val != shift_value) {
61 PM8001_FAIL_DBG(pm8001_ha,
62 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
63 " = 0x%x\n", reg_val));
64 return -1;
65 }
66 return 0;
67 }
68
69 void pm80xx_pci_mem_copy(struct pm8001_hba_info *pm8001_ha, u32 soffset,
70 const void *destination,
71 u32 dw_count, u32 bus_base_number)
72 {
73 u32 index, value, offset;
74 u32 *destination1;
75 destination1 = (u32 *)destination;
76
77 for (index = 0; index < dw_count; index += 4, destination1++) {
78 offset = (soffset + index / 4);
79 if (offset < (64 * 1024)) {
80 value = pm8001_cr32(pm8001_ha, bus_base_number, offset);
81 *destination1 = cpu_to_le32(value);
82 }
83 }
84 return;
85 }
86
87 ssize_t pm80xx_get_fatal_dump(struct device *cdev,
88 struct device_attribute *attr, char *buf)
89 {
90 struct Scsi_Host *shost = class_to_shost(cdev);
91 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
92 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
93 void __iomem *fatal_table_address = pm8001_ha->fatal_tbl_addr;
94 u32 status = 1;
95 u32 accum_len , reg_val, index, *temp;
96 unsigned long start;
97 u8 *direct_data;
98 char *fatal_error_data = buf;
99
100 pm8001_ha->forensic_info.data_buf.direct_data = buf;
101 if (pm8001_ha->chip_id == chip_8001) {
102 pm8001_ha->forensic_info.data_buf.direct_data +=
103 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
104 "Not supported for SPC controller");
105 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
106 (char *)buf;
107 }
108 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
109 PM8001_IO_DBG(pm8001_ha,
110 pm8001_printk("forensic_info TYPE_NON_FATAL..............\n"));
111 direct_data = (u8 *)fatal_error_data;
112 pm8001_ha->forensic_info.data_type = TYPE_NON_FATAL;
113 pm8001_ha->forensic_info.data_buf.direct_len = SYSFS_OFFSET;
114 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
115 pm8001_ha->forensic_info.data_buf.read_len = 0;
116
117 pm8001_ha->forensic_info.data_buf.direct_data = direct_data;
118 }
119
120 if (pm8001_ha->forensic_info.data_buf.direct_offset == 0) {
121 /* start to get data */
122 /* Program the MEMBASE II Shifting Register with 0x00.*/
123 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
124 pm8001_ha->fatal_forensic_shift_offset);
125 pm8001_ha->forensic_last_offset = 0;
126 pm8001_ha->forensic_fatal_step = 0;
127 pm8001_ha->fatal_bar_loc = 0;
128 }
129 /* Read until accum_len is retrived */
130 accum_len = pm8001_mr32(fatal_table_address,
131 MPI_FATAL_EDUMP_TABLE_ACCUM_LEN);
132 PM8001_IO_DBG(pm8001_ha, pm8001_printk("accum_len 0x%x\n",
133 accum_len));
134 if (accum_len == 0xFFFFFFFF) {
135 PM8001_IO_DBG(pm8001_ha,
136 pm8001_printk("Possible PCI issue 0x%x not expected\n",
137 accum_len));
138 return status;
139 }
140 if (accum_len == 0 || accum_len >= 0x100000) {
141 pm8001_ha->forensic_info.data_buf.direct_data +=
142 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
143 "%08x ", 0xFFFFFFFF);
144 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
145 (char *)buf;
146 }
147 temp = (u32 *)pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr;
148 if (pm8001_ha->forensic_fatal_step == 0) {
149 moreData:
150 if (pm8001_ha->forensic_info.data_buf.direct_data) {
151 /* Data is in bar, copy to host memory */
152 pm80xx_pci_mem_copy(pm8001_ha, pm8001_ha->fatal_bar_loc,
153 pm8001_ha->memoryMap.region[FORENSIC_MEM].virt_ptr,
154 pm8001_ha->forensic_info.data_buf.direct_len ,
155 1);
156 }
157 pm8001_ha->fatal_bar_loc +=
158 pm8001_ha->forensic_info.data_buf.direct_len;
159 pm8001_ha->forensic_info.data_buf.direct_offset +=
160 pm8001_ha->forensic_info.data_buf.direct_len;
161 pm8001_ha->forensic_last_offset +=
162 pm8001_ha->forensic_info.data_buf.direct_len;
163 pm8001_ha->forensic_info.data_buf.read_len =
164 pm8001_ha->forensic_info.data_buf.direct_len;
165
166 if (pm8001_ha->forensic_last_offset >= accum_len) {
167 pm8001_ha->forensic_info.data_buf.direct_data +=
168 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
169 "%08x ", 3);
170 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
171 pm8001_ha->forensic_info.data_buf.direct_data +=
172 sprintf(pm8001_ha->
173 forensic_info.data_buf.direct_data,
174 "%08x ", *(temp + index));
175 }
176
177 pm8001_ha->fatal_bar_loc = 0;
178 pm8001_ha->forensic_fatal_step = 1;
179 pm8001_ha->fatal_forensic_shift_offset = 0;
180 pm8001_ha->forensic_last_offset = 0;
181 status = 0;
182 return (char *)pm8001_ha->
183 forensic_info.data_buf.direct_data -
184 (char *)buf;
185 }
186 if (pm8001_ha->fatal_bar_loc < (64 * 1024)) {
187 pm8001_ha->forensic_info.data_buf.direct_data +=
188 sprintf(pm8001_ha->
189 forensic_info.data_buf.direct_data,
190 "%08x ", 2);
191 for (index = 0; index < (SYSFS_OFFSET / 4); index++) {
192 pm8001_ha->forensic_info.data_buf.direct_data +=
193 sprintf(pm8001_ha->
194 forensic_info.data_buf.direct_data,
195 "%08x ", *(temp + index));
196 }
197 status = 0;
198 return (char *)pm8001_ha->
199 forensic_info.data_buf.direct_data -
200 (char *)buf;
201 }
202
203 /* Increment the MEMBASE II Shifting Register value by 0x100.*/
204 pm8001_ha->forensic_info.data_buf.direct_data +=
205 sprintf(pm8001_ha->forensic_info.data_buf.direct_data,
206 "%08x ", 2);
207 for (index = 0; index < 256; index++) {
208 pm8001_ha->forensic_info.data_buf.direct_data +=
209 sprintf(pm8001_ha->
210 forensic_info.data_buf.direct_data,
211 "%08x ", *(temp + index));
212 }
213 pm8001_ha->fatal_forensic_shift_offset += 0x100;
214 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
215 pm8001_ha->fatal_forensic_shift_offset);
216 pm8001_ha->fatal_bar_loc = 0;
217 status = 0;
218 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
219 (char *)buf;
220 }
221 if (pm8001_ha->forensic_fatal_step == 1) {
222 pm8001_ha->fatal_forensic_shift_offset = 0;
223 /* Read 64K of the debug data. */
224 pm8001_cw32(pm8001_ha, 0, MEMBASE_II_SHIFT_REGISTER,
225 pm8001_ha->fatal_forensic_shift_offset);
226 pm8001_mw32(fatal_table_address,
227 MPI_FATAL_EDUMP_TABLE_HANDSHAKE,
228 MPI_FATAL_EDUMP_HANDSHAKE_RDY);
229
230 /* Poll FDDHSHK until clear */
231 start = jiffies + (2 * HZ); /* 2 sec */
232
233 do {
234 reg_val = pm8001_mr32(fatal_table_address,
235 MPI_FATAL_EDUMP_TABLE_HANDSHAKE);
236 } while ((reg_val) && time_before(jiffies, start));
237
238 if (reg_val != 0) {
239 PM8001_FAIL_DBG(pm8001_ha,
240 pm8001_printk("TIMEOUT:MEMBASE_II_SHIFT_REGISTER"
241 " = 0x%x\n", reg_val));
242 return -1;
243 }
244
245 /* Read the next 64K of the debug data. */
246 pm8001_ha->forensic_fatal_step = 0;
247 if (pm8001_mr32(fatal_table_address,
248 MPI_FATAL_EDUMP_TABLE_STATUS) !=
249 MPI_FATAL_EDUMP_TABLE_STAT_NF_SUCCESS_DONE) {
250 pm8001_mw32(fatal_table_address,
251 MPI_FATAL_EDUMP_TABLE_HANDSHAKE, 0);
252 goto moreData;
253 } else {
254 pm8001_ha->forensic_info.data_buf.direct_data +=
255 sprintf(pm8001_ha->
256 forensic_info.data_buf.direct_data,
257 "%08x ", 4);
258 pm8001_ha->forensic_info.data_buf.read_len = 0xFFFFFFFF;
259 pm8001_ha->forensic_info.data_buf.direct_len = 0;
260 pm8001_ha->forensic_info.data_buf.direct_offset = 0;
261 pm8001_ha->forensic_info.data_buf.read_len = 0;
262 status = 0;
263 }
264 }
265
266 return (char *)pm8001_ha->forensic_info.data_buf.direct_data -
267 (char *)buf;
268 }
269
270 /**
271 * read_main_config_table - read the configure table and save it.
272 * @pm8001_ha: our hba card information
273 */
274 static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
275 {
276 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
277
278 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
279 pm8001_mr32(address, MAIN_SIGNATURE_OFFSET);
280 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
281 pm8001_mr32(address, MAIN_INTERFACE_REVISION);
282 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
283 pm8001_mr32(address, MAIN_FW_REVISION);
284 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
285 pm8001_mr32(address, MAIN_MAX_OUTSTANDING_IO_OFFSET);
286 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
287 pm8001_mr32(address, MAIN_MAX_SGL_OFFSET);
288 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
289 pm8001_mr32(address, MAIN_CNTRL_CAP_OFFSET);
290 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
291 pm8001_mr32(address, MAIN_GST_OFFSET);
292 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
293 pm8001_mr32(address, MAIN_IBQ_OFFSET);
294 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
295 pm8001_mr32(address, MAIN_OBQ_OFFSET);
296
297 /* read Error Dump Offset and Length */
298 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
299 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
300 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
301 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
302 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
303 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
304 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
305 pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
306
307 /* read GPIO LED settings from the configuration table */
308 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
309 pm8001_mr32(address, MAIN_GPIO_LED_FLAGS_OFFSET);
310
311 /* read analog Setting offset from the configuration table */
312 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
313 pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
314
315 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
316 pm8001_mr32(address, MAIN_INT_VECTOR_TABLE_OFFSET);
317 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
318 pm8001_mr32(address, MAIN_SAS_PHY_ATTR_TABLE_OFFSET);
319 }
320
321 /**
322 * read_general_status_table - read the general status table and save it.
323 * @pm8001_ha: our hba card information
324 */
325 static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
326 {
327 void __iomem *address = pm8001_ha->general_stat_tbl_addr;
328 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
329 pm8001_mr32(address, GST_GSTLEN_MPIS_OFFSET);
330 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
331 pm8001_mr32(address, GST_IQ_FREEZE_STATE0_OFFSET);
332 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
333 pm8001_mr32(address, GST_IQ_FREEZE_STATE1_OFFSET);
334 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
335 pm8001_mr32(address, GST_MSGUTCNT_OFFSET);
336 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
337 pm8001_mr32(address, GST_IOPTCNT_OFFSET);
338 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
339 pm8001_mr32(address, GST_GPIO_INPUT_VAL);
340 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
341 pm8001_mr32(address, GST_RERRINFO_OFFSET0);
342 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
343 pm8001_mr32(address, GST_RERRINFO_OFFSET1);
344 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
345 pm8001_mr32(address, GST_RERRINFO_OFFSET2);
346 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
347 pm8001_mr32(address, GST_RERRINFO_OFFSET3);
348 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
349 pm8001_mr32(address, GST_RERRINFO_OFFSET4);
350 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
351 pm8001_mr32(address, GST_RERRINFO_OFFSET5);
352 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
353 pm8001_mr32(address, GST_RERRINFO_OFFSET6);
354 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
355 pm8001_mr32(address, GST_RERRINFO_OFFSET7);
356 }
357 /**
358 * read_phy_attr_table - read the phy attribute table and save it.
359 * @pm8001_ha: our hba card information
360 */
361 static void read_phy_attr_table(struct pm8001_hba_info *pm8001_ha)
362 {
363 void __iomem *address = pm8001_ha->pspa_q_tbl_addr;
364 pm8001_ha->phy_attr_table.phystart1_16[0] =
365 pm8001_mr32(address, PSPA_PHYSTATE0_OFFSET);
366 pm8001_ha->phy_attr_table.phystart1_16[1] =
367 pm8001_mr32(address, PSPA_PHYSTATE1_OFFSET);
368 pm8001_ha->phy_attr_table.phystart1_16[2] =
369 pm8001_mr32(address, PSPA_PHYSTATE2_OFFSET);
370 pm8001_ha->phy_attr_table.phystart1_16[3] =
371 pm8001_mr32(address, PSPA_PHYSTATE3_OFFSET);
372 pm8001_ha->phy_attr_table.phystart1_16[4] =
373 pm8001_mr32(address, PSPA_PHYSTATE4_OFFSET);
374 pm8001_ha->phy_attr_table.phystart1_16[5] =
375 pm8001_mr32(address, PSPA_PHYSTATE5_OFFSET);
376 pm8001_ha->phy_attr_table.phystart1_16[6] =
377 pm8001_mr32(address, PSPA_PHYSTATE6_OFFSET);
378 pm8001_ha->phy_attr_table.phystart1_16[7] =
379 pm8001_mr32(address, PSPA_PHYSTATE7_OFFSET);
380 pm8001_ha->phy_attr_table.phystart1_16[8] =
381 pm8001_mr32(address, PSPA_PHYSTATE8_OFFSET);
382 pm8001_ha->phy_attr_table.phystart1_16[9] =
383 pm8001_mr32(address, PSPA_PHYSTATE9_OFFSET);
384 pm8001_ha->phy_attr_table.phystart1_16[10] =
385 pm8001_mr32(address, PSPA_PHYSTATE10_OFFSET);
386 pm8001_ha->phy_attr_table.phystart1_16[11] =
387 pm8001_mr32(address, PSPA_PHYSTATE11_OFFSET);
388 pm8001_ha->phy_attr_table.phystart1_16[12] =
389 pm8001_mr32(address, PSPA_PHYSTATE12_OFFSET);
390 pm8001_ha->phy_attr_table.phystart1_16[13] =
391 pm8001_mr32(address, PSPA_PHYSTATE13_OFFSET);
392 pm8001_ha->phy_attr_table.phystart1_16[14] =
393 pm8001_mr32(address, PSPA_PHYSTATE14_OFFSET);
394 pm8001_ha->phy_attr_table.phystart1_16[15] =
395 pm8001_mr32(address, PSPA_PHYSTATE15_OFFSET);
396
397 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[0] =
398 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID0_OFFSET);
399 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[1] =
400 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID1_OFFSET);
401 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[2] =
402 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID2_OFFSET);
403 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[3] =
404 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID3_OFFSET);
405 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[4] =
406 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID4_OFFSET);
407 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[5] =
408 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID5_OFFSET);
409 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[6] =
410 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID6_OFFSET);
411 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[7] =
412 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID7_OFFSET);
413 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[8] =
414 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID8_OFFSET);
415 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[9] =
416 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID9_OFFSET);
417 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[10] =
418 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID10_OFFSET);
419 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[11] =
420 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID11_OFFSET);
421 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[12] =
422 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID12_OFFSET);
423 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[13] =
424 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID13_OFFSET);
425 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[14] =
426 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID14_OFFSET);
427 pm8001_ha->phy_attr_table.outbound_hw_event_pid1_16[15] =
428 pm8001_mr32(address, PSPA_OB_HW_EVENT_PID15_OFFSET);
429
430 }
431
432 /**
433 * read_inbnd_queue_table - read the inbound queue table and save it.
434 * @pm8001_ha: our hba card information
435 */
436 static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
437 {
438 int i;
439 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
440 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
441 u32 offset = i * 0x20;
442 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
443 get_pci_bar_index(pm8001_mr32(address,
444 (offset + IB_PIPCI_BAR)));
445 pm8001_ha->inbnd_q_tbl[i].pi_offset =
446 pm8001_mr32(address, (offset + IB_PIPCI_BAR_OFFSET));
447 }
448 }
449
450 /**
451 * read_outbnd_queue_table - read the outbound queue table and save it.
452 * @pm8001_ha: our hba card information
453 */
454 static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
455 {
456 int i;
457 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
458 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
459 u32 offset = i * 0x24;
460 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
461 get_pci_bar_index(pm8001_mr32(address,
462 (offset + OB_CIPCI_BAR)));
463 pm8001_ha->outbnd_q_tbl[i].ci_offset =
464 pm8001_mr32(address, (offset + OB_CIPCI_BAR_OFFSET));
465 }
466 }
467
468 /**
469 * init_default_table_values - init the default table.
470 * @pm8001_ha: our hba card information
471 */
472 static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
473 {
474 int i;
475 u32 offsetib, offsetob;
476 void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
477 void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
478
479 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
480 pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
481 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
482 pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
483 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
484 PM8001_EVENT_LOG_SIZE;
485 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
486 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
487 pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
488 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
489 pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
490 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
491 PM8001_EVENT_LOG_SIZE;
492 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
493 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
494
495 /* Disable end to end CRC checking */
496 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
497
498 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
499 pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt =
500 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
501 pm8001_ha->inbnd_q_tbl[i].upper_base_addr =
502 pm8001_ha->memoryMap.region[IB + i].phys_addr_hi;
503 pm8001_ha->inbnd_q_tbl[i].lower_base_addr =
504 pm8001_ha->memoryMap.region[IB + i].phys_addr_lo;
505 pm8001_ha->inbnd_q_tbl[i].base_virt =
506 (u8 *)pm8001_ha->memoryMap.region[IB + i].virt_ptr;
507 pm8001_ha->inbnd_q_tbl[i].total_length =
508 pm8001_ha->memoryMap.region[IB + i].total_len;
509 pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr =
510 pm8001_ha->memoryMap.region[CI + i].phys_addr_hi;
511 pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr =
512 pm8001_ha->memoryMap.region[CI + i].phys_addr_lo;
513 pm8001_ha->inbnd_q_tbl[i].ci_virt =
514 pm8001_ha->memoryMap.region[CI + i].virt_ptr;
515 offsetib = i * 0x20;
516 pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
517 get_pci_bar_index(pm8001_mr32(addressib,
518 (offsetib + 0x14)));
519 pm8001_ha->inbnd_q_tbl[i].pi_offset =
520 pm8001_mr32(addressib, (offsetib + 0x18));
521 pm8001_ha->inbnd_q_tbl[i].producer_idx = 0;
522 pm8001_ha->inbnd_q_tbl[i].consumer_index = 0;
523 }
524 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
525 pm8001_ha->outbnd_q_tbl[i].element_size_cnt =
526 PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
527 pm8001_ha->outbnd_q_tbl[i].upper_base_addr =
528 pm8001_ha->memoryMap.region[OB + i].phys_addr_hi;
529 pm8001_ha->outbnd_q_tbl[i].lower_base_addr =
530 pm8001_ha->memoryMap.region[OB + i].phys_addr_lo;
531 pm8001_ha->outbnd_q_tbl[i].base_virt =
532 (u8 *)pm8001_ha->memoryMap.region[OB + i].virt_ptr;
533 pm8001_ha->outbnd_q_tbl[i].total_length =
534 pm8001_ha->memoryMap.region[OB + i].total_len;
535 pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr =
536 pm8001_ha->memoryMap.region[PI + i].phys_addr_hi;
537 pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr =
538 pm8001_ha->memoryMap.region[PI + i].phys_addr_lo;
539 /* interrupt vector based on oq */
540 pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay = (i << 24);
541 pm8001_ha->outbnd_q_tbl[i].pi_virt =
542 pm8001_ha->memoryMap.region[PI + i].virt_ptr;
543 offsetob = i * 0x24;
544 pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
545 get_pci_bar_index(pm8001_mr32(addressob,
546 offsetob + 0x14));
547 pm8001_ha->outbnd_q_tbl[i].ci_offset =
548 pm8001_mr32(addressob, (offsetob + 0x18));
549 pm8001_ha->outbnd_q_tbl[i].consumer_idx = 0;
550 pm8001_ha->outbnd_q_tbl[i].producer_index = 0;
551 }
552 }
553
554 /**
555 * update_main_config_table - update the main default table to the HBA.
556 * @pm8001_ha: our hba card information
557 */
558 static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
559 {
560 void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
561 pm8001_mw32(address, MAIN_IQNPPD_HPPD_OFFSET,
562 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
563 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_HI,
564 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
565 pm8001_mw32(address, MAIN_EVENT_LOG_ADDR_LO,
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
567 pm8001_mw32(address, MAIN_EVENT_LOG_BUFF_SIZE,
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
569 pm8001_mw32(address, MAIN_EVENT_LOG_OPTION,
570 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
571 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_HI,
572 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
573 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_ADDR_LO,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
575 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_BUFF_SIZE,
576 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
577 pm8001_mw32(address, MAIN_PCS_EVENT_LOG_OPTION,
578 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
579 pm8001_mw32(address, MAIN_FATAL_ERROR_INTERRUPT,
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
581 pm8001_mw32(address, MAIN_EVENT_CRC_CHECK,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
583
584 /* SPCv specific */
585 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
586 /* Set GPIOLED to 0x2 for LED indicator */
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
588 pm8001_mw32(address, MAIN_GPIO_LED_FLAGS_OFFSET,
589 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
590
591 pm8001_mw32(address, MAIN_PORT_RECOVERY_TIMER,
592 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
593 pm8001_mw32(address, MAIN_INT_REASSERTION_DELAY,
594 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
595 }
596
597 /**
598 * update_inbnd_queue_table - update the inbound queue table to the HBA.
599 * @pm8001_ha: our hba card information
600 */
601 static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
602 int number)
603 {
604 void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
605 u16 offset = number * 0x20;
606 pm8001_mw32(address, offset + IB_PROPERITY_OFFSET,
607 pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
608 pm8001_mw32(address, offset + IB_BASE_ADDR_HI_OFFSET,
609 pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
610 pm8001_mw32(address, offset + IB_BASE_ADDR_LO_OFFSET,
611 pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
612 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_HI_OFFSET,
613 pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
614 pm8001_mw32(address, offset + IB_CI_BASE_ADDR_LO_OFFSET,
615 pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
616 }
617
618 /**
619 * update_outbnd_queue_table - update the outbound queue table to the HBA.
620 * @pm8001_ha: our hba card information
621 */
622 static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
623 int number)
624 {
625 void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
626 u16 offset = number * 0x24;
627 pm8001_mw32(address, offset + OB_PROPERITY_OFFSET,
628 pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
629 pm8001_mw32(address, offset + OB_BASE_ADDR_HI_OFFSET,
630 pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
631 pm8001_mw32(address, offset + OB_BASE_ADDR_LO_OFFSET,
632 pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
633 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_HI_OFFSET,
634 pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
635 pm8001_mw32(address, offset + OB_PI_BASE_ADDR_LO_OFFSET,
636 pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
637 pm8001_mw32(address, offset + OB_INTERRUPT_COALES_OFFSET,
638 pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
639 }
640
641 /**
642 * mpi_init_check - check firmware initialization status.
643 * @pm8001_ha: our hba card information
644 */
645 static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
646 {
647 u32 max_wait_count;
648 u32 value;
649 u32 gst_len_mpistate;
650
651 /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
652 table is updated */
653 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_UPDATE);
654 /* wait until Inbound DoorBell Clear Register toggled */
655 if (IS_SPCV_12G(pm8001_ha->pdev)) {
656 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
657 } else {
658 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
659 }
660 do {
661 udelay(1);
662 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
663 value &= SPCv_MSGU_CFG_TABLE_UPDATE;
664 } while ((value != 0) && (--max_wait_count));
665
666 if (!max_wait_count)
667 return -1;
668 /* check the MPI-State for initialization upto 100ms*/
669 max_wait_count = 100 * 1000;/* 100 msec */
670 do {
671 udelay(1);
672 gst_len_mpistate =
673 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
674 GST_GSTLEN_MPIS_OFFSET);
675 } while ((GST_MPI_STATE_INIT !=
676 (gst_len_mpistate & GST_MPI_STATE_MASK)) && (--max_wait_count));
677 if (!max_wait_count)
678 return -1;
679
680 /* check MPI Initialization error */
681 gst_len_mpistate = gst_len_mpistate >> 16;
682 if (0x0000 != gst_len_mpistate)
683 return -1;
684
685 return 0;
686 }
687
688 /**
689 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
690 * @pm8001_ha: our hba card information
691 */
692 static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
693 {
694 u32 value;
695 u32 max_wait_count;
696 u32 max_wait_time;
697 int ret = 0;
698
699 /* reset / PCIe ready */
700 max_wait_time = max_wait_count = 100 * 1000; /* 100 milli sec */
701 do {
702 udelay(1);
703 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
704 } while ((value == 0xFFFFFFFF) && (--max_wait_count));
705
706 /* check ila status */
707 max_wait_time = max_wait_count = 1000 * 1000; /* 1000 milli sec */
708 do {
709 udelay(1);
710 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
711 } while (((value & SCRATCH_PAD_ILA_READY) !=
712 SCRATCH_PAD_ILA_READY) && (--max_wait_count));
713 if (!max_wait_count)
714 ret = -1;
715 else {
716 PM8001_MSG_DBG(pm8001_ha,
717 pm8001_printk(" ila ready status in %d millisec\n",
718 (max_wait_time - max_wait_count)));
719 }
720
721 /* check RAAE status */
722 max_wait_time = max_wait_count = 1800 * 1000; /* 1800 milli sec */
723 do {
724 udelay(1);
725 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
726 } while (((value & SCRATCH_PAD_RAAE_READY) !=
727 SCRATCH_PAD_RAAE_READY) && (--max_wait_count));
728 if (!max_wait_count)
729 ret = -1;
730 else {
731 PM8001_MSG_DBG(pm8001_ha,
732 pm8001_printk(" raae ready status in %d millisec\n",
733 (max_wait_time - max_wait_count)));
734 }
735
736 /* check iop0 status */
737 max_wait_time = max_wait_count = 600 * 1000; /* 600 milli sec */
738 do {
739 udelay(1);
740 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
741 } while (((value & SCRATCH_PAD_IOP0_READY) != SCRATCH_PAD_IOP0_READY) &&
742 (--max_wait_count));
743 if (!max_wait_count)
744 ret = -1;
745 else {
746 PM8001_MSG_DBG(pm8001_ha,
747 pm8001_printk(" iop0 ready status in %d millisec\n",
748 (max_wait_time - max_wait_count)));
749 }
750
751 /* check iop1 status only for 16 port controllers */
752 if ((pm8001_ha->chip_id != chip_8008) &&
753 (pm8001_ha->chip_id != chip_8009)) {
754 /* 200 milli sec */
755 max_wait_time = max_wait_count = 200 * 1000;
756 do {
757 udelay(1);
758 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
759 } while (((value & SCRATCH_PAD_IOP1_READY) !=
760 SCRATCH_PAD_IOP1_READY) && (--max_wait_count));
761 if (!max_wait_count)
762 ret = -1;
763 else {
764 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
765 "iop1 ready status in %d millisec\n",
766 (max_wait_time - max_wait_count)));
767 }
768 }
769
770 return ret;
771 }
772
773 static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
774 {
775 void __iomem *base_addr;
776 u32 value;
777 u32 offset;
778 u32 pcibar;
779 u32 pcilogic;
780
781 value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
782 offset = value & 0x03FFFFFF; /* scratch pad 0 TBL address */
783
784 PM8001_INIT_DBG(pm8001_ha,
785 pm8001_printk("Scratchpad 0 Offset: 0x%x value 0x%x\n",
786 offset, value));
787 pcilogic = (value & 0xFC000000) >> 26;
788 pcibar = get_pci_bar_index(pcilogic);
789 PM8001_INIT_DBG(pm8001_ha,
790 pm8001_printk("Scratchpad 0 PCI BAR: %d\n", pcibar));
791 pm8001_ha->main_cfg_tbl_addr = base_addr =
792 pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
793 pm8001_ha->general_stat_tbl_addr =
794 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x18) &
795 0xFFFFFF);
796 pm8001_ha->inbnd_q_tbl_addr =
797 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C) &
798 0xFFFFFF);
799 pm8001_ha->outbnd_q_tbl_addr =
800 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x20) &
801 0xFFFFFF);
802 pm8001_ha->ivt_tbl_addr =
803 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C) &
804 0xFFFFFF);
805 pm8001_ha->pspa_q_tbl_addr =
806 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0x90) &
807 0xFFFFFF);
808 pm8001_ha->fatal_tbl_addr =
809 base_addr + (pm8001_cr32(pm8001_ha, pcibar, offset + 0xA0) &
810 0xFFFFFF);
811
812 PM8001_INIT_DBG(pm8001_ha,
813 pm8001_printk("GST OFFSET 0x%x\n",
814 pm8001_cr32(pm8001_ha, pcibar, offset + 0x18)));
815 PM8001_INIT_DBG(pm8001_ha,
816 pm8001_printk("INBND OFFSET 0x%x\n",
817 pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C)));
818 PM8001_INIT_DBG(pm8001_ha,
819 pm8001_printk("OBND OFFSET 0x%x\n",
820 pm8001_cr32(pm8001_ha, pcibar, offset + 0x20)));
821 PM8001_INIT_DBG(pm8001_ha,
822 pm8001_printk("IVT OFFSET 0x%x\n",
823 pm8001_cr32(pm8001_ha, pcibar, offset + 0x8C)));
824 PM8001_INIT_DBG(pm8001_ha,
825 pm8001_printk("PSPA OFFSET 0x%x\n",
826 pm8001_cr32(pm8001_ha, pcibar, offset + 0x90)));
827 PM8001_INIT_DBG(pm8001_ha,
828 pm8001_printk("addr - main cfg %p general status %p\n",
829 pm8001_ha->main_cfg_tbl_addr,
830 pm8001_ha->general_stat_tbl_addr));
831 PM8001_INIT_DBG(pm8001_ha,
832 pm8001_printk("addr - inbnd %p obnd %p\n",
833 pm8001_ha->inbnd_q_tbl_addr,
834 pm8001_ha->outbnd_q_tbl_addr));
835 PM8001_INIT_DBG(pm8001_ha,
836 pm8001_printk("addr - pspa %p ivt %p\n",
837 pm8001_ha->pspa_q_tbl_addr,
838 pm8001_ha->ivt_tbl_addr));
839 }
840
841 /**
842 * pm80xx_set_thermal_config - support the thermal configuration
843 * @pm8001_ha: our hba card information.
844 */
845 int
846 pm80xx_set_thermal_config(struct pm8001_hba_info *pm8001_ha)
847 {
848 struct set_ctrl_cfg_req payload;
849 struct inbound_queue_table *circularQ;
850 int rc;
851 u32 tag;
852 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
853
854 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
855 rc = pm8001_tag_alloc(pm8001_ha, &tag);
856 if (rc)
857 return -1;
858
859 circularQ = &pm8001_ha->inbnd_q_tbl[0];
860 payload.tag = cpu_to_le32(tag);
861 payload.cfg_pg[0] = (THERMAL_LOG_ENABLE << 9) |
862 (THERMAL_ENABLE << 8) | THERMAL_OP_CODE;
863 payload.cfg_pg[1] = (LTEMPHIL << 24) | (RTEMPHIL << 8);
864
865 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
866 return rc;
867
868 }
869
870 /**
871 * pm80xx_set_sas_protocol_timer_config - support the SAS Protocol
872 * Timer configuration page
873 * @pm8001_ha: our hba card information.
874 */
875 static int
876 pm80xx_set_sas_protocol_timer_config(struct pm8001_hba_info *pm8001_ha)
877 {
878 struct set_ctrl_cfg_req payload;
879 struct inbound_queue_table *circularQ;
880 SASProtocolTimerConfig_t SASConfigPage;
881 int rc;
882 u32 tag;
883 u32 opc = OPC_INB_SET_CONTROLLER_CONFIG;
884
885 memset(&payload, 0, sizeof(struct set_ctrl_cfg_req));
886 memset(&SASConfigPage, 0, sizeof(SASProtocolTimerConfig_t));
887
888 rc = pm8001_tag_alloc(pm8001_ha, &tag);
889
890 if (rc)
891 return -1;
892
893 circularQ = &pm8001_ha->inbnd_q_tbl[0];
894 payload.tag = cpu_to_le32(tag);
895
896 SASConfigPage.pageCode = SAS_PROTOCOL_TIMER_CONFIG_PAGE;
897 SASConfigPage.MST_MSI = 3 << 15;
898 SASConfigPage.STP_SSP_MCT_TMO = (STP_MCT_TMO << 16) | SSP_MCT_TMO;
899 SASConfigPage.STP_FRM_TMO = (SAS_MAX_OPEN_TIME << 24) |
900 (SMP_MAX_CONN_TIMER << 16) | STP_FRM_TIMER;
901 SASConfigPage.STP_IDLE_TMO = STP_IDLE_TIME;
902
903 if (SASConfigPage.STP_IDLE_TMO > 0x3FFFFFF)
904 SASConfigPage.STP_IDLE_TMO = 0x3FFFFFF;
905
906
907 SASConfigPage.OPNRJT_RTRY_INTVL = (SAS_MFD << 16) |
908 SAS_OPNRJT_RTRY_INTVL;
909 SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO = (SAS_DOPNRJT_RTRY_TMO << 16)
910 | SAS_COPNRJT_RTRY_TMO;
911 SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR = (SAS_DOPNRJT_RTRY_THR << 16)
912 | SAS_COPNRJT_RTRY_THR;
913 SASConfigPage.MAX_AIP = SAS_MAX_AIP;
914
915 PM8001_INIT_DBG(pm8001_ha,
916 pm8001_printk("SASConfigPage.pageCode "
917 "0x%08x\n", SASConfigPage.pageCode));
918 PM8001_INIT_DBG(pm8001_ha,
919 pm8001_printk("SASConfigPage.MST_MSI "
920 " 0x%08x\n", SASConfigPage.MST_MSI));
921 PM8001_INIT_DBG(pm8001_ha,
922 pm8001_printk("SASConfigPage.STP_SSP_MCT_TMO "
923 " 0x%08x\n", SASConfigPage.STP_SSP_MCT_TMO));
924 PM8001_INIT_DBG(pm8001_ha,
925 pm8001_printk("SASConfigPage.STP_FRM_TMO "
926 " 0x%08x\n", SASConfigPage.STP_FRM_TMO));
927 PM8001_INIT_DBG(pm8001_ha,
928 pm8001_printk("SASConfigPage.STP_IDLE_TMO "
929 " 0x%08x\n", SASConfigPage.STP_IDLE_TMO));
930 PM8001_INIT_DBG(pm8001_ha,
931 pm8001_printk("SASConfigPage.OPNRJT_RTRY_INTVL "
932 " 0x%08x\n", SASConfigPage.OPNRJT_RTRY_INTVL));
933 PM8001_INIT_DBG(pm8001_ha,
934 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO "
935 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_TMO));
936 PM8001_INIT_DBG(pm8001_ha,
937 pm8001_printk("SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR "
938 " 0x%08x\n", SASConfigPage.Data_Cmd_OPNRJT_RTRY_THR));
939 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("SASConfigPage.MAX_AIP "
940 " 0x%08x\n", SASConfigPage.MAX_AIP));
941
942 memcpy(&payload.cfg_pg, &SASConfigPage,
943 sizeof(SASProtocolTimerConfig_t));
944
945 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
946
947 return rc;
948 }
949
950 /**
951 * pm80xx_get_encrypt_info - Check for encryption
952 * @pm8001_ha: our hba card information.
953 */
954 static int
955 pm80xx_get_encrypt_info(struct pm8001_hba_info *pm8001_ha)
956 {
957 u32 scratch3_value;
958 int ret;
959
960 /* Read encryption status from SCRATCH PAD 3 */
961 scratch3_value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
962
963 if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
964 SCRATCH_PAD3_ENC_READY) {
965 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
966 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
967 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
968 SCRATCH_PAD3_SMF_ENABLED)
969 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
970 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
971 SCRATCH_PAD3_SMA_ENABLED)
972 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
973 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
974 SCRATCH_PAD3_SMB_ENABLED)
975 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
976 pm8001_ha->encrypt_info.status = 0;
977 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
978 "Encryption: SCRATCH_PAD3_ENC_READY 0x%08X."
979 "Cipher mode 0x%x Sec mode 0x%x status 0x%x\n",
980 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
981 pm8001_ha->encrypt_info.sec_mode,
982 pm8001_ha->encrypt_info.status));
983 ret = 0;
984 } else if ((scratch3_value & SCRATCH_PAD3_ENC_READY) ==
985 SCRATCH_PAD3_ENC_DISABLED) {
986 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
987 "Encryption: SCRATCH_PAD3_ENC_DISABLED 0x%08X\n",
988 scratch3_value));
989 pm8001_ha->encrypt_info.status = 0xFFFFFFFF;
990 pm8001_ha->encrypt_info.cipher_mode = 0;
991 pm8001_ha->encrypt_info.sec_mode = 0;
992 return 0;
993 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
994 SCRATCH_PAD3_ENC_DIS_ERR) {
995 pm8001_ha->encrypt_info.status =
996 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
997 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
998 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
999 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1000 SCRATCH_PAD3_SMF_ENABLED)
1001 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1002 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1003 SCRATCH_PAD3_SMA_ENABLED)
1004 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1005 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1006 SCRATCH_PAD3_SMB_ENABLED)
1007 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1008 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1009 "Encryption: SCRATCH_PAD3_DIS_ERR 0x%08X."
1010 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1011 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1012 pm8001_ha->encrypt_info.sec_mode,
1013 pm8001_ha->encrypt_info.status));
1014 ret = -1;
1015 } else if ((scratch3_value & SCRATCH_PAD3_ENC_MASK) ==
1016 SCRATCH_PAD3_ENC_ENA_ERR) {
1017
1018 pm8001_ha->encrypt_info.status =
1019 (scratch3_value & SCRATCH_PAD3_ERR_CODE) >> 16;
1020 if (scratch3_value & SCRATCH_PAD3_XTS_ENABLED)
1021 pm8001_ha->encrypt_info.cipher_mode = CIPHER_MODE_XTS;
1022 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1023 SCRATCH_PAD3_SMF_ENABLED)
1024 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMF;
1025 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1026 SCRATCH_PAD3_SMA_ENABLED)
1027 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMA;
1028 if ((scratch3_value & SCRATCH_PAD3_SM_MASK) ==
1029 SCRATCH_PAD3_SMB_ENABLED)
1030 pm8001_ha->encrypt_info.sec_mode = SEC_MODE_SMB;
1031
1032 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1033 "Encryption: SCRATCH_PAD3_ENA_ERR 0x%08X."
1034 "Cipher mode 0x%x sec mode 0x%x status 0x%x\n",
1035 scratch3_value, pm8001_ha->encrypt_info.cipher_mode,
1036 pm8001_ha->encrypt_info.sec_mode,
1037 pm8001_ha->encrypt_info.status));
1038 ret = -1;
1039 }
1040 return ret;
1041 }
1042
1043 /**
1044 * pm80xx_encrypt_update - update flash with encryption informtion
1045 * @pm8001_ha: our hba card information.
1046 */
1047 static int pm80xx_encrypt_update(struct pm8001_hba_info *pm8001_ha)
1048 {
1049 struct kek_mgmt_req payload;
1050 struct inbound_queue_table *circularQ;
1051 int rc;
1052 u32 tag;
1053 u32 opc = OPC_INB_KEK_MANAGEMENT;
1054
1055 memset(&payload, 0, sizeof(struct kek_mgmt_req));
1056 rc = pm8001_tag_alloc(pm8001_ha, &tag);
1057 if (rc)
1058 return -1;
1059
1060 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1061 payload.tag = cpu_to_le32(tag);
1062 /* Currently only one key is used. New KEK index is 1.
1063 * Current KEK index is 1. Store KEK to NVRAM is 1.
1064 */
1065 payload.new_curidx_ksop = ((1 << 24) | (1 << 16) | (1 << 8) |
1066 KEK_MGMT_SUBOP_KEYCARDUPDATE);
1067
1068 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
1069
1070 return rc;
1071 }
1072
1073 /**
1074 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
1075 * @pm8001_ha: our hba card information
1076 */
1077 static int pm80xx_chip_init(struct pm8001_hba_info *pm8001_ha)
1078 {
1079 int ret;
1080 u8 i = 0;
1081
1082 /* check the firmware status */
1083 if (-1 == check_fw_ready(pm8001_ha)) {
1084 PM8001_FAIL_DBG(pm8001_ha,
1085 pm8001_printk("Firmware is not ready!\n"));
1086 return -EBUSY;
1087 }
1088
1089 /* Initialize pci space address eg: mpi offset */
1090 init_pci_device_addresses(pm8001_ha);
1091 init_default_table_values(pm8001_ha);
1092 read_main_config_table(pm8001_ha);
1093 read_general_status_table(pm8001_ha);
1094 read_inbnd_queue_table(pm8001_ha);
1095 read_outbnd_queue_table(pm8001_ha);
1096 read_phy_attr_table(pm8001_ha);
1097
1098 /* update main config table ,inbound table and outbound table */
1099 update_main_config_table(pm8001_ha);
1100 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++)
1101 update_inbnd_queue_table(pm8001_ha, i);
1102 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++)
1103 update_outbnd_queue_table(pm8001_ha, i);
1104
1105 /* notify firmware update finished and check initialization status */
1106 if (0 == mpi_init_check(pm8001_ha)) {
1107 PM8001_INIT_DBG(pm8001_ha,
1108 pm8001_printk("MPI initialize successful!\n"));
1109 } else
1110 return -EBUSY;
1111
1112 /* send SAS protocol timer configuration page to FW */
1113 ret = pm80xx_set_sas_protocol_timer_config(pm8001_ha);
1114
1115 /* Check for encryption */
1116 if (pm8001_ha->chip->encrypt) {
1117 PM8001_INIT_DBG(pm8001_ha,
1118 pm8001_printk("Checking for encryption\n"));
1119 ret = pm80xx_get_encrypt_info(pm8001_ha);
1120 if (ret == -1) {
1121 PM8001_INIT_DBG(pm8001_ha,
1122 pm8001_printk("Encryption error !!\n"));
1123 if (pm8001_ha->encrypt_info.status == 0x81) {
1124 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
1125 "Encryption enabled with error."
1126 "Saving encryption key to flash\n"));
1127 pm80xx_encrypt_update(pm8001_ha);
1128 }
1129 }
1130 }
1131 return 0;
1132 }
1133
1134 static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
1135 {
1136 u32 max_wait_count;
1137 u32 value;
1138 u32 gst_len_mpistate;
1139 init_pci_device_addresses(pm8001_ha);
1140 /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
1141 table is stop */
1142 pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPCv_MSGU_CFG_TABLE_RESET);
1143
1144 /* wait until Inbound DoorBell Clear Register toggled */
1145 if (IS_SPCV_12G(pm8001_ha->pdev)) {
1146 max_wait_count = 4 * 1000 * 1000;/* 4 sec */
1147 } else {
1148 max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1149 }
1150 do {
1151 udelay(1);
1152 value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
1153 value &= SPCv_MSGU_CFG_TABLE_RESET;
1154 } while ((value != 0) && (--max_wait_count));
1155
1156 if (!max_wait_count) {
1157 PM8001_FAIL_DBG(pm8001_ha,
1158 pm8001_printk("TIMEOUT:IBDB value/=%x\n", value));
1159 return -1;
1160 }
1161
1162 /* check the MPI-State for termination in progress */
1163 /* wait until Inbound DoorBell Clear Register toggled */
1164 max_wait_count = 2 * 1000 * 1000; /* 2 sec for spcv/ve */
1165 do {
1166 udelay(1);
1167 gst_len_mpistate =
1168 pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
1169 GST_GSTLEN_MPIS_OFFSET);
1170 if (GST_MPI_STATE_UNINIT ==
1171 (gst_len_mpistate & GST_MPI_STATE_MASK))
1172 break;
1173 } while (--max_wait_count);
1174 if (!max_wait_count) {
1175 PM8001_FAIL_DBG(pm8001_ha,
1176 pm8001_printk(" TIME OUT MPI State = 0x%x\n",
1177 gst_len_mpistate & GST_MPI_STATE_MASK));
1178 return -1;
1179 }
1180
1181 return 0;
1182 }
1183
1184 /**
1185 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
1186 * the FW register status to the originated status.
1187 * @pm8001_ha: our hba card information
1188 */
1189
1190 static int
1191 pm80xx_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
1192 {
1193 u32 regval;
1194 u32 bootloader_state;
1195 u32 ibutton0, ibutton1;
1196
1197 /* Check if MPI is in ready state to reset */
1198 if (mpi_uninit_check(pm8001_ha) != 0) {
1199 PM8001_FAIL_DBG(pm8001_ha,
1200 pm8001_printk("MPI state is not ready\n"));
1201 return -1;
1202 }
1203
1204 /* checked for reset register normal state; 0x0 */
1205 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1206 PM8001_INIT_DBG(pm8001_ha,
1207 pm8001_printk("reset register before write : 0x%x\n", regval));
1208
1209 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, SPCv_NORMAL_RESET_VALUE);
1210 mdelay(500);
1211
1212 regval = pm8001_cr32(pm8001_ha, 0, SPC_REG_SOFT_RESET);
1213 PM8001_INIT_DBG(pm8001_ha,
1214 pm8001_printk("reset register after write 0x%x\n", regval));
1215
1216 if ((regval & SPCv_SOFT_RESET_READ_MASK) ==
1217 SPCv_SOFT_RESET_NORMAL_RESET_OCCURED) {
1218 PM8001_MSG_DBG(pm8001_ha,
1219 pm8001_printk(" soft reset successful [regval: 0x%x]\n",
1220 regval));
1221 } else {
1222 PM8001_MSG_DBG(pm8001_ha,
1223 pm8001_printk(" soft reset failed [regval: 0x%x]\n",
1224 regval));
1225
1226 /* check bootloader is successfully executed or in HDA mode */
1227 bootloader_state =
1228 pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1229 SCRATCH_PAD1_BOOTSTATE_MASK;
1230
1231 if (bootloader_state == SCRATCH_PAD1_BOOTSTATE_HDA_SEEPROM) {
1232 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1233 "Bootloader state - HDA mode SEEPROM\n"));
1234 } else if (bootloader_state ==
1235 SCRATCH_PAD1_BOOTSTATE_HDA_BOOTSTRAP) {
1236 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1237 "Bootloader state - HDA mode Bootstrap Pin\n"));
1238 } else if (bootloader_state ==
1239 SCRATCH_PAD1_BOOTSTATE_HDA_SOFTRESET) {
1240 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1241 "Bootloader state - HDA mode soft reset\n"));
1242 } else if (bootloader_state ==
1243 SCRATCH_PAD1_BOOTSTATE_CRIT_ERROR) {
1244 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
1245 "Bootloader state-HDA mode critical error\n"));
1246 }
1247 return -EBUSY;
1248 }
1249
1250 /* check the firmware status after reset */
1251 if (-1 == check_fw_ready(pm8001_ha)) {
1252 PM8001_FAIL_DBG(pm8001_ha,
1253 pm8001_printk("Firmware is not ready!\n"));
1254 /* check iButton feature support for motherboard controller */
1255 if (pm8001_ha->pdev->subsystem_vendor !=
1256 PCI_VENDOR_ID_ADAPTEC2 &&
1257 pm8001_ha->pdev->subsystem_vendor != 0) {
1258 ibutton0 = pm8001_cr32(pm8001_ha, 0,
1259 MSGU_HOST_SCRATCH_PAD_6);
1260 ibutton1 = pm8001_cr32(pm8001_ha, 0,
1261 MSGU_HOST_SCRATCH_PAD_7);
1262 if (!ibutton0 && !ibutton1) {
1263 PM8001_FAIL_DBG(pm8001_ha,
1264 pm8001_printk("iButton Feature is"
1265 " not Available!!!\n"));
1266 return -EBUSY;
1267 }
1268 if (ibutton0 == 0xdeadbeef && ibutton1 == 0xdeadbeef) {
1269 PM8001_FAIL_DBG(pm8001_ha,
1270 pm8001_printk("CRC Check for iButton"
1271 " Feature Failed!!!\n"));
1272 return -EBUSY;
1273 }
1274 }
1275 }
1276 PM8001_INIT_DBG(pm8001_ha,
1277 pm8001_printk("SPCv soft reset Complete\n"));
1278 return 0;
1279 }
1280
1281 static void pm80xx_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1282 {
1283 u32 i;
1284
1285 PM8001_INIT_DBG(pm8001_ha,
1286 pm8001_printk("chip reset start\n"));
1287
1288 /* do SPCv chip reset. */
1289 pm8001_cw32(pm8001_ha, 0, SPC_REG_SOFT_RESET, 0x11);
1290 PM8001_INIT_DBG(pm8001_ha,
1291 pm8001_printk("SPC soft reset Complete\n"));
1292
1293 /* Check this ..whether delay is required or no */
1294 /* delay 10 usec */
1295 udelay(10);
1296
1297 /* wait for 20 msec until the firmware gets reloaded */
1298 i = 20;
1299 do {
1300 mdelay(1);
1301 } while ((--i) != 0);
1302
1303 PM8001_INIT_DBG(pm8001_ha,
1304 pm8001_printk("chip reset finished\n"));
1305 }
1306
1307 /**
1308 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1309 * @pm8001_ha: our hba card information
1310 */
1311 static void
1312 pm80xx_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1313 {
1314 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1315 pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1316 }
1317
1318 /**
1319 * pm8001_chip_intx_interrupt_disable- disable PM8001 chip interrupt
1320 * @pm8001_ha: our hba card information
1321 */
1322 static void
1323 pm80xx_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1324 {
1325 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, ODMR_MASK_ALL);
1326 }
1327
1328 /**
1329 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1330 * @pm8001_ha: our hba card information
1331 */
1332 static void
1333 pm80xx_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1334 {
1335 #ifdef PM8001_USE_MSIX
1336 u32 mask;
1337 mask = (u32)(1 << vec);
1338
1339 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR_CLR, (u32)(mask & 0xFFFFFFFF));
1340 return;
1341 #endif
1342 pm80xx_chip_intx_interrupt_enable(pm8001_ha);
1343
1344 }
1345
1346 /**
1347 * pm8001_chip_interrupt_disable- disable PM8001 chip interrupt
1348 * @pm8001_ha: our hba card information
1349 */
1350 static void
1351 pm80xx_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1352 {
1353 #ifdef PM8001_USE_MSIX
1354 u32 mask;
1355 if (vec == 0xFF)
1356 mask = 0xFFFFFFFF;
1357 else
1358 mask = (u32)(1 << vec);
1359 pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, (u32)(mask & 0xFFFFFFFF));
1360 return;
1361 #endif
1362 pm80xx_chip_intx_interrupt_disable(pm8001_ha);
1363 }
1364
1365 static void pm80xx_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1366 struct pm8001_device *pm8001_ha_dev)
1367 {
1368 int res;
1369 u32 ccb_tag;
1370 struct pm8001_ccb_info *ccb;
1371 struct sas_task *task = NULL;
1372 struct task_abort_req task_abort;
1373 struct inbound_queue_table *circularQ;
1374 u32 opc = OPC_INB_SATA_ABORT;
1375 int ret;
1376
1377 if (!pm8001_ha_dev) {
1378 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("dev is null\n"));
1379 return;
1380 }
1381
1382 task = sas_alloc_slow_task(GFP_ATOMIC);
1383
1384 if (!task) {
1385 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("cannot "
1386 "allocate task\n"));
1387 return;
1388 }
1389
1390 task->task_done = pm8001_task_done;
1391
1392 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1393 if (res)
1394 return;
1395
1396 ccb = &pm8001_ha->ccb_info[ccb_tag];
1397 ccb->device = pm8001_ha_dev;
1398 ccb->ccb_tag = ccb_tag;
1399 ccb->task = task;
1400
1401 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1402
1403 memset(&task_abort, 0, sizeof(task_abort));
1404 task_abort.abort_all = cpu_to_le32(1);
1405 task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1406 task_abort.tag = cpu_to_le32(ccb_tag);
1407
1408 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort, 0);
1409
1410 }
1411
1412 static void pm80xx_send_read_log(struct pm8001_hba_info *pm8001_ha,
1413 struct pm8001_device *pm8001_ha_dev)
1414 {
1415 struct sata_start_req sata_cmd;
1416 int res;
1417 u32 ccb_tag;
1418 struct pm8001_ccb_info *ccb;
1419 struct sas_task *task = NULL;
1420 struct host_to_dev_fis fis;
1421 struct domain_device *dev;
1422 struct inbound_queue_table *circularQ;
1423 u32 opc = OPC_INB_SATA_HOST_OPSTART;
1424
1425 task = sas_alloc_slow_task(GFP_ATOMIC);
1426
1427 if (!task) {
1428 PM8001_FAIL_DBG(pm8001_ha,
1429 pm8001_printk("cannot allocate task !!!\n"));
1430 return;
1431 }
1432 task->task_done = pm8001_task_done;
1433
1434 res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1435 if (res) {
1436 PM8001_FAIL_DBG(pm8001_ha,
1437 pm8001_printk("cannot allocate tag !!!\n"));
1438 return;
1439 }
1440
1441 /* allocate domain device by ourselves as libsas
1442 * is not going to provide any
1443 */
1444 dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1445 if (!dev) {
1446 PM8001_FAIL_DBG(pm8001_ha,
1447 pm8001_printk("Domain device cannot be allocated\n"));
1448 sas_free_task(task);
1449 return;
1450 } else {
1451 task->dev = dev;
1452 task->dev->lldd_dev = pm8001_ha_dev;
1453 }
1454
1455 ccb = &pm8001_ha->ccb_info[ccb_tag];
1456 ccb->device = pm8001_ha_dev;
1457 ccb->ccb_tag = ccb_tag;
1458 ccb->task = task;
1459 pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1460 pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1461
1462 memset(&sata_cmd, 0, sizeof(sata_cmd));
1463 circularQ = &pm8001_ha->inbnd_q_tbl[0];
1464
1465 /* construct read log FIS */
1466 memset(&fis, 0, sizeof(struct host_to_dev_fis));
1467 fis.fis_type = 0x27;
1468 fis.flags = 0x80;
1469 fis.command = ATA_CMD_READ_LOG_EXT;
1470 fis.lbal = 0x10;
1471 fis.sector_count = 0x1;
1472
1473 sata_cmd.tag = cpu_to_le32(ccb_tag);
1474 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1475 sata_cmd.ncqtag_atap_dir_m_dad |= ((0x1 << 7) | (0x5 << 9));
1476 memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1477
1478 res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd, 0);
1479
1480 }
1481
1482 /**
1483 * mpi_ssp_completion- process the event that FW response to the SSP request.
1484 * @pm8001_ha: our hba card information
1485 * @piomb: the message contents of this outbound message.
1486 *
1487 * When FW has completed a ssp request for example a IO request, after it has
1488 * filled the SG data with the data, it will trigger this event represent
1489 * that he has finished the job,please check the coresponding buffer.
1490 * So we will tell the caller who maybe waiting the result to tell upper layer
1491 * that the task has been finished.
1492 */
1493 static void
1494 mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha , void *piomb)
1495 {
1496 struct sas_task *t;
1497 struct pm8001_ccb_info *ccb;
1498 unsigned long flags;
1499 u32 status;
1500 u32 param;
1501 u32 tag;
1502 struct ssp_completion_resp *psspPayload;
1503 struct task_status_struct *ts;
1504 struct ssp_response_iu *iu;
1505 struct pm8001_device *pm8001_dev;
1506 psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1507 status = le32_to_cpu(psspPayload->status);
1508 tag = le32_to_cpu(psspPayload->tag);
1509 ccb = &pm8001_ha->ccb_info[tag];
1510 if ((status == IO_ABORTED) && ccb->open_retry) {
1511 /* Being completed by another */
1512 ccb->open_retry = 0;
1513 return;
1514 }
1515 pm8001_dev = ccb->device;
1516 param = le32_to_cpu(psspPayload->param);
1517 t = ccb->task;
1518
1519 if (status && status != IO_UNDERFLOW)
1520 PM8001_FAIL_DBG(pm8001_ha,
1521 pm8001_printk("sas IO status 0x%x\n", status));
1522 if (unlikely(!t || !t->lldd_task || !t->dev))
1523 return;
1524 ts = &t->task_status;
1525 /* Print sas address of IO failed device */
1526 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1527 (status != IO_UNDERFLOW))
1528 PM8001_FAIL_DBG(pm8001_ha,
1529 pm8001_printk("SAS Address of IO Failure Drive"
1530 ":%016llx", SAS_ADDR(t->dev->sas_addr)));
1531
1532 switch (status) {
1533 case IO_SUCCESS:
1534 PM8001_IO_DBG(pm8001_ha,
1535 pm8001_printk("IO_SUCCESS ,param = 0x%x\n",
1536 param));
1537 if (param == 0) {
1538 ts->resp = SAS_TASK_COMPLETE;
1539 ts->stat = SAM_STAT_GOOD;
1540 } else {
1541 ts->resp = SAS_TASK_COMPLETE;
1542 ts->stat = SAS_PROTO_RESPONSE;
1543 ts->residual = param;
1544 iu = &psspPayload->ssp_resp_iu;
1545 sas_ssp_task_response(pm8001_ha->dev, t, iu);
1546 }
1547 if (pm8001_dev)
1548 pm8001_dev->running_req--;
1549 break;
1550 case IO_ABORTED:
1551 PM8001_IO_DBG(pm8001_ha,
1552 pm8001_printk("IO_ABORTED IOMB Tag\n"));
1553 ts->resp = SAS_TASK_COMPLETE;
1554 ts->stat = SAS_ABORTED_TASK;
1555 break;
1556 case IO_UNDERFLOW:
1557 /* SSP Completion with error */
1558 PM8001_IO_DBG(pm8001_ha,
1559 pm8001_printk("IO_UNDERFLOW ,param = 0x%x\n",
1560 param));
1561 ts->resp = SAS_TASK_COMPLETE;
1562 ts->stat = SAS_DATA_UNDERRUN;
1563 ts->residual = param;
1564 if (pm8001_dev)
1565 pm8001_dev->running_req--;
1566 break;
1567 case IO_NO_DEVICE:
1568 PM8001_IO_DBG(pm8001_ha,
1569 pm8001_printk("IO_NO_DEVICE\n"));
1570 ts->resp = SAS_TASK_UNDELIVERED;
1571 ts->stat = SAS_PHY_DOWN;
1572 break;
1573 case IO_XFER_ERROR_BREAK:
1574 PM8001_IO_DBG(pm8001_ha,
1575 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1576 ts->resp = SAS_TASK_COMPLETE;
1577 ts->stat = SAS_OPEN_REJECT;
1578 /* Force the midlayer to retry */
1579 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1580 break;
1581 case IO_XFER_ERROR_PHY_NOT_READY:
1582 PM8001_IO_DBG(pm8001_ha,
1583 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1584 ts->resp = SAS_TASK_COMPLETE;
1585 ts->stat = SAS_OPEN_REJECT;
1586 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1587 break;
1588 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1589 PM8001_IO_DBG(pm8001_ha,
1590 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1591 ts->resp = SAS_TASK_COMPLETE;
1592 ts->stat = SAS_OPEN_REJECT;
1593 ts->open_rej_reason = SAS_OREJ_EPROTO;
1594 break;
1595 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1596 PM8001_IO_DBG(pm8001_ha,
1597 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1598 ts->resp = SAS_TASK_COMPLETE;
1599 ts->stat = SAS_OPEN_REJECT;
1600 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1601 break;
1602 case IO_OPEN_CNX_ERROR_BREAK:
1603 PM8001_IO_DBG(pm8001_ha,
1604 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1605 ts->resp = SAS_TASK_COMPLETE;
1606 ts->stat = SAS_OPEN_REJECT;
1607 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1608 break;
1609 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1610 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1611 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1612 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1613 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1614 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1615 PM8001_IO_DBG(pm8001_ha,
1616 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1617 ts->resp = SAS_TASK_COMPLETE;
1618 ts->stat = SAS_OPEN_REJECT;
1619 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1620 if (!t->uldd_task)
1621 pm8001_handle_event(pm8001_ha,
1622 pm8001_dev,
1623 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1624 break;
1625 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1626 PM8001_IO_DBG(pm8001_ha,
1627 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1628 ts->resp = SAS_TASK_COMPLETE;
1629 ts->stat = SAS_OPEN_REJECT;
1630 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1631 break;
1632 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1633 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1634 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1635 ts->resp = SAS_TASK_COMPLETE;
1636 ts->stat = SAS_OPEN_REJECT;
1637 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1638 break;
1639 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1640 PM8001_IO_DBG(pm8001_ha,
1641 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1642 ts->resp = SAS_TASK_UNDELIVERED;
1643 ts->stat = SAS_OPEN_REJECT;
1644 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1645 break;
1646 case IO_XFER_ERROR_NAK_RECEIVED:
1647 PM8001_IO_DBG(pm8001_ha,
1648 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1649 ts->resp = SAS_TASK_COMPLETE;
1650 ts->stat = SAS_OPEN_REJECT;
1651 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1652 break;
1653 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1654 PM8001_IO_DBG(pm8001_ha,
1655 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1656 ts->resp = SAS_TASK_COMPLETE;
1657 ts->stat = SAS_NAK_R_ERR;
1658 break;
1659 case IO_XFER_ERROR_DMA:
1660 PM8001_IO_DBG(pm8001_ha,
1661 pm8001_printk("IO_XFER_ERROR_DMA\n"));
1662 ts->resp = SAS_TASK_COMPLETE;
1663 ts->stat = SAS_OPEN_REJECT;
1664 break;
1665 case IO_XFER_OPEN_RETRY_TIMEOUT:
1666 PM8001_IO_DBG(pm8001_ha,
1667 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1668 ts->resp = SAS_TASK_COMPLETE;
1669 ts->stat = SAS_OPEN_REJECT;
1670 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1671 break;
1672 case IO_XFER_ERROR_OFFSET_MISMATCH:
1673 PM8001_IO_DBG(pm8001_ha,
1674 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1675 ts->resp = SAS_TASK_COMPLETE;
1676 ts->stat = SAS_OPEN_REJECT;
1677 break;
1678 case IO_PORT_IN_RESET:
1679 PM8001_IO_DBG(pm8001_ha,
1680 pm8001_printk("IO_PORT_IN_RESET\n"));
1681 ts->resp = SAS_TASK_COMPLETE;
1682 ts->stat = SAS_OPEN_REJECT;
1683 break;
1684 case IO_DS_NON_OPERATIONAL:
1685 PM8001_IO_DBG(pm8001_ha,
1686 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
1687 ts->resp = SAS_TASK_COMPLETE;
1688 ts->stat = SAS_OPEN_REJECT;
1689 if (!t->uldd_task)
1690 pm8001_handle_event(pm8001_ha,
1691 pm8001_dev,
1692 IO_DS_NON_OPERATIONAL);
1693 break;
1694 case IO_DS_IN_RECOVERY:
1695 PM8001_IO_DBG(pm8001_ha,
1696 pm8001_printk("IO_DS_IN_RECOVERY\n"));
1697 ts->resp = SAS_TASK_COMPLETE;
1698 ts->stat = SAS_OPEN_REJECT;
1699 break;
1700 case IO_TM_TAG_NOT_FOUND:
1701 PM8001_IO_DBG(pm8001_ha,
1702 pm8001_printk("IO_TM_TAG_NOT_FOUND\n"));
1703 ts->resp = SAS_TASK_COMPLETE;
1704 ts->stat = SAS_OPEN_REJECT;
1705 break;
1706 case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
1707 PM8001_IO_DBG(pm8001_ha,
1708 pm8001_printk("IO_SSP_EXT_IU_ZERO_LEN_ERROR\n"));
1709 ts->resp = SAS_TASK_COMPLETE;
1710 ts->stat = SAS_OPEN_REJECT;
1711 break;
1712 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
1713 PM8001_IO_DBG(pm8001_ha,
1714 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
1715 ts->resp = SAS_TASK_COMPLETE;
1716 ts->stat = SAS_OPEN_REJECT;
1717 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1718 break;
1719 default:
1720 PM8001_IO_DBG(pm8001_ha,
1721 pm8001_printk("Unknown status 0x%x\n", status));
1722 /* not allowed case. Therefore, return failed status */
1723 ts->resp = SAS_TASK_COMPLETE;
1724 ts->stat = SAS_OPEN_REJECT;
1725 break;
1726 }
1727 PM8001_IO_DBG(pm8001_ha,
1728 pm8001_printk("scsi_status = 0x%x\n ",
1729 psspPayload->ssp_resp_iu.status));
1730 spin_lock_irqsave(&t->task_state_lock, flags);
1731 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1732 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1733 t->task_state_flags |= SAS_TASK_STATE_DONE;
1734 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1735 spin_unlock_irqrestore(&t->task_state_lock, flags);
1736 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1737 "task 0x%p done with io_status 0x%x resp 0x%x "
1738 "stat 0x%x but aborted by upper layer!\n",
1739 t, status, ts->resp, ts->stat));
1740 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1741 } else {
1742 spin_unlock_irqrestore(&t->task_state_lock, flags);
1743 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1744 mb();/* in order to force CPU ordering */
1745 t->task_done(t);
1746 }
1747 }
1748
1749 /*See the comments for mpi_ssp_completion */
1750 static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
1751 {
1752 struct sas_task *t;
1753 unsigned long flags;
1754 struct task_status_struct *ts;
1755 struct pm8001_ccb_info *ccb;
1756 struct pm8001_device *pm8001_dev;
1757 struct ssp_event_resp *psspPayload =
1758 (struct ssp_event_resp *)(piomb + 4);
1759 u32 event = le32_to_cpu(psspPayload->event);
1760 u32 tag = le32_to_cpu(psspPayload->tag);
1761 u32 port_id = le32_to_cpu(psspPayload->port_id);
1762
1763 ccb = &pm8001_ha->ccb_info[tag];
1764 t = ccb->task;
1765 pm8001_dev = ccb->device;
1766 if (event)
1767 PM8001_FAIL_DBG(pm8001_ha,
1768 pm8001_printk("sas IO status 0x%x\n", event));
1769 if (unlikely(!t || !t->lldd_task || !t->dev))
1770 return;
1771 ts = &t->task_status;
1772 PM8001_IO_DBG(pm8001_ha,
1773 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
1774 port_id, tag, event));
1775 switch (event) {
1776 case IO_OVERFLOW:
1777 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n");)
1778 ts->resp = SAS_TASK_COMPLETE;
1779 ts->stat = SAS_DATA_OVERRUN;
1780 ts->residual = 0;
1781 if (pm8001_dev)
1782 pm8001_dev->running_req--;
1783 break;
1784 case IO_XFER_ERROR_BREAK:
1785 PM8001_IO_DBG(pm8001_ha,
1786 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
1787 pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
1788 return;
1789 case IO_XFER_ERROR_PHY_NOT_READY:
1790 PM8001_IO_DBG(pm8001_ha,
1791 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
1792 ts->resp = SAS_TASK_COMPLETE;
1793 ts->stat = SAS_OPEN_REJECT;
1794 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1795 break;
1796 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1797 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1798 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
1799 ts->resp = SAS_TASK_COMPLETE;
1800 ts->stat = SAS_OPEN_REJECT;
1801 ts->open_rej_reason = SAS_OREJ_EPROTO;
1802 break;
1803 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1804 PM8001_IO_DBG(pm8001_ha,
1805 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
1806 ts->resp = SAS_TASK_COMPLETE;
1807 ts->stat = SAS_OPEN_REJECT;
1808 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1809 break;
1810 case IO_OPEN_CNX_ERROR_BREAK:
1811 PM8001_IO_DBG(pm8001_ha,
1812 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
1813 ts->resp = SAS_TASK_COMPLETE;
1814 ts->stat = SAS_OPEN_REJECT;
1815 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1816 break;
1817 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1818 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
1819 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
1820 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
1821 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
1822 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
1823 PM8001_IO_DBG(pm8001_ha,
1824 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
1825 ts->resp = SAS_TASK_COMPLETE;
1826 ts->stat = SAS_OPEN_REJECT;
1827 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1828 if (!t->uldd_task)
1829 pm8001_handle_event(pm8001_ha,
1830 pm8001_dev,
1831 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
1832 break;
1833 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
1834 PM8001_IO_DBG(pm8001_ha,
1835 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
1836 ts->resp = SAS_TASK_COMPLETE;
1837 ts->stat = SAS_OPEN_REJECT;
1838 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
1839 break;
1840 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
1841 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
1842 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
1843 ts->resp = SAS_TASK_COMPLETE;
1844 ts->stat = SAS_OPEN_REJECT;
1845 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
1846 break;
1847 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
1848 PM8001_IO_DBG(pm8001_ha,
1849 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
1850 ts->resp = SAS_TASK_COMPLETE;
1851 ts->stat = SAS_OPEN_REJECT;
1852 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
1853 break;
1854 case IO_XFER_ERROR_NAK_RECEIVED:
1855 PM8001_IO_DBG(pm8001_ha,
1856 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
1857 ts->resp = SAS_TASK_COMPLETE;
1858 ts->stat = SAS_OPEN_REJECT;
1859 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1860 break;
1861 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
1862 PM8001_IO_DBG(pm8001_ha,
1863 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
1864 ts->resp = SAS_TASK_COMPLETE;
1865 ts->stat = SAS_NAK_R_ERR;
1866 break;
1867 case IO_XFER_OPEN_RETRY_TIMEOUT:
1868 PM8001_IO_DBG(pm8001_ha,
1869 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
1870 pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
1871 return;
1872 case IO_XFER_ERROR_UNEXPECTED_PHASE:
1873 PM8001_IO_DBG(pm8001_ha,
1874 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
1875 ts->resp = SAS_TASK_COMPLETE;
1876 ts->stat = SAS_DATA_OVERRUN;
1877 break;
1878 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
1879 PM8001_IO_DBG(pm8001_ha,
1880 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
1881 ts->resp = SAS_TASK_COMPLETE;
1882 ts->stat = SAS_DATA_OVERRUN;
1883 break;
1884 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
1885 PM8001_IO_DBG(pm8001_ha,
1886 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
1887 ts->resp = SAS_TASK_COMPLETE;
1888 ts->stat = SAS_DATA_OVERRUN;
1889 break;
1890 case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
1891 PM8001_IO_DBG(pm8001_ha,
1892 pm8001_printk("IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n"));
1893 ts->resp = SAS_TASK_COMPLETE;
1894 ts->stat = SAS_DATA_OVERRUN;
1895 break;
1896 case IO_XFER_ERROR_OFFSET_MISMATCH:
1897 PM8001_IO_DBG(pm8001_ha,
1898 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
1899 ts->resp = SAS_TASK_COMPLETE;
1900 ts->stat = SAS_DATA_OVERRUN;
1901 break;
1902 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
1903 PM8001_IO_DBG(pm8001_ha,
1904 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
1905 ts->resp = SAS_TASK_COMPLETE;
1906 ts->stat = SAS_DATA_OVERRUN;
1907 break;
1908 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
1909 PM8001_IO_DBG(pm8001_ha,
1910 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
1911 /* TBC: used default set values */
1912 ts->resp = SAS_TASK_COMPLETE;
1913 ts->stat = SAS_DATA_OVERRUN;
1914 break;
1915 case IO_XFER_CMD_FRAME_ISSUED:
1916 PM8001_IO_DBG(pm8001_ha,
1917 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
1918 return;
1919 default:
1920 PM8001_IO_DBG(pm8001_ha,
1921 pm8001_printk("Unknown status 0x%x\n", event));
1922 /* not allowed case. Therefore, return failed status */
1923 ts->resp = SAS_TASK_COMPLETE;
1924 ts->stat = SAS_DATA_OVERRUN;
1925 break;
1926 }
1927 spin_lock_irqsave(&t->task_state_lock, flags);
1928 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1929 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1930 t->task_state_flags |= SAS_TASK_STATE_DONE;
1931 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1932 spin_unlock_irqrestore(&t->task_state_lock, flags);
1933 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1934 "task 0x%p done with event 0x%x resp 0x%x "
1935 "stat 0x%x but aborted by upper layer!\n",
1936 t, event, ts->resp, ts->stat));
1937 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1938 } else {
1939 spin_unlock_irqrestore(&t->task_state_lock, flags);
1940 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1941 mb();/* in order to force CPU ordering */
1942 t->task_done(t);
1943 }
1944 }
1945
1946 /*See the comments for mpi_ssp_completion */
1947 static void
1948 mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1949 {
1950 struct sas_task *t;
1951 struct pm8001_ccb_info *ccb;
1952 u32 param;
1953 u32 status;
1954 u32 tag;
1955 int i, j;
1956 u8 sata_addr_low[4];
1957 u32 temp_sata_addr_low, temp_sata_addr_hi;
1958 u8 sata_addr_hi[4];
1959 struct sata_completion_resp *psataPayload;
1960 struct task_status_struct *ts;
1961 struct ata_task_resp *resp ;
1962 u32 *sata_resp;
1963 struct pm8001_device *pm8001_dev;
1964 unsigned long flags;
1965
1966 psataPayload = (struct sata_completion_resp *)(piomb + 4);
1967 status = le32_to_cpu(psataPayload->status);
1968 tag = le32_to_cpu(psataPayload->tag);
1969
1970 if (!tag) {
1971 PM8001_FAIL_DBG(pm8001_ha,
1972 pm8001_printk("tag null\n"));
1973 return;
1974 }
1975 ccb = &pm8001_ha->ccb_info[tag];
1976 param = le32_to_cpu(psataPayload->param);
1977 if (ccb) {
1978 t = ccb->task;
1979 pm8001_dev = ccb->device;
1980 } else {
1981 PM8001_FAIL_DBG(pm8001_ha,
1982 pm8001_printk("ccb null\n"));
1983 return;
1984 }
1985
1986 if (t) {
1987 if (t->dev && (t->dev->lldd_dev))
1988 pm8001_dev = t->dev->lldd_dev;
1989 } else {
1990 PM8001_FAIL_DBG(pm8001_ha,
1991 pm8001_printk("task null\n"));
1992 return;
1993 }
1994
1995 if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
1996 && unlikely(!t || !t->lldd_task || !t->dev)) {
1997 PM8001_FAIL_DBG(pm8001_ha,
1998 pm8001_printk("task or dev null\n"));
1999 return;
2000 }
2001
2002 ts = &t->task_status;
2003 if (!ts) {
2004 PM8001_FAIL_DBG(pm8001_ha,
2005 pm8001_printk("ts null\n"));
2006 return;
2007 }
2008 /* Print sas address of IO failed device */
2009 if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2010 (status != IO_UNDERFLOW)) {
2011 if (!((t->dev->parent) &&
2012 (DEV_IS_EXPANDER(t->dev->parent->dev_type)))) {
2013 for (i = 0 , j = 4; i <= 3 && j <= 7; i++ , j++)
2014 sata_addr_low[i] = pm8001_ha->sas_addr[j];
2015 for (i = 0 , j = 0; i <= 3 && j <= 3; i++ , j++)
2016 sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2017 memcpy(&temp_sata_addr_low, sata_addr_low,
2018 sizeof(sata_addr_low));
2019 memcpy(&temp_sata_addr_hi, sata_addr_hi,
2020 sizeof(sata_addr_hi));
2021 temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2022 |((temp_sata_addr_hi << 8) &
2023 0xff0000) |
2024 ((temp_sata_addr_hi >> 8)
2025 & 0xff00) |
2026 ((temp_sata_addr_hi << 24) &
2027 0xff000000));
2028 temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2029 & 0xff) |
2030 ((temp_sata_addr_low << 8)
2031 & 0xff0000) |
2032 ((temp_sata_addr_low >> 8)
2033 & 0xff00) |
2034 ((temp_sata_addr_low << 24)
2035 & 0xff000000)) +
2036 pm8001_dev->attached_phy +
2037 0x10);
2038 PM8001_FAIL_DBG(pm8001_ha,
2039 pm8001_printk("SAS Address of IO Failure Drive:"
2040 "%08x%08x", temp_sata_addr_hi,
2041 temp_sata_addr_low));
2042
2043 } else {
2044 PM8001_FAIL_DBG(pm8001_ha,
2045 pm8001_printk("SAS Address of IO Failure Drive:"
2046 "%016llx", SAS_ADDR(t->dev->sas_addr)));
2047 }
2048 }
2049 switch (status) {
2050 case IO_SUCCESS:
2051 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2052 if (param == 0) {
2053 ts->resp = SAS_TASK_COMPLETE;
2054 ts->stat = SAM_STAT_GOOD;
2055 /* check if response is for SEND READ LOG */
2056 if (pm8001_dev &&
2057 (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2058 /* set new bit for abort_all */
2059 pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2060 /* clear bit for read log */
2061 pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2062 pm80xx_send_abort_all(pm8001_ha, pm8001_dev);
2063 /* Free the tag */
2064 pm8001_tag_free(pm8001_ha, tag);
2065 sas_free_task(t);
2066 return;
2067 }
2068 } else {
2069 u8 len;
2070 ts->resp = SAS_TASK_COMPLETE;
2071 ts->stat = SAS_PROTO_RESPONSE;
2072 ts->residual = param;
2073 PM8001_IO_DBG(pm8001_ha,
2074 pm8001_printk("SAS_PROTO_RESPONSE len = %d\n",
2075 param));
2076 sata_resp = &psataPayload->sata_resp[0];
2077 resp = (struct ata_task_resp *)ts->buf;
2078 if (t->ata_task.dma_xfer == 0 &&
2079 t->data_dir == PCI_DMA_FROMDEVICE) {
2080 len = sizeof(struct pio_setup_fis);
2081 PM8001_IO_DBG(pm8001_ha,
2082 pm8001_printk("PIO read len = %d\n", len));
2083 } else if (t->ata_task.use_ncq) {
2084 len = sizeof(struct set_dev_bits_fis);
2085 PM8001_IO_DBG(pm8001_ha,
2086 pm8001_printk("FPDMA len = %d\n", len));
2087 } else {
2088 len = sizeof(struct dev_to_host_fis);
2089 PM8001_IO_DBG(pm8001_ha,
2090 pm8001_printk("other len = %d\n", len));
2091 }
2092 if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2093 resp->frame_len = len;
2094 memcpy(&resp->ending_fis[0], sata_resp, len);
2095 ts->buf_valid_size = sizeof(*resp);
2096 } else
2097 PM8001_IO_DBG(pm8001_ha,
2098 pm8001_printk("response to large\n"));
2099 }
2100 if (pm8001_dev)
2101 pm8001_dev->running_req--;
2102 break;
2103 case IO_ABORTED:
2104 PM8001_IO_DBG(pm8001_ha,
2105 pm8001_printk("IO_ABORTED IOMB Tag\n"));
2106 ts->resp = SAS_TASK_COMPLETE;
2107 ts->stat = SAS_ABORTED_TASK;
2108 if (pm8001_dev)
2109 pm8001_dev->running_req--;
2110 break;
2111 /* following cases are to do cases */
2112 case IO_UNDERFLOW:
2113 /* SATA Completion with error */
2114 PM8001_IO_DBG(pm8001_ha,
2115 pm8001_printk("IO_UNDERFLOW param = %d\n", param));
2116 ts->resp = SAS_TASK_COMPLETE;
2117 ts->stat = SAS_DATA_UNDERRUN;
2118 ts->residual = param;
2119 if (pm8001_dev)
2120 pm8001_dev->running_req--;
2121 break;
2122 case IO_NO_DEVICE:
2123 PM8001_IO_DBG(pm8001_ha,
2124 pm8001_printk("IO_NO_DEVICE\n"));
2125 ts->resp = SAS_TASK_UNDELIVERED;
2126 ts->stat = SAS_PHY_DOWN;
2127 break;
2128 case IO_XFER_ERROR_BREAK:
2129 PM8001_IO_DBG(pm8001_ha,
2130 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2131 ts->resp = SAS_TASK_COMPLETE;
2132 ts->stat = SAS_INTERRUPTED;
2133 break;
2134 case IO_XFER_ERROR_PHY_NOT_READY:
2135 PM8001_IO_DBG(pm8001_ha,
2136 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2137 ts->resp = SAS_TASK_COMPLETE;
2138 ts->stat = SAS_OPEN_REJECT;
2139 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2140 break;
2141 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2142 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2143 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2144 ts->resp = SAS_TASK_COMPLETE;
2145 ts->stat = SAS_OPEN_REJECT;
2146 ts->open_rej_reason = SAS_OREJ_EPROTO;
2147 break;
2148 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2149 PM8001_IO_DBG(pm8001_ha,
2150 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2151 ts->resp = SAS_TASK_COMPLETE;
2152 ts->stat = SAS_OPEN_REJECT;
2153 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2154 break;
2155 case IO_OPEN_CNX_ERROR_BREAK:
2156 PM8001_IO_DBG(pm8001_ha,
2157 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2158 ts->resp = SAS_TASK_COMPLETE;
2159 ts->stat = SAS_OPEN_REJECT;
2160 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2161 break;
2162 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2163 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2164 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2165 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2166 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2167 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2168 PM8001_IO_DBG(pm8001_ha,
2169 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2170 ts->resp = SAS_TASK_COMPLETE;
2171 ts->stat = SAS_DEV_NO_RESPONSE;
2172 if (!t->uldd_task) {
2173 pm8001_handle_event(pm8001_ha,
2174 pm8001_dev,
2175 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2176 ts->resp = SAS_TASK_UNDELIVERED;
2177 ts->stat = SAS_QUEUE_FULL;
2178 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2179 mb();/*in order to force CPU ordering*/
2180 spin_unlock_irq(&pm8001_ha->lock);
2181 t->task_done(t);
2182 spin_lock_irq(&pm8001_ha->lock);
2183 return;
2184 }
2185 break;
2186 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2187 PM8001_IO_DBG(pm8001_ha,
2188 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2189 ts->resp = SAS_TASK_UNDELIVERED;
2190 ts->stat = SAS_OPEN_REJECT;
2191 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2192 if (!t->uldd_task) {
2193 pm8001_handle_event(pm8001_ha,
2194 pm8001_dev,
2195 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2196 ts->resp = SAS_TASK_UNDELIVERED;
2197 ts->stat = SAS_QUEUE_FULL;
2198 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2199 mb();/*ditto*/
2200 spin_unlock_irq(&pm8001_ha->lock);
2201 t->task_done(t);
2202 spin_lock_irq(&pm8001_ha->lock);
2203 return;
2204 }
2205 break;
2206 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2207 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2208 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2209 ts->resp = SAS_TASK_COMPLETE;
2210 ts->stat = SAS_OPEN_REJECT;
2211 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2212 break;
2213 case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2214 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2215 "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n"));
2216 ts->resp = SAS_TASK_COMPLETE;
2217 ts->stat = SAS_DEV_NO_RESPONSE;
2218 if (!t->uldd_task) {
2219 pm8001_handle_event(pm8001_ha,
2220 pm8001_dev,
2221 IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2222 ts->resp = SAS_TASK_UNDELIVERED;
2223 ts->stat = SAS_QUEUE_FULL;
2224 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2225 mb();/* ditto*/
2226 spin_unlock_irq(&pm8001_ha->lock);
2227 t->task_done(t);
2228 spin_lock_irq(&pm8001_ha->lock);
2229 return;
2230 }
2231 break;
2232 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2233 PM8001_IO_DBG(pm8001_ha,
2234 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2235 ts->resp = SAS_TASK_COMPLETE;
2236 ts->stat = SAS_OPEN_REJECT;
2237 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2238 break;
2239 case IO_XFER_ERROR_NAK_RECEIVED:
2240 PM8001_IO_DBG(pm8001_ha,
2241 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2242 ts->resp = SAS_TASK_COMPLETE;
2243 ts->stat = SAS_NAK_R_ERR;
2244 break;
2245 case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2246 PM8001_IO_DBG(pm8001_ha,
2247 pm8001_printk("IO_XFER_ERROR_ACK_NAK_TIMEOUT\n"));
2248 ts->resp = SAS_TASK_COMPLETE;
2249 ts->stat = SAS_NAK_R_ERR;
2250 break;
2251 case IO_XFER_ERROR_DMA:
2252 PM8001_IO_DBG(pm8001_ha,
2253 pm8001_printk("IO_XFER_ERROR_DMA\n"));
2254 ts->resp = SAS_TASK_COMPLETE;
2255 ts->stat = SAS_ABORTED_TASK;
2256 break;
2257 case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2258 PM8001_IO_DBG(pm8001_ha,
2259 pm8001_printk("IO_XFER_ERROR_SATA_LINK_TIMEOUT\n"));
2260 ts->resp = SAS_TASK_UNDELIVERED;
2261 ts->stat = SAS_DEV_NO_RESPONSE;
2262 break;
2263 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2264 PM8001_IO_DBG(pm8001_ha,
2265 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2266 ts->resp = SAS_TASK_COMPLETE;
2267 ts->stat = SAS_DATA_UNDERRUN;
2268 break;
2269 case IO_XFER_OPEN_RETRY_TIMEOUT:
2270 PM8001_IO_DBG(pm8001_ha,
2271 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2272 ts->resp = SAS_TASK_COMPLETE;
2273 ts->stat = SAS_OPEN_TO;
2274 break;
2275 case IO_PORT_IN_RESET:
2276 PM8001_IO_DBG(pm8001_ha,
2277 pm8001_printk("IO_PORT_IN_RESET\n"));
2278 ts->resp = SAS_TASK_COMPLETE;
2279 ts->stat = SAS_DEV_NO_RESPONSE;
2280 break;
2281 case IO_DS_NON_OPERATIONAL:
2282 PM8001_IO_DBG(pm8001_ha,
2283 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2284 ts->resp = SAS_TASK_COMPLETE;
2285 ts->stat = SAS_DEV_NO_RESPONSE;
2286 if (!t->uldd_task) {
2287 pm8001_handle_event(pm8001_ha, pm8001_dev,
2288 IO_DS_NON_OPERATIONAL);
2289 ts->resp = SAS_TASK_UNDELIVERED;
2290 ts->stat = SAS_QUEUE_FULL;
2291 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2292 mb();/*ditto*/
2293 spin_unlock_irq(&pm8001_ha->lock);
2294 t->task_done(t);
2295 spin_lock_irq(&pm8001_ha->lock);
2296 return;
2297 }
2298 break;
2299 case IO_DS_IN_RECOVERY:
2300 PM8001_IO_DBG(pm8001_ha,
2301 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2302 ts->resp = SAS_TASK_COMPLETE;
2303 ts->stat = SAS_DEV_NO_RESPONSE;
2304 break;
2305 case IO_DS_IN_ERROR:
2306 PM8001_IO_DBG(pm8001_ha,
2307 pm8001_printk("IO_DS_IN_ERROR\n"));
2308 ts->resp = SAS_TASK_COMPLETE;
2309 ts->stat = SAS_DEV_NO_RESPONSE;
2310 if (!t->uldd_task) {
2311 pm8001_handle_event(pm8001_ha, pm8001_dev,
2312 IO_DS_IN_ERROR);
2313 ts->resp = SAS_TASK_UNDELIVERED;
2314 ts->stat = SAS_QUEUE_FULL;
2315 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2316 mb();/*ditto*/
2317 spin_unlock_irq(&pm8001_ha->lock);
2318 t->task_done(t);
2319 spin_lock_irq(&pm8001_ha->lock);
2320 return;
2321 }
2322 break;
2323 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2324 PM8001_IO_DBG(pm8001_ha,
2325 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2326 ts->resp = SAS_TASK_COMPLETE;
2327 ts->stat = SAS_OPEN_REJECT;
2328 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2329 default:
2330 PM8001_IO_DBG(pm8001_ha,
2331 pm8001_printk("Unknown status 0x%x\n", status));
2332 /* not allowed case. Therefore, return failed status */
2333 ts->resp = SAS_TASK_COMPLETE;
2334 ts->stat = SAS_DEV_NO_RESPONSE;
2335 break;
2336 }
2337 spin_lock_irqsave(&t->task_state_lock, flags);
2338 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2339 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2340 t->task_state_flags |= SAS_TASK_STATE_DONE;
2341 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2342 spin_unlock_irqrestore(&t->task_state_lock, flags);
2343 PM8001_FAIL_DBG(pm8001_ha,
2344 pm8001_printk("task 0x%p done with io_status 0x%x"
2345 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2346 t, status, ts->resp, ts->stat));
2347 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2348 } else if (t->uldd_task) {
2349 spin_unlock_irqrestore(&t->task_state_lock, flags);
2350 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2351 mb();/* ditto */
2352 spin_unlock_irq(&pm8001_ha->lock);
2353 t->task_done(t);
2354 spin_lock_irq(&pm8001_ha->lock);
2355 } else if (!t->uldd_task) {
2356 spin_unlock_irqrestore(&t->task_state_lock, flags);
2357 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2358 mb();/*ditto*/
2359 spin_unlock_irq(&pm8001_ha->lock);
2360 t->task_done(t);
2361 spin_lock_irq(&pm8001_ha->lock);
2362 }
2363 }
2364
2365 /*See the comments for mpi_ssp_completion */
2366 static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha , void *piomb)
2367 {
2368 struct sas_task *t;
2369 struct task_status_struct *ts;
2370 struct pm8001_ccb_info *ccb;
2371 struct pm8001_device *pm8001_dev;
2372 struct sata_event_resp *psataPayload =
2373 (struct sata_event_resp *)(piomb + 4);
2374 u32 event = le32_to_cpu(psataPayload->event);
2375 u32 tag = le32_to_cpu(psataPayload->tag);
2376 u32 port_id = le32_to_cpu(psataPayload->port_id);
2377 u32 dev_id = le32_to_cpu(psataPayload->device_id);
2378 unsigned long flags;
2379
2380 ccb = &pm8001_ha->ccb_info[tag];
2381
2382 if (ccb) {
2383 t = ccb->task;
2384 pm8001_dev = ccb->device;
2385 } else {
2386 PM8001_FAIL_DBG(pm8001_ha,
2387 pm8001_printk("No CCB !!!. returning\n"));
2388 return;
2389 }
2390 if (event)
2391 PM8001_FAIL_DBG(pm8001_ha,
2392 pm8001_printk("SATA EVENT 0x%x\n", event));
2393
2394 /* Check if this is NCQ error */
2395 if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2396 /* find device using device id */
2397 pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2398 /* send read log extension */
2399 if (pm8001_dev)
2400 pm80xx_send_read_log(pm8001_ha, pm8001_dev);
2401 return;
2402 }
2403
2404 if (unlikely(!t || !t->lldd_task || !t->dev)) {
2405 PM8001_FAIL_DBG(pm8001_ha,
2406 pm8001_printk("task or dev null\n"));
2407 return;
2408 }
2409
2410 ts = &t->task_status;
2411 PM8001_IO_DBG(pm8001_ha,
2412 pm8001_printk("port_id:0x%x, tag:0x%x, event:0x%x\n",
2413 port_id, tag, event));
2414 switch (event) {
2415 case IO_OVERFLOW:
2416 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2417 ts->resp = SAS_TASK_COMPLETE;
2418 ts->stat = SAS_DATA_OVERRUN;
2419 ts->residual = 0;
2420 if (pm8001_dev)
2421 pm8001_dev->running_req--;
2422 break;
2423 case IO_XFER_ERROR_BREAK:
2424 PM8001_IO_DBG(pm8001_ha,
2425 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2426 ts->resp = SAS_TASK_COMPLETE;
2427 ts->stat = SAS_INTERRUPTED;
2428 break;
2429 case IO_XFER_ERROR_PHY_NOT_READY:
2430 PM8001_IO_DBG(pm8001_ha,
2431 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2432 ts->resp = SAS_TASK_COMPLETE;
2433 ts->stat = SAS_OPEN_REJECT;
2434 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2435 break;
2436 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2437 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2438 "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2439 ts->resp = SAS_TASK_COMPLETE;
2440 ts->stat = SAS_OPEN_REJECT;
2441 ts->open_rej_reason = SAS_OREJ_EPROTO;
2442 break;
2443 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2444 PM8001_IO_DBG(pm8001_ha,
2445 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2446 ts->resp = SAS_TASK_COMPLETE;
2447 ts->stat = SAS_OPEN_REJECT;
2448 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2449 break;
2450 case IO_OPEN_CNX_ERROR_BREAK:
2451 PM8001_IO_DBG(pm8001_ha,
2452 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2453 ts->resp = SAS_TASK_COMPLETE;
2454 ts->stat = SAS_OPEN_REJECT;
2455 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2456 break;
2457 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2458 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2459 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2460 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2461 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2462 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2463 PM8001_FAIL_DBG(pm8001_ha,
2464 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2465 ts->resp = SAS_TASK_UNDELIVERED;
2466 ts->stat = SAS_DEV_NO_RESPONSE;
2467 if (!t->uldd_task) {
2468 pm8001_handle_event(pm8001_ha,
2469 pm8001_dev,
2470 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2471 ts->resp = SAS_TASK_COMPLETE;
2472 ts->stat = SAS_QUEUE_FULL;
2473 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2474 mb();/*ditto*/
2475 spin_unlock_irq(&pm8001_ha->lock);
2476 t->task_done(t);
2477 spin_lock_irq(&pm8001_ha->lock);
2478 return;
2479 }
2480 break;
2481 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2482 PM8001_IO_DBG(pm8001_ha,
2483 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2484 ts->resp = SAS_TASK_UNDELIVERED;
2485 ts->stat = SAS_OPEN_REJECT;
2486 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2487 break;
2488 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2489 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2490 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2491 ts->resp = SAS_TASK_COMPLETE;
2492 ts->stat = SAS_OPEN_REJECT;
2493 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2494 break;
2495 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2496 PM8001_IO_DBG(pm8001_ha,
2497 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2498 ts->resp = SAS_TASK_COMPLETE;
2499 ts->stat = SAS_OPEN_REJECT;
2500 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2501 break;
2502 case IO_XFER_ERROR_NAK_RECEIVED:
2503 PM8001_IO_DBG(pm8001_ha,
2504 pm8001_printk("IO_XFER_ERROR_NAK_RECEIVED\n"));
2505 ts->resp = SAS_TASK_COMPLETE;
2506 ts->stat = SAS_NAK_R_ERR;
2507 break;
2508 case IO_XFER_ERROR_PEER_ABORTED:
2509 PM8001_IO_DBG(pm8001_ha,
2510 pm8001_printk("IO_XFER_ERROR_PEER_ABORTED\n"));
2511 ts->resp = SAS_TASK_COMPLETE;
2512 ts->stat = SAS_NAK_R_ERR;
2513 break;
2514 case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2515 PM8001_IO_DBG(pm8001_ha,
2516 pm8001_printk("IO_XFER_ERROR_REJECTED_NCQ_MODE\n"));
2517 ts->resp = SAS_TASK_COMPLETE;
2518 ts->stat = SAS_DATA_UNDERRUN;
2519 break;
2520 case IO_XFER_OPEN_RETRY_TIMEOUT:
2521 PM8001_IO_DBG(pm8001_ha,
2522 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2523 ts->resp = SAS_TASK_COMPLETE;
2524 ts->stat = SAS_OPEN_TO;
2525 break;
2526 case IO_XFER_ERROR_UNEXPECTED_PHASE:
2527 PM8001_IO_DBG(pm8001_ha,
2528 pm8001_printk("IO_XFER_ERROR_UNEXPECTED_PHASE\n"));
2529 ts->resp = SAS_TASK_COMPLETE;
2530 ts->stat = SAS_OPEN_TO;
2531 break;
2532 case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2533 PM8001_IO_DBG(pm8001_ha,
2534 pm8001_printk("IO_XFER_ERROR_XFER_RDY_OVERRUN\n"));
2535 ts->resp = SAS_TASK_COMPLETE;
2536 ts->stat = SAS_OPEN_TO;
2537 break;
2538 case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2539 PM8001_IO_DBG(pm8001_ha,
2540 pm8001_printk("IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n"));
2541 ts->resp = SAS_TASK_COMPLETE;
2542 ts->stat = SAS_OPEN_TO;
2543 break;
2544 case IO_XFER_ERROR_OFFSET_MISMATCH:
2545 PM8001_IO_DBG(pm8001_ha,
2546 pm8001_printk("IO_XFER_ERROR_OFFSET_MISMATCH\n"));
2547 ts->resp = SAS_TASK_COMPLETE;
2548 ts->stat = SAS_OPEN_TO;
2549 break;
2550 case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2551 PM8001_IO_DBG(pm8001_ha,
2552 pm8001_printk("IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n"));
2553 ts->resp = SAS_TASK_COMPLETE;
2554 ts->stat = SAS_OPEN_TO;
2555 break;
2556 case IO_XFER_CMD_FRAME_ISSUED:
2557 PM8001_IO_DBG(pm8001_ha,
2558 pm8001_printk("IO_XFER_CMD_FRAME_ISSUED\n"));
2559 break;
2560 case IO_XFER_PIO_SETUP_ERROR:
2561 PM8001_IO_DBG(pm8001_ha,
2562 pm8001_printk("IO_XFER_PIO_SETUP_ERROR\n"));
2563 ts->resp = SAS_TASK_COMPLETE;
2564 ts->stat = SAS_OPEN_TO;
2565 break;
2566 case IO_XFER_ERROR_INTERNAL_CRC_ERROR:
2567 PM8001_FAIL_DBG(pm8001_ha,
2568 pm8001_printk("IO_XFR_ERROR_INTERNAL_CRC_ERROR\n"));
2569 /* TBC: used default set values */
2570 ts->resp = SAS_TASK_COMPLETE;
2571 ts->stat = SAS_OPEN_TO;
2572 break;
2573 case IO_XFER_DMA_ACTIVATE_TIMEOUT:
2574 PM8001_FAIL_DBG(pm8001_ha,
2575 pm8001_printk("IO_XFR_DMA_ACTIVATE_TIMEOUT\n"));
2576 /* TBC: used default set values */
2577 ts->resp = SAS_TASK_COMPLETE;
2578 ts->stat = SAS_OPEN_TO;
2579 break;
2580 default:
2581 PM8001_IO_DBG(pm8001_ha,
2582 pm8001_printk("Unknown status 0x%x\n", event));
2583 /* not allowed case. Therefore, return failed status */
2584 ts->resp = SAS_TASK_COMPLETE;
2585 ts->stat = SAS_OPEN_TO;
2586 break;
2587 }
2588 spin_lock_irqsave(&t->task_state_lock, flags);
2589 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2590 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2591 t->task_state_flags |= SAS_TASK_STATE_DONE;
2592 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2593 spin_unlock_irqrestore(&t->task_state_lock, flags);
2594 PM8001_FAIL_DBG(pm8001_ha,
2595 pm8001_printk("task 0x%p done with io_status 0x%x"
2596 " resp 0x%x stat 0x%x but aborted by upper layer!\n",
2597 t, event, ts->resp, ts->stat));
2598 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2599 } else if (t->uldd_task) {
2600 spin_unlock_irqrestore(&t->task_state_lock, flags);
2601 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2602 mb();/* ditto */
2603 spin_unlock_irq(&pm8001_ha->lock);
2604 t->task_done(t);
2605 spin_lock_irq(&pm8001_ha->lock);
2606 } else if (!t->uldd_task) {
2607 spin_unlock_irqrestore(&t->task_state_lock, flags);
2608 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2609 mb();/*ditto*/
2610 spin_unlock_irq(&pm8001_ha->lock);
2611 t->task_done(t);
2612 spin_lock_irq(&pm8001_ha->lock);
2613 }
2614 }
2615
2616 /*See the comments for mpi_ssp_completion */
2617 static void
2618 mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2619 {
2620 u32 param, i;
2621 struct sas_task *t;
2622 struct pm8001_ccb_info *ccb;
2623 unsigned long flags;
2624 u32 status;
2625 u32 tag;
2626 struct smp_completion_resp *psmpPayload;
2627 struct task_status_struct *ts;
2628 struct pm8001_device *pm8001_dev;
2629 char *pdma_respaddr = NULL;
2630
2631 psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2632 status = le32_to_cpu(psmpPayload->status);
2633 tag = le32_to_cpu(psmpPayload->tag);
2634
2635 ccb = &pm8001_ha->ccb_info[tag];
2636 param = le32_to_cpu(psmpPayload->param);
2637 t = ccb->task;
2638 ts = &t->task_status;
2639 pm8001_dev = ccb->device;
2640 if (status)
2641 PM8001_FAIL_DBG(pm8001_ha,
2642 pm8001_printk("smp IO status 0x%x\n", status));
2643 if (unlikely(!t || !t->lldd_task || !t->dev))
2644 return;
2645
2646 switch (status) {
2647
2648 case IO_SUCCESS:
2649 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_SUCCESS\n"));
2650 ts->resp = SAS_TASK_COMPLETE;
2651 ts->stat = SAM_STAT_GOOD;
2652 if (pm8001_dev)
2653 pm8001_dev->running_req--;
2654 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
2655 PM8001_IO_DBG(pm8001_ha,
2656 pm8001_printk("DIRECT RESPONSE Length:%d\n",
2657 param));
2658 pdma_respaddr = (char *)(phys_to_virt(cpu_to_le64
2659 ((u64)sg_dma_address
2660 (&t->smp_task.smp_resp))));
2661 for (i = 0; i < param; i++) {
2662 *(pdma_respaddr+i) = psmpPayload->_r_a[i];
2663 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
2664 "SMP Byte%d DMA data 0x%x psmp 0x%x\n",
2665 i, *(pdma_respaddr+i),
2666 psmpPayload->_r_a[i]));
2667 }
2668 }
2669 break;
2670 case IO_ABORTED:
2671 PM8001_IO_DBG(pm8001_ha,
2672 pm8001_printk("IO_ABORTED IOMB\n"));
2673 ts->resp = SAS_TASK_COMPLETE;
2674 ts->stat = SAS_ABORTED_TASK;
2675 if (pm8001_dev)
2676 pm8001_dev->running_req--;
2677 break;
2678 case IO_OVERFLOW:
2679 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_UNDERFLOW\n"));
2680 ts->resp = SAS_TASK_COMPLETE;
2681 ts->stat = SAS_DATA_OVERRUN;
2682 ts->residual = 0;
2683 if (pm8001_dev)
2684 pm8001_dev->running_req--;
2685 break;
2686 case IO_NO_DEVICE:
2687 PM8001_IO_DBG(pm8001_ha, pm8001_printk("IO_NO_DEVICE\n"));
2688 ts->resp = SAS_TASK_COMPLETE;
2689 ts->stat = SAS_PHY_DOWN;
2690 break;
2691 case IO_ERROR_HW_TIMEOUT:
2692 PM8001_IO_DBG(pm8001_ha,
2693 pm8001_printk("IO_ERROR_HW_TIMEOUT\n"));
2694 ts->resp = SAS_TASK_COMPLETE;
2695 ts->stat = SAM_STAT_BUSY;
2696 break;
2697 case IO_XFER_ERROR_BREAK:
2698 PM8001_IO_DBG(pm8001_ha,
2699 pm8001_printk("IO_XFER_ERROR_BREAK\n"));
2700 ts->resp = SAS_TASK_COMPLETE;
2701 ts->stat = SAM_STAT_BUSY;
2702 break;
2703 case IO_XFER_ERROR_PHY_NOT_READY:
2704 PM8001_IO_DBG(pm8001_ha,
2705 pm8001_printk("IO_XFER_ERROR_PHY_NOT_READY\n"));
2706 ts->resp = SAS_TASK_COMPLETE;
2707 ts->stat = SAM_STAT_BUSY;
2708 break;
2709 case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2710 PM8001_IO_DBG(pm8001_ha,
2711 pm8001_printk("IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n"));
2712 ts->resp = SAS_TASK_COMPLETE;
2713 ts->stat = SAS_OPEN_REJECT;
2714 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2715 break;
2716 case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2717 PM8001_IO_DBG(pm8001_ha,
2718 pm8001_printk("IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n"));
2719 ts->resp = SAS_TASK_COMPLETE;
2720 ts->stat = SAS_OPEN_REJECT;
2721 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2722 break;
2723 case IO_OPEN_CNX_ERROR_BREAK:
2724 PM8001_IO_DBG(pm8001_ha,
2725 pm8001_printk("IO_OPEN_CNX_ERROR_BREAK\n"));
2726 ts->resp = SAS_TASK_COMPLETE;
2727 ts->stat = SAS_OPEN_REJECT;
2728 ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2729 break;
2730 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2731 case IO_XFER_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED:
2732 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO:
2733 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST:
2734 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE:
2735 case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED:
2736 PM8001_IO_DBG(pm8001_ha,
2737 pm8001_printk("IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n"));
2738 ts->resp = SAS_TASK_COMPLETE;
2739 ts->stat = SAS_OPEN_REJECT;
2740 ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2741 pm8001_handle_event(pm8001_ha,
2742 pm8001_dev,
2743 IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2744 break;
2745 case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2746 PM8001_IO_DBG(pm8001_ha,
2747 pm8001_printk("IO_OPEN_CNX_ERROR_BAD_DESTINATION\n"));
2748 ts->resp = SAS_TASK_COMPLETE;
2749 ts->stat = SAS_OPEN_REJECT;
2750 ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2751 break;
2752 case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2753 PM8001_IO_DBG(pm8001_ha, pm8001_printk(\
2754 "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n"));
2755 ts->resp = SAS_TASK_COMPLETE;
2756 ts->stat = SAS_OPEN_REJECT;
2757 ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2758 break;
2759 case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2760 PM8001_IO_DBG(pm8001_ha,
2761 pm8001_printk("IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n"));
2762 ts->resp = SAS_TASK_COMPLETE;
2763 ts->stat = SAS_OPEN_REJECT;
2764 ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2765 break;
2766 case IO_XFER_ERROR_RX_FRAME:
2767 PM8001_IO_DBG(pm8001_ha,
2768 pm8001_printk("IO_XFER_ERROR_RX_FRAME\n"));
2769 ts->resp = SAS_TASK_COMPLETE;
2770 ts->stat = SAS_DEV_NO_RESPONSE;
2771 break;
2772 case IO_XFER_OPEN_RETRY_TIMEOUT:
2773 PM8001_IO_DBG(pm8001_ha,
2774 pm8001_printk("IO_XFER_OPEN_RETRY_TIMEOUT\n"));
2775 ts->resp = SAS_TASK_COMPLETE;
2776 ts->stat = SAS_OPEN_REJECT;
2777 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2778 break;
2779 case IO_ERROR_INTERNAL_SMP_RESOURCE:
2780 PM8001_IO_DBG(pm8001_ha,
2781 pm8001_printk("IO_ERROR_INTERNAL_SMP_RESOURCE\n"));
2782 ts->resp = SAS_TASK_COMPLETE;
2783 ts->stat = SAS_QUEUE_FULL;
2784 break;
2785 case IO_PORT_IN_RESET:
2786 PM8001_IO_DBG(pm8001_ha,
2787 pm8001_printk("IO_PORT_IN_RESET\n"));
2788 ts->resp = SAS_TASK_COMPLETE;
2789 ts->stat = SAS_OPEN_REJECT;
2790 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2791 break;
2792 case IO_DS_NON_OPERATIONAL:
2793 PM8001_IO_DBG(pm8001_ha,
2794 pm8001_printk("IO_DS_NON_OPERATIONAL\n"));
2795 ts->resp = SAS_TASK_COMPLETE;
2796 ts->stat = SAS_DEV_NO_RESPONSE;
2797 break;
2798 case IO_DS_IN_RECOVERY:
2799 PM8001_IO_DBG(pm8001_ha,
2800 pm8001_printk("IO_DS_IN_RECOVERY\n"));
2801 ts->resp = SAS_TASK_COMPLETE;
2802 ts->stat = SAS_OPEN_REJECT;
2803 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2804 break;
2805 case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2806 PM8001_IO_DBG(pm8001_ha,
2807 pm8001_printk("IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n"));
2808 ts->resp = SAS_TASK_COMPLETE;
2809 ts->stat = SAS_OPEN_REJECT;
2810 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2811 break;
2812 default:
2813 PM8001_IO_DBG(pm8001_ha,
2814 pm8001_printk("Unknown status 0x%x\n", status));
2815 ts->resp = SAS_TASK_COMPLETE;
2816 ts->stat = SAS_DEV_NO_RESPONSE;
2817 /* not allowed case. Therefore, return failed status */
2818 break;
2819 }
2820 spin_lock_irqsave(&t->task_state_lock, flags);
2821 t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2822 t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2823 t->task_state_flags |= SAS_TASK_STATE_DONE;
2824 if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2825 spin_unlock_irqrestore(&t->task_state_lock, flags);
2826 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
2827 "task 0x%p done with io_status 0x%x resp 0x%x"
2828 "stat 0x%x but aborted by upper layer!\n",
2829 t, status, ts->resp, ts->stat));
2830 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2831 } else {
2832 spin_unlock_irqrestore(&t->task_state_lock, flags);
2833 pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2834 mb();/* in order to force CPU ordering */
2835 t->task_done(t);
2836 }
2837 }
2838
2839 /**
2840 * pm80xx_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
2841 * @pm8001_ha: our hba card information
2842 * @Qnum: the outbound queue message number.
2843 * @SEA: source of event to ack
2844 * @port_id: port id.
2845 * @phyId: phy id.
2846 * @param0: parameter 0.
2847 * @param1: parameter 1.
2848 */
2849 static void pm80xx_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
2850 u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
2851 {
2852 struct hw_event_ack_req payload;
2853 u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
2854
2855 struct inbound_queue_table *circularQ;
2856
2857 memset((u8 *)&payload, 0, sizeof(payload));
2858 circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
2859 payload.tag = cpu_to_le32(1);
2860 payload.phyid_sea_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
2861 ((phyId & 0xFF) << 24) | (port_id & 0xFF));
2862 payload.param0 = cpu_to_le32(param0);
2863 payload.param1 = cpu_to_le32(param1);
2864 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
2865 }
2866
2867 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
2868 u32 phyId, u32 phy_op);
2869
2870 /**
2871 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
2872 * @pm8001_ha: our hba card information
2873 * @piomb: IO message buffer
2874 */
2875 static void
2876 hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2877 {
2878 struct hw_event_resp *pPayload =
2879 (struct hw_event_resp *)(piomb + 4);
2880 u32 lr_status_evt_portid =
2881 le32_to_cpu(pPayload->lr_status_evt_portid);
2882 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2883
2884 u8 link_rate =
2885 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2886 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2887 u8 phy_id =
2888 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2889 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2890
2891 struct pm8001_port *port = &pm8001_ha->port[port_id];
2892 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2893 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2894 unsigned long flags;
2895 u8 deviceType = pPayload->sas_identify.dev_type;
2896 port->port_state = portstate;
2897 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2898 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2899 "portid:%d; phyid:%d; linkrate:%d; "
2900 "portstate:%x; devicetype:%x\n",
2901 port_id, phy_id, link_rate, portstate, deviceType));
2902
2903 switch (deviceType) {
2904 case SAS_PHY_UNUSED:
2905 PM8001_MSG_DBG(pm8001_ha,
2906 pm8001_printk("device type no device.\n"));
2907 break;
2908 case SAS_END_DEVICE:
2909 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("end device.\n"));
2910 pm80xx_chip_phy_ctl_req(pm8001_ha, phy_id,
2911 PHY_NOTIFY_ENABLE_SPINUP);
2912 port->port_attached = 1;
2913 pm8001_get_lrate_mode(phy, link_rate);
2914 break;
2915 case SAS_EDGE_EXPANDER_DEVICE:
2916 PM8001_MSG_DBG(pm8001_ha,
2917 pm8001_printk("expander device.\n"));
2918 port->port_attached = 1;
2919 pm8001_get_lrate_mode(phy, link_rate);
2920 break;
2921 case SAS_FANOUT_EXPANDER_DEVICE:
2922 PM8001_MSG_DBG(pm8001_ha,
2923 pm8001_printk("fanout expander device.\n"));
2924 port->port_attached = 1;
2925 pm8001_get_lrate_mode(phy, link_rate);
2926 break;
2927 default:
2928 PM8001_MSG_DBG(pm8001_ha,
2929 pm8001_printk("unknown device type(%x)\n", deviceType));
2930 break;
2931 }
2932 phy->phy_type |= PORT_TYPE_SAS;
2933 phy->identify.device_type = deviceType;
2934 phy->phy_attached = 1;
2935 if (phy->identify.device_type == SAS_END_DEVICE)
2936 phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
2937 else if (phy->identify.device_type != SAS_PHY_UNUSED)
2938 phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
2939 phy->sas_phy.oob_mode = SAS_OOB_MODE;
2940 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2941 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2942 memcpy(phy->frame_rcvd, &pPayload->sas_identify,
2943 sizeof(struct sas_identify_frame)-4);
2944 phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
2945 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2946 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2947 if (pm8001_ha->flags == PM8001F_RUN_TIME)
2948 mdelay(200);/*delay a moment to wait disk to spinup*/
2949 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2950 }
2951
2952 /**
2953 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
2954 * @pm8001_ha: our hba card information
2955 * @piomb: IO message buffer
2956 */
2957 static void
2958 hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
2959 {
2960 struct hw_event_resp *pPayload =
2961 (struct hw_event_resp *)(piomb + 4);
2962 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
2963 u32 lr_status_evt_portid =
2964 le32_to_cpu(pPayload->lr_status_evt_portid);
2965 u8 link_rate =
2966 (u8)((lr_status_evt_portid & 0xF0000000) >> 28);
2967 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
2968 u8 phy_id =
2969 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
2970
2971 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
2972
2973 struct pm8001_port *port = &pm8001_ha->port[port_id];
2974 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
2975 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
2976 unsigned long flags;
2977 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
2978 "port id %d, phy id %d link_rate %d portstate 0x%x\n",
2979 port_id, phy_id, link_rate, portstate));
2980
2981 port->port_state = portstate;
2982 phy->phy_state = PHY_STATE_LINK_UP_SPCV;
2983 port->port_attached = 1;
2984 pm8001_get_lrate_mode(phy, link_rate);
2985 phy->phy_type |= PORT_TYPE_SATA;
2986 phy->phy_attached = 1;
2987 phy->sas_phy.oob_mode = SATA_OOB_MODE;
2988 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE);
2989 spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
2990 memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
2991 sizeof(struct dev_to_host_fis));
2992 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
2993 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
2994 phy->identify.device_type = SAS_SATA_DEV;
2995 pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
2996 spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
2997 pm8001_bytes_dmaed(pm8001_ha, phy_id);
2998 }
2999
3000 /**
3001 * hw_event_phy_down -we should notify the libsas the phy is down.
3002 * @pm8001_ha: our hba card information
3003 * @piomb: IO message buffer
3004 */
3005 static void
3006 hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3007 {
3008 struct hw_event_resp *pPayload =
3009 (struct hw_event_resp *)(piomb + 4);
3010
3011 u32 lr_status_evt_portid =
3012 le32_to_cpu(pPayload->lr_status_evt_portid);
3013 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3014 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3015 u8 phy_id =
3016 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3017 u8 portstate = (u8)(phyid_npip_portstate & 0x0000000F);
3018
3019 struct pm8001_port *port = &pm8001_ha->port[port_id];
3020 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3021 port->port_state = portstate;
3022 phy->phy_type = 0;
3023 phy->identify.device_type = 0;
3024 phy->phy_attached = 0;
3025 memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3026 switch (portstate) {
3027 case PORT_VALID:
3028 break;
3029 case PORT_INVALID:
3030 PM8001_MSG_DBG(pm8001_ha,
3031 pm8001_printk(" PortInvalid portID %d\n", port_id));
3032 PM8001_MSG_DBG(pm8001_ha,
3033 pm8001_printk(" Last phy Down and port invalid\n"));
3034 port->port_attached = 0;
3035 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3036 port_id, phy_id, 0, 0);
3037 break;
3038 case PORT_IN_RESET:
3039 PM8001_MSG_DBG(pm8001_ha,
3040 pm8001_printk(" Port In Reset portID %d\n", port_id));
3041 break;
3042 case PORT_NOT_ESTABLISHED:
3043 PM8001_MSG_DBG(pm8001_ha,
3044 pm8001_printk(" phy Down and PORT_NOT_ESTABLISHED\n"));
3045 port->port_attached = 0;
3046 break;
3047 case PORT_LOSTCOMM:
3048 PM8001_MSG_DBG(pm8001_ha,
3049 pm8001_printk(" phy Down and PORT_LOSTCOMM\n"));
3050 PM8001_MSG_DBG(pm8001_ha,
3051 pm8001_printk(" Last phy Down and port invalid\n"));
3052 port->port_attached = 0;
3053 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3054 port_id, phy_id, 0, 0);
3055 break;
3056 default:
3057 port->port_attached = 0;
3058 PM8001_MSG_DBG(pm8001_ha,
3059 pm8001_printk(" phy Down and(default) = 0x%x\n",
3060 portstate));
3061 break;
3062
3063 }
3064 }
3065
3066 static int mpi_phy_start_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3067 {
3068 struct phy_start_resp *pPayload =
3069 (struct phy_start_resp *)(piomb + 4);
3070 u32 status =
3071 le32_to_cpu(pPayload->status);
3072 u32 phy_id =
3073 le32_to_cpu(pPayload->phyid);
3074 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3075
3076 PM8001_INIT_DBG(pm8001_ha,
3077 pm8001_printk("phy start resp status:0x%x, phyid:0x%x\n",
3078 status, phy_id));
3079 if (status == 0) {
3080 phy->phy_state = 1;
3081 if (pm8001_ha->flags == PM8001F_RUN_TIME)
3082 complete(phy->enable_completion);
3083 }
3084 return 0;
3085
3086 }
3087
3088 /**
3089 * mpi_thermal_hw_event -The hw event has come.
3090 * @pm8001_ha: our hba card information
3091 * @piomb: IO message buffer
3092 */
3093 static int mpi_thermal_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3094 {
3095 struct thermal_hw_event *pPayload =
3096 (struct thermal_hw_event *)(piomb + 4);
3097
3098 u32 thermal_event = le32_to_cpu(pPayload->thermal_event);
3099 u32 rht_lht = le32_to_cpu(pPayload->rht_lht);
3100
3101 if (thermal_event & 0x40) {
3102 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3103 "Thermal Event: Local high temperature violated!\n"));
3104 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3105 "Thermal Event: Measured local high temperature %d\n",
3106 ((rht_lht & 0xFF00) >> 8)));
3107 }
3108 if (thermal_event & 0x10) {
3109 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3110 "Thermal Event: Remote high temperature violated!\n"));
3111 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3112 "Thermal Event: Measured remote high temperature %d\n",
3113 ((rht_lht & 0xFF000000) >> 24)));
3114 }
3115 return 0;
3116 }
3117
3118 /**
3119 * mpi_hw_event -The hw event has come.
3120 * @pm8001_ha: our hba card information
3121 * @piomb: IO message buffer
3122 */
3123 static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3124 {
3125 unsigned long flags;
3126 struct hw_event_resp *pPayload =
3127 (struct hw_event_resp *)(piomb + 4);
3128 u32 lr_status_evt_portid =
3129 le32_to_cpu(pPayload->lr_status_evt_portid);
3130 u32 phyid_npip_portstate = le32_to_cpu(pPayload->phyid_npip_portstate);
3131 u8 port_id = (u8)(lr_status_evt_portid & 0x000000FF);
3132 u8 phy_id =
3133 (u8)((phyid_npip_portstate & 0xFF0000) >> 16);
3134 u16 eventType =
3135 (u16)((lr_status_evt_portid & 0x00FFFF00) >> 8);
3136 u8 status =
3137 (u8)((lr_status_evt_portid & 0x0F000000) >> 24);
3138
3139 struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3140 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3141 struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3142 PM8001_MSG_DBG(pm8001_ha,
3143 pm8001_printk("portid:%d phyid:%d event:0x%x status:0x%x\n",
3144 port_id, phy_id, eventType, status));
3145
3146 switch (eventType) {
3147
3148 case HW_EVENT_SAS_PHY_UP:
3149 PM8001_MSG_DBG(pm8001_ha,
3150 pm8001_printk("HW_EVENT_PHY_START_STATUS\n"));
3151 hw_event_sas_phy_up(pm8001_ha, piomb);
3152 break;
3153 case HW_EVENT_SATA_PHY_UP:
3154 PM8001_MSG_DBG(pm8001_ha,
3155 pm8001_printk("HW_EVENT_SATA_PHY_UP\n"));
3156 hw_event_sata_phy_up(pm8001_ha, piomb);
3157 break;
3158 case HW_EVENT_SATA_SPINUP_HOLD:
3159 PM8001_MSG_DBG(pm8001_ha,
3160 pm8001_printk("HW_EVENT_SATA_SPINUP_HOLD\n"));
3161 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD);
3162 break;
3163 case HW_EVENT_PHY_DOWN:
3164 PM8001_MSG_DBG(pm8001_ha,
3165 pm8001_printk("HW_EVENT_PHY_DOWN\n"));
3166 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL);
3167 phy->phy_attached = 0;
3168 phy->phy_state = 0;
3169 hw_event_phy_down(pm8001_ha, piomb);
3170 break;
3171 case HW_EVENT_PORT_INVALID:
3172 PM8001_MSG_DBG(pm8001_ha,
3173 pm8001_printk("HW_EVENT_PORT_INVALID\n"));
3174 sas_phy_disconnected(sas_phy);
3175 phy->phy_attached = 0;
3176 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3177 break;
3178 /* the broadcast change primitive received, tell the LIBSAS this event
3179 to revalidate the sas domain*/
3180 case HW_EVENT_BROADCAST_CHANGE:
3181 PM8001_MSG_DBG(pm8001_ha,
3182 pm8001_printk("HW_EVENT_BROADCAST_CHANGE\n"));
3183 pm80xx_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_BROADCAST_CHANGE,
3184 port_id, phy_id, 1, 0);
3185 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3186 sas_phy->sas_prim = HW_EVENT_BROADCAST_CHANGE;
3187 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3188 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3189 break;
3190 case HW_EVENT_PHY_ERROR:
3191 PM8001_MSG_DBG(pm8001_ha,
3192 pm8001_printk("HW_EVENT_PHY_ERROR\n"));
3193 sas_phy_disconnected(&phy->sas_phy);
3194 phy->phy_attached = 0;
3195 sas_ha->notify_phy_event(&phy->sas_phy, PHYE_OOB_ERROR);
3196 break;
3197 case HW_EVENT_BROADCAST_EXP:
3198 PM8001_MSG_DBG(pm8001_ha,
3199 pm8001_printk("HW_EVENT_BROADCAST_EXP\n"));
3200 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3201 sas_phy->sas_prim = HW_EVENT_BROADCAST_EXP;
3202 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3203 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3204 break;
3205 case HW_EVENT_LINK_ERR_INVALID_DWORD:
3206 PM8001_MSG_DBG(pm8001_ha,
3207 pm8001_printk("HW_EVENT_LINK_ERR_INVALID_DWORD\n"));
3208 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3209 HW_EVENT_LINK_ERR_INVALID_DWORD, port_id, phy_id, 0, 0);
3210 sas_phy_disconnected(sas_phy);
3211 phy->phy_attached = 0;
3212 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3213 break;
3214 case HW_EVENT_LINK_ERR_DISPARITY_ERROR:
3215 PM8001_MSG_DBG(pm8001_ha,
3216 pm8001_printk("HW_EVENT_LINK_ERR_DISPARITY_ERROR\n"));
3217 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3218 HW_EVENT_LINK_ERR_DISPARITY_ERROR,
3219 port_id, phy_id, 0, 0);
3220 sas_phy_disconnected(sas_phy);
3221 phy->phy_attached = 0;
3222 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3223 break;
3224 case HW_EVENT_LINK_ERR_CODE_VIOLATION:
3225 PM8001_MSG_DBG(pm8001_ha,
3226 pm8001_printk("HW_EVENT_LINK_ERR_CODE_VIOLATION\n"));
3227 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3228 HW_EVENT_LINK_ERR_CODE_VIOLATION,
3229 port_id, phy_id, 0, 0);
3230 sas_phy_disconnected(sas_phy);
3231 phy->phy_attached = 0;
3232 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3233 break;
3234 case HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH:
3235 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3236 "HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH\n"));
3237 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3238 HW_EVENT_LINK_ERR_LOSS_OF_DWORD_SYNCH,
3239 port_id, phy_id, 0, 0);
3240 sas_phy_disconnected(sas_phy);
3241 phy->phy_attached = 0;
3242 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3243 break;
3244 case HW_EVENT_MALFUNCTION:
3245 PM8001_MSG_DBG(pm8001_ha,
3246 pm8001_printk("HW_EVENT_MALFUNCTION\n"));
3247 break;
3248 case HW_EVENT_BROADCAST_SES:
3249 PM8001_MSG_DBG(pm8001_ha,
3250 pm8001_printk("HW_EVENT_BROADCAST_SES\n"));
3251 spin_lock_irqsave(&sas_phy->sas_prim_lock, flags);
3252 sas_phy->sas_prim = HW_EVENT_BROADCAST_SES;
3253 spin_unlock_irqrestore(&sas_phy->sas_prim_lock, flags);
3254 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
3255 break;
3256 case HW_EVENT_INBOUND_CRC_ERROR:
3257 PM8001_MSG_DBG(pm8001_ha,
3258 pm8001_printk("HW_EVENT_INBOUND_CRC_ERROR\n"));
3259 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3260 HW_EVENT_INBOUND_CRC_ERROR,
3261 port_id, phy_id, 0, 0);
3262 break;
3263 case HW_EVENT_HARD_RESET_RECEIVED:
3264 PM8001_MSG_DBG(pm8001_ha,
3265 pm8001_printk("HW_EVENT_HARD_RESET_RECEIVED\n"));
3266 sas_ha->notify_port_event(sas_phy, PORTE_HARD_RESET);
3267 break;
3268 case HW_EVENT_ID_FRAME_TIMEOUT:
3269 PM8001_MSG_DBG(pm8001_ha,
3270 pm8001_printk("HW_EVENT_ID_FRAME_TIMEOUT\n"));
3271 sas_phy_disconnected(sas_phy);
3272 phy->phy_attached = 0;
3273 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3274 break;
3275 case HW_EVENT_LINK_ERR_PHY_RESET_FAILED:
3276 PM8001_MSG_DBG(pm8001_ha,
3277 pm8001_printk("HW_EVENT_LINK_ERR_PHY_RESET_FAILED\n"));
3278 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3279 HW_EVENT_LINK_ERR_PHY_RESET_FAILED,
3280 port_id, phy_id, 0, 0);
3281 sas_phy_disconnected(sas_phy);
3282 phy->phy_attached = 0;
3283 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3284 break;
3285 case HW_EVENT_PORT_RESET_TIMER_TMO:
3286 PM8001_MSG_DBG(pm8001_ha,
3287 pm8001_printk("HW_EVENT_PORT_RESET_TIMER_TMO\n"));
3288 sas_phy_disconnected(sas_phy);
3289 phy->phy_attached = 0;
3290 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3291 break;
3292 case HW_EVENT_PORT_RECOVERY_TIMER_TMO:
3293 PM8001_MSG_DBG(pm8001_ha,
3294 pm8001_printk("HW_EVENT_PORT_RECOVERY_TIMER_TMO\n"));
3295 pm80xx_hw_event_ack_req(pm8001_ha, 0,
3296 HW_EVENT_PORT_RECOVERY_TIMER_TMO,
3297 port_id, phy_id, 0, 0);
3298 sas_phy_disconnected(sas_phy);
3299 phy->phy_attached = 0;
3300 sas_ha->notify_port_event(sas_phy, PORTE_LINK_RESET_ERR);
3301 break;
3302 case HW_EVENT_PORT_RECOVER:
3303 PM8001_MSG_DBG(pm8001_ha,
3304 pm8001_printk("HW_EVENT_PORT_RECOVER\n"));
3305 break;
3306 case HW_EVENT_PORT_RESET_COMPLETE:
3307 PM8001_MSG_DBG(pm8001_ha,
3308 pm8001_printk("HW_EVENT_PORT_RESET_COMPLETE\n"));
3309 break;
3310 case EVENT_BROADCAST_ASYNCH_EVENT:
3311 PM8001_MSG_DBG(pm8001_ha,
3312 pm8001_printk("EVENT_BROADCAST_ASYNCH_EVENT\n"));
3313 break;
3314 default:
3315 PM8001_MSG_DBG(pm8001_ha,
3316 pm8001_printk("Unknown event type 0x%x\n", eventType));
3317 break;
3318 }
3319 return 0;
3320 }
3321
3322 /**
3323 * mpi_phy_stop_resp - SPCv specific
3324 * @pm8001_ha: our hba card information
3325 * @piomb: IO message buffer
3326 */
3327 static int mpi_phy_stop_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3328 {
3329 struct phy_stop_resp *pPayload =
3330 (struct phy_stop_resp *)(piomb + 4);
3331 u32 status =
3332 le32_to_cpu(pPayload->status);
3333 u32 phyid =
3334 le32_to_cpu(pPayload->phyid);
3335 struct pm8001_phy *phy = &pm8001_ha->phy[phyid];
3336 PM8001_MSG_DBG(pm8001_ha,
3337 pm8001_printk("phy:0x%x status:0x%x\n",
3338 phyid, status));
3339 if (status == 0)
3340 phy->phy_state = 0;
3341 return 0;
3342 }
3343
3344 /**
3345 * mpi_set_controller_config_resp - SPCv specific
3346 * @pm8001_ha: our hba card information
3347 * @piomb: IO message buffer
3348 */
3349 static int mpi_set_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3350 void *piomb)
3351 {
3352 struct set_ctrl_cfg_resp *pPayload =
3353 (struct set_ctrl_cfg_resp *)(piomb + 4);
3354 u32 status = le32_to_cpu(pPayload->status);
3355 u32 err_qlfr_pgcd = le32_to_cpu(pPayload->err_qlfr_pgcd);
3356
3357 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3358 "SET CONTROLLER RESP: status 0x%x qlfr_pgcd 0x%x\n",
3359 status, err_qlfr_pgcd));
3360
3361 return 0;
3362 }
3363
3364 /**
3365 * mpi_get_controller_config_resp - SPCv specific
3366 * @pm8001_ha: our hba card information
3367 * @piomb: IO message buffer
3368 */
3369 static int mpi_get_controller_config_resp(struct pm8001_hba_info *pm8001_ha,
3370 void *piomb)
3371 {
3372 PM8001_MSG_DBG(pm8001_ha,
3373 pm8001_printk(" pm80xx_addition_functionality\n"));
3374
3375 return 0;
3376 }
3377
3378 /**
3379 * mpi_get_phy_profile_resp - SPCv specific
3380 * @pm8001_ha: our hba card information
3381 * @piomb: IO message buffer
3382 */
3383 static int mpi_get_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3384 void *piomb)
3385 {
3386 PM8001_MSG_DBG(pm8001_ha,
3387 pm8001_printk(" pm80xx_addition_functionality\n"));
3388
3389 return 0;
3390 }
3391
3392 /**
3393 * mpi_flash_op_ext_resp - SPCv specific
3394 * @pm8001_ha: our hba card information
3395 * @piomb: IO message buffer
3396 */
3397 static int mpi_flash_op_ext_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3398 {
3399 PM8001_MSG_DBG(pm8001_ha,
3400 pm8001_printk(" pm80xx_addition_functionality\n"));
3401
3402 return 0;
3403 }
3404
3405 /**
3406 * mpi_set_phy_profile_resp - SPCv specific
3407 * @pm8001_ha: our hba card information
3408 * @piomb: IO message buffer
3409 */
3410 static int mpi_set_phy_profile_resp(struct pm8001_hba_info *pm8001_ha,
3411 void *piomb)
3412 {
3413 u8 page_code;
3414 struct set_phy_profile_resp *pPayload =
3415 (struct set_phy_profile_resp *)(piomb + 4);
3416 u32 ppc_phyid = le32_to_cpu(pPayload->ppc_phyid);
3417 u32 status = le32_to_cpu(pPayload->status);
3418
3419 page_code = (u8)((ppc_phyid & 0xFF00) >> 8);
3420 if (status) {
3421 /* status is FAILED */
3422 PM8001_FAIL_DBG(pm8001_ha,
3423 pm8001_printk("PhyProfile command failed with status "
3424 "0x%08X \n", status));
3425 return -1;
3426 } else {
3427 if (page_code != SAS_PHY_ANALOG_SETTINGS_PAGE) {
3428 PM8001_FAIL_DBG(pm8001_ha,
3429 pm8001_printk("Invalid page code 0x%X\n",
3430 page_code));
3431 return -1;
3432 }
3433 }
3434 return 0;
3435 }
3436
3437 /**
3438 * mpi_kek_management_resp - SPCv specific
3439 * @pm8001_ha: our hba card information
3440 * @piomb: IO message buffer
3441 */
3442 static int mpi_kek_management_resp(struct pm8001_hba_info *pm8001_ha,
3443 void *piomb)
3444 {
3445 struct kek_mgmt_resp *pPayload = (struct kek_mgmt_resp *)(piomb + 4);
3446
3447 u32 status = le32_to_cpu(pPayload->status);
3448 u32 kidx_new_curr_ksop = le32_to_cpu(pPayload->kidx_new_curr_ksop);
3449 u32 err_qlfr = le32_to_cpu(pPayload->err_qlfr);
3450
3451 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3452 "KEK MGMT RESP. Status 0x%x idx_ksop 0x%x err_qlfr 0x%x\n",
3453 status, kidx_new_curr_ksop, err_qlfr));
3454
3455 return 0;
3456 }
3457
3458 /**
3459 * mpi_dek_management_resp - SPCv specific
3460 * @pm8001_ha: our hba card information
3461 * @piomb: IO message buffer
3462 */
3463 static int mpi_dek_management_resp(struct pm8001_hba_info *pm8001_ha,
3464 void *piomb)
3465 {
3466 PM8001_MSG_DBG(pm8001_ha,
3467 pm8001_printk(" pm80xx_addition_functionality\n"));
3468
3469 return 0;
3470 }
3471
3472 /**
3473 * ssp_coalesced_comp_resp - SPCv specific
3474 * @pm8001_ha: our hba card information
3475 * @piomb: IO message buffer
3476 */
3477 static int ssp_coalesced_comp_resp(struct pm8001_hba_info *pm8001_ha,
3478 void *piomb)
3479 {
3480 PM8001_MSG_DBG(pm8001_ha,
3481 pm8001_printk(" pm80xx_addition_functionality\n"));
3482
3483 return 0;
3484 }
3485
3486 /**
3487 * process_one_iomb - process one outbound Queue memory block
3488 * @pm8001_ha: our hba card information
3489 * @piomb: IO message buffer
3490 */
3491 static void process_one_iomb(struct pm8001_hba_info *pm8001_ha, void *piomb)
3492 {
3493 __le32 pHeader = *(__le32 *)piomb;
3494 u32 opc = (u32)((le32_to_cpu(pHeader)) & 0xFFF);
3495
3496 switch (opc) {
3497 case OPC_OUB_ECHO:
3498 PM8001_MSG_DBG(pm8001_ha, pm8001_printk("OPC_OUB_ECHO\n"));
3499 break;
3500 case OPC_OUB_HW_EVENT:
3501 PM8001_MSG_DBG(pm8001_ha,
3502 pm8001_printk("OPC_OUB_HW_EVENT\n"));
3503 mpi_hw_event(pm8001_ha, piomb);
3504 break;
3505 case OPC_OUB_THERM_HW_EVENT:
3506 PM8001_MSG_DBG(pm8001_ha,
3507 pm8001_printk("OPC_OUB_THERMAL_EVENT\n"));
3508 mpi_thermal_hw_event(pm8001_ha, piomb);
3509 break;
3510 case OPC_OUB_SSP_COMP:
3511 PM8001_MSG_DBG(pm8001_ha,
3512 pm8001_printk("OPC_OUB_SSP_COMP\n"));
3513 mpi_ssp_completion(pm8001_ha, piomb);
3514 break;
3515 case OPC_OUB_SMP_COMP:
3516 PM8001_MSG_DBG(pm8001_ha,
3517 pm8001_printk("OPC_OUB_SMP_COMP\n"));
3518 mpi_smp_completion(pm8001_ha, piomb);
3519 break;
3520 case OPC_OUB_LOCAL_PHY_CNTRL:
3521 PM8001_MSG_DBG(pm8001_ha,
3522 pm8001_printk("OPC_OUB_LOCAL_PHY_CNTRL\n"));
3523 pm8001_mpi_local_phy_ctl(pm8001_ha, piomb);
3524 break;
3525 case OPC_OUB_DEV_REGIST:
3526 PM8001_MSG_DBG(pm8001_ha,
3527 pm8001_printk("OPC_OUB_DEV_REGIST\n"));
3528 pm8001_mpi_reg_resp(pm8001_ha, piomb);
3529 break;
3530 case OPC_OUB_DEREG_DEV:
3531 PM8001_MSG_DBG(pm8001_ha,
3532 pm8001_printk("unregister the device\n"));
3533 pm8001_mpi_dereg_resp(pm8001_ha, piomb);
3534 break;
3535 case OPC_OUB_GET_DEV_HANDLE:
3536 PM8001_MSG_DBG(pm8001_ha,
3537 pm8001_printk("OPC_OUB_GET_DEV_HANDLE\n"));
3538 break;
3539 case OPC_OUB_SATA_COMP:
3540 PM8001_MSG_DBG(pm8001_ha,
3541 pm8001_printk("OPC_OUB_SATA_COMP\n"));
3542 mpi_sata_completion(pm8001_ha, piomb);
3543 break;
3544 case OPC_OUB_SATA_EVENT:
3545 PM8001_MSG_DBG(pm8001_ha,
3546 pm8001_printk("OPC_OUB_SATA_EVENT\n"));
3547 mpi_sata_event(pm8001_ha, piomb);
3548 break;
3549 case OPC_OUB_SSP_EVENT:
3550 PM8001_MSG_DBG(pm8001_ha,
3551 pm8001_printk("OPC_OUB_SSP_EVENT\n"));
3552 mpi_ssp_event(pm8001_ha, piomb);
3553 break;
3554 case OPC_OUB_DEV_HANDLE_ARRIV:
3555 PM8001_MSG_DBG(pm8001_ha,
3556 pm8001_printk("OPC_OUB_DEV_HANDLE_ARRIV\n"));
3557 /*This is for target*/
3558 break;
3559 case OPC_OUB_SSP_RECV_EVENT:
3560 PM8001_MSG_DBG(pm8001_ha,
3561 pm8001_printk("OPC_OUB_SSP_RECV_EVENT\n"));
3562 /*This is for target*/
3563 break;
3564 case OPC_OUB_FW_FLASH_UPDATE:
3565 PM8001_MSG_DBG(pm8001_ha,
3566 pm8001_printk("OPC_OUB_FW_FLASH_UPDATE\n"));
3567 pm8001_mpi_fw_flash_update_resp(pm8001_ha, piomb);
3568 break;
3569 case OPC_OUB_GPIO_RESPONSE:
3570 PM8001_MSG_DBG(pm8001_ha,
3571 pm8001_printk("OPC_OUB_GPIO_RESPONSE\n"));
3572 break;
3573 case OPC_OUB_GPIO_EVENT:
3574 PM8001_MSG_DBG(pm8001_ha,
3575 pm8001_printk("OPC_OUB_GPIO_EVENT\n"));
3576 break;
3577 case OPC_OUB_GENERAL_EVENT:
3578 PM8001_MSG_DBG(pm8001_ha,
3579 pm8001_printk("OPC_OUB_GENERAL_EVENT\n"));
3580 pm8001_mpi_general_event(pm8001_ha, piomb);
3581 break;
3582 case OPC_OUB_SSP_ABORT_RSP:
3583 PM8001_MSG_DBG(pm8001_ha,
3584 pm8001_printk("OPC_OUB_SSP_ABORT_RSP\n"));
3585 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3586 break;
3587 case OPC_OUB_SATA_ABORT_RSP:
3588 PM8001_MSG_DBG(pm8001_ha,
3589 pm8001_printk("OPC_OUB_SATA_ABORT_RSP\n"));
3590 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3591 break;
3592 case OPC_OUB_SAS_DIAG_MODE_START_END:
3593 PM8001_MSG_DBG(pm8001_ha,
3594 pm8001_printk("OPC_OUB_SAS_DIAG_MODE_START_END\n"));
3595 break;
3596 case OPC_OUB_SAS_DIAG_EXECUTE:
3597 PM8001_MSG_DBG(pm8001_ha,
3598 pm8001_printk("OPC_OUB_SAS_DIAG_EXECUTE\n"));
3599 break;
3600 case OPC_OUB_GET_TIME_STAMP:
3601 PM8001_MSG_DBG(pm8001_ha,
3602 pm8001_printk("OPC_OUB_GET_TIME_STAMP\n"));
3603 break;
3604 case OPC_OUB_SAS_HW_EVENT_ACK:
3605 PM8001_MSG_DBG(pm8001_ha,
3606 pm8001_printk("OPC_OUB_SAS_HW_EVENT_ACK\n"));
3607 break;
3608 case OPC_OUB_PORT_CONTROL:
3609 PM8001_MSG_DBG(pm8001_ha,
3610 pm8001_printk("OPC_OUB_PORT_CONTROL\n"));
3611 break;
3612 case OPC_OUB_SMP_ABORT_RSP:
3613 PM8001_MSG_DBG(pm8001_ha,
3614 pm8001_printk("OPC_OUB_SMP_ABORT_RSP\n"));
3615 pm8001_mpi_task_abort_resp(pm8001_ha, piomb);
3616 break;
3617 case OPC_OUB_GET_NVMD_DATA:
3618 PM8001_MSG_DBG(pm8001_ha,
3619 pm8001_printk("OPC_OUB_GET_NVMD_DATA\n"));
3620 pm8001_mpi_get_nvmd_resp(pm8001_ha, piomb);
3621 break;
3622 case OPC_OUB_SET_NVMD_DATA:
3623 PM8001_MSG_DBG(pm8001_ha,
3624 pm8001_printk("OPC_OUB_SET_NVMD_DATA\n"));
3625 pm8001_mpi_set_nvmd_resp(pm8001_ha, piomb);
3626 break;
3627 case OPC_OUB_DEVICE_HANDLE_REMOVAL:
3628 PM8001_MSG_DBG(pm8001_ha,
3629 pm8001_printk("OPC_OUB_DEVICE_HANDLE_REMOVAL\n"));
3630 break;
3631 case OPC_OUB_SET_DEVICE_STATE:
3632 PM8001_MSG_DBG(pm8001_ha,
3633 pm8001_printk("OPC_OUB_SET_DEVICE_STATE\n"));
3634 pm8001_mpi_set_dev_state_resp(pm8001_ha, piomb);
3635 break;
3636 case OPC_OUB_GET_DEVICE_STATE:
3637 PM8001_MSG_DBG(pm8001_ha,
3638 pm8001_printk("OPC_OUB_GET_DEVICE_STATE\n"));
3639 break;
3640 case OPC_OUB_SET_DEV_INFO:
3641 PM8001_MSG_DBG(pm8001_ha,
3642 pm8001_printk("OPC_OUB_SET_DEV_INFO\n"));
3643 break;
3644 /* spcv specifc commands */
3645 case OPC_OUB_PHY_START_RESP:
3646 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3647 "OPC_OUB_PHY_START_RESP opcode:%x\n", opc));
3648 mpi_phy_start_resp(pm8001_ha, piomb);
3649 break;
3650 case OPC_OUB_PHY_STOP_RESP:
3651 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3652 "OPC_OUB_PHY_STOP_RESP opcode:%x\n", opc));
3653 mpi_phy_stop_resp(pm8001_ha, piomb);
3654 break;
3655 case OPC_OUB_SET_CONTROLLER_CONFIG:
3656 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3657 "OPC_OUB_SET_CONTROLLER_CONFIG opcode:%x\n", opc));
3658 mpi_set_controller_config_resp(pm8001_ha, piomb);
3659 break;
3660 case OPC_OUB_GET_CONTROLLER_CONFIG:
3661 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3662 "OPC_OUB_GET_CONTROLLER_CONFIG opcode:%x\n", opc));
3663 mpi_get_controller_config_resp(pm8001_ha, piomb);
3664 break;
3665 case OPC_OUB_GET_PHY_PROFILE:
3666 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3667 "OPC_OUB_GET_PHY_PROFILE opcode:%x\n", opc));
3668 mpi_get_phy_profile_resp(pm8001_ha, piomb);
3669 break;
3670 case OPC_OUB_FLASH_OP_EXT:
3671 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3672 "OPC_OUB_FLASH_OP_EXT opcode:%x\n", opc));
3673 mpi_flash_op_ext_resp(pm8001_ha, piomb);
3674 break;
3675 case OPC_OUB_SET_PHY_PROFILE:
3676 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3677 "OPC_OUB_SET_PHY_PROFILE opcode:%x\n", opc));
3678 mpi_set_phy_profile_resp(pm8001_ha, piomb);
3679 break;
3680 case OPC_OUB_KEK_MANAGEMENT_RESP:
3681 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3682 "OPC_OUB_KEK_MANAGEMENT_RESP opcode:%x\n", opc));
3683 mpi_kek_management_resp(pm8001_ha, piomb);
3684 break;
3685 case OPC_OUB_DEK_MANAGEMENT_RESP:
3686 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3687 "OPC_OUB_DEK_MANAGEMENT_RESP opcode:%x\n", opc));
3688 mpi_dek_management_resp(pm8001_ha, piomb);
3689 break;
3690 case OPC_OUB_SSP_COALESCED_COMP_RESP:
3691 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3692 "OPC_OUB_SSP_COALESCED_COMP_RESP opcode:%x\n", opc));
3693 ssp_coalesced_comp_resp(pm8001_ha, piomb);
3694 break;
3695 default:
3696 PM8001_MSG_DBG(pm8001_ha, pm8001_printk(
3697 "Unknown outbound Queue IOMB OPC = 0x%x\n", opc));
3698 break;
3699 }
3700 }
3701
3702 static int process_oq(struct pm8001_hba_info *pm8001_ha, u8 vec)
3703 {
3704 struct outbound_queue_table *circularQ;
3705 void *pMsg1 = NULL;
3706 u8 uninitialized_var(bc);
3707 u32 ret = MPI_IO_STATUS_FAIL;
3708 unsigned long flags;
3709
3710 spin_lock_irqsave(&pm8001_ha->lock, flags);
3711 circularQ = &pm8001_ha->outbnd_q_tbl[vec];
3712 do {
3713 ret = pm8001_mpi_msg_consume(pm8001_ha, circularQ, &pMsg1, &bc);
3714 if (MPI_IO_STATUS_SUCCESS == ret) {
3715 /* process the outbound message */
3716 process_one_iomb(pm8001_ha, (void *)(pMsg1 - 4));
3717 /* free the message from the outbound circular buffer */
3718 pm8001_mpi_msg_free_set(pm8001_ha, pMsg1,
3719 circularQ, bc);
3720 }
3721 if (MPI_IO_STATUS_BUSY == ret) {
3722 /* Update the producer index from SPC */
3723 circularQ->producer_index =
3724 cpu_to_le32(pm8001_read_32(circularQ->pi_virt));
3725 if (le32_to_cpu(circularQ->producer_index) ==
3726 circularQ->consumer_idx)
3727 /* OQ is empty */
3728 break;
3729 }
3730 } while (1);
3731 spin_unlock_irqrestore(&pm8001_ha->lock, flags);
3732 return ret;
3733 }
3734
3735 /* PCI_DMA_... to our direction translation. */
3736 static const u8 data_dir_flags[] = {
3737 [PCI_DMA_BIDIRECTIONAL] = DATA_DIR_BYRECIPIENT,/* UNSPECIFIED */
3738 [PCI_DMA_TODEVICE] = DATA_DIR_OUT,/* OUTBOUND */
3739 [PCI_DMA_FROMDEVICE] = DATA_DIR_IN,/* INBOUND */
3740 [PCI_DMA_NONE] = DATA_DIR_NONE,/* NO TRANSFER */
3741 };
3742
3743 static void build_smp_cmd(u32 deviceID, __le32 hTag,
3744 struct smp_req *psmp_cmd, int mode, int length)
3745 {
3746 psmp_cmd->tag = hTag;
3747 psmp_cmd->device_id = cpu_to_le32(deviceID);
3748 if (mode == SMP_DIRECT) {
3749 length = length - 4; /* subtract crc */
3750 psmp_cmd->len_ip_ir = cpu_to_le32(length << 16);
3751 } else {
3752 psmp_cmd->len_ip_ir = cpu_to_le32(1|(1 << 1));
3753 }
3754 }
3755
3756 /**
3757 * pm8001_chip_smp_req - send a SMP task to FW
3758 * @pm8001_ha: our hba card information.
3759 * @ccb: the ccb information this request used.
3760 */
3761 static int pm80xx_chip_smp_req(struct pm8001_hba_info *pm8001_ha,
3762 struct pm8001_ccb_info *ccb)
3763 {
3764 int elem, rc;
3765 struct sas_task *task = ccb->task;
3766 struct domain_device *dev = task->dev;
3767 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3768 struct scatterlist *sg_req, *sg_resp;
3769 u32 req_len, resp_len;
3770 struct smp_req smp_cmd;
3771 u32 opc;
3772 struct inbound_queue_table *circularQ;
3773 char *preq_dma_addr = NULL;
3774 __le64 tmp_addr;
3775 u32 i, length;
3776
3777 memset(&smp_cmd, 0, sizeof(smp_cmd));
3778 /*
3779 * DMA-map SMP request, response buffers
3780 */
3781 sg_req = &task->smp_task.smp_req;
3782 elem = dma_map_sg(pm8001_ha->dev, sg_req, 1, PCI_DMA_TODEVICE);
3783 if (!elem)
3784 return -ENOMEM;
3785 req_len = sg_dma_len(sg_req);
3786
3787 sg_resp = &task->smp_task.smp_resp;
3788 elem = dma_map_sg(pm8001_ha->dev, sg_resp, 1, PCI_DMA_FROMDEVICE);
3789 if (!elem) {
3790 rc = -ENOMEM;
3791 goto err_out;
3792 }
3793 resp_len = sg_dma_len(sg_resp);
3794 /* must be in dwords */
3795 if ((req_len & 0x3) || (resp_len & 0x3)) {
3796 rc = -EINVAL;
3797 goto err_out_2;
3798 }
3799
3800 opc = OPC_INB_SMP_REQUEST;
3801 circularQ = &pm8001_ha->inbnd_q_tbl[0];
3802 smp_cmd.tag = cpu_to_le32(ccb->ccb_tag);
3803
3804 length = sg_req->length;
3805 PM8001_IO_DBG(pm8001_ha,
3806 pm8001_printk("SMP Frame Length %d\n", sg_req->length));
3807 if (!(length - 8))
3808 pm8001_ha->smp_exp_mode = SMP_DIRECT;
3809 else
3810 pm8001_ha->smp_exp_mode = SMP_INDIRECT;
3811
3812
3813 tmp_addr = cpu_to_le64((u64)sg_dma_address(&task->smp_task.smp_req));
3814 preq_dma_addr = (char *)phys_to_virt(tmp_addr);
3815
3816 /* INDIRECT MODE command settings. Use DMA */
3817 if (pm8001_ha->smp_exp_mode == SMP_INDIRECT) {
3818 PM8001_IO_DBG(pm8001_ha,
3819 pm8001_printk("SMP REQUEST INDIRECT MODE\n"));
3820 /* for SPCv indirect mode. Place the top 4 bytes of
3821 * SMP Request header here. */
3822 for (i = 0; i < 4; i++)
3823 smp_cmd.smp_req16[i] = *(preq_dma_addr + i);
3824 /* exclude top 4 bytes for SMP req header */
3825 smp_cmd.long_smp_req.long_req_addr =
3826 cpu_to_le64((u64)sg_dma_address
3827 (&task->smp_task.smp_req) + 4);
3828 /* exclude 4 bytes for SMP req header and CRC */
3829 smp_cmd.long_smp_req.long_req_size =
3830 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-8);
3831 smp_cmd.long_smp_req.long_resp_addr =
3832 cpu_to_le64((u64)sg_dma_address
3833 (&task->smp_task.smp_resp));
3834 smp_cmd.long_smp_req.long_resp_size =
3835 cpu_to_le32((u32)sg_dma_len
3836 (&task->smp_task.smp_resp)-4);
3837 } else { /* DIRECT MODE */
3838 smp_cmd.long_smp_req.long_req_addr =
3839 cpu_to_le64((u64)sg_dma_address
3840 (&task->smp_task.smp_req));
3841 smp_cmd.long_smp_req.long_req_size =
3842 cpu_to_le32((u32)sg_dma_len(&task->smp_task.smp_req)-4);
3843 smp_cmd.long_smp_req.long_resp_addr =
3844 cpu_to_le64((u64)sg_dma_address
3845 (&task->smp_task.smp_resp));
3846 smp_cmd.long_smp_req.long_resp_size =
3847 cpu_to_le32
3848 ((u32)sg_dma_len(&task->smp_task.smp_resp)-4);
3849 }
3850 if (pm8001_ha->smp_exp_mode == SMP_DIRECT) {
3851 PM8001_IO_DBG(pm8001_ha,
3852 pm8001_printk("SMP REQUEST DIRECT MODE\n"));
3853 for (i = 0; i < length; i++)
3854 if (i < 16) {
3855 smp_cmd.smp_req16[i] = *(preq_dma_addr+i);
3856 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3857 "Byte[%d]:%x (DMA data:%x)\n",
3858 i, smp_cmd.smp_req16[i],
3859 *(preq_dma_addr)));
3860 } else {
3861 smp_cmd.smp_req[i] = *(preq_dma_addr+i);
3862 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3863 "Byte[%d]:%x (DMA data:%x)\n",
3864 i, smp_cmd.smp_req[i],
3865 *(preq_dma_addr)));
3866 }
3867 }
3868
3869 build_smp_cmd(pm8001_dev->device_id, smp_cmd.tag,
3870 &smp_cmd, pm8001_ha->smp_exp_mode, length);
3871 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, (u32 *)&smp_cmd, 0);
3872 return 0;
3873
3874 err_out_2:
3875 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_resp, 1,
3876 PCI_DMA_FROMDEVICE);
3877 err_out:
3878 dma_unmap_sg(pm8001_ha->dev, &ccb->task->smp_task.smp_req, 1,
3879 PCI_DMA_TODEVICE);
3880 return rc;
3881 }
3882
3883 static int check_enc_sas_cmd(struct sas_task *task)
3884 {
3885 u8 cmd = task->ssp_task.cmd->cmnd[0];
3886
3887 if (cmd == READ_10 || cmd == WRITE_10 || cmd == WRITE_VERIFY)
3888 return 1;
3889 else
3890 return 0;
3891 }
3892
3893 static int check_enc_sat_cmd(struct sas_task *task)
3894 {
3895 int ret = 0;
3896 switch (task->ata_task.fis.command) {
3897 case ATA_CMD_FPDMA_READ:
3898 case ATA_CMD_READ_EXT:
3899 case ATA_CMD_READ:
3900 case ATA_CMD_FPDMA_WRITE:
3901 case ATA_CMD_WRITE_EXT:
3902 case ATA_CMD_WRITE:
3903 case ATA_CMD_PIO_READ:
3904 case ATA_CMD_PIO_READ_EXT:
3905 case ATA_CMD_PIO_WRITE:
3906 case ATA_CMD_PIO_WRITE_EXT:
3907 ret = 1;
3908 break;
3909 default:
3910 ret = 0;
3911 break;
3912 }
3913 return ret;
3914 }
3915
3916 /**
3917 * pm80xx_chip_ssp_io_req - send a SSP task to FW
3918 * @pm8001_ha: our hba card information.
3919 * @ccb: the ccb information this request used.
3920 */
3921 static int pm80xx_chip_ssp_io_req(struct pm8001_hba_info *pm8001_ha,
3922 struct pm8001_ccb_info *ccb)
3923 {
3924 struct sas_task *task = ccb->task;
3925 struct domain_device *dev = task->dev;
3926 struct pm8001_device *pm8001_dev = dev->lldd_dev;
3927 struct ssp_ini_io_start_req ssp_cmd;
3928 u32 tag = ccb->ccb_tag;
3929 int ret;
3930 u64 phys_addr, start_addr, end_addr;
3931 u32 end_addr_high, end_addr_low;
3932 struct inbound_queue_table *circularQ;
3933 u32 q_index;
3934 u32 opc = OPC_INB_SSPINIIOSTART;
3935 memset(&ssp_cmd, 0, sizeof(ssp_cmd));
3936 memcpy(ssp_cmd.ssp_iu.lun, task->ssp_task.LUN, 8);
3937 /* data address domain added for spcv; set to 0 by host,
3938 * used internally by controller
3939 * 0 for SAS 1.1 and SAS 2.0 compatible TLR
3940 */
3941 ssp_cmd.dad_dir_m_tlr =
3942 cpu_to_le32(data_dir_flags[task->data_dir] << 8 | 0x0);
3943 ssp_cmd.data_len = cpu_to_le32(task->total_xfer_len);
3944 ssp_cmd.device_id = cpu_to_le32(pm8001_dev->device_id);
3945 ssp_cmd.tag = cpu_to_le32(tag);
3946 if (task->ssp_task.enable_first_burst)
3947 ssp_cmd.ssp_iu.efb_prio_attr |= 0x80;
3948 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_prio << 3);
3949 ssp_cmd.ssp_iu.efb_prio_attr |= (task->ssp_task.task_attr & 7);
3950 memcpy(ssp_cmd.ssp_iu.cdb, task->ssp_task.cmd->cmnd,
3951 task->ssp_task.cmd->cmd_len);
3952 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
3953 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
3954
3955 /* Check if encryption is set */
3956 if (pm8001_ha->chip->encrypt &&
3957 !(pm8001_ha->encrypt_info.status) && check_enc_sas_cmd(task)) {
3958 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
3959 "Encryption enabled.Sending Encrypt SAS command 0x%x\n",
3960 task->ssp_task.cmd->cmnd[0]));
3961 opc = OPC_INB_SSP_INI_DIF_ENC_IO;
3962 /* enable encryption. 0 for SAS 1.1 and SAS 2.0 compatible TLR*/
3963 ssp_cmd.dad_dir_m_tlr = cpu_to_le32
3964 ((data_dir_flags[task->data_dir] << 8) | 0x20 | 0x0);
3965
3966 /* fill in PRD (scatter/gather) table, if any */
3967 if (task->num_scatter > 1) {
3968 pm8001_chip_make_sg(task->scatter,
3969 ccb->n_elem, ccb->buf_prd);
3970 phys_addr = ccb->ccb_dma_handle +
3971 offsetof(struct pm8001_ccb_info, buf_prd[0]);
3972 ssp_cmd.enc_addr_low =
3973 cpu_to_le32(lower_32_bits(phys_addr));
3974 ssp_cmd.enc_addr_high =
3975 cpu_to_le32(upper_32_bits(phys_addr));
3976 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
3977 } else if (task->num_scatter == 1) {
3978 u64 dma_addr = sg_dma_address(task->scatter);
3979 ssp_cmd.enc_addr_low =
3980 cpu_to_le32(lower_32_bits(dma_addr));
3981 ssp_cmd.enc_addr_high =
3982 cpu_to_le32(upper_32_bits(dma_addr));
3983 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
3984 ssp_cmd.enc_esgl = 0;
3985 /* Check 4G Boundary */
3986 start_addr = cpu_to_le64(dma_addr);
3987 end_addr = (start_addr + ssp_cmd.enc_len) - 1;
3988 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
3989 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
3990 if (end_addr_high != ssp_cmd.enc_addr_high) {
3991 PM8001_FAIL_DBG(pm8001_ha,
3992 pm8001_printk("The sg list address "
3993 "start_addr=0x%016llx data_len=0x%x "
3994 "end_addr_high=0x%08x end_addr_low="
3995 "0x%08x has crossed 4G boundary\n",
3996 start_addr, ssp_cmd.enc_len,
3997 end_addr_high, end_addr_low));
3998 pm8001_chip_make_sg(task->scatter, 1,
3999 ccb->buf_prd);
4000 phys_addr = ccb->ccb_dma_handle +
4001 offsetof(struct pm8001_ccb_info,
4002 buf_prd[0]);
4003 ssp_cmd.enc_addr_low =
4004 cpu_to_le32(lower_32_bits(phys_addr));
4005 ssp_cmd.enc_addr_high =
4006 cpu_to_le32(upper_32_bits(phys_addr));
4007 ssp_cmd.enc_esgl = cpu_to_le32(1<<31);
4008 }
4009 } else if (task->num_scatter == 0) {
4010 ssp_cmd.enc_addr_low = 0;
4011 ssp_cmd.enc_addr_high = 0;
4012 ssp_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4013 ssp_cmd.enc_esgl = 0;
4014 }
4015 /* XTS mode. All other fields are 0 */
4016 ssp_cmd.key_cmode = 0x6 << 4;
4017 /* set tweak values. Should be the start lba */
4018 ssp_cmd.twk_val0 = cpu_to_le32((task->ssp_task.cmd->cmnd[2] << 24) |
4019 (task->ssp_task.cmd->cmnd[3] << 16) |
4020 (task->ssp_task.cmd->cmnd[4] << 8) |
4021 (task->ssp_task.cmd->cmnd[5]));
4022 } else {
4023 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4024 "Sending Normal SAS command 0x%x inb q %x\n",
4025 task->ssp_task.cmd->cmnd[0], q_index));
4026 /* fill in PRD (scatter/gather) table, if any */
4027 if (task->num_scatter > 1) {
4028 pm8001_chip_make_sg(task->scatter, ccb->n_elem,
4029 ccb->buf_prd);
4030 phys_addr = ccb->ccb_dma_handle +
4031 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4032 ssp_cmd.addr_low =
4033 cpu_to_le32(lower_32_bits(phys_addr));
4034 ssp_cmd.addr_high =
4035 cpu_to_le32(upper_32_bits(phys_addr));
4036 ssp_cmd.esgl = cpu_to_le32(1<<31);
4037 } else if (task->num_scatter == 1) {
4038 u64 dma_addr = sg_dma_address(task->scatter);
4039 ssp_cmd.addr_low = cpu_to_le32(lower_32_bits(dma_addr));
4040 ssp_cmd.addr_high =
4041 cpu_to_le32(upper_32_bits(dma_addr));
4042 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4043 ssp_cmd.esgl = 0;
4044 /* Check 4G Boundary */
4045 start_addr = cpu_to_le64(dma_addr);
4046 end_addr = (start_addr + ssp_cmd.len) - 1;
4047 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4048 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4049 if (end_addr_high != ssp_cmd.addr_high) {
4050 PM8001_FAIL_DBG(pm8001_ha,
4051 pm8001_printk("The sg list address "
4052 "start_addr=0x%016llx data_len=0x%x "
4053 "end_addr_high=0x%08x end_addr_low="
4054 "0x%08x has crossed 4G boundary\n",
4055 start_addr, ssp_cmd.len,
4056 end_addr_high, end_addr_low));
4057 pm8001_chip_make_sg(task->scatter, 1,
4058 ccb->buf_prd);
4059 phys_addr = ccb->ccb_dma_handle +
4060 offsetof(struct pm8001_ccb_info,
4061 buf_prd[0]);
4062 ssp_cmd.addr_low =
4063 cpu_to_le32(lower_32_bits(phys_addr));
4064 ssp_cmd.addr_high =
4065 cpu_to_le32(upper_32_bits(phys_addr));
4066 ssp_cmd.esgl = cpu_to_le32(1<<31);
4067 }
4068 } else if (task->num_scatter == 0) {
4069 ssp_cmd.addr_low = 0;
4070 ssp_cmd.addr_high = 0;
4071 ssp_cmd.len = cpu_to_le32(task->total_xfer_len);
4072 ssp_cmd.esgl = 0;
4073 }
4074 }
4075 q_index = (u32) (pm8001_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4076 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4077 &ssp_cmd, q_index);
4078 return ret;
4079 }
4080
4081 static int pm80xx_chip_sata_req(struct pm8001_hba_info *pm8001_ha,
4082 struct pm8001_ccb_info *ccb)
4083 {
4084 struct sas_task *task = ccb->task;
4085 struct domain_device *dev = task->dev;
4086 struct pm8001_device *pm8001_ha_dev = dev->lldd_dev;
4087 u32 tag = ccb->ccb_tag;
4088 int ret;
4089 u32 q_index;
4090 struct sata_start_req sata_cmd;
4091 u32 hdr_tag, ncg_tag = 0;
4092 u64 phys_addr, start_addr, end_addr;
4093 u32 end_addr_high, end_addr_low;
4094 u32 ATAP = 0x0;
4095 u32 dir;
4096 struct inbound_queue_table *circularQ;
4097 unsigned long flags;
4098 u32 opc = OPC_INB_SATA_HOST_OPSTART;
4099 memset(&sata_cmd, 0, sizeof(sata_cmd));
4100 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_INB_NUM;
4101 circularQ = &pm8001_ha->inbnd_q_tbl[q_index];
4102
4103 if (task->data_dir == PCI_DMA_NONE) {
4104 ATAP = 0x04; /* no data*/
4105 PM8001_IO_DBG(pm8001_ha, pm8001_printk("no data\n"));
4106 } else if (likely(!task->ata_task.device_control_reg_update)) {
4107 if (task->ata_task.dma_xfer) {
4108 ATAP = 0x06; /* DMA */
4109 PM8001_IO_DBG(pm8001_ha, pm8001_printk("DMA\n"));
4110 } else {
4111 ATAP = 0x05; /* PIO*/
4112 PM8001_IO_DBG(pm8001_ha, pm8001_printk("PIO\n"));
4113 }
4114 if (task->ata_task.use_ncq &&
4115 dev->sata_dev.command_set != ATAPI_COMMAND_SET) {
4116 ATAP = 0x07; /* FPDMA */
4117 PM8001_IO_DBG(pm8001_ha, pm8001_printk("FPDMA\n"));
4118 }
4119 }
4120 if (task->ata_task.use_ncq && pm8001_get_ncq_tag(task, &hdr_tag)) {
4121 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
4122 ncg_tag = hdr_tag;
4123 }
4124 dir = data_dir_flags[task->data_dir] << 8;
4125 sata_cmd.tag = cpu_to_le32(tag);
4126 sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
4127 sata_cmd.data_len = cpu_to_le32(task->total_xfer_len);
4128
4129 sata_cmd.sata_fis = task->ata_task.fis;
4130 if (likely(!task->ata_task.device_control_reg_update))
4131 sata_cmd.sata_fis.flags |= 0x80;/* C=1: update ATA cmd reg */
4132 sata_cmd.sata_fis.flags &= 0xF0;/* PM_PORT field shall be 0 */
4133
4134 /* Check if encryption is set */
4135 if (pm8001_ha->chip->encrypt &&
4136 !(pm8001_ha->encrypt_info.status) && check_enc_sat_cmd(task)) {
4137 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4138 "Encryption enabled.Sending Encrypt SATA cmd 0x%x\n",
4139 sata_cmd.sata_fis.command));
4140 opc = OPC_INB_SATA_DIF_ENC_IO;
4141
4142 /* set encryption bit */
4143 sata_cmd.ncqtag_atap_dir_m_dad =
4144 cpu_to_le32(((ncg_tag & 0xff)<<16)|
4145 ((ATAP & 0x3f) << 10) | 0x20 | dir);
4146 /* dad (bit 0-1) is 0 */
4147 /* fill in PRD (scatter/gather) table, if any */
4148 if (task->num_scatter > 1) {
4149 pm8001_chip_make_sg(task->scatter,
4150 ccb->n_elem, ccb->buf_prd);
4151 phys_addr = ccb->ccb_dma_handle +
4152 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4153 sata_cmd.enc_addr_low = lower_32_bits(phys_addr);
4154 sata_cmd.enc_addr_high = upper_32_bits(phys_addr);
4155 sata_cmd.enc_esgl = cpu_to_le32(1 << 31);
4156 } else if (task->num_scatter == 1) {
4157 u64 dma_addr = sg_dma_address(task->scatter);
4158 sata_cmd.enc_addr_low = lower_32_bits(dma_addr);
4159 sata_cmd.enc_addr_high = upper_32_bits(dma_addr);
4160 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4161 sata_cmd.enc_esgl = 0;
4162 /* Check 4G Boundary */
4163 start_addr = cpu_to_le64(dma_addr);
4164 end_addr = (start_addr + sata_cmd.enc_len) - 1;
4165 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4166 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4167 if (end_addr_high != sata_cmd.enc_addr_high) {
4168 PM8001_FAIL_DBG(pm8001_ha,
4169 pm8001_printk("The sg list address "
4170 "start_addr=0x%016llx data_len=0x%x "
4171 "end_addr_high=0x%08x end_addr_low"
4172 "=0x%08x has crossed 4G boundary\n",
4173 start_addr, sata_cmd.enc_len,
4174 end_addr_high, end_addr_low));
4175 pm8001_chip_make_sg(task->scatter, 1,
4176 ccb->buf_prd);
4177 phys_addr = ccb->ccb_dma_handle +
4178 offsetof(struct pm8001_ccb_info,
4179 buf_prd[0]);
4180 sata_cmd.enc_addr_low =
4181 lower_32_bits(phys_addr);
4182 sata_cmd.enc_addr_high =
4183 upper_32_bits(phys_addr);
4184 sata_cmd.enc_esgl =
4185 cpu_to_le32(1 << 31);
4186 }
4187 } else if (task->num_scatter == 0) {
4188 sata_cmd.enc_addr_low = 0;
4189 sata_cmd.enc_addr_high = 0;
4190 sata_cmd.enc_len = cpu_to_le32(task->total_xfer_len);
4191 sata_cmd.enc_esgl = 0;
4192 }
4193 /* XTS mode. All other fields are 0 */
4194 sata_cmd.key_index_mode = 0x6 << 4;
4195 /* set tweak values. Should be the start lba */
4196 sata_cmd.twk_val0 =
4197 cpu_to_le32((sata_cmd.sata_fis.lbal_exp << 24) |
4198 (sata_cmd.sata_fis.lbah << 16) |
4199 (sata_cmd.sata_fis.lbam << 8) |
4200 (sata_cmd.sata_fis.lbal));
4201 sata_cmd.twk_val1 =
4202 cpu_to_le32((sata_cmd.sata_fis.lbah_exp << 8) |
4203 (sata_cmd.sata_fis.lbam_exp));
4204 } else {
4205 PM8001_IO_DBG(pm8001_ha, pm8001_printk(
4206 "Sending Normal SATA command 0x%x inb %x\n",
4207 sata_cmd.sata_fis.command, q_index));
4208 /* dad (bit 0-1) is 0 */
4209 sata_cmd.ncqtag_atap_dir_m_dad =
4210 cpu_to_le32(((ncg_tag & 0xff)<<16) |
4211 ((ATAP & 0x3f) << 10) | dir);
4212
4213 /* fill in PRD (scatter/gather) table, if any */
4214 if (task->num_scatter > 1) {
4215 pm8001_chip_make_sg(task->scatter,
4216 ccb->n_elem, ccb->buf_prd);
4217 phys_addr = ccb->ccb_dma_handle +
4218 offsetof(struct pm8001_ccb_info, buf_prd[0]);
4219 sata_cmd.addr_low = lower_32_bits(phys_addr);
4220 sata_cmd.addr_high = upper_32_bits(phys_addr);
4221 sata_cmd.esgl = cpu_to_le32(1 << 31);
4222 } else if (task->num_scatter == 1) {
4223 u64 dma_addr = sg_dma_address(task->scatter);
4224 sata_cmd.addr_low = lower_32_bits(dma_addr);
4225 sata_cmd.addr_high = upper_32_bits(dma_addr);
4226 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4227 sata_cmd.esgl = 0;
4228 /* Check 4G Boundary */
4229 start_addr = cpu_to_le64(dma_addr);
4230 end_addr = (start_addr + sata_cmd.len) - 1;
4231 end_addr_low = cpu_to_le32(lower_32_bits(end_addr));
4232 end_addr_high = cpu_to_le32(upper_32_bits(end_addr));
4233 if (end_addr_high != sata_cmd.addr_high) {
4234 PM8001_FAIL_DBG(pm8001_ha,
4235 pm8001_printk("The sg list address "
4236 "start_addr=0x%016llx data_len=0x%x"
4237 "end_addr_high=0x%08x end_addr_low="
4238 "0x%08x has crossed 4G boundary\n",
4239 start_addr, sata_cmd.len,
4240 end_addr_high, end_addr_low));
4241 pm8001_chip_make_sg(task->scatter, 1,
4242 ccb->buf_prd);
4243 phys_addr = ccb->ccb_dma_handle +
4244 offsetof(struct pm8001_ccb_info,
4245 buf_prd[0]);
4246 sata_cmd.addr_low =
4247 lower_32_bits(phys_addr);
4248 sata_cmd.addr_high =
4249 upper_32_bits(phys_addr);
4250 sata_cmd.esgl = cpu_to_le32(1 << 31);
4251 }
4252 } else if (task->num_scatter == 0) {
4253 sata_cmd.addr_low = 0;
4254 sata_cmd.addr_high = 0;
4255 sata_cmd.len = cpu_to_le32(task->total_xfer_len);
4256 sata_cmd.esgl = 0;
4257 }
4258 /* scsi cdb */
4259 sata_cmd.atapi_scsi_cdb[0] =
4260 cpu_to_le32(((task->ata_task.atapi_packet[0]) |
4261 (task->ata_task.atapi_packet[1] << 8) |
4262 (task->ata_task.atapi_packet[2] << 16) |
4263 (task->ata_task.atapi_packet[3] << 24)));
4264 sata_cmd.atapi_scsi_cdb[1] =
4265 cpu_to_le32(((task->ata_task.atapi_packet[4]) |
4266 (task->ata_task.atapi_packet[5] << 8) |
4267 (task->ata_task.atapi_packet[6] << 16) |
4268 (task->ata_task.atapi_packet[7] << 24)));
4269 sata_cmd.atapi_scsi_cdb[2] =
4270 cpu_to_le32(((task->ata_task.atapi_packet[8]) |
4271 (task->ata_task.atapi_packet[9] << 8) |
4272 (task->ata_task.atapi_packet[10] << 16) |
4273 (task->ata_task.atapi_packet[11] << 24)));
4274 sata_cmd.atapi_scsi_cdb[3] =
4275 cpu_to_le32(((task->ata_task.atapi_packet[12]) |
4276 (task->ata_task.atapi_packet[13] << 8) |
4277 (task->ata_task.atapi_packet[14] << 16) |
4278 (task->ata_task.atapi_packet[15] << 24)));
4279 }
4280
4281 /* Check for read log for failed drive and return */
4282 if (sata_cmd.sata_fis.command == 0x2f) {
4283 if (pm8001_ha_dev && ((pm8001_ha_dev->id & NCQ_READ_LOG_FLAG) ||
4284 (pm8001_ha_dev->id & NCQ_ABORT_ALL_FLAG) ||
4285 (pm8001_ha_dev->id & NCQ_2ND_RLE_FLAG))) {
4286 struct task_status_struct *ts;
4287
4288 pm8001_ha_dev->id &= 0xDFFFFFFF;
4289 ts = &task->task_status;
4290
4291 spin_lock_irqsave(&task->task_state_lock, flags);
4292 ts->resp = SAS_TASK_COMPLETE;
4293 ts->stat = SAM_STAT_GOOD;
4294 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
4295 task->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
4296 task->task_state_flags |= SAS_TASK_STATE_DONE;
4297 if (unlikely((task->task_state_flags &
4298 SAS_TASK_STATE_ABORTED))) {
4299 spin_unlock_irqrestore(&task->task_state_lock,
4300 flags);
4301 PM8001_FAIL_DBG(pm8001_ha,
4302 pm8001_printk("task 0x%p resp 0x%x "
4303 " stat 0x%x but aborted by upper layer "
4304 "\n", task, ts->resp, ts->stat));
4305 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4306 return 0;
4307 } else if (task->uldd_task) {
4308 spin_unlock_irqrestore(&task->task_state_lock,
4309 flags);
4310 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4311 mb();/* ditto */
4312 spin_unlock_irq(&pm8001_ha->lock);
4313 task->task_done(task);
4314 spin_lock_irq(&pm8001_ha->lock);
4315 return 0;
4316 } else if (!task->uldd_task) {
4317 spin_unlock_irqrestore(&task->task_state_lock,
4318 flags);
4319 pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
4320 mb();/*ditto*/
4321 spin_unlock_irq(&pm8001_ha->lock);
4322 task->task_done(task);
4323 spin_lock_irq(&pm8001_ha->lock);
4324 return 0;
4325 }
4326 }
4327 }
4328 q_index = (u32) (pm8001_ha_dev->id & 0x00ffffff) % PM8001_MAX_OUTB_NUM;
4329 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc,
4330 &sata_cmd, q_index);
4331 return ret;
4332 }
4333
4334 /**
4335 * pm80xx_chip_phy_start_req - start phy via PHY_START COMMAND
4336 * @pm8001_ha: our hba card information.
4337 * @num: the inbound queue number
4338 * @phy_id: the phy id which we wanted to start up.
4339 */
4340 static int
4341 pm80xx_chip_phy_start_req(struct pm8001_hba_info *pm8001_ha, u8 phy_id)
4342 {
4343 struct phy_start_req payload;
4344 struct inbound_queue_table *circularQ;
4345 int ret;
4346 u32 tag = 0x01;
4347 u32 opcode = OPC_INB_PHYSTART;
4348 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4349 memset(&payload, 0, sizeof(payload));
4350 payload.tag = cpu_to_le32(tag);
4351
4352 PM8001_INIT_DBG(pm8001_ha,
4353 pm8001_printk("PHY START REQ for phy_id %d\n", phy_id));
4354 /*
4355 ** [0:7] PHY Identifier
4356 ** [8:11] link rate 1.5G, 3G, 6G
4357 ** [12:13] link mode 01b SAS mode; 10b SATA mode; 11b Auto mode
4358 ** [14] 0b disable spin up hold; 1b enable spin up hold
4359 ** [15] ob no change in current PHY analig setup 1b enable using SPAST
4360 */
4361 if (!IS_SPCV_12G(pm8001_ha->pdev))
4362 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4363 LINKMODE_AUTO | LINKRATE_15 |
4364 LINKRATE_30 | LINKRATE_60 | phy_id);
4365 else
4366 payload.ase_sh_lm_slr_phyid = cpu_to_le32(SPINHOLD_DISABLE |
4367 LINKMODE_AUTO | LINKRATE_15 |
4368 LINKRATE_30 | LINKRATE_60 | LINKRATE_120 |
4369 phy_id);
4370
4371 /* SSC Disable and SAS Analog ST configuration */
4372 /**
4373 payload.ase_sh_lm_slr_phyid =
4374 cpu_to_le32(SSC_DISABLE_30 | SAS_ASE | SPINHOLD_DISABLE |
4375 LINKMODE_AUTO | LINKRATE_15 | LINKRATE_30 | LINKRATE_60 |
4376 phy_id);
4377 Have to add "SAS PHY Analog Setup SPASTI 1 Byte" Based on need
4378 **/
4379
4380 payload.sas_identify.dev_type = SAS_END_DEVICE;
4381 payload.sas_identify.initiator_bits = SAS_PROTOCOL_ALL;
4382 memcpy(payload.sas_identify.sas_addr,
4383 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
4384 payload.sas_identify.phy_id = phy_id;
4385 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4386 return ret;
4387 }
4388
4389 /**
4390 * pm8001_chip_phy_stop_req - start phy via PHY_STOP COMMAND
4391 * @pm8001_ha: our hba card information.
4392 * @num: the inbound queue number
4393 * @phy_id: the phy id which we wanted to start up.
4394 */
4395 static int pm80xx_chip_phy_stop_req(struct pm8001_hba_info *pm8001_ha,
4396 u8 phy_id)
4397 {
4398 struct phy_stop_req payload;
4399 struct inbound_queue_table *circularQ;
4400 int ret;
4401 u32 tag = 0x01;
4402 u32 opcode = OPC_INB_PHYSTOP;
4403 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4404 memset(&payload, 0, sizeof(payload));
4405 payload.tag = cpu_to_le32(tag);
4406 payload.phy_id = cpu_to_le32(phy_id);
4407 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opcode, &payload, 0);
4408 return ret;
4409 }
4410
4411 /**
4412 * see comments on pm8001_mpi_reg_resp.
4413 */
4414 static int pm80xx_chip_reg_dev_req(struct pm8001_hba_info *pm8001_ha,
4415 struct pm8001_device *pm8001_dev, u32 flag)
4416 {
4417 struct reg_dev_req payload;
4418 u32 opc;
4419 u32 stp_sspsmp_sata = 0x4;
4420 struct inbound_queue_table *circularQ;
4421 u32 linkrate, phy_id;
4422 int rc, tag = 0xdeadbeef;
4423 struct pm8001_ccb_info *ccb;
4424 u8 retryFlag = 0x1;
4425 u16 firstBurstSize = 0;
4426 u16 ITNT = 2000;
4427 struct domain_device *dev = pm8001_dev->sas_device;
4428 struct domain_device *parent_dev = dev->parent;
4429 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4430
4431 memset(&payload, 0, sizeof(payload));
4432 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4433 if (rc)
4434 return rc;
4435 ccb = &pm8001_ha->ccb_info[tag];
4436 ccb->device = pm8001_dev;
4437 ccb->ccb_tag = tag;
4438 payload.tag = cpu_to_le32(tag);
4439
4440 if (flag == 1) {
4441 stp_sspsmp_sata = 0x02; /*direct attached sata */
4442 } else {
4443 if (pm8001_dev->dev_type == SAS_SATA_DEV)
4444 stp_sspsmp_sata = 0x00; /* stp*/
4445 else if (pm8001_dev->dev_type == SAS_END_DEVICE ||
4446 pm8001_dev->dev_type == SAS_EDGE_EXPANDER_DEVICE ||
4447 pm8001_dev->dev_type == SAS_FANOUT_EXPANDER_DEVICE)
4448 stp_sspsmp_sata = 0x01; /*ssp or smp*/
4449 }
4450 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
4451 phy_id = parent_dev->ex_dev.ex_phy->phy_id;
4452 else
4453 phy_id = pm8001_dev->attached_phy;
4454
4455 opc = OPC_INB_REG_DEV;
4456
4457 linkrate = (pm8001_dev->sas_device->linkrate < dev->port->linkrate) ?
4458 pm8001_dev->sas_device->linkrate : dev->port->linkrate;
4459
4460 payload.phyid_portid =
4461 cpu_to_le32(((pm8001_dev->sas_device->port->id) & 0xFF) |
4462 ((phy_id & 0xFF) << 8));
4463
4464 payload.dtype_dlr_mcn_ir_retry = cpu_to_le32((retryFlag & 0x01) |
4465 ((linkrate & 0x0F) << 24) |
4466 ((stp_sspsmp_sata & 0x03) << 28));
4467 payload.firstburstsize_ITNexustimeout =
4468 cpu_to_le32(ITNT | (firstBurstSize * 0x10000));
4469
4470 memcpy(payload.sas_addr, pm8001_dev->sas_device->sas_addr,
4471 SAS_ADDR_SIZE);
4472
4473 rc = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4474
4475 return rc;
4476 }
4477
4478 /**
4479 * pm80xx_chip_phy_ctl_req - support the local phy operation
4480 * @pm8001_ha: our hba card information.
4481 * @num: the inbound queue number
4482 * @phy_id: the phy id which we wanted to operate
4483 * @phy_op:
4484 */
4485 static int pm80xx_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
4486 u32 phyId, u32 phy_op)
4487 {
4488 struct local_phy_ctl_req payload;
4489 struct inbound_queue_table *circularQ;
4490 int ret;
4491 u32 opc = OPC_INB_LOCAL_PHY_CONTROL;
4492 memset(&payload, 0, sizeof(payload));
4493 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4494 payload.tag = cpu_to_le32(1);
4495 payload.phyop_phyid =
4496 cpu_to_le32(((phy_op & 0xFF) << 8) | (phyId & 0xFF));
4497 ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4498 return ret;
4499 }
4500
4501 static u32 pm80xx_chip_is_our_interupt(struct pm8001_hba_info *pm8001_ha)
4502 {
4503 u32 value;
4504 #ifdef PM8001_USE_MSIX
4505 return 1;
4506 #endif
4507 value = pm8001_cr32(pm8001_ha, 0, MSGU_ODR);
4508 if (value)
4509 return 1;
4510 return 0;
4511
4512 }
4513
4514 /**
4515 * pm8001_chip_isr - PM8001 isr handler.
4516 * @pm8001_ha: our hba card information.
4517 * @irq: irq number.
4518 * @stat: stat.
4519 */
4520 static irqreturn_t
4521 pm80xx_chip_isr(struct pm8001_hba_info *pm8001_ha, u8 vec)
4522 {
4523 pm80xx_chip_interrupt_disable(pm8001_ha, vec);
4524 process_oq(pm8001_ha, vec);
4525 pm80xx_chip_interrupt_enable(pm8001_ha, vec);
4526 return IRQ_HANDLED;
4527 }
4528
4529 void mpi_set_phy_profile_req(struct pm8001_hba_info *pm8001_ha,
4530 u32 operation, u32 phyid, u32 length, u32 *buf)
4531 {
4532 u32 tag , i, j = 0;
4533 int rc;
4534 struct set_phy_profile_req payload;
4535 struct inbound_queue_table *circularQ;
4536 u32 opc = OPC_INB_SET_PHY_PROFILE;
4537
4538 memset(&payload, 0, sizeof(payload));
4539 rc = pm8001_tag_alloc(pm8001_ha, &tag);
4540 if (rc)
4541 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk("Invalid tag\n"));
4542 circularQ = &pm8001_ha->inbnd_q_tbl[0];
4543 payload.tag = cpu_to_le32(tag);
4544 payload.ppc_phyid = (((operation & 0xF) << 8) | (phyid & 0xFF));
4545 PM8001_INIT_DBG(pm8001_ha,
4546 pm8001_printk(" phy profile command for phy %x ,length is %d\n",
4547 payload.ppc_phyid, length));
4548 for (i = length; i < (length + PHY_DWORD_LENGTH - 1); i++) {
4549 payload.reserved[j] = cpu_to_le32(*((u32 *)buf + i));
4550 j++;
4551 }
4552 pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload, 0);
4553 }
4554
4555 void pm8001_set_phy_profile(struct pm8001_hba_info *pm8001_ha,
4556 u32 length, u8 *buf)
4557 {
4558 u32 page_code, i;
4559
4560 page_code = SAS_PHY_ANALOG_SETTINGS_PAGE;
4561 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
4562 mpi_set_phy_profile_req(pm8001_ha,
4563 SAS_PHY_ANALOG_SETTINGS_PAGE, i, length, (u32 *)buf);
4564 length = length + PHY_DWORD_LENGTH;
4565 }
4566 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("phy settings completed\n"));
4567 }
4568 const struct pm8001_dispatch pm8001_80xx_dispatch = {
4569 .name = "pmc80xx",
4570 .chip_init = pm80xx_chip_init,
4571 .chip_soft_rst = pm80xx_chip_soft_rst,
4572 .chip_rst = pm80xx_hw_chip_rst,
4573 .chip_iounmap = pm8001_chip_iounmap,
4574 .isr = pm80xx_chip_isr,
4575 .is_our_interupt = pm80xx_chip_is_our_interupt,
4576 .isr_process_oq = process_oq,
4577 .interrupt_enable = pm80xx_chip_interrupt_enable,
4578 .interrupt_disable = pm80xx_chip_interrupt_disable,
4579 .make_prd = pm8001_chip_make_sg,
4580 .smp_req = pm80xx_chip_smp_req,
4581 .ssp_io_req = pm80xx_chip_ssp_io_req,
4582 .sata_req = pm80xx_chip_sata_req,
4583 .phy_start_req = pm80xx_chip_phy_start_req,
4584 .phy_stop_req = pm80xx_chip_phy_stop_req,
4585 .reg_dev_req = pm80xx_chip_reg_dev_req,
4586 .dereg_dev_req = pm8001_chip_dereg_dev_req,
4587 .phy_ctl_req = pm80xx_chip_phy_ctl_req,
4588 .task_abort = pm8001_chip_abort_task,
4589 .ssp_tm_req = pm8001_chip_ssp_tm_req,
4590 .get_nvmd_req = pm8001_chip_get_nvmd_req,
4591 .set_nvmd_req = pm8001_chip_set_nvmd_req,
4592 .fw_flash_update_req = pm8001_chip_fw_flash_update_req,
4593 .set_dev_state_req = pm8001_chip_set_dev_state_req,
4594 };
Linux with added FPC-III support