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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / scsi / qla4xxx / ql4_mbx.c
blob9ae8ca3b69f937ddfaf4527d97f6625c6ad2a4b6
1 /*
2 * QLogic iSCSI HBA Driver
3 * Copyright (c) 2003-2013 QLogic Corporation
4 *
5 * See LICENSE.qla4xxx for copyright and licensing details.
6 */
7
8 #include <linux/ctype.h>
9 #include "ql4_def.h"
10 #include "ql4_glbl.h"
11 #include "ql4_dbg.h"
12 #include "ql4_inline.h"
13 #include "ql4_version.h"
14
15 void qla4xxx_queue_mbox_cmd(struct scsi_qla_host *ha, uint32_t *mbx_cmd,
16 int in_count)
17 {
18 int i;
19
20 /* Load all mailbox registers, except mailbox 0. */
21 for (i = 1; i < in_count; i++)
22 writel(mbx_cmd[i], &ha->reg->mailbox[i]);
23
24 /* Wakeup firmware */
25 writel(mbx_cmd[0], &ha->reg->mailbox[0]);
26 readl(&ha->reg->mailbox[0]);
27 writel(set_rmask(CSR_INTR_RISC), &ha->reg->ctrl_status);
28 readl(&ha->reg->ctrl_status);
29 }
30
31 void qla4xxx_process_mbox_intr(struct scsi_qla_host *ha, int out_count)
32 {
33 int intr_status;
34
35 intr_status = readl(&ha->reg->ctrl_status);
36 if (intr_status & INTR_PENDING) {
37 /*
38 * Service the interrupt.
39 * The ISR will save the mailbox status registers
40 * to a temporary storage location in the adapter structure.
41 */
42 ha->mbox_status_count = out_count;
43 ha->isp_ops->interrupt_service_routine(ha, intr_status);
44 }
45 }
46
47 /**
48 * qla4xxx_is_intr_poll_mode – Are we allowed to poll for interrupts?
49 * @ha: Pointer to host adapter structure.
50 * @ret: 1=polling mode, 0=non-polling mode
51 **/
52 static int qla4xxx_is_intr_poll_mode(struct scsi_qla_host *ha)
53 {
54 int rval = 1;
55
56 if (is_qla8032(ha) || is_qla8042(ha)) {
57 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
58 test_bit(AF_83XX_MBOX_INTR_ON, &ha->flags))
59 rval = 0;
60 } else {
61 if (test_bit(AF_IRQ_ATTACHED, &ha->flags) &&
62 test_bit(AF_INTERRUPTS_ON, &ha->flags) &&
63 test_bit(AF_ONLINE, &ha->flags) &&
64 !test_bit(AF_HA_REMOVAL, &ha->flags))
65 rval = 0;
66 }
67
68 return rval;
69 }
70
71 /**
72 * qla4xxx_mailbox_command - issues mailbox commands
73 * @ha: Pointer to host adapter structure.
74 * @inCount: number of mailbox registers to load.
75 * @outCount: number of mailbox registers to return.
76 * @mbx_cmd: data pointer for mailbox in registers.
77 * @mbx_sts: data pointer for mailbox out registers.
78 *
79 * This routine issue mailbox commands and waits for completion.
80 * If outCount is 0, this routine completes successfully WITHOUT waiting
81 * for the mailbox command to complete.
82 **/
83 int qla4xxx_mailbox_command(struct scsi_qla_host *ha, uint8_t inCount,
84 uint8_t outCount, uint32_t *mbx_cmd,
85 uint32_t *mbx_sts)
86 {
87 int status = QLA_ERROR;
88 uint8_t i;
89 u_long wait_count;
90 unsigned long flags = 0;
91 uint32_t dev_state;
92
93 /* Make sure that pointers are valid */
94 if (!mbx_cmd || !mbx_sts) {
95 DEBUG2(printk("scsi%ld: %s: Invalid mbx_cmd or mbx_sts "
96 "pointer\n", ha->host_no, __func__));
97 return status;
98 }
99
100 if (is_qla40XX(ha)) {
101 if (test_bit(AF_HA_REMOVAL, &ha->flags)) {
102 DEBUG2(ql4_printk(KERN_WARNING, ha, "scsi%ld: %s: "
103 "prematurely completing mbx cmd as "
104 "adapter removal detected\n",
105 ha->host_no, __func__));
106 return status;
107 }
108 }
109
110 if ((is_aer_supported(ha)) &&
111 (test_bit(AF_PCI_CHANNEL_IO_PERM_FAILURE, &ha->flags))) {
112 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: Perm failure on EEH, "
113 "timeout MBX Exiting.\n", ha->host_no, __func__));
114 return status;
115 }
116
117 /* Mailbox code active */
118 wait_count = MBOX_TOV * 100;
119
120 while (wait_count--) {
121 mutex_lock(&ha->mbox_sem);
122 if (!test_bit(AF_MBOX_COMMAND, &ha->flags)) {
123 set_bit(AF_MBOX_COMMAND, &ha->flags);
124 mutex_unlock(&ha->mbox_sem);
125 break;
126 }
127 mutex_unlock(&ha->mbox_sem);
128 if (!wait_count) {
129 DEBUG2(printk("scsi%ld: %s: mbox_sem failed\n",
130 ha->host_no, __func__));
131 return status;
132 }
133 msleep(10);
134 }
135
136 if (is_qla80XX(ha)) {
137 if (test_bit(AF_FW_RECOVERY, &ha->flags)) {
138 DEBUG2(ql4_printk(KERN_WARNING, ha,
139 "scsi%ld: %s: prematurely completing mbx cmd as firmware recovery detected\n",
140 ha->host_no, __func__));
141 goto mbox_exit;
142 }
143 /* Do not send any mbx cmd if h/w is in failed state*/
144 ha->isp_ops->idc_lock(ha);
145 dev_state = qla4_8xxx_rd_direct(ha, QLA8XXX_CRB_DEV_STATE);
146 ha->isp_ops->idc_unlock(ha);
147 if (dev_state == QLA8XXX_DEV_FAILED) {
148 ql4_printk(KERN_WARNING, ha,
149 "scsi%ld: %s: H/W is in failed state, do not send any mailbox commands\n",
150 ha->host_no, __func__);
151 goto mbox_exit;
152 }
153 }
154
155 spin_lock_irqsave(&ha->hardware_lock, flags);
156
157 ha->mbox_status_count = outCount;
158 for (i = 0; i < outCount; i++)
159 ha->mbox_status[i] = 0;
160
161 /* Queue the mailbox command to the firmware */
162 ha->isp_ops->queue_mailbox_command(ha, mbx_cmd, inCount);
163
164 spin_unlock_irqrestore(&ha->hardware_lock, flags);
165
166 /* Wait for completion */
167
168 /*
169 * If we don't want status, don't wait for the mailbox command to
170 * complete. For example, MBOX_CMD_RESET_FW doesn't return status,
171 * you must poll the inbound Interrupt Mask for completion.
172 */
173 if (outCount == 0) {
174 status = QLA_SUCCESS;
175 goto mbox_exit;
176 }
177
178 /*
179 * Wait for completion: Poll or completion queue
180 */
181 if (qla4xxx_is_intr_poll_mode(ha)) {
182 /* Poll for command to complete */
183 wait_count = jiffies + MBOX_TOV * HZ;
184 while (test_bit(AF_MBOX_COMMAND_DONE, &ha->flags) == 0) {
185 if (time_after_eq(jiffies, wait_count))
186 break;
187 /*
188 * Service the interrupt.
189 * The ISR will save the mailbox status registers
190 * to a temporary storage location in the adapter
191 * structure.
192 */
193 spin_lock_irqsave(&ha->hardware_lock, flags);
194 ha->isp_ops->process_mailbox_interrupt(ha, outCount);
195 spin_unlock_irqrestore(&ha->hardware_lock, flags);
196 msleep(10);
197 }
198 } else {
199 /* Do not poll for completion. Use completion queue */
200 set_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
201 wait_for_completion_timeout(&ha->mbx_intr_comp, MBOX_TOV * HZ);
202 clear_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags);
203 }
204
205 /* Check for mailbox timeout. */
206 if (!test_bit(AF_MBOX_COMMAND_DONE, &ha->flags)) {
207 if (is_qla80XX(ha) &&
208 test_bit(AF_FW_RECOVERY, &ha->flags)) {
209 DEBUG2(ql4_printk(KERN_INFO, ha,
210 "scsi%ld: %s: prematurely completing mbx cmd as "
211 "firmware recovery detected\n",
212 ha->host_no, __func__));
213 goto mbox_exit;
214 }
215 DEBUG2(printk("scsi%ld: Mailbox Cmd 0x%08X timed out ...,"
216 " Scheduling Adapter Reset\n", ha->host_no,
217 mbx_cmd[0]));
218 ha->mailbox_timeout_count++;
219 mbx_sts[0] = (-1);
220 set_bit(DPC_RESET_HA, &ha->dpc_flags);
221 if (is_qla8022(ha)) {
222 ql4_printk(KERN_INFO, ha,
223 "disabling pause transmit on port 0 & 1.\n");
224 qla4_82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
225 CRB_NIU_XG_PAUSE_CTL_P0 |
226 CRB_NIU_XG_PAUSE_CTL_P1);
227 } else if (is_qla8032(ha) || is_qla8042(ha)) {
228 ql4_printk(KERN_INFO, ha, " %s: disabling pause transmit on port 0 & 1.\n",
229 __func__);
230 qla4_83xx_disable_pause(ha);
231 }
232 goto mbox_exit;
233 }
234
235 /*
236 * Copy the mailbox out registers to the caller's mailbox in/out
237 * structure.
238 */
239 spin_lock_irqsave(&ha->hardware_lock, flags);
240 for (i = 0; i < outCount; i++)
241 mbx_sts[i] = ha->mbox_status[i];
242
243 /* Set return status and error flags (if applicable). */
244 switch (ha->mbox_status[0]) {
245 case MBOX_STS_COMMAND_COMPLETE:
246 status = QLA_SUCCESS;
247 break;
248
249 case MBOX_STS_INTERMEDIATE_COMPLETION:
250 status = QLA_SUCCESS;
251 break;
252
253 case MBOX_STS_BUSY:
254 DEBUG2( printk("scsi%ld: %s: Cmd = %08X, ISP BUSY\n",
255 ha->host_no, __func__, mbx_cmd[0]));
256 ha->mailbox_timeout_count++;
257 break;
258
259 default:
260 DEBUG2(printk("scsi%ld: %s: **** FAILED, cmd = %08X, "
261 "sts = %08X ****\n", ha->host_no, __func__,
262 mbx_cmd[0], mbx_sts[0]));
263 break;
264 }
265 spin_unlock_irqrestore(&ha->hardware_lock, flags);
266
267 mbox_exit:
268 mutex_lock(&ha->mbox_sem);
269 clear_bit(AF_MBOX_COMMAND, &ha->flags);
270 mutex_unlock(&ha->mbox_sem);
271 clear_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
272
273 return status;
274 }
275
276 /**
277 * qla4xxx_get_minidump_template - Get the firmware template
278 * @ha: Pointer to host adapter structure.
279 * @phys_addr: dma address for template
280 *
281 * Obtain the minidump template from firmware during initialization
282 * as it may not be available when minidump is desired.
283 **/
284 int qla4xxx_get_minidump_template(struct scsi_qla_host *ha,
285 dma_addr_t phys_addr)
286 {
287 uint32_t mbox_cmd[MBOX_REG_COUNT];
288 uint32_t mbox_sts[MBOX_REG_COUNT];
289 int status;
290
291 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
292 memset(&mbox_sts, 0, sizeof(mbox_sts));
293
294 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
295 mbox_cmd[1] = MINIDUMP_GET_TMPLT_SUBCOMMAND;
296 mbox_cmd[2] = LSDW(phys_addr);
297 mbox_cmd[3] = MSDW(phys_addr);
298 mbox_cmd[4] = ha->fw_dump_tmplt_size;
299 mbox_cmd[5] = 0;
300
301 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
302 &mbox_sts[0]);
303 if (status != QLA_SUCCESS) {
304 DEBUG2(ql4_printk(KERN_INFO, ha,
305 "scsi%ld: %s: Cmd = %08X, mbx[0] = 0x%04x, mbx[1] = 0x%04x\n",
306 ha->host_no, __func__, mbox_cmd[0],
307 mbox_sts[0], mbox_sts[1]));
308 }
309 return status;
310 }
311
312 /**
313 * qla4xxx_req_template_size - Get minidump template size from firmware.
314 * @ha: Pointer to host adapter structure.
315 **/
316 int qla4xxx_req_template_size(struct scsi_qla_host *ha)
317 {
318 uint32_t mbox_cmd[MBOX_REG_COUNT];
319 uint32_t mbox_sts[MBOX_REG_COUNT];
320 int status;
321
322 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
323 memset(&mbox_sts, 0, sizeof(mbox_sts));
324
325 mbox_cmd[0] = MBOX_CMD_MINIDUMP;
326 mbox_cmd[1] = MINIDUMP_GET_SIZE_SUBCOMMAND;
327
328 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 8, &mbox_cmd[0],
329 &mbox_sts[0]);
330 if (status == QLA_SUCCESS) {
331 ha->fw_dump_tmplt_size = mbox_sts[1];
332 DEBUG2(ql4_printk(KERN_INFO, ha,
333 "%s: sts[0]=0x%04x, template size=0x%04x, size_cm_02=0x%04x, size_cm_04=0x%04x, size_cm_08=0x%04x, size_cm_10=0x%04x, size_cm_FF=0x%04x, version=0x%04x\n",
334 __func__, mbox_sts[0], mbox_sts[1],
335 mbox_sts[2], mbox_sts[3], mbox_sts[4],
336 mbox_sts[5], mbox_sts[6], mbox_sts[7]));
337 if (ha->fw_dump_tmplt_size == 0)
338 status = QLA_ERROR;
339 } else {
340 ql4_printk(KERN_WARNING, ha,
341 "%s: Error sts[0]=0x%04x, mbx[1]=0x%04x\n",
342 __func__, mbox_sts[0], mbox_sts[1]);
343 status = QLA_ERROR;
344 }
345
346 return status;
347 }
348
349 void qla4xxx_mailbox_premature_completion(struct scsi_qla_host *ha)
350 {
351 set_bit(AF_FW_RECOVERY, &ha->flags);
352 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: set FW RECOVERY!\n",
353 ha->host_no, __func__);
354
355 if (test_bit(AF_MBOX_COMMAND, &ha->flags)) {
356 if (test_bit(AF_MBOX_COMMAND_NOPOLL, &ha->flags)) {
357 complete(&ha->mbx_intr_comp);
358 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
359 "recovery, doing premature completion of "
360 "mbx cmd\n", ha->host_no, __func__);
361
362 } else {
363 set_bit(AF_MBOX_COMMAND_DONE, &ha->flags);
364 ql4_printk(KERN_INFO, ha, "scsi%ld: %s: Due to fw "
365 "recovery, doing premature completion of "
366 "polling mbx cmd\n", ha->host_no, __func__);
367 }
368 }
369 }
370
371 static uint8_t
372 qla4xxx_set_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
373 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
374 {
375 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
376 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
377
378 if (is_qla8022(ha))
379 qla4_82xx_wr_32(ha, ha->nx_db_wr_ptr, 0);
380
381 mbox_cmd[0] = MBOX_CMD_INITIALIZE_FIRMWARE;
382 mbox_cmd[1] = 0;
383 mbox_cmd[2] = LSDW(init_fw_cb_dma);
384 mbox_cmd[3] = MSDW(init_fw_cb_dma);
385 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
386 mbox_cmd[5] = (IFCB_VER_MAX << 8) | IFCB_VER_MIN;
387
388 if (qla4xxx_mailbox_command(ha, 6, 6, mbox_cmd, mbox_sts) !=
389 QLA_SUCCESS) {
390 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
391 "MBOX_CMD_INITIALIZE_FIRMWARE"
392 " failed w/ status %04X\n",
393 ha->host_no, __func__, mbox_sts[0]));
394 return QLA_ERROR;
395 }
396 return QLA_SUCCESS;
397 }
398
399 uint8_t
400 qla4xxx_get_ifcb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
401 uint32_t *mbox_sts, dma_addr_t init_fw_cb_dma)
402 {
403 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
404 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
405 mbox_cmd[0] = MBOX_CMD_GET_INIT_FW_CTRL_BLOCK;
406 mbox_cmd[2] = LSDW(init_fw_cb_dma);
407 mbox_cmd[3] = MSDW(init_fw_cb_dma);
408 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
409
410 if (qla4xxx_mailbox_command(ha, 5, 5, mbox_cmd, mbox_sts) !=
411 QLA_SUCCESS) {
412 DEBUG2(printk(KERN_WARNING "scsi%ld: %s: "
413 "MBOX_CMD_GET_INIT_FW_CTRL_BLOCK"
414 " failed w/ status %04X\n",
415 ha->host_no, __func__, mbox_sts[0]));
416 return QLA_ERROR;
417 }
418 return QLA_SUCCESS;
419 }
420
421 uint8_t qla4xxx_set_ipaddr_state(uint8_t fw_ipaddr_state)
422 {
423 uint8_t ipaddr_state;
424
425 switch (fw_ipaddr_state) {
426 case IP_ADDRSTATE_UNCONFIGURED:
427 ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
428 break;
429 case IP_ADDRSTATE_INVALID:
430 ipaddr_state = ISCSI_IPDDRESS_STATE_INVALID;
431 break;
432 case IP_ADDRSTATE_ACQUIRING:
433 ipaddr_state = ISCSI_IPDDRESS_STATE_ACQUIRING;
434 break;
435 case IP_ADDRSTATE_TENTATIVE:
436 ipaddr_state = ISCSI_IPDDRESS_STATE_TENTATIVE;
437 break;
438 case IP_ADDRSTATE_DEPRICATED:
439 ipaddr_state = ISCSI_IPDDRESS_STATE_DEPRECATED;
440 break;
441 case IP_ADDRSTATE_PREFERRED:
442 ipaddr_state = ISCSI_IPDDRESS_STATE_VALID;
443 break;
444 case IP_ADDRSTATE_DISABLING:
445 ipaddr_state = ISCSI_IPDDRESS_STATE_DISABLING;
446 break;
447 default:
448 ipaddr_state = ISCSI_IPDDRESS_STATE_UNCONFIGURED;
449 }
450 return ipaddr_state;
451 }
452
453 static void
454 qla4xxx_update_local_ip(struct scsi_qla_host *ha,
455 struct addr_ctrl_blk *init_fw_cb)
456 {
457 ha->ip_config.tcp_options = le16_to_cpu(init_fw_cb->ipv4_tcp_opts);
458 ha->ip_config.ipv4_options = le16_to_cpu(init_fw_cb->ipv4_ip_opts);
459 ha->ip_config.ipv4_addr_state =
460 qla4xxx_set_ipaddr_state(init_fw_cb->ipv4_addr_state);
461 ha->ip_config.eth_mtu_size =
462 le16_to_cpu(init_fw_cb->eth_mtu_size);
463 ha->ip_config.ipv4_port = le16_to_cpu(init_fw_cb->ipv4_port);
464
465 if (ha->acb_version == ACB_SUPPORTED) {
466 ha->ip_config.ipv6_options = le16_to_cpu(init_fw_cb->ipv6_opts);
467 ha->ip_config.ipv6_addl_options =
468 le16_to_cpu(init_fw_cb->ipv6_addtl_opts);
469 ha->ip_config.ipv6_tcp_options =
470 le16_to_cpu(init_fw_cb->ipv6_tcp_opts);
471 }
472
473 /* Save IPv4 Address Info */
474 memcpy(ha->ip_config.ip_address, init_fw_cb->ipv4_addr,
475 min(sizeof(ha->ip_config.ip_address),
476 sizeof(init_fw_cb->ipv4_addr)));
477 memcpy(ha->ip_config.subnet_mask, init_fw_cb->ipv4_subnet,
478 min(sizeof(ha->ip_config.subnet_mask),
479 sizeof(init_fw_cb->ipv4_subnet)));
480 memcpy(ha->ip_config.gateway, init_fw_cb->ipv4_gw_addr,
481 min(sizeof(ha->ip_config.gateway),
482 sizeof(init_fw_cb->ipv4_gw_addr)));
483
484 ha->ip_config.ipv4_vlan_tag = be16_to_cpu(init_fw_cb->ipv4_vlan_tag);
485 ha->ip_config.control = init_fw_cb->control;
486 ha->ip_config.tcp_wsf = init_fw_cb->ipv4_tcp_wsf;
487 ha->ip_config.ipv4_tos = init_fw_cb->ipv4_tos;
488 ha->ip_config.ipv4_cache_id = init_fw_cb->ipv4_cacheid;
489 ha->ip_config.ipv4_alt_cid_len = init_fw_cb->ipv4_dhcp_alt_cid_len;
490 memcpy(ha->ip_config.ipv4_alt_cid, init_fw_cb->ipv4_dhcp_alt_cid,
491 min(sizeof(ha->ip_config.ipv4_alt_cid),
492 sizeof(init_fw_cb->ipv4_dhcp_alt_cid)));
493 ha->ip_config.ipv4_vid_len = init_fw_cb->ipv4_dhcp_vid_len;
494 memcpy(ha->ip_config.ipv4_vid, init_fw_cb->ipv4_dhcp_vid,
495 min(sizeof(ha->ip_config.ipv4_vid),
496 sizeof(init_fw_cb->ipv4_dhcp_vid)));
497 ha->ip_config.ipv4_ttl = init_fw_cb->ipv4_ttl;
498 ha->ip_config.def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
499 ha->ip_config.abort_timer = init_fw_cb->abort_timer;
500 ha->ip_config.iscsi_options = le16_to_cpu(init_fw_cb->iscsi_opts);
501 ha->ip_config.iscsi_max_pdu_size =
502 le16_to_cpu(init_fw_cb->iscsi_max_pdu_size);
503 ha->ip_config.iscsi_first_burst_len =
504 le16_to_cpu(init_fw_cb->iscsi_fburst_len);
505 ha->ip_config.iscsi_max_outstnd_r2t =
506 le16_to_cpu(init_fw_cb->iscsi_max_outstnd_r2t);
507 ha->ip_config.iscsi_max_burst_len =
508 le16_to_cpu(init_fw_cb->iscsi_max_burst_len);
509 memcpy(ha->ip_config.iscsi_name, init_fw_cb->iscsi_name,
510 min(sizeof(ha->ip_config.iscsi_name),
511 sizeof(init_fw_cb->iscsi_name)));
512
513 if (is_ipv6_enabled(ha)) {
514 /* Save IPv6 Address */
515 ha->ip_config.ipv6_link_local_state =
516 qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_lnk_lcl_addr_state);
517 ha->ip_config.ipv6_addr0_state =
518 qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr0_state);
519 ha->ip_config.ipv6_addr1_state =
520 qla4xxx_set_ipaddr_state(init_fw_cb->ipv6_addr1_state);
521
522 switch (le16_to_cpu(init_fw_cb->ipv6_dflt_rtr_state)) {
523 case IPV6_RTRSTATE_UNKNOWN:
524 ha->ip_config.ipv6_default_router_state =
525 ISCSI_ROUTER_STATE_UNKNOWN;
526 break;
527 case IPV6_RTRSTATE_MANUAL:
528 ha->ip_config.ipv6_default_router_state =
529 ISCSI_ROUTER_STATE_MANUAL;
530 break;
531 case IPV6_RTRSTATE_ADVERTISED:
532 ha->ip_config.ipv6_default_router_state =
533 ISCSI_ROUTER_STATE_ADVERTISED;
534 break;
535 case IPV6_RTRSTATE_STALE:
536 ha->ip_config.ipv6_default_router_state =
537 ISCSI_ROUTER_STATE_STALE;
538 break;
539 default:
540 ha->ip_config.ipv6_default_router_state =
541 ISCSI_ROUTER_STATE_UNKNOWN;
542 }
543
544 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[0] = 0xFE;
545 ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[1] = 0x80;
546
547 memcpy(&ha->ip_config.ipv6_link_local_addr.in6_u.u6_addr8[8],
548 init_fw_cb->ipv6_if_id,
549 min(sizeof(ha->ip_config.ipv6_link_local_addr)/2,
550 sizeof(init_fw_cb->ipv6_if_id)));
551 memcpy(&ha->ip_config.ipv6_addr0, init_fw_cb->ipv6_addr0,
552 min(sizeof(ha->ip_config.ipv6_addr0),
553 sizeof(init_fw_cb->ipv6_addr0)));
554 memcpy(&ha->ip_config.ipv6_addr1, init_fw_cb->ipv6_addr1,
555 min(sizeof(ha->ip_config.ipv6_addr1),
556 sizeof(init_fw_cb->ipv6_addr1)));
557 memcpy(&ha->ip_config.ipv6_default_router_addr,
558 init_fw_cb->ipv6_dflt_rtr_addr,
559 min(sizeof(ha->ip_config.ipv6_default_router_addr),
560 sizeof(init_fw_cb->ipv6_dflt_rtr_addr)));
561 ha->ip_config.ipv6_vlan_tag =
562 be16_to_cpu(init_fw_cb->ipv6_vlan_tag);
563 ha->ip_config.ipv6_port = le16_to_cpu(init_fw_cb->ipv6_port);
564 ha->ip_config.ipv6_cache_id = init_fw_cb->ipv6_cache_id;
565 ha->ip_config.ipv6_flow_lbl =
566 le16_to_cpu(init_fw_cb->ipv6_flow_lbl);
567 ha->ip_config.ipv6_traffic_class =
568 init_fw_cb->ipv6_traffic_class;
569 ha->ip_config.ipv6_hop_limit = init_fw_cb->ipv6_hop_limit;
570 ha->ip_config.ipv6_nd_reach_time =
571 le32_to_cpu(init_fw_cb->ipv6_nd_reach_time);
572 ha->ip_config.ipv6_nd_rexmit_timer =
573 le32_to_cpu(init_fw_cb->ipv6_nd_rexmit_timer);
574 ha->ip_config.ipv6_nd_stale_timeout =
575 le32_to_cpu(init_fw_cb->ipv6_nd_stale_timeout);
576 ha->ip_config.ipv6_dup_addr_detect_count =
577 init_fw_cb->ipv6_dup_addr_detect_count;
578 ha->ip_config.ipv6_gw_advrt_mtu =
579 le32_to_cpu(init_fw_cb->ipv6_gw_advrt_mtu);
580 ha->ip_config.ipv6_tcp_wsf = init_fw_cb->ipv6_tcp_wsf;
581 }
582 }
583
584 uint8_t
585 qla4xxx_update_local_ifcb(struct scsi_qla_host *ha,
586 uint32_t *mbox_cmd,
587 uint32_t *mbox_sts,
588 struct addr_ctrl_blk *init_fw_cb,
589 dma_addr_t init_fw_cb_dma)
590 {
591 if (qla4xxx_get_ifcb(ha, mbox_cmd, mbox_sts, init_fw_cb_dma)
592 != QLA_SUCCESS) {
593 DEBUG2(printk(KERN_WARNING
594 "scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
595 ha->host_no, __func__));
596 return QLA_ERROR;
597 }
598
599 DEBUG2(qla4xxx_dump_buffer(init_fw_cb, sizeof(struct addr_ctrl_blk)));
600
601 /* Save some info in adapter structure. */
602 ha->acb_version = init_fw_cb->acb_version;
603 ha->firmware_options = le16_to_cpu(init_fw_cb->fw_options);
604 ha->heartbeat_interval = init_fw_cb->hb_interval;
605 memcpy(ha->name_string, init_fw_cb->iscsi_name,
606 min(sizeof(ha->name_string),
607 sizeof(init_fw_cb->iscsi_name)));
608 ha->def_timeout = le16_to_cpu(init_fw_cb->def_timeout);
609 /*memcpy(ha->alias, init_fw_cb->Alias,
610 min(sizeof(ha->alias), sizeof(init_fw_cb->Alias)));*/
611
612 qla4xxx_update_local_ip(ha, init_fw_cb);
613
614 return QLA_SUCCESS;
615 }
616
617 /**
618 * qla4xxx_initialize_fw_cb - initializes firmware control block.
619 * @ha: Pointer to host adapter structure.
620 **/
621 int qla4xxx_initialize_fw_cb(struct scsi_qla_host * ha)
622 {
623 struct addr_ctrl_blk *init_fw_cb;
624 dma_addr_t init_fw_cb_dma;
625 uint32_t mbox_cmd[MBOX_REG_COUNT];
626 uint32_t mbox_sts[MBOX_REG_COUNT];
627 int status = QLA_ERROR;
628
629 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
630 sizeof(struct addr_ctrl_blk),
631 &init_fw_cb_dma, GFP_KERNEL);
632 if (init_fw_cb == NULL) {
633 DEBUG2(printk("scsi%ld: %s: Unable to alloc init_cb\n",
634 ha->host_no, __func__));
635 goto exit_init_fw_cb_no_free;
636 }
637 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
638
639 /* Get Initialize Firmware Control Block. */
640 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
641 memset(&mbox_sts, 0, sizeof(mbox_sts));
642
643 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
644 QLA_SUCCESS) {
645 dma_free_coherent(&ha->pdev->dev,
646 sizeof(struct addr_ctrl_blk),
647 init_fw_cb, init_fw_cb_dma);
648 goto exit_init_fw_cb;
649 }
650
651 /* Initialize request and response queues. */
652 qla4xxx_init_rings(ha);
653
654 /* Fill in the request and response queue information. */
655 init_fw_cb->rqq_consumer_idx = cpu_to_le16(ha->request_out);
656 init_fw_cb->compq_producer_idx = cpu_to_le16(ha->response_in);
657 init_fw_cb->rqq_len = __constant_cpu_to_le16(REQUEST_QUEUE_DEPTH);
658 init_fw_cb->compq_len = __constant_cpu_to_le16(RESPONSE_QUEUE_DEPTH);
659 init_fw_cb->rqq_addr_lo = cpu_to_le32(LSDW(ha->request_dma));
660 init_fw_cb->rqq_addr_hi = cpu_to_le32(MSDW(ha->request_dma));
661 init_fw_cb->compq_addr_lo = cpu_to_le32(LSDW(ha->response_dma));
662 init_fw_cb->compq_addr_hi = cpu_to_le32(MSDW(ha->response_dma));
663 init_fw_cb->shdwreg_addr_lo = cpu_to_le32(LSDW(ha->shadow_regs_dma));
664 init_fw_cb->shdwreg_addr_hi = cpu_to_le32(MSDW(ha->shadow_regs_dma));
665
666 /* Set up required options. */
667 init_fw_cb->fw_options |=
668 __constant_cpu_to_le16(FWOPT_SESSION_MODE |
669 FWOPT_INITIATOR_MODE);
670
671 if (is_qla80XX(ha))
672 init_fw_cb->fw_options |=
673 __constant_cpu_to_le16(FWOPT_ENABLE_CRBDB);
674
675 init_fw_cb->fw_options &= __constant_cpu_to_le16(~FWOPT_TARGET_MODE);
676
677 init_fw_cb->add_fw_options = 0;
678 init_fw_cb->add_fw_options |=
679 __constant_cpu_to_le16(ADFWOPT_SERIALIZE_TASK_MGMT);
680 init_fw_cb->add_fw_options |=
681 __constant_cpu_to_le16(ADFWOPT_AUTOCONN_DISABLE);
682
683 if (qla4xxx_set_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma)
684 != QLA_SUCCESS) {
685 DEBUG2(printk(KERN_WARNING
686 "scsi%ld: %s: Failed to set init_fw_ctrl_blk\n",
687 ha->host_no, __func__));
688 goto exit_init_fw_cb;
689 }
690
691 if (qla4xxx_update_local_ifcb(ha, &mbox_cmd[0], &mbox_sts[0],
692 init_fw_cb, init_fw_cb_dma) != QLA_SUCCESS) {
693 DEBUG2(printk("scsi%ld: %s: Failed to update local ifcb\n",
694 ha->host_no, __func__));
695 goto exit_init_fw_cb;
696 }
697 status = QLA_SUCCESS;
698
699 exit_init_fw_cb:
700 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
701 init_fw_cb, init_fw_cb_dma);
702 exit_init_fw_cb_no_free:
703 return status;
704 }
705
706 /**
707 * qla4xxx_get_dhcp_ip_address - gets HBA ip address via DHCP
708 * @ha: Pointer to host adapter structure.
709 **/
710 int qla4xxx_get_dhcp_ip_address(struct scsi_qla_host * ha)
711 {
712 struct addr_ctrl_blk *init_fw_cb;
713 dma_addr_t init_fw_cb_dma;
714 uint32_t mbox_cmd[MBOX_REG_COUNT];
715 uint32_t mbox_sts[MBOX_REG_COUNT];
716
717 init_fw_cb = dma_alloc_coherent(&ha->pdev->dev,
718 sizeof(struct addr_ctrl_blk),
719 &init_fw_cb_dma, GFP_KERNEL);
720 if (init_fw_cb == NULL) {
721 printk("scsi%ld: %s: Unable to alloc init_cb\n", ha->host_no,
722 __func__);
723 return QLA_ERROR;
724 }
725
726 /* Get Initialize Firmware Control Block. */
727 memset(init_fw_cb, 0, sizeof(struct addr_ctrl_blk));
728 if (qla4xxx_get_ifcb(ha, &mbox_cmd[0], &mbox_sts[0], init_fw_cb_dma) !=
729 QLA_SUCCESS) {
730 DEBUG2(printk("scsi%ld: %s: Failed to get init_fw_ctrl_blk\n",
731 ha->host_no, __func__));
732 dma_free_coherent(&ha->pdev->dev,
733 sizeof(struct addr_ctrl_blk),
734 init_fw_cb, init_fw_cb_dma);
735 return QLA_ERROR;
736 }
737
738 /* Save IP Address. */
739 qla4xxx_update_local_ip(ha, init_fw_cb);
740 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk),
741 init_fw_cb, init_fw_cb_dma);
742
743 return QLA_SUCCESS;
744 }
745
746 /**
747 * qla4xxx_get_firmware_state - gets firmware state of HBA
748 * @ha: Pointer to host adapter structure.
749 **/
750 int qla4xxx_get_firmware_state(struct scsi_qla_host * ha)
751 {
752 uint32_t mbox_cmd[MBOX_REG_COUNT];
753 uint32_t mbox_sts[MBOX_REG_COUNT];
754
755 /* Get firmware version */
756 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
757 memset(&mbox_sts, 0, sizeof(mbox_sts));
758
759 mbox_cmd[0] = MBOX_CMD_GET_FW_STATE;
760
761 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 4, &mbox_cmd[0], &mbox_sts[0]) !=
762 QLA_SUCCESS) {
763 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATE failed w/ "
764 "status %04X\n", ha->host_no, __func__,
765 mbox_sts[0]));
766 return QLA_ERROR;
767 }
768 ha->firmware_state = mbox_sts[1];
769 ha->board_id = mbox_sts[2];
770 ha->addl_fw_state = mbox_sts[3];
771 DEBUG2(printk("scsi%ld: %s firmware_state=0x%x\n",
772 ha->host_no, __func__, ha->firmware_state);)
773
774 return QLA_SUCCESS;
775 }
776
777 /**
778 * qla4xxx_get_firmware_status - retrieves firmware status
779 * @ha: Pointer to host adapter structure.
780 **/
781 int qla4xxx_get_firmware_status(struct scsi_qla_host * ha)
782 {
783 uint32_t mbox_cmd[MBOX_REG_COUNT];
784 uint32_t mbox_sts[MBOX_REG_COUNT];
785
786 /* Get firmware version */
787 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
788 memset(&mbox_sts, 0, sizeof(mbox_sts));
789
790 mbox_cmd[0] = MBOX_CMD_GET_FW_STATUS;
791
792 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0], &mbox_sts[0]) !=
793 QLA_SUCCESS) {
794 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_FW_STATUS failed w/ "
795 "status %04X\n", ha->host_no, __func__,
796 mbox_sts[0]));
797 return QLA_ERROR;
798 }
799
800 /* High-water mark of IOCBs */
801 ha->iocb_hiwat = mbox_sts[2];
802 DEBUG2(ql4_printk(KERN_INFO, ha,
803 "%s: firmware IOCBs available = %d\n", __func__,
804 ha->iocb_hiwat));
805
806 if (ha->iocb_hiwat > IOCB_HIWAT_CUSHION)
807 ha->iocb_hiwat -= IOCB_HIWAT_CUSHION;
808
809 /* Ideally, we should not enter this code, as the # of firmware
810 * IOCBs is hard-coded in the firmware. We set a default
811 * iocb_hiwat here just in case */
812 if (ha->iocb_hiwat == 0) {
813 ha->iocb_hiwat = REQUEST_QUEUE_DEPTH / 4;
814 DEBUG2(ql4_printk(KERN_WARNING, ha,
815 "%s: Setting IOCB's to = %d\n", __func__,
816 ha->iocb_hiwat));
817 }
818
819 return QLA_SUCCESS;
820 }
821
822 /**
823 * qla4xxx_get_fwddb_entry - retrieves firmware ddb entry
824 * @ha: Pointer to host adapter structure.
825 * @fw_ddb_index: Firmware's device database index
826 * @fw_ddb_entry: Pointer to firmware's device database entry structure
827 * @num_valid_ddb_entries: Pointer to number of valid ddb entries
828 * @next_ddb_index: Pointer to next valid device database index
829 * @fw_ddb_device_state: Pointer to device state
830 **/
831 int qla4xxx_get_fwddb_entry(struct scsi_qla_host *ha,
832 uint16_t fw_ddb_index,
833 struct dev_db_entry *fw_ddb_entry,
834 dma_addr_t fw_ddb_entry_dma,
835 uint32_t *num_valid_ddb_entries,
836 uint32_t *next_ddb_index,
837 uint32_t *fw_ddb_device_state,
838 uint32_t *conn_err_detail,
839 uint16_t *tcp_source_port_num,
840 uint16_t *connection_id)
841 {
842 int status = QLA_ERROR;
843 uint16_t options;
844 uint32_t mbox_cmd[MBOX_REG_COUNT];
845 uint32_t mbox_sts[MBOX_REG_COUNT];
846
847 /* Make sure the device index is valid */
848 if (fw_ddb_index >= MAX_DDB_ENTRIES) {
849 DEBUG2(printk("scsi%ld: %s: ddb [%d] out of range.\n",
850 ha->host_no, __func__, fw_ddb_index));
851 goto exit_get_fwddb;
852 }
853 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
854 memset(&mbox_sts, 0, sizeof(mbox_sts));
855 if (fw_ddb_entry)
856 memset(fw_ddb_entry, 0, sizeof(struct dev_db_entry));
857
858 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY;
859 mbox_cmd[1] = (uint32_t) fw_ddb_index;
860 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
861 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
862 mbox_cmd[4] = sizeof(struct dev_db_entry);
863
864 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 7, &mbox_cmd[0], &mbox_sts[0]) ==
865 QLA_ERROR) {
866 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_GET_DATABASE_ENTRY failed"
867 " with status 0x%04X\n", ha->host_no, __func__,
868 mbox_sts[0]));
869 goto exit_get_fwddb;
870 }
871 if (fw_ddb_index != mbox_sts[1]) {
872 DEBUG2(printk("scsi%ld: %s: ddb mismatch [%d] != [%d].\n",
873 ha->host_no, __func__, fw_ddb_index,
874 mbox_sts[1]));
875 goto exit_get_fwddb;
876 }
877 if (fw_ddb_entry) {
878 options = le16_to_cpu(fw_ddb_entry->options);
879 if (options & DDB_OPT_IPV6_DEVICE) {
880 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
881 "Next %d State %04x ConnErr %08x %pI6 "
882 ":%04d \"%s\"\n", __func__, fw_ddb_index,
883 mbox_sts[0], mbox_sts[2], mbox_sts[3],
884 mbox_sts[4], mbox_sts[5],
885 fw_ddb_entry->ip_addr,
886 le16_to_cpu(fw_ddb_entry->port),
887 fw_ddb_entry->iscsi_name);
888 } else {
889 ql4_printk(KERN_INFO, ha, "%s: DDB[%d] MB0 %04x Tot %d "
890 "Next %d State %04x ConnErr %08x %pI4 "
891 ":%04d \"%s\"\n", __func__, fw_ddb_index,
892 mbox_sts[0], mbox_sts[2], mbox_sts[3],
893 mbox_sts[4], mbox_sts[5],
894 fw_ddb_entry->ip_addr,
895 le16_to_cpu(fw_ddb_entry->port),
896 fw_ddb_entry->iscsi_name);
897 }
898 }
899 if (num_valid_ddb_entries)
900 *num_valid_ddb_entries = mbox_sts[2];
901 if (next_ddb_index)
902 *next_ddb_index = mbox_sts[3];
903 if (fw_ddb_device_state)
904 *fw_ddb_device_state = mbox_sts[4];
905
906 /*
907 * RA: This mailbox has been changed to pass connection error and
908 * details. Its true for ISP4010 as per Version E - Not sure when it
909 * was changed. Get the time2wait from the fw_dd_entry field :
910 * default_time2wait which we call it as minTime2Wait DEV_DB_ENTRY
911 * struct.
912 */
913 if (conn_err_detail)
914 *conn_err_detail = mbox_sts[5];
915 if (tcp_source_port_num)
916 *tcp_source_port_num = (uint16_t) (mbox_sts[6] >> 16);
917 if (connection_id)
918 *connection_id = (uint16_t) mbox_sts[6] & 0x00FF;
919 status = QLA_SUCCESS;
920
921 exit_get_fwddb:
922 return status;
923 }
924
925 int qla4xxx_conn_open(struct scsi_qla_host *ha, uint16_t fw_ddb_index)
926 {
927 uint32_t mbox_cmd[MBOX_REG_COUNT];
928 uint32_t mbox_sts[MBOX_REG_COUNT];
929 int status;
930
931 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
932 memset(&mbox_sts, 0, sizeof(mbox_sts));
933
934 mbox_cmd[0] = MBOX_CMD_CONN_OPEN;
935 mbox_cmd[1] = fw_ddb_index;
936
937 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
938 &mbox_sts[0]);
939 DEBUG2(ql4_printk(KERN_INFO, ha,
940 "%s: status = %d mbx0 = 0x%x mbx1 = 0x%x\n",
941 __func__, status, mbox_sts[0], mbox_sts[1]));
942 return status;
943 }
944
945 /**
946 * qla4xxx_set_fwddb_entry - sets a ddb entry.
947 * @ha: Pointer to host adapter structure.
948 * @fw_ddb_index: Firmware's device database index
949 * @fw_ddb_entry_dma: dma address of ddb entry
950 * @mbx_sts: mailbox 0 to be returned or NULL
951 *
952 * This routine initializes or updates the adapter's device database
953 * entry for the specified device.
954 **/
955 int qla4xxx_set_ddb_entry(struct scsi_qla_host * ha, uint16_t fw_ddb_index,
956 dma_addr_t fw_ddb_entry_dma, uint32_t *mbx_sts)
957 {
958 uint32_t mbox_cmd[MBOX_REG_COUNT];
959 uint32_t mbox_sts[MBOX_REG_COUNT];
960 int status;
961
962 /* Do not wait for completion. The firmware will send us an
963 * ASTS_DATABASE_CHANGED (0x8014) to notify us of the login status.
964 */
965 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
966 memset(&mbox_sts, 0, sizeof(mbox_sts));
967
968 mbox_cmd[0] = MBOX_CMD_SET_DATABASE_ENTRY;
969 mbox_cmd[1] = (uint32_t) fw_ddb_index;
970 mbox_cmd[2] = LSDW(fw_ddb_entry_dma);
971 mbox_cmd[3] = MSDW(fw_ddb_entry_dma);
972 mbox_cmd[4] = sizeof(struct dev_db_entry);
973
974 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
975 &mbox_sts[0]);
976 if (mbx_sts)
977 *mbx_sts = mbox_sts[0];
978 DEBUG2(printk("scsi%ld: %s: status=%d mbx0=0x%x mbx4=0x%x\n",
979 ha->host_no, __func__, status, mbox_sts[0], mbox_sts[4]);)
980
981 return status;
982 }
983
984 int qla4xxx_session_logout_ddb(struct scsi_qla_host *ha,
985 struct ddb_entry *ddb_entry, int options)
986 {
987 int status;
988 uint32_t mbox_cmd[MBOX_REG_COUNT];
989 uint32_t mbox_sts[MBOX_REG_COUNT];
990
991 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
992 memset(&mbox_sts, 0, sizeof(mbox_sts));
993
994 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
995 mbox_cmd[1] = ddb_entry->fw_ddb_index;
996 mbox_cmd[3] = options;
997
998 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0],
999 &mbox_sts[0]);
1000 if (status != QLA_SUCCESS) {
1001 DEBUG2(ql4_printk(KERN_INFO, ha,
1002 "%s: MBOX_CMD_CONN_CLOSE_SESS_LOGOUT "
1003 "failed sts %04X %04X", __func__,
1004 mbox_sts[0], mbox_sts[1]));
1005 }
1006
1007 return status;
1008 }
1009
1010 /**
1011 * qla4xxx_get_crash_record - retrieves crash record.
1012 * @ha: Pointer to host adapter structure.
1013 *
1014 * This routine retrieves a crash record from the QLA4010 after an 8002h aen.
1015 **/
1016 void qla4xxx_get_crash_record(struct scsi_qla_host * ha)
1017 {
1018 uint32_t mbox_cmd[MBOX_REG_COUNT];
1019 uint32_t mbox_sts[MBOX_REG_COUNT];
1020 struct crash_record *crash_record = NULL;
1021 dma_addr_t crash_record_dma = 0;
1022 uint32_t crash_record_size = 0;
1023
1024 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1025 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1026
1027 /* Get size of crash record. */
1028 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
1029
1030 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1031 QLA_SUCCESS) {
1032 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve size!\n",
1033 ha->host_no, __func__));
1034 goto exit_get_crash_record;
1035 }
1036 crash_record_size = mbox_sts[4];
1037 if (crash_record_size == 0) {
1038 DEBUG2(printk("scsi%ld: %s: ERROR: Crash record size is 0!\n",
1039 ha->host_no, __func__));
1040 goto exit_get_crash_record;
1041 }
1042
1043 /* Alloc Memory for Crash Record. */
1044 crash_record = dma_alloc_coherent(&ha->pdev->dev, crash_record_size,
1045 &crash_record_dma, GFP_KERNEL);
1046 if (crash_record == NULL)
1047 goto exit_get_crash_record;
1048
1049 /* Get Crash Record. */
1050 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1051 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1052
1053 mbox_cmd[0] = MBOX_CMD_GET_CRASH_RECORD;
1054 mbox_cmd[2] = LSDW(crash_record_dma);
1055 mbox_cmd[3] = MSDW(crash_record_dma);
1056 mbox_cmd[4] = crash_record_size;
1057
1058 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1059 QLA_SUCCESS)
1060 goto exit_get_crash_record;
1061
1062 /* Dump Crash Record. */
1063
1064 exit_get_crash_record:
1065 if (crash_record)
1066 dma_free_coherent(&ha->pdev->dev, crash_record_size,
1067 crash_record, crash_record_dma);
1068 }
1069
1070 /**
1071 * qla4xxx_get_conn_event_log - retrieves connection event log
1072 * @ha: Pointer to host adapter structure.
1073 **/
1074 void qla4xxx_get_conn_event_log(struct scsi_qla_host * ha)
1075 {
1076 uint32_t mbox_cmd[MBOX_REG_COUNT];
1077 uint32_t mbox_sts[MBOX_REG_COUNT];
1078 struct conn_event_log_entry *event_log = NULL;
1079 dma_addr_t event_log_dma = 0;
1080 uint32_t event_log_size = 0;
1081 uint32_t num_valid_entries;
1082 uint32_t oldest_entry = 0;
1083 uint32_t max_event_log_entries;
1084 uint8_t i;
1085
1086 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1087 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1088
1089 /* Get size of crash record. */
1090 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1091
1092 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1093 QLA_SUCCESS)
1094 goto exit_get_event_log;
1095
1096 event_log_size = mbox_sts[4];
1097 if (event_log_size == 0)
1098 goto exit_get_event_log;
1099
1100 /* Alloc Memory for Crash Record. */
1101 event_log = dma_alloc_coherent(&ha->pdev->dev, event_log_size,
1102 &event_log_dma, GFP_KERNEL);
1103 if (event_log == NULL)
1104 goto exit_get_event_log;
1105
1106 /* Get Crash Record. */
1107 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1108 memset(&mbox_sts, 0, sizeof(mbox_cmd));
1109
1110 mbox_cmd[0] = MBOX_CMD_GET_CONN_EVENT_LOG;
1111 mbox_cmd[2] = LSDW(event_log_dma);
1112 mbox_cmd[3] = MSDW(event_log_dma);
1113
1114 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0], &mbox_sts[0]) !=
1115 QLA_SUCCESS) {
1116 DEBUG2(printk("scsi%ld: %s: ERROR: Unable to retrieve event "
1117 "log!\n", ha->host_no, __func__));
1118 goto exit_get_event_log;
1119 }
1120
1121 /* Dump Event Log. */
1122 num_valid_entries = mbox_sts[1];
1123
1124 max_event_log_entries = event_log_size /
1125 sizeof(struct conn_event_log_entry);
1126
1127 if (num_valid_entries > max_event_log_entries)
1128 oldest_entry = num_valid_entries % max_event_log_entries;
1129
1130 DEBUG3(printk("scsi%ld: Connection Event Log Dump (%d entries):\n",
1131 ha->host_no, num_valid_entries));
1132
1133 if (ql4xextended_error_logging == 3) {
1134 if (oldest_entry == 0) {
1135 /* Circular Buffer has not wrapped around */
1136 for (i=0; i < num_valid_entries; i++) {
1137 qla4xxx_dump_buffer((uint8_t *)event_log+
1138 (i*sizeof(*event_log)),
1139 sizeof(*event_log));
1140 }
1141 }
1142 else {
1143 /* Circular Buffer has wrapped around -
1144 * display accordingly*/
1145 for (i=oldest_entry; i < max_event_log_entries; i++) {
1146 qla4xxx_dump_buffer((uint8_t *)event_log+
1147 (i*sizeof(*event_log)),
1148 sizeof(*event_log));
1149 }
1150 for (i=0; i < oldest_entry; i++) {
1151 qla4xxx_dump_buffer((uint8_t *)event_log+
1152 (i*sizeof(*event_log)),
1153 sizeof(*event_log));
1154 }
1155 }
1156 }
1157
1158 exit_get_event_log:
1159 if (event_log)
1160 dma_free_coherent(&ha->pdev->dev, event_log_size, event_log,
1161 event_log_dma);
1162 }
1163
1164 /**
1165 * qla4xxx_abort_task - issues Abort Task
1166 * @ha: Pointer to host adapter structure.
1167 * @srb: Pointer to srb entry
1168 *
1169 * This routine performs a LUN RESET on the specified target/lun.
1170 * The caller must ensure that the ddb_entry and lun_entry pointers
1171 * are valid before calling this routine.
1172 **/
1173 int qla4xxx_abort_task(struct scsi_qla_host *ha, struct srb *srb)
1174 {
1175 uint32_t mbox_cmd[MBOX_REG_COUNT];
1176 uint32_t mbox_sts[MBOX_REG_COUNT];
1177 struct scsi_cmnd *cmd = srb->cmd;
1178 int status = QLA_SUCCESS;
1179 unsigned long flags = 0;
1180 uint32_t index;
1181
1182 /*
1183 * Send abort task command to ISP, so that the ISP will return
1184 * request with ABORT status
1185 */
1186 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1187 memset(&mbox_sts, 0, sizeof(mbox_sts));
1188
1189 spin_lock_irqsave(&ha->hardware_lock, flags);
1190 index = (unsigned long)(unsigned char *)cmd->host_scribble;
1191 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1192
1193 /* Firmware already posted completion on response queue */
1194 if (index == MAX_SRBS)
1195 return status;
1196
1197 mbox_cmd[0] = MBOX_CMD_ABORT_TASK;
1198 mbox_cmd[1] = srb->ddb->fw_ddb_index;
1199 mbox_cmd[2] = index;
1200 /* Immediate Command Enable */
1201 mbox_cmd[5] = 0x01;
1202
1203 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 5, &mbox_cmd[0],
1204 &mbox_sts[0]);
1205 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE) {
1206 status = QLA_ERROR;
1207
1208 DEBUG2(printk(KERN_WARNING "scsi%ld:%d:%d: abort task FAILED: "
1209 "mbx0=%04X, mb1=%04X, mb2=%04X, mb3=%04X, mb4=%04X\n",
1210 ha->host_no, cmd->device->id, cmd->device->lun, mbox_sts[0],
1211 mbox_sts[1], mbox_sts[2], mbox_sts[3], mbox_sts[4]));
1212 }
1213
1214 return status;
1215 }
1216
1217 /**
1218 * qla4xxx_reset_lun - issues LUN Reset
1219 * @ha: Pointer to host adapter structure.
1220 * @ddb_entry: Pointer to device database entry
1221 * @lun: lun number
1222 *
1223 * This routine performs a LUN RESET on the specified target/lun.
1224 * The caller must ensure that the ddb_entry and lun_entry pointers
1225 * are valid before calling this routine.
1226 **/
1227 int qla4xxx_reset_lun(struct scsi_qla_host * ha, struct ddb_entry * ddb_entry,
1228 int lun)
1229 {
1230 uint32_t mbox_cmd[MBOX_REG_COUNT];
1231 uint32_t mbox_sts[MBOX_REG_COUNT];
1232 uint32_t scsi_lun[2];
1233 int status = QLA_SUCCESS;
1234
1235 DEBUG2(printk("scsi%ld:%d:%d: lun reset issued\n", ha->host_no,
1236 ddb_entry->fw_ddb_index, lun));
1237
1238 /*
1239 * Send lun reset command to ISP, so that the ISP will return all
1240 * outstanding requests with RESET status
1241 */
1242 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1243 memset(&mbox_sts, 0, sizeof(mbox_sts));
1244 int_to_scsilun(lun, (struct scsi_lun *) scsi_lun);
1245
1246 mbox_cmd[0] = MBOX_CMD_LUN_RESET;
1247 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1248 /* FW expects LUN bytes 0-3 in Incoming Mailbox 2
1249 * (LUN byte 0 is LSByte, byte 3 is MSByte) */
1250 mbox_cmd[2] = cpu_to_le32(scsi_lun[0]);
1251 /* FW expects LUN bytes 4-7 in Incoming Mailbox 3
1252 * (LUN byte 4 is LSByte, byte 7 is MSByte) */
1253 mbox_cmd[3] = cpu_to_le32(scsi_lun[1]);
1254 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1255
1256 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]);
1257 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1258 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1259 status = QLA_ERROR;
1260
1261 return status;
1262 }
1263
1264 /**
1265 * qla4xxx_reset_target - issues target Reset
1266 * @ha: Pointer to host adapter structure.
1267 * @db_entry: Pointer to device database entry
1268 * @un_entry: Pointer to lun entry structure
1269 *
1270 * This routine performs a TARGET RESET on the specified target.
1271 * The caller must ensure that the ddb_entry pointers
1272 * are valid before calling this routine.
1273 **/
1274 int qla4xxx_reset_target(struct scsi_qla_host *ha,
1275 struct ddb_entry *ddb_entry)
1276 {
1277 uint32_t mbox_cmd[MBOX_REG_COUNT];
1278 uint32_t mbox_sts[MBOX_REG_COUNT];
1279 int status = QLA_SUCCESS;
1280
1281 DEBUG2(printk("scsi%ld:%d: target reset issued\n", ha->host_no,
1282 ddb_entry->fw_ddb_index));
1283
1284 /*
1285 * Send target reset command to ISP, so that the ISP will return all
1286 * outstanding requests with RESET status
1287 */
1288 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1289 memset(&mbox_sts, 0, sizeof(mbox_sts));
1290
1291 mbox_cmd[0] = MBOX_CMD_TARGET_WARM_RESET;
1292 mbox_cmd[1] = ddb_entry->fw_ddb_index;
1293 mbox_cmd[5] = 0x01; /* Immediate Command Enable */
1294
1295 qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1296 &mbox_sts[0]);
1297 if (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE &&
1298 mbox_sts[0] != MBOX_STS_COMMAND_ERROR)
1299 status = QLA_ERROR;
1300
1301 return status;
1302 }
1303
1304 int qla4xxx_get_flash(struct scsi_qla_host * ha, dma_addr_t dma_addr,
1305 uint32_t offset, uint32_t len)
1306 {
1307 uint32_t mbox_cmd[MBOX_REG_COUNT];
1308 uint32_t mbox_sts[MBOX_REG_COUNT];
1309
1310 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1311 memset(&mbox_sts, 0, sizeof(mbox_sts));
1312
1313 mbox_cmd[0] = MBOX_CMD_READ_FLASH;
1314 mbox_cmd[1] = LSDW(dma_addr);
1315 mbox_cmd[2] = MSDW(dma_addr);
1316 mbox_cmd[3] = offset;
1317 mbox_cmd[4] = len;
1318
1319 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, &mbox_cmd[0], &mbox_sts[0]) !=
1320 QLA_SUCCESS) {
1321 DEBUG2(printk("scsi%ld: %s: MBOX_CMD_READ_FLASH, failed w/ "
1322 "status %04X %04X, offset %08x, len %08x\n", ha->host_no,
1323 __func__, mbox_sts[0], mbox_sts[1], offset, len));
1324 return QLA_ERROR;
1325 }
1326 return QLA_SUCCESS;
1327 }
1328
1329 /**
1330 * qla4xxx_about_firmware - gets FW, iscsi draft and boot loader version
1331 * @ha: Pointer to host adapter structure.
1332 *
1333 * Retrieves the FW version, iSCSI draft version & bootloader version of HBA.
1334 * Mailboxes 2 & 3 may hold an address for data. Make sure that we write 0 to
1335 * those mailboxes, if unused.
1336 **/
1337 int qla4xxx_about_firmware(struct scsi_qla_host *ha)
1338 {
1339 struct about_fw_info *about_fw = NULL;
1340 dma_addr_t about_fw_dma;
1341 uint32_t mbox_cmd[MBOX_REG_COUNT];
1342 uint32_t mbox_sts[MBOX_REG_COUNT];
1343 int status = QLA_ERROR;
1344
1345 about_fw = dma_alloc_coherent(&ha->pdev->dev,
1346 sizeof(struct about_fw_info),
1347 &about_fw_dma, GFP_KERNEL);
1348 if (!about_fw) {
1349 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: Unable to alloc memory "
1350 "for about_fw\n", __func__));
1351 return status;
1352 }
1353
1354 memset(about_fw, 0, sizeof(struct about_fw_info));
1355 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1356 memset(&mbox_sts, 0, sizeof(mbox_sts));
1357
1358 mbox_cmd[0] = MBOX_CMD_ABOUT_FW;
1359 mbox_cmd[2] = LSDW(about_fw_dma);
1360 mbox_cmd[3] = MSDW(about_fw_dma);
1361 mbox_cmd[4] = sizeof(struct about_fw_info);
1362
1363 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1364 &mbox_cmd[0], &mbox_sts[0]);
1365 if (status != QLA_SUCCESS) {
1366 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_ABOUT_FW "
1367 "failed w/ status %04X\n", __func__,
1368 mbox_sts[0]));
1369 goto exit_about_fw;
1370 }
1371
1372 /* Save version information. */
1373 ha->fw_info.fw_major = le16_to_cpu(about_fw->fw_major);
1374 ha->fw_info.fw_minor = le16_to_cpu(about_fw->fw_minor);
1375 ha->fw_info.fw_patch = le16_to_cpu(about_fw->fw_patch);
1376 ha->fw_info.fw_build = le16_to_cpu(about_fw->fw_build);
1377 memcpy(ha->fw_info.fw_build_date, about_fw->fw_build_date,
1378 sizeof(about_fw->fw_build_date));
1379 memcpy(ha->fw_info.fw_build_time, about_fw->fw_build_time,
1380 sizeof(about_fw->fw_build_time));
1381 strcpy((char *)ha->fw_info.fw_build_user,
1382 skip_spaces((char *)about_fw->fw_build_user));
1383 ha->fw_info.fw_load_source = le16_to_cpu(about_fw->fw_load_source);
1384 ha->fw_info.iscsi_major = le16_to_cpu(about_fw->iscsi_major);
1385 ha->fw_info.iscsi_minor = le16_to_cpu(about_fw->iscsi_minor);
1386 ha->fw_info.bootload_major = le16_to_cpu(about_fw->bootload_major);
1387 ha->fw_info.bootload_minor = le16_to_cpu(about_fw->bootload_minor);
1388 ha->fw_info.bootload_patch = le16_to_cpu(about_fw->bootload_patch);
1389 ha->fw_info.bootload_build = le16_to_cpu(about_fw->bootload_build);
1390 strcpy((char *)ha->fw_info.extended_timestamp,
1391 skip_spaces((char *)about_fw->extended_timestamp));
1392
1393 ha->fw_uptime_secs = le32_to_cpu(mbox_sts[5]);
1394 ha->fw_uptime_msecs = le32_to_cpu(mbox_sts[6]);
1395 status = QLA_SUCCESS;
1396
1397 exit_about_fw:
1398 dma_free_coherent(&ha->pdev->dev, sizeof(struct about_fw_info),
1399 about_fw, about_fw_dma);
1400 return status;
1401 }
1402
1403 int qla4xxx_get_default_ddb(struct scsi_qla_host *ha, uint32_t options,
1404 dma_addr_t dma_addr)
1405 {
1406 uint32_t mbox_cmd[MBOX_REG_COUNT];
1407 uint32_t mbox_sts[MBOX_REG_COUNT];
1408
1409 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1410 memset(&mbox_sts, 0, sizeof(mbox_sts));
1411
1412 mbox_cmd[0] = MBOX_CMD_GET_DATABASE_ENTRY_DEFAULTS;
1413 mbox_cmd[1] = options;
1414 mbox_cmd[2] = LSDW(dma_addr);
1415 mbox_cmd[3] = MSDW(dma_addr);
1416
1417 if (qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0], &mbox_sts[0]) !=
1418 QLA_SUCCESS) {
1419 DEBUG2(printk("scsi%ld: %s: failed status %04X\n",
1420 ha->host_no, __func__, mbox_sts[0]));
1421 return QLA_ERROR;
1422 }
1423 return QLA_SUCCESS;
1424 }
1425
1426 int qla4xxx_req_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index,
1427 uint32_t *mbx_sts)
1428 {
1429 int status;
1430 uint32_t mbox_cmd[MBOX_REG_COUNT];
1431 uint32_t mbox_sts[MBOX_REG_COUNT];
1432
1433 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1434 memset(&mbox_sts, 0, sizeof(mbox_sts));
1435
1436 mbox_cmd[0] = MBOX_CMD_REQUEST_DATABASE_ENTRY;
1437 mbox_cmd[1] = ddb_index;
1438
1439 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
1440 &mbox_sts[0]);
1441 if (status != QLA_SUCCESS) {
1442 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1443 __func__, mbox_sts[0]));
1444 }
1445
1446 *mbx_sts = mbox_sts[0];
1447 return status;
1448 }
1449
1450 int qla4xxx_clear_ddb_entry(struct scsi_qla_host *ha, uint32_t ddb_index)
1451 {
1452 int status;
1453 uint32_t mbox_cmd[MBOX_REG_COUNT];
1454 uint32_t mbox_sts[MBOX_REG_COUNT];
1455
1456 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1457 memset(&mbox_sts, 0, sizeof(mbox_sts));
1458
1459 mbox_cmd[0] = MBOX_CMD_CLEAR_DATABASE_ENTRY;
1460 mbox_cmd[1] = ddb_index;
1461
1462 status = qla4xxx_mailbox_command(ha, 2, 1, &mbox_cmd[0],
1463 &mbox_sts[0]);
1464 if (status != QLA_SUCCESS) {
1465 DEBUG2(ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
1466 __func__, mbox_sts[0]));
1467 }
1468
1469 return status;
1470 }
1471
1472 int qla4xxx_set_flash(struct scsi_qla_host *ha, dma_addr_t dma_addr,
1473 uint32_t offset, uint32_t length, uint32_t options)
1474 {
1475 uint32_t mbox_cmd[MBOX_REG_COUNT];
1476 uint32_t mbox_sts[MBOX_REG_COUNT];
1477 int status = QLA_SUCCESS;
1478
1479 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1480 memset(&mbox_sts, 0, sizeof(mbox_sts));
1481
1482 mbox_cmd[0] = MBOX_CMD_WRITE_FLASH;
1483 mbox_cmd[1] = LSDW(dma_addr);
1484 mbox_cmd[2] = MSDW(dma_addr);
1485 mbox_cmd[3] = offset;
1486 mbox_cmd[4] = length;
1487 mbox_cmd[5] = options;
1488
1489 status = qla4xxx_mailbox_command(ha, 6, 2, &mbox_cmd[0], &mbox_sts[0]);
1490 if (status != QLA_SUCCESS) {
1491 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_WRITE_FLASH "
1492 "failed w/ status %04X, mbx1 %04X\n",
1493 __func__, mbox_sts[0], mbox_sts[1]));
1494 }
1495 return status;
1496 }
1497
1498 int qla4xxx_bootdb_by_index(struct scsi_qla_host *ha,
1499 struct dev_db_entry *fw_ddb_entry,
1500 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1501 {
1502 uint32_t dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1503 uint32_t dev_db_end_offset;
1504 int status = QLA_ERROR;
1505
1506 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1507
1508 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1509 dev_db_end_offset = FLASH_OFFSET_DB_END;
1510
1511 if (dev_db_start_offset > dev_db_end_offset) {
1512 DEBUG2(ql4_printk(KERN_ERR, ha,
1513 "%s:Invalid DDB index %d", __func__,
1514 ddb_index));
1515 goto exit_bootdb_failed;
1516 }
1517
1518 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1519 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1520 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash"
1521 "failed\n", ha->host_no, __func__);
1522 goto exit_bootdb_failed;
1523 }
1524
1525 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1526 status = QLA_SUCCESS;
1527
1528 exit_bootdb_failed:
1529 return status;
1530 }
1531
1532 int qla4xxx_flashdb_by_index(struct scsi_qla_host *ha,
1533 struct dev_db_entry *fw_ddb_entry,
1534 dma_addr_t fw_ddb_entry_dma, uint16_t ddb_index)
1535 {
1536 uint32_t dev_db_start_offset;
1537 uint32_t dev_db_end_offset;
1538 int status = QLA_ERROR;
1539
1540 memset(fw_ddb_entry, 0, sizeof(*fw_ddb_entry));
1541
1542 if (is_qla40XX(ha)) {
1543 dev_db_start_offset = FLASH_OFFSET_DB_INFO;
1544 dev_db_end_offset = FLASH_OFFSET_DB_END;
1545 } else {
1546 dev_db_start_offset = FLASH_RAW_ACCESS_ADDR +
1547 (ha->hw.flt_region_ddb << 2);
1548 /* flt_ddb_size is DDB table size for both ports
1549 * so divide it by 2 to calculate the offset for second port
1550 */
1551 if (ha->port_num == 1)
1552 dev_db_start_offset += (ha->hw.flt_ddb_size / 2);
1553
1554 dev_db_end_offset = dev_db_start_offset +
1555 (ha->hw.flt_ddb_size / 2);
1556 }
1557
1558 dev_db_start_offset += (ddb_index * sizeof(*fw_ddb_entry));
1559
1560 if (dev_db_start_offset > dev_db_end_offset) {
1561 DEBUG2(ql4_printk(KERN_ERR, ha,
1562 "%s:Invalid DDB index %d", __func__,
1563 ddb_index));
1564 goto exit_fdb_failed;
1565 }
1566
1567 if (qla4xxx_get_flash(ha, fw_ddb_entry_dma, dev_db_start_offset,
1568 sizeof(*fw_ddb_entry)) != QLA_SUCCESS) {
1569 ql4_printk(KERN_ERR, ha, "scsi%ld: %s: Get Flash failed\n",
1570 ha->host_no, __func__);
1571 goto exit_fdb_failed;
1572 }
1573
1574 if (fw_ddb_entry->cookie == DDB_VALID_COOKIE)
1575 status = QLA_SUCCESS;
1576
1577 exit_fdb_failed:
1578 return status;
1579 }
1580
1581 int qla4xxx_get_chap(struct scsi_qla_host *ha, char *username, char *password,
1582 uint16_t idx)
1583 {
1584 int ret = 0;
1585 int rval = QLA_ERROR;
1586 uint32_t offset = 0, chap_size;
1587 struct ql4_chap_table *chap_table;
1588 dma_addr_t chap_dma;
1589
1590 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1591 if (chap_table == NULL)
1592 return -ENOMEM;
1593
1594 chap_size = sizeof(struct ql4_chap_table);
1595 memset(chap_table, 0, chap_size);
1596
1597 if (is_qla40XX(ha))
1598 offset = FLASH_CHAP_OFFSET | (idx * chap_size);
1599 else {
1600 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1601 /* flt_chap_size is CHAP table size for both ports
1602 * so divide it by 2 to calculate the offset for second port
1603 */
1604 if (ha->port_num == 1)
1605 offset += (ha->hw.flt_chap_size / 2);
1606 offset += (idx * chap_size);
1607 }
1608
1609 rval = qla4xxx_get_flash(ha, chap_dma, offset, chap_size);
1610 if (rval != QLA_SUCCESS) {
1611 ret = -EINVAL;
1612 goto exit_get_chap;
1613 }
1614
1615 DEBUG2(ql4_printk(KERN_INFO, ha, "Chap Cookie: x%x\n",
1616 __le16_to_cpu(chap_table->cookie)));
1617
1618 if (__le16_to_cpu(chap_table->cookie) != CHAP_VALID_COOKIE) {
1619 ql4_printk(KERN_ERR, ha, "No valid chap entry found\n");
1620 goto exit_get_chap;
1621 }
1622
1623 strncpy(password, chap_table->secret, QL4_CHAP_MAX_SECRET_LEN);
1624 strncpy(username, chap_table->name, QL4_CHAP_MAX_NAME_LEN);
1625 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1626
1627 exit_get_chap:
1628 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1629 return ret;
1630 }
1631
1632 /**
1633 * qla4xxx_set_chap - Make a chap entry at the given index
1634 * @ha: pointer to adapter structure
1635 * @username: CHAP username to set
1636 * @password: CHAP password to set
1637 * @idx: CHAP index at which to make the entry
1638 * @bidi: type of chap entry (chap_in or chap_out)
1639 *
1640 * Create chap entry at the given index with the information provided.
1641 *
1642 * Note: Caller should acquire the chap lock before getting here.
1643 **/
1644 int qla4xxx_set_chap(struct scsi_qla_host *ha, char *username, char *password,
1645 uint16_t idx, int bidi)
1646 {
1647 int ret = 0;
1648 int rval = QLA_ERROR;
1649 uint32_t offset = 0;
1650 struct ql4_chap_table *chap_table;
1651 uint32_t chap_size = 0;
1652 dma_addr_t chap_dma;
1653
1654 chap_table = dma_pool_alloc(ha->chap_dma_pool, GFP_KERNEL, &chap_dma);
1655 if (chap_table == NULL) {
1656 ret = -ENOMEM;
1657 goto exit_set_chap;
1658 }
1659
1660 memset(chap_table, 0, sizeof(struct ql4_chap_table));
1661 if (bidi)
1662 chap_table->flags |= BIT_6; /* peer */
1663 else
1664 chap_table->flags |= BIT_7; /* local */
1665 chap_table->secret_len = strlen(password);
1666 strncpy(chap_table->secret, password, MAX_CHAP_SECRET_LEN);
1667 strncpy(chap_table->name, username, MAX_CHAP_NAME_LEN);
1668 chap_table->cookie = __constant_cpu_to_le16(CHAP_VALID_COOKIE);
1669
1670 if (is_qla40XX(ha)) {
1671 chap_size = MAX_CHAP_ENTRIES_40XX * sizeof(*chap_table);
1672 offset = FLASH_CHAP_OFFSET;
1673 } else { /* Single region contains CHAP info for both ports which is
1674 * divided into half for each port.
1675 */
1676 chap_size = ha->hw.flt_chap_size / 2;
1677 offset = FLASH_RAW_ACCESS_ADDR + (ha->hw.flt_region_chap << 2);
1678 if (ha->port_num == 1)
1679 offset += chap_size;
1680 }
1681
1682 offset += (idx * sizeof(struct ql4_chap_table));
1683 rval = qla4xxx_set_flash(ha, chap_dma, offset,
1684 sizeof(struct ql4_chap_table),
1685 FLASH_OPT_RMW_COMMIT);
1686
1687 if (rval == QLA_SUCCESS && ha->chap_list) {
1688 /* Update ha chap_list cache */
1689 memcpy((struct ql4_chap_table *)ha->chap_list + idx,
1690 chap_table, sizeof(struct ql4_chap_table));
1691 }
1692 dma_pool_free(ha->chap_dma_pool, chap_table, chap_dma);
1693 if (rval != QLA_SUCCESS)
1694 ret = -EINVAL;
1695
1696 exit_set_chap:
1697 return ret;
1698 }
1699
1700
1701 int qla4xxx_get_uni_chap_at_index(struct scsi_qla_host *ha, char *username,
1702 char *password, uint16_t chap_index)
1703 {
1704 int rval = QLA_ERROR;
1705 struct ql4_chap_table *chap_table = NULL;
1706 int max_chap_entries;
1707
1708 if (!ha->chap_list) {
1709 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1710 rval = QLA_ERROR;
1711 goto exit_uni_chap;
1712 }
1713
1714 if (!username || !password) {
1715 ql4_printk(KERN_ERR, ha, "No memory for username & secret\n");
1716 rval = QLA_ERROR;
1717 goto exit_uni_chap;
1718 }
1719
1720 if (is_qla80XX(ha))
1721 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1722 sizeof(struct ql4_chap_table);
1723 else
1724 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1725
1726 if (chap_index > max_chap_entries) {
1727 ql4_printk(KERN_ERR, ha, "Invalid Chap index\n");
1728 rval = QLA_ERROR;
1729 goto exit_uni_chap;
1730 }
1731
1732 mutex_lock(&ha->chap_sem);
1733 chap_table = (struct ql4_chap_table *)ha->chap_list + chap_index;
1734 if (chap_table->cookie != __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1735 rval = QLA_ERROR;
1736 goto exit_unlock_uni_chap;
1737 }
1738
1739 if (!(chap_table->flags & BIT_7)) {
1740 ql4_printk(KERN_ERR, ha, "Unidirectional entry not set\n");
1741 rval = QLA_ERROR;
1742 goto exit_unlock_uni_chap;
1743 }
1744
1745 strncpy(password, chap_table->secret, MAX_CHAP_SECRET_LEN);
1746 strncpy(username, chap_table->name, MAX_CHAP_NAME_LEN);
1747
1748 rval = QLA_SUCCESS;
1749
1750 exit_unlock_uni_chap:
1751 mutex_unlock(&ha->chap_sem);
1752 exit_uni_chap:
1753 return rval;
1754 }
1755
1756 /**
1757 * qla4xxx_get_chap_index - Get chap index given username and secret
1758 * @ha: pointer to adapter structure
1759 * @username: CHAP username to be searched
1760 * @password: CHAP password to be searched
1761 * @bidi: Is this a BIDI CHAP
1762 * @chap_index: CHAP index to be returned
1763 *
1764 * Match the username and password in the chap_list, return the index if a
1765 * match is found. If a match is not found then add the entry in FLASH and
1766 * return the index at which entry is written in the FLASH.
1767 **/
1768 int qla4xxx_get_chap_index(struct scsi_qla_host *ha, char *username,
1769 char *password, int bidi, uint16_t *chap_index)
1770 {
1771 int i, rval;
1772 int free_index = -1;
1773 int found_index = 0;
1774 int max_chap_entries = 0;
1775 struct ql4_chap_table *chap_table;
1776
1777 if (is_qla80XX(ha))
1778 max_chap_entries = (ha->hw.flt_chap_size / 2) /
1779 sizeof(struct ql4_chap_table);
1780 else
1781 max_chap_entries = MAX_CHAP_ENTRIES_40XX;
1782
1783 if (!ha->chap_list) {
1784 ql4_printk(KERN_ERR, ha, "Do not have CHAP table cache\n");
1785 return QLA_ERROR;
1786 }
1787
1788 if (!username || !password) {
1789 ql4_printk(KERN_ERR, ha, "Do not have username and psw\n");
1790 return QLA_ERROR;
1791 }
1792
1793 mutex_lock(&ha->chap_sem);
1794 for (i = 0; i < max_chap_entries; i++) {
1795 chap_table = (struct ql4_chap_table *)ha->chap_list + i;
1796 if (chap_table->cookie !=
1797 __constant_cpu_to_le16(CHAP_VALID_COOKIE)) {
1798 if (i > MAX_RESRV_CHAP_IDX && free_index == -1)
1799 free_index = i;
1800 continue;
1801 }
1802 if (bidi) {
1803 if (chap_table->flags & BIT_7)
1804 continue;
1805 } else {
1806 if (chap_table->flags & BIT_6)
1807 continue;
1808 }
1809 if (!strncmp(chap_table->secret, password,
1810 MAX_CHAP_SECRET_LEN) &&
1811 !strncmp(chap_table->name, username,
1812 MAX_CHAP_NAME_LEN)) {
1813 *chap_index = i;
1814 found_index = 1;
1815 break;
1816 }
1817 }
1818
1819 /* If chap entry is not present and a free index is available then
1820 * write the entry in flash
1821 */
1822 if (!found_index && free_index != -1) {
1823 rval = qla4xxx_set_chap(ha, username, password,
1824 free_index, bidi);
1825 if (!rval) {
1826 *chap_index = free_index;
1827 found_index = 1;
1828 }
1829 }
1830
1831 mutex_unlock(&ha->chap_sem);
1832
1833 if (found_index)
1834 return QLA_SUCCESS;
1835 return QLA_ERROR;
1836 }
1837
1838 int qla4xxx_conn_close_sess_logout(struct scsi_qla_host *ha,
1839 uint16_t fw_ddb_index,
1840 uint16_t connection_id,
1841 uint16_t option)
1842 {
1843 uint32_t mbox_cmd[MBOX_REG_COUNT];
1844 uint32_t mbox_sts[MBOX_REG_COUNT];
1845 int status = QLA_SUCCESS;
1846
1847 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1848 memset(&mbox_sts, 0, sizeof(mbox_sts));
1849
1850 mbox_cmd[0] = MBOX_CMD_CONN_CLOSE_SESS_LOGOUT;
1851 mbox_cmd[1] = fw_ddb_index;
1852 mbox_cmd[2] = connection_id;
1853 mbox_cmd[3] = option;
1854
1855 status = qla4xxx_mailbox_command(ha, 4, 2, &mbox_cmd[0], &mbox_sts[0]);
1856 if (status != QLA_SUCCESS) {
1857 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_CONN_CLOSE "
1858 "option %04x failed w/ status %04X %04X\n",
1859 __func__, option, mbox_sts[0], mbox_sts[1]));
1860 }
1861 return status;
1862 }
1863
1864 /**
1865 * qla4_84xx_extend_idc_tmo - Extend IDC Timeout.
1866 * @ha: Pointer to host adapter structure.
1867 * @ext_tmo: idc timeout value
1868 *
1869 * Requests firmware to extend the idc timeout value.
1870 **/
1871 static int qla4_84xx_extend_idc_tmo(struct scsi_qla_host *ha, uint32_t ext_tmo)
1872 {
1873 uint32_t mbox_cmd[MBOX_REG_COUNT];
1874 uint32_t mbox_sts[MBOX_REG_COUNT];
1875 int status;
1876
1877 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1878 memset(&mbox_sts, 0, sizeof(mbox_sts));
1879 ext_tmo &= 0xf;
1880
1881 mbox_cmd[0] = MBOX_CMD_IDC_TIME_EXTEND;
1882 mbox_cmd[1] = ((ha->idc_info.request_desc & 0xfffff0ff) |
1883 (ext_tmo << 8)); /* new timeout */
1884 mbox_cmd[2] = ha->idc_info.info1;
1885 mbox_cmd[3] = ha->idc_info.info2;
1886 mbox_cmd[4] = ha->idc_info.info3;
1887
1888 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
1889 mbox_cmd, mbox_sts);
1890 if (status != QLA_SUCCESS) {
1891 DEBUG2(ql4_printk(KERN_INFO, ha,
1892 "scsi%ld: %s: failed status %04X\n",
1893 ha->host_no, __func__, mbox_sts[0]));
1894 return QLA_ERROR;
1895 } else {
1896 ql4_printk(KERN_INFO, ha, "%s: IDC timeout extended by %d secs\n",
1897 __func__, ext_tmo);
1898 }
1899
1900 return QLA_SUCCESS;
1901 }
1902
1903 int qla4xxx_disable_acb(struct scsi_qla_host *ha)
1904 {
1905 uint32_t mbox_cmd[MBOX_REG_COUNT];
1906 uint32_t mbox_sts[MBOX_REG_COUNT];
1907 int status = QLA_SUCCESS;
1908
1909 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1910 memset(&mbox_sts, 0, sizeof(mbox_sts));
1911
1912 mbox_cmd[0] = MBOX_CMD_DISABLE_ACB;
1913
1914 status = qla4xxx_mailbox_command(ha, 8, 5, &mbox_cmd[0], &mbox_sts[0]);
1915 if (status != QLA_SUCCESS) {
1916 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_DISABLE_ACB "
1917 "failed w/ status %04X %04X %04X", __func__,
1918 mbox_sts[0], mbox_sts[1], mbox_sts[2]));
1919 } else {
1920 if (is_qla8042(ha) &&
1921 (mbox_sts[0] != MBOX_STS_COMMAND_COMPLETE)) {
1922 /*
1923 * Disable ACB mailbox command takes time to complete
1924 * based on the total number of targets connected.
1925 * For 512 targets, it took approximately 5 secs to
1926 * complete. Setting the timeout value to 8, with the 3
1927 * secs buffer.
1928 */
1929 qla4_84xx_extend_idc_tmo(ha, IDC_EXTEND_TOV);
1930 if (!wait_for_completion_timeout(&ha->disable_acb_comp,
1931 IDC_EXTEND_TOV * HZ)) {
1932 ql4_printk(KERN_WARNING, ha, "%s: Disable ACB Completion not received\n",
1933 __func__);
1934 }
1935 }
1936 }
1937 return status;
1938 }
1939
1940 int qla4xxx_get_acb(struct scsi_qla_host *ha, dma_addr_t acb_dma,
1941 uint32_t acb_type, uint32_t len)
1942 {
1943 uint32_t mbox_cmd[MBOX_REG_COUNT];
1944 uint32_t mbox_sts[MBOX_REG_COUNT];
1945 int status = QLA_SUCCESS;
1946
1947 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
1948 memset(&mbox_sts, 0, sizeof(mbox_sts));
1949
1950 mbox_cmd[0] = MBOX_CMD_GET_ACB;
1951 mbox_cmd[1] = acb_type;
1952 mbox_cmd[2] = LSDW(acb_dma);
1953 mbox_cmd[3] = MSDW(acb_dma);
1954 mbox_cmd[4] = len;
1955
1956 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1957 if (status != QLA_SUCCESS) {
1958 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_GET_ACB "
1959 "failed w/ status %04X\n", __func__,
1960 mbox_sts[0]));
1961 }
1962 return status;
1963 }
1964
1965 int qla4xxx_set_acb(struct scsi_qla_host *ha, uint32_t *mbox_cmd,
1966 uint32_t *mbox_sts, dma_addr_t acb_dma)
1967 {
1968 int status = QLA_SUCCESS;
1969
1970 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
1971 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
1972 mbox_cmd[0] = MBOX_CMD_SET_ACB;
1973 mbox_cmd[1] = 0; /* Primary ACB */
1974 mbox_cmd[2] = LSDW(acb_dma);
1975 mbox_cmd[3] = MSDW(acb_dma);
1976 mbox_cmd[4] = sizeof(struct addr_ctrl_blk);
1977
1978 status = qla4xxx_mailbox_command(ha, 5, 5, &mbox_cmd[0], &mbox_sts[0]);
1979 if (status != QLA_SUCCESS) {
1980 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: MBOX_CMD_SET_ACB "
1981 "failed w/ status %04X\n", __func__,
1982 mbox_sts[0]));
1983 }
1984 return status;
1985 }
1986
1987 int qla4xxx_set_param_ddbentry(struct scsi_qla_host *ha,
1988 struct ddb_entry *ddb_entry,
1989 struct iscsi_cls_conn *cls_conn,
1990 uint32_t *mbx_sts)
1991 {
1992 struct dev_db_entry *fw_ddb_entry;
1993 struct iscsi_conn *conn;
1994 struct iscsi_session *sess;
1995 struct qla_conn *qla_conn;
1996 struct sockaddr *dst_addr;
1997 dma_addr_t fw_ddb_entry_dma;
1998 int status = QLA_SUCCESS;
1999 int rval = 0;
2000 struct sockaddr_in *addr;
2001 struct sockaddr_in6 *addr6;
2002 char *ip;
2003 uint16_t iscsi_opts = 0;
2004 uint32_t options = 0;
2005 uint16_t idx, *ptid;
2006
2007 fw_ddb_entry = dma_alloc_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
2008 &fw_ddb_entry_dma, GFP_KERNEL);
2009 if (!fw_ddb_entry) {
2010 DEBUG2(ql4_printk(KERN_ERR, ha,
2011 "%s: Unable to allocate dma buffer.\n",
2012 __func__));
2013 rval = -ENOMEM;
2014 goto exit_set_param_no_free;
2015 }
2016
2017 conn = cls_conn->dd_data;
2018 qla_conn = conn->dd_data;
2019 sess = conn->session;
2020 dst_addr = (struct sockaddr *)&qla_conn->qla_ep->dst_addr;
2021
2022 if (dst_addr->sa_family == AF_INET6)
2023 options |= IPV6_DEFAULT_DDB_ENTRY;
2024
2025 status = qla4xxx_get_default_ddb(ha, options, fw_ddb_entry_dma);
2026 if (status == QLA_ERROR) {
2027 rval = -EINVAL;
2028 goto exit_set_param;
2029 }
2030
2031 ptid = (uint16_t *)&fw_ddb_entry->isid[1];
2032 *ptid = cpu_to_le16((uint16_t)ddb_entry->sess->target_id);
2033
2034 DEBUG2(ql4_printk(KERN_INFO, ha, "ISID [%02x%02x%02x%02x%02x%02x]\n",
2035 fw_ddb_entry->isid[5], fw_ddb_entry->isid[4],
2036 fw_ddb_entry->isid[3], fw_ddb_entry->isid[2],
2037 fw_ddb_entry->isid[1], fw_ddb_entry->isid[0]));
2038
2039 iscsi_opts = le16_to_cpu(fw_ddb_entry->iscsi_options);
2040 memset(fw_ddb_entry->iscsi_alias, 0, sizeof(fw_ddb_entry->iscsi_alias));
2041
2042 memset(fw_ddb_entry->iscsi_name, 0, sizeof(fw_ddb_entry->iscsi_name));
2043
2044 if (sess->targetname != NULL) {
2045 memcpy(fw_ddb_entry->iscsi_name, sess->targetname,
2046 min(strlen(sess->targetname),
2047 sizeof(fw_ddb_entry->iscsi_name)));
2048 }
2049
2050 memset(fw_ddb_entry->ip_addr, 0, sizeof(fw_ddb_entry->ip_addr));
2051 memset(fw_ddb_entry->tgt_addr, 0, sizeof(fw_ddb_entry->tgt_addr));
2052
2053 fw_ddb_entry->options = DDB_OPT_TARGET | DDB_OPT_AUTO_SENDTGTS_DISABLE;
2054
2055 if (dst_addr->sa_family == AF_INET) {
2056 addr = (struct sockaddr_in *)dst_addr;
2057 ip = (char *)&addr->sin_addr;
2058 memcpy(fw_ddb_entry->ip_addr, ip, IP_ADDR_LEN);
2059 fw_ddb_entry->port = cpu_to_le16(ntohs(addr->sin_port));
2060 DEBUG2(ql4_printk(KERN_INFO, ha,
2061 "%s: Destination Address [%pI4]: index [%d]\n",
2062 __func__, fw_ddb_entry->ip_addr,
2063 ddb_entry->fw_ddb_index));
2064 } else if (dst_addr->sa_family == AF_INET6) {
2065 addr6 = (struct sockaddr_in6 *)dst_addr;
2066 ip = (char *)&addr6->sin6_addr;
2067 memcpy(fw_ddb_entry->ip_addr, ip, IPv6_ADDR_LEN);
2068 fw_ddb_entry->port = cpu_to_le16(ntohs(addr6->sin6_port));
2069 fw_ddb_entry->options |= DDB_OPT_IPV6_DEVICE;
2070 DEBUG2(ql4_printk(KERN_INFO, ha,
2071 "%s: Destination Address [%pI6]: index [%d]\n",
2072 __func__, fw_ddb_entry->ip_addr,
2073 ddb_entry->fw_ddb_index));
2074 } else {
2075 ql4_printk(KERN_ERR, ha,
2076 "%s: Failed to get IP Address\n",
2077 __func__);
2078 rval = -EINVAL;
2079 goto exit_set_param;
2080 }
2081
2082 /* CHAP */
2083 if (sess->username != NULL && sess->password != NULL) {
2084 if (strlen(sess->username) && strlen(sess->password)) {
2085 iscsi_opts |= BIT_7;
2086
2087 rval = qla4xxx_get_chap_index(ha, sess->username,
2088 sess->password,
2089 LOCAL_CHAP, &idx);
2090 if (rval)
2091 goto exit_set_param;
2092
2093 fw_ddb_entry->chap_tbl_idx = cpu_to_le16(idx);
2094 }
2095 }
2096
2097 if (sess->username_in != NULL && sess->password_in != NULL) {
2098 /* Check if BIDI CHAP */
2099 if (strlen(sess->username_in) && strlen(sess->password_in)) {
2100 iscsi_opts |= BIT_4;
2101
2102 rval = qla4xxx_get_chap_index(ha, sess->username_in,
2103 sess->password_in,
2104 BIDI_CHAP, &idx);
2105 if (rval)
2106 goto exit_set_param;
2107 }
2108 }
2109
2110 if (sess->initial_r2t_en)
2111 iscsi_opts |= BIT_10;
2112
2113 if (sess->imm_data_en)
2114 iscsi_opts |= BIT_11;
2115
2116 fw_ddb_entry->iscsi_options = cpu_to_le16(iscsi_opts);
2117
2118 if (conn->max_recv_dlength)
2119 fw_ddb_entry->iscsi_max_rcv_data_seg_len =
2120 __constant_cpu_to_le16((conn->max_recv_dlength / BYTE_UNITS));
2121
2122 if (sess->max_r2t)
2123 fw_ddb_entry->iscsi_max_outsnd_r2t = cpu_to_le16(sess->max_r2t);
2124
2125 if (sess->first_burst)
2126 fw_ddb_entry->iscsi_first_burst_len =
2127 __constant_cpu_to_le16((sess->first_burst / BYTE_UNITS));
2128
2129 if (sess->max_burst)
2130 fw_ddb_entry->iscsi_max_burst_len =
2131 __constant_cpu_to_le16((sess->max_burst / BYTE_UNITS));
2132
2133 if (sess->time2wait)
2134 fw_ddb_entry->iscsi_def_time2wait =
2135 cpu_to_le16(sess->time2wait);
2136
2137 if (sess->time2retain)
2138 fw_ddb_entry->iscsi_def_time2retain =
2139 cpu_to_le16(sess->time2retain);
2140
2141 status = qla4xxx_set_ddb_entry(ha, ddb_entry->fw_ddb_index,
2142 fw_ddb_entry_dma, mbx_sts);
2143
2144 if (status != QLA_SUCCESS)
2145 rval = -EINVAL;
2146 exit_set_param:
2147 dma_free_coherent(&ha->pdev->dev, sizeof(*fw_ddb_entry),
2148 fw_ddb_entry, fw_ddb_entry_dma);
2149 exit_set_param_no_free:
2150 return rval;
2151 }
2152
2153 int qla4xxx_get_mgmt_data(struct scsi_qla_host *ha, uint16_t fw_ddb_index,
2154 uint16_t stats_size, dma_addr_t stats_dma)
2155 {
2156 int status = QLA_SUCCESS;
2157 uint32_t mbox_cmd[MBOX_REG_COUNT];
2158 uint32_t mbox_sts[MBOX_REG_COUNT];
2159
2160 memset(mbox_cmd, 0, sizeof(mbox_cmd[0]) * MBOX_REG_COUNT);
2161 memset(mbox_sts, 0, sizeof(mbox_sts[0]) * MBOX_REG_COUNT);
2162 mbox_cmd[0] = MBOX_CMD_GET_MANAGEMENT_DATA;
2163 mbox_cmd[1] = fw_ddb_index;
2164 mbox_cmd[2] = LSDW(stats_dma);
2165 mbox_cmd[3] = MSDW(stats_dma);
2166 mbox_cmd[4] = stats_size;
2167
2168 status = qla4xxx_mailbox_command(ha, 5, 1, &mbox_cmd[0], &mbox_sts[0]);
2169 if (status != QLA_SUCCESS) {
2170 DEBUG2(ql4_printk(KERN_WARNING, ha,
2171 "%s: MBOX_CMD_GET_MANAGEMENT_DATA "
2172 "failed w/ status %04X\n", __func__,
2173 mbox_sts[0]));
2174 }
2175 return status;
2176 }
2177
2178 int qla4xxx_get_ip_state(struct scsi_qla_host *ha, uint32_t acb_idx,
2179 uint32_t ip_idx, uint32_t *sts)
2180 {
2181 uint32_t mbox_cmd[MBOX_REG_COUNT];
2182 uint32_t mbox_sts[MBOX_REG_COUNT];
2183 int status = QLA_SUCCESS;
2184
2185 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2186 memset(&mbox_sts, 0, sizeof(mbox_sts));
2187 mbox_cmd[0] = MBOX_CMD_GET_IP_ADDR_STATE;
2188 mbox_cmd[1] = acb_idx;
2189 mbox_cmd[2] = ip_idx;
2190
2191 status = qla4xxx_mailbox_command(ha, 3, 8, &mbox_cmd[0], &mbox_sts[0]);
2192 if (status != QLA_SUCCESS) {
2193 DEBUG2(ql4_printk(KERN_WARNING, ha, "%s: "
2194 "MBOX_CMD_GET_IP_ADDR_STATE failed w/ "
2195 "status %04X\n", __func__, mbox_sts[0]));
2196 }
2197 memcpy(sts, mbox_sts, sizeof(mbox_sts));
2198 return status;
2199 }
2200
2201 int qla4xxx_get_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
2202 uint32_t offset, uint32_t size)
2203 {
2204 int status = QLA_SUCCESS;
2205 uint32_t mbox_cmd[MBOX_REG_COUNT];
2206 uint32_t mbox_sts[MBOX_REG_COUNT];
2207
2208 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2209 memset(&mbox_sts, 0, sizeof(mbox_sts));
2210
2211 mbox_cmd[0] = MBOX_CMD_GET_NVRAM;
2212 mbox_cmd[1] = LSDW(nvram_dma);
2213 mbox_cmd[2] = MSDW(nvram_dma);
2214 mbox_cmd[3] = offset;
2215 mbox_cmd[4] = size;
2216
2217 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2218 &mbox_sts[0]);
2219 if (status != QLA_SUCCESS) {
2220 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2221 "status %04X\n", ha->host_no, __func__,
2222 mbox_sts[0]));
2223 }
2224 return status;
2225 }
2226
2227 int qla4xxx_set_nvram(struct scsi_qla_host *ha, dma_addr_t nvram_dma,
2228 uint32_t offset, uint32_t size)
2229 {
2230 int status = QLA_SUCCESS;
2231 uint32_t mbox_cmd[MBOX_REG_COUNT];
2232 uint32_t mbox_sts[MBOX_REG_COUNT];
2233
2234 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2235 memset(&mbox_sts, 0, sizeof(mbox_sts));
2236
2237 mbox_cmd[0] = MBOX_CMD_SET_NVRAM;
2238 mbox_cmd[1] = LSDW(nvram_dma);
2239 mbox_cmd[2] = MSDW(nvram_dma);
2240 mbox_cmd[3] = offset;
2241 mbox_cmd[4] = size;
2242
2243 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 1, &mbox_cmd[0],
2244 &mbox_sts[0]);
2245 if (status != QLA_SUCCESS) {
2246 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2247 "status %04X\n", ha->host_no, __func__,
2248 mbox_sts[0]));
2249 }
2250 return status;
2251 }
2252
2253 int qla4xxx_restore_factory_defaults(struct scsi_qla_host *ha,
2254 uint32_t region, uint32_t field0,
2255 uint32_t field1)
2256 {
2257 int status = QLA_SUCCESS;
2258 uint32_t mbox_cmd[MBOX_REG_COUNT];
2259 uint32_t mbox_sts[MBOX_REG_COUNT];
2260
2261 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2262 memset(&mbox_sts, 0, sizeof(mbox_sts));
2263
2264 mbox_cmd[0] = MBOX_CMD_RESTORE_FACTORY_DEFAULTS;
2265 mbox_cmd[3] = region;
2266 mbox_cmd[4] = field0;
2267 mbox_cmd[5] = field1;
2268
2269 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 3, &mbox_cmd[0],
2270 &mbox_sts[0]);
2271 if (status != QLA_SUCCESS) {
2272 DEBUG2(ql4_printk(KERN_ERR, ha, "scsi%ld: %s: failed "
2273 "status %04X\n", ha->host_no, __func__,
2274 mbox_sts[0]));
2275 }
2276 return status;
2277 }
2278
2279 /**
2280 * qla4_8xxx_set_param - set driver version in firmware.
2281 * @ha: Pointer to host adapter structure.
2282 * @param: Parameter to set i.e driver version
2283 **/
2284 int qla4_8xxx_set_param(struct scsi_qla_host *ha, int param)
2285 {
2286 uint32_t mbox_cmd[MBOX_REG_COUNT];
2287 uint32_t mbox_sts[MBOX_REG_COUNT];
2288 uint32_t status;
2289
2290 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2291 memset(&mbox_sts, 0, sizeof(mbox_sts));
2292
2293 mbox_cmd[0] = MBOX_CMD_SET_PARAM;
2294 if (param == SET_DRVR_VERSION) {
2295 mbox_cmd[1] = SET_DRVR_VERSION;
2296 strncpy((char *)&mbox_cmd[2], QLA4XXX_DRIVER_VERSION,
2297 MAX_DRVR_VER_LEN);
2298 } else {
2299 ql4_printk(KERN_ERR, ha, "%s: invalid parameter 0x%x\n",
2300 __func__, param);
2301 status = QLA_ERROR;
2302 goto exit_set_param;
2303 }
2304
2305 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, 2, mbox_cmd,
2306 mbox_sts);
2307 if (status == QLA_ERROR)
2308 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n",
2309 __func__, mbox_sts[0]);
2310
2311 exit_set_param:
2312 return status;
2313 }
2314
2315 /**
2316 * qla4_83xx_post_idc_ack - post IDC ACK
2317 * @ha: Pointer to host adapter structure.
2318 *
2319 * Posts IDC ACK for IDC Request Notification AEN.
2320 **/
2321 int qla4_83xx_post_idc_ack(struct scsi_qla_host *ha)
2322 {
2323 uint32_t mbox_cmd[MBOX_REG_COUNT];
2324 uint32_t mbox_sts[MBOX_REG_COUNT];
2325 int status;
2326
2327 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2328 memset(&mbox_sts, 0, sizeof(mbox_sts));
2329
2330 mbox_cmd[0] = MBOX_CMD_IDC_ACK;
2331 mbox_cmd[1] = ha->idc_info.request_desc;
2332 mbox_cmd[2] = ha->idc_info.info1;
2333 mbox_cmd[3] = ha->idc_info.info2;
2334 mbox_cmd[4] = ha->idc_info.info3;
2335
2336 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2337 mbox_cmd, mbox_sts);
2338 if (status == QLA_ERROR)
2339 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2340 mbox_sts[0]);
2341 else
2342 ql4_printk(KERN_INFO, ha, "%s: IDC ACK posted\n", __func__);
2343
2344 return status;
2345 }
2346
2347 int qla4_84xx_config_acb(struct scsi_qla_host *ha, int acb_config)
2348 {
2349 uint32_t mbox_cmd[MBOX_REG_COUNT];
2350 uint32_t mbox_sts[MBOX_REG_COUNT];
2351 struct addr_ctrl_blk *acb = NULL;
2352 uint32_t acb_len = sizeof(struct addr_ctrl_blk);
2353 int rval = QLA_SUCCESS;
2354 dma_addr_t acb_dma;
2355
2356 acb = dma_alloc_coherent(&ha->pdev->dev,
2357 sizeof(struct addr_ctrl_blk),
2358 &acb_dma, GFP_KERNEL);
2359 if (!acb) {
2360 ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n", __func__);
2361 rval = QLA_ERROR;
2362 goto exit_config_acb;
2363 }
2364 memset(acb, 0, acb_len);
2365
2366 switch (acb_config) {
2367 case ACB_CONFIG_DISABLE:
2368 rval = qla4xxx_get_acb(ha, acb_dma, 0, acb_len);
2369 if (rval != QLA_SUCCESS)
2370 goto exit_free_acb;
2371
2372 rval = qla4xxx_disable_acb(ha);
2373 if (rval != QLA_SUCCESS)
2374 goto exit_free_acb;
2375
2376 if (!ha->saved_acb)
2377 ha->saved_acb = kzalloc(acb_len, GFP_KERNEL);
2378
2379 if (!ha->saved_acb) {
2380 ql4_printk(KERN_ERR, ha, "%s: Unable to alloc acb\n",
2381 __func__);
2382 rval = QLA_ERROR;
2383 goto exit_config_acb;
2384 }
2385 memcpy(ha->saved_acb, acb, acb_len);
2386 break;
2387 case ACB_CONFIG_SET:
2388
2389 if (!ha->saved_acb) {
2390 ql4_printk(KERN_ERR, ha, "%s: Can't set ACB, Saved ACB not available\n",
2391 __func__);
2392 rval = QLA_ERROR;
2393 goto exit_free_acb;
2394 }
2395
2396 memcpy(acb, ha->saved_acb, acb_len);
2397 kfree(ha->saved_acb);
2398 ha->saved_acb = NULL;
2399
2400 rval = qla4xxx_set_acb(ha, &mbox_cmd[0], &mbox_sts[0], acb_dma);
2401 if (rval != QLA_SUCCESS)
2402 goto exit_free_acb;
2403
2404 break;
2405 default:
2406 ql4_printk(KERN_ERR, ha, "%s: Invalid ACB Configuration\n",
2407 __func__);
2408 }
2409
2410 exit_free_acb:
2411 dma_free_coherent(&ha->pdev->dev, sizeof(struct addr_ctrl_blk), acb,
2412 acb_dma);
2413 exit_config_acb:
2414 DEBUG2(ql4_printk(KERN_INFO, ha,
2415 "%s %s\n", __func__,
2416 rval == QLA_SUCCESS ? "SUCCEEDED" : "FAILED"));
2417 return rval;
2418 }
2419
2420 int qla4_83xx_get_port_config(struct scsi_qla_host *ha, uint32_t *config)
2421 {
2422 uint32_t mbox_cmd[MBOX_REG_COUNT];
2423 uint32_t mbox_sts[MBOX_REG_COUNT];
2424 int status;
2425
2426 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2427 memset(&mbox_sts, 0, sizeof(mbox_sts));
2428
2429 mbox_cmd[0] = MBOX_CMD_GET_PORT_CONFIG;
2430
2431 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2432 mbox_cmd, mbox_sts);
2433 if (status == QLA_SUCCESS)
2434 *config = mbox_sts[1];
2435 else
2436 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2437 mbox_sts[0]);
2438
2439 return status;
2440 }
2441
2442 int qla4_83xx_set_port_config(struct scsi_qla_host *ha, uint32_t *config)
2443 {
2444 uint32_t mbox_cmd[MBOX_REG_COUNT];
2445 uint32_t mbox_sts[MBOX_REG_COUNT];
2446 int status;
2447
2448 memset(&mbox_cmd, 0, sizeof(mbox_cmd));
2449 memset(&mbox_sts, 0, sizeof(mbox_sts));
2450
2451 mbox_cmd[0] = MBOX_CMD_SET_PORT_CONFIG;
2452 mbox_cmd[1] = *config;
2453
2454 status = qla4xxx_mailbox_command(ha, MBOX_REG_COUNT, MBOX_REG_COUNT,
2455 mbox_cmd, mbox_sts);
2456 if (status != QLA_SUCCESS)
2457 ql4_printk(KERN_ERR, ha, "%s: failed status %04X\n", __func__,
2458 mbox_sts[0]);
2459
2460 return status;
2461 }
Linux with added FPC-III support