drivers/spi/spi-ath79.c

   1 /*
   2  * SPI controller driver for the Atheros AR71XX/AR724X/AR913X SoCs
   3  *
   4  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This driver has been based on the spi-gpio.c:
   7  *      Copyright (C) 2006,2008 David Brownell
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/workqueue.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/spi/spi.h>
  24 #include <linux/spi/spi_bitbang.h>
  25 #include <linux/bitops.h>
  26 #include <linux/gpio.h>
  27 #include <linux/clk.h>
  28 #include <linux/err.h>
  29
  30 #include <asm/mach-ath79/ar71xx_regs.h>
  31 #include <asm/mach-ath79/ath79_spi_platform.h>
  32
  33 #define DRV_NAME        "ath79-spi"
  34
  35 #define ATH79_SPI_RRW_DELAY_FACTOR      12000
  36 #define MHZ                             (1000 * 1000)
  37
  38 struct ath79_spi {
  39         struct spi_bitbang      bitbang;
  40         u32                     ioc_base;
  41         u32                     reg_ctrl;
  42         void __iomem            *base;
  43         struct clk              *clk;
  44         unsigned                rrw_delay;
  45 };
  46
  47 static inline u32 ath79_spi_rr(struct ath79_spi *sp, unsigned reg)
  48 {
  49         return ioread32(sp->base + reg);
  50 }
  51
  52 static inline void ath79_spi_wr(struct ath79_spi *sp, unsigned reg, u32 val)
  53 {
  54         iowrite32(val, sp->base + reg);
  55 }
  56
  57 static inline struct ath79_spi *ath79_spidev_to_sp(struct spi_device *spi)
  58 {
  59         return spi_master_get_devdata(spi->master);
  60 }
  61
  62 static inline void ath79_spi_delay(struct ath79_spi *sp, unsigned nsecs)
  63 {
  64         if (nsecs > sp->rrw_delay)
  65                 ndelay(nsecs - sp->rrw_delay);
  66 }
  67
  68 static void ath79_spi_chipselect(struct spi_device *spi, int is_active)
  69 {
  70         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
  71         int cs_high = (spi->mode & SPI_CS_HIGH) ? is_active : !is_active;
  72
  73         if (is_active) {
  74                 /* set initial clock polarity */
  75                 if (spi->mode & SPI_CPOL)
  76                         sp->ioc_base |= AR71XX_SPI_IOC_CLK;
  77                 else
  78                         sp->ioc_base &= ~AR71XX_SPI_IOC_CLK;
  79
  80                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  81         }
  82
  83         if (spi->chip_select) {
  84                 struct ath79_spi_controller_data *cdata = spi->controller_data;
  85
  86                 /* SPI is normally active-low */
  87                 gpio_set_value(cdata->gpio, cs_high);
  88         } else {
  89                 if (cs_high)
  90                         sp->ioc_base |= AR71XX_SPI_IOC_CS0;
  91                 else
  92                         sp->ioc_base &= ~AR71XX_SPI_IOC_CS0;
  93
  94                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, sp->ioc_base);
  95         }
  96
  97 }
  98
  99 static void ath79_spi_enable(struct ath79_spi *sp)
 100 {
 101         /* enable GPIO mode */
 102         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, AR71XX_SPI_FS_GPIO);
 103
 104         /* save CTRL register */
 105         sp->reg_ctrl = ath79_spi_rr(sp, AR71XX_SPI_REG_CTRL);
 106         sp->ioc_base = ath79_spi_rr(sp, AR71XX_SPI_REG_IOC);
 107
 108         /* TODO: setup speed? */
 109         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, 0x43);
 110 }
 111
 112 static void ath79_spi_disable(struct ath79_spi *sp)
 113 {
 114         /* restore CTRL register */
 115         ath79_spi_wr(sp, AR71XX_SPI_REG_CTRL, sp->reg_ctrl);
 116         /* disable GPIO mode */
 117         ath79_spi_wr(sp, AR71XX_SPI_REG_FS, 0);
 118 }
 119
 120 static int ath79_spi_setup_cs(struct spi_device *spi)
 121 {
 122         struct ath79_spi_controller_data *cdata;
 123         int status;
 124
 125         cdata = spi->controller_data;
 126         if (spi->chip_select && !cdata)
 127                 return -EINVAL;
 128
 129         status = 0;
 130         if (spi->chip_select) {
 131                 unsigned long flags;
 132
 133                 flags = GPIOF_DIR_OUT;
 134                 if (spi->mode & SPI_CS_HIGH)
 135                         flags |= GPIOF_INIT_HIGH;
 136                 else
 137                         flags |= GPIOF_INIT_LOW;
 138
 139                 status = gpio_request_one(cdata->gpio, flags,
 140                                           dev_name(&spi->dev));
 141         }
 142
 143         return status;
 144 }
 145
 146 static void ath79_spi_cleanup_cs(struct spi_device *spi)
 147 {
 148         if (spi->chip_select) {
 149                 struct ath79_spi_controller_data *cdata = spi->controller_data;
 150                 gpio_free(cdata->gpio);
 151         }
 152 }
 153
 154 static int ath79_spi_setup(struct spi_device *spi)
 155 {
 156         int status = 0;
 157
 158         if (!spi->controller_state) {
 159                 status = ath79_spi_setup_cs(spi);
 160                 if (status)
 161                         return status;
 162         }
 163
 164         status = spi_bitbang_setup(spi);
 165         if (status && !spi->controller_state)
 166                 ath79_spi_cleanup_cs(spi);
 167
 168         return status;
 169 }
 170
 171 static void ath79_spi_cleanup(struct spi_device *spi)
 172 {
 173         ath79_spi_cleanup_cs(spi);
 174         spi_bitbang_cleanup(spi);
 175 }
 176
 177 static u32 ath79_spi_txrx_mode0(struct spi_device *spi, unsigned nsecs,
 178                                u32 word, u8 bits)
 179 {
 180         struct ath79_spi *sp = ath79_spidev_to_sp(spi);
 181         u32 ioc = sp->ioc_base;
 182
 183         /* clock starts at inactive polarity */
 184         for (word <<= (32 - bits); likely(bits); bits--) {
 185                 u32 out;
 186
 187                 if (word & (1 << 31))
 188                         out = ioc | AR71XX_SPI_IOC_DO;
 189                 else
 190                         out = ioc & ~AR71XX_SPI_IOC_DO;
 191
 192                 /* setup MSB (to slave) on trailing edge */
 193                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
 194                 ath79_spi_delay(sp, nsecs);
 195                 ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out | AR71XX_SPI_IOC_CLK);
 196                 ath79_spi_delay(sp, nsecs);
 197                 if (bits == 1)
 198                         ath79_spi_wr(sp, AR71XX_SPI_REG_IOC, out);
 199
 200                 word <<= 1;
 201         }
 202
 203         return ath79_spi_rr(sp, AR71XX_SPI_REG_RDS);
 204 }
 205
 206 static int ath79_spi_probe(struct platform_device *pdev)
 207 {
 208         struct spi_master *master;
 209         struct ath79_spi *sp;
 210         struct ath79_spi_platform_data *pdata;
 211         struct resource *r;
 212         unsigned long rate;
 213         int ret;
 214
 215         master = spi_alloc_master(&pdev->dev, sizeof(*sp));
 216         if (master == NULL) {
 217                 dev_err(&pdev->dev, "failed to allocate spi master\n");
 218                 return -ENOMEM;
 219         }
 220
 221         sp = spi_master_get_devdata(master);
 222         platform_set_drvdata(pdev, sp);
 223
 224         pdata = dev_get_platdata(&pdev->dev);
 225
 226         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
 227         master->setup = ath79_spi_setup;
 228         master->cleanup = ath79_spi_cleanup;
 229         if (pdata) {
 230                 master->bus_num = pdata->bus_num;
 231                 master->num_chipselect = pdata->num_chipselect;
 232         }
 233
 234         sp->bitbang.master = master;
 235         sp->bitbang.chipselect = ath79_spi_chipselect;
 236         sp->bitbang.txrx_word[SPI_MODE_0] = ath79_spi_txrx_mode0;
 237         sp->bitbang.setup_transfer = spi_bitbang_setup_transfer;
 238         sp->bitbang.flags = SPI_CS_HIGH;
 239
 240         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 241         if (r == NULL) {
 242                 ret = -ENOENT;
 243                 goto err_put_master;
 244         }
 245
 246         sp->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 247         if (!sp->base) {
 248                 ret = -ENXIO;
 249                 goto err_put_master;
 250         }
 251
 252         sp->clk = devm_clk_get(&pdev->dev, "ahb");
 253         if (IS_ERR(sp->clk)) {
 254                 ret = PTR_ERR(sp->clk);
 255                 goto err_put_master;
 256         }
 257
 258         ret = clk_enable(sp->clk);
 259         if (ret)
 260                 goto err_put_master;
 261
 262         rate = DIV_ROUND_UP(clk_get_rate(sp->clk), MHZ);
 263         if (!rate) {
 264                 ret = -EINVAL;
 265                 goto err_clk_disable;
 266         }
 267
 268         sp->rrw_delay = ATH79_SPI_RRW_DELAY_FACTOR / rate;
 269         dev_dbg(&pdev->dev, "register read/write delay is %u nsecs\n",
 270                 sp->rrw_delay);
 271
 272         ath79_spi_enable(sp);
 273         ret = spi_bitbang_start(&sp->bitbang);
 274         if (ret)
 275                 goto err_disable;
 276
 277         return 0;
 278
 279 err_disable:
 280         ath79_spi_disable(sp);
 281 err_clk_disable:
 282         clk_disable(sp->clk);
 283 err_put_master:
 284         spi_master_put(sp->bitbang.master);
 285
 286         return ret;
 287 }
 288
 289 static int ath79_spi_remove(struct platform_device *pdev)
 290 {
 291         struct ath79_spi *sp = platform_get_drvdata(pdev);
 292
 293         spi_bitbang_stop(&sp->bitbang);
 294         ath79_spi_disable(sp);
 295         clk_disable(sp->clk);
 296         spi_master_put(sp->bitbang.master);
 297
 298         return 0;
 299 }
 300
 301 static void ath79_spi_shutdown(struct platform_device *pdev)
 302 {
 303         ath79_spi_remove(pdev);
 304 }
 305
 306 static struct platform_driver ath79_spi_driver = {
 307         .probe          = ath79_spi_probe,
 308         .remove         = ath79_spi_remove,
 309         .shutdown       = ath79_spi_shutdown,
 310         .driver         = {
 311                 .name   = DRV_NAME,
 312                 .owner  = THIS_MODULE,
 313         },
 314 };
 315 module_platform_driver(ath79_spi_driver);
 316
 317 MODULE_DESCRIPTION("SPI controller driver for Atheros AR71XX/AR724X/AR913X");
 318 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 319 MODULE_LICENSE("GPL v2");
 320 MODULE_ALIAS("platform:" DRV_NAME);