drivers/spi/spi-fsl-espi.c

   1 /*
   2  * Freescale eSPI controller driver.
   3  *
   4  * Copyright 2010 Freescale Semiconductor, Inc.
   5  *
   6  * This program is free software; you can redistribute  it and/or modify it
   7  * under  the terms of  the GNU General  Public License as published by the
   8  * Free Software Foundation;  either version 2 of the  License, or (at your
   9  * option) any later version.
  10  */
  11 #include <linux/module.h>
  12 #include <linux/delay.h>
  13 #include <linux/irq.h>
  14 #include <linux/spi/spi.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/fsl_devices.h>
  17 #include <linux/mm.h>
  18 #include <linux/of.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_platform.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/err.h>
  24 #include <sysdev/fsl_soc.h>
  25
  26 #include "spi-fsl-lib.h"
  27
  28 /* eSPI Controller registers */
  29 struct fsl_espi_reg {
  30         __be32 mode;            /* 0x000 - eSPI mode register */
  31         __be32 event;           /* 0x004 - eSPI event register */
  32         __be32 mask;            /* 0x008 - eSPI mask register */
  33         __be32 command;         /* 0x00c - eSPI command register */
  34         __be32 transmit;        /* 0x010 - eSPI transmit FIFO access register*/
  35         __be32 receive;         /* 0x014 - eSPI receive FIFO access register*/
  36         u8 res[8];              /* 0x018 - 0x01c reserved */
  37         __be32 csmode[4];       /* 0x020 - 0x02c eSPI cs mode register */
  38 };
  39
  40 struct fsl_espi_transfer {
  41         const void *tx_buf;
  42         void *rx_buf;
  43         unsigned len;
  44         unsigned n_tx;
  45         unsigned n_rx;
  46         unsigned actual_length;
  47         int status;
  48 };
  49
  50 /* eSPI Controller mode register definitions */
  51 #define SPMODE_ENABLE           (1 << 31)
  52 #define SPMODE_LOOP             (1 << 30)
  53 #define SPMODE_TXTHR(x)         ((x) << 8)
  54 #define SPMODE_RXTHR(x)         ((x) << 0)
  55
  56 /* eSPI Controller CS mode register definitions */
  57 #define CSMODE_CI_INACTIVEHIGH  (1 << 31)
  58 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
  59 #define CSMODE_REV              (1 << 29)
  60 #define CSMODE_DIV16            (1 << 28)
  61 #define CSMODE_PM(x)            ((x) << 24)
  62 #define CSMODE_POL_1            (1 << 20)
  63 #define CSMODE_LEN(x)           ((x) << 16)
  64 #define CSMODE_BEF(x)           ((x) << 12)
  65 #define CSMODE_AFT(x)           ((x) << 8)
  66 #define CSMODE_CG(x)            ((x) << 3)
  67
  68 /* Default mode/csmode for eSPI controller */
  69 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
  70 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
  71                 | CSMODE_AFT(0) | CSMODE_CG(1))
  72
  73 /* SPIE register values */
  74 #define SPIE_NE         0x00000200      /* Not empty */
  75 #define SPIE_NF         0x00000100      /* Not full */
  76
  77 /* SPIM register values */
  78 #define SPIM_NE         0x00000200      /* Not empty */
  79 #define SPIM_NF         0x00000100      /* Not full */
  80 #define SPIE_RXCNT(reg)     ((reg >> 24) & 0x3F)
  81 #define SPIE_TXCNT(reg)     ((reg >> 16) & 0x3F)
  82
  83 /* SPCOM register values */
  84 #define SPCOM_CS(x)             ((x) << 30)
  85 #define SPCOM_TRANLEN(x)        ((x) << 0)
  86 #define SPCOM_TRANLEN_MAX       0xFFFF  /* Max transaction length */
  87
  88 static void fsl_espi_change_mode(struct spi_device *spi)
  89 {
  90         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
  91         struct spi_mpc8xxx_cs *cs = spi->controller_state;
  92         struct fsl_espi_reg *reg_base = mspi->reg_base;
  93         __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
  94         __be32 __iomem *espi_mode = &reg_base->mode;
  95         u32 tmp;
  96         unsigned long flags;
  97
  98         /* Turn off IRQs locally to minimize time that SPI is disabled. */
  99         local_irq_save(flags);
 100
 101         /* Turn off SPI unit prior changing mode */
 102         tmp = mpc8xxx_spi_read_reg(espi_mode);
 103         mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
 104         mpc8xxx_spi_write_reg(mode, cs->hw_mode);
 105         mpc8xxx_spi_write_reg(espi_mode, tmp);
 106
 107         local_irq_restore(flags);
 108 }
 109
 110 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
 111 {
 112         u32 data;
 113         u16 data_h;
 114         u16 data_l;
 115         const u32 *tx = mpc8xxx_spi->tx;
 116
 117         if (!tx)
 118                 return 0;
 119
 120         data = *tx++ << mpc8xxx_spi->tx_shift;
 121         data_l = data & 0xffff;
 122         data_h = (data >> 16) & 0xffff;
 123         swab16s(&data_l);
 124         swab16s(&data_h);
 125         data = data_h | data_l;
 126
 127         mpc8xxx_spi->tx = tx;
 128         return data;
 129 }
 130
 131 static int fsl_espi_setup_transfer(struct spi_device *spi,
 132                                         struct spi_transfer *t)
 133 {
 134         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 135         int bits_per_word = 0;
 136         u8 pm;
 137         u32 hz = 0;
 138         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 139
 140         if (t) {
 141                 bits_per_word = t->bits_per_word;
 142                 hz = t->speed_hz;
 143         }
 144
 145         /* spi_transfer level calls that work per-word */
 146         if (!bits_per_word)
 147                 bits_per_word = spi->bits_per_word;
 148
 149         if (!hz)
 150                 hz = spi->max_speed_hz;
 151
 152         cs->rx_shift = 0;
 153         cs->tx_shift = 0;
 154         cs->get_rx = mpc8xxx_spi_rx_buf_u32;
 155         cs->get_tx = mpc8xxx_spi_tx_buf_u32;
 156         if (bits_per_word <= 8) {
 157                 cs->rx_shift = 8 - bits_per_word;
 158         } else {
 159                 cs->rx_shift = 16 - bits_per_word;
 160                 if (spi->mode & SPI_LSB_FIRST)
 161                         cs->get_tx = fsl_espi_tx_buf_lsb;
 162         }
 163
 164         mpc8xxx_spi->rx_shift = cs->rx_shift;
 165         mpc8xxx_spi->tx_shift = cs->tx_shift;
 166         mpc8xxx_spi->get_rx = cs->get_rx;
 167         mpc8xxx_spi->get_tx = cs->get_tx;
 168
 169         bits_per_word = bits_per_word - 1;
 170
 171         /* mask out bits we are going to set */
 172         cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
 173
 174         cs->hw_mode |= CSMODE_LEN(bits_per_word);
 175
 176         if ((mpc8xxx_spi->spibrg / hz) > 64) {
 177                 cs->hw_mode |= CSMODE_DIV16;
 178                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
 179
 180                 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
 181                           "Will use %d Hz instead.\n", dev_name(&spi->dev),
 182                                 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
 183                 if (pm > 33)
 184                         pm = 33;
 185         } else {
 186                 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
 187         }
 188         if (pm)
 189                 pm--;
 190         if (pm < 2)
 191                 pm = 2;
 192
 193         cs->hw_mode |= CSMODE_PM(pm);
 194
 195         fsl_espi_change_mode(spi);
 196         return 0;
 197 }
 198
 199 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
 200                 unsigned int len)
 201 {
 202         u32 word;
 203         struct fsl_espi_reg *reg_base = mspi->reg_base;
 204
 205         mspi->count = len;
 206
 207         /* enable rx ints */
 208         mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
 209
 210         /* transmit word */
 211         word = mspi->get_tx(mspi);
 212         mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 213
 214         return 0;
 215 }
 216
 217 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
 218 {
 219         struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
 220         struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
 221         unsigned int len = t->len;
 222         u8 bits_per_word;
 223         int ret;
 224
 225         bits_per_word = spi->bits_per_word;
 226         if (t->bits_per_word)
 227                 bits_per_word = t->bits_per_word;
 228
 229         mpc8xxx_spi->len = t->len;
 230         len = roundup(len, 4) / 4;
 231
 232         mpc8xxx_spi->tx = t->tx_buf;
 233         mpc8xxx_spi->rx = t->rx_buf;
 234
 235         reinit_completion(&mpc8xxx_spi->done);
 236
 237         /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
 238         if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
 239                 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
 240                                 " beyond the SPCOM[TRANLEN] field\n", t->len);
 241                 return -EINVAL;
 242         }
 243         mpc8xxx_spi_write_reg(&reg_base->command,
 244                 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
 245
 246         ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
 247         if (ret)
 248                 return ret;
 249
 250         wait_for_completion(&mpc8xxx_spi->done);
 251
 252         /* disable rx ints */
 253         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 254
 255         return mpc8xxx_spi->count;
 256 }
 257
 258 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
 259 {
 260         if (cmd) {
 261                 cmd[1] = (u8)(addr >> 16);
 262                 cmd[2] = (u8)(addr >> 8);
 263                 cmd[3] = (u8)(addr >> 0);
 264         }
 265 }
 266
 267 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
 268 {
 269         if (cmd)
 270                 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
 271
 272         return 0;
 273 }
 274
 275 static void fsl_espi_do_trans(struct spi_message *m,
 276                                 struct fsl_espi_transfer *tr)
 277 {
 278         struct spi_device *spi = m->spi;
 279         struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
 280         struct fsl_espi_transfer *espi_trans = tr;
 281         struct spi_message message;
 282         struct spi_transfer *t, *first, trans;
 283         int status = 0;
 284
 285         spi_message_init(&message);
 286         memset(&trans, 0, sizeof(trans));
 287
 288         first = list_first_entry(&m->transfers, struct spi_transfer,
 289                         transfer_list);
 290         list_for_each_entry(t, &m->transfers, transfer_list) {
 291                 if ((first->bits_per_word != t->bits_per_word) ||
 292                         (first->speed_hz != t->speed_hz)) {
 293                         espi_trans->status = -EINVAL;
 294                         dev_err(mspi->dev,
 295                                 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
 296                         return;
 297                 }
 298
 299                 trans.speed_hz = t->speed_hz;
 300                 trans.bits_per_word = t->bits_per_word;
 301                 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
 302         }
 303
 304         trans.len = espi_trans->len;
 305         trans.tx_buf = espi_trans->tx_buf;
 306         trans.rx_buf = espi_trans->rx_buf;
 307         spi_message_add_tail(&trans, &message);
 308
 309         list_for_each_entry(t, &message.transfers, transfer_list) {
 310                 if (t->bits_per_word || t->speed_hz) {
 311                         status = -EINVAL;
 312
 313                         status = fsl_espi_setup_transfer(spi, t);
 314                         if (status < 0)
 315                                 break;
 316                 }
 317
 318                 if (t->len)
 319                         status = fsl_espi_bufs(spi, t);
 320
 321                 if (status) {
 322                         status = -EMSGSIZE;
 323                         break;
 324                 }
 325
 326                 if (t->delay_usecs)
 327                         udelay(t->delay_usecs);
 328         }
 329
 330         espi_trans->status = status;
 331         fsl_espi_setup_transfer(spi, NULL);
 332 }
 333
 334 static void fsl_espi_cmd_trans(struct spi_message *m,
 335                                 struct fsl_espi_transfer *trans, u8 *rx_buff)
 336 {
 337         struct spi_transfer *t;
 338         u8 *local_buf;
 339         int i = 0;
 340         struct fsl_espi_transfer *espi_trans = trans;
 341
 342         local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
 343         if (!local_buf) {
 344                 espi_trans->status = -ENOMEM;
 345                 return;
 346         }
 347
 348         list_for_each_entry(t, &m->transfers, transfer_list) {
 349                 if (t->tx_buf) {
 350                         memcpy(local_buf + i, t->tx_buf, t->len);
 351                         i += t->len;
 352                 }
 353         }
 354
 355         espi_trans->tx_buf = local_buf;
 356         espi_trans->rx_buf = local_buf + espi_trans->n_tx;
 357         fsl_espi_do_trans(m, espi_trans);
 358
 359         espi_trans->actual_length = espi_trans->len;
 360         kfree(local_buf);
 361 }
 362
 363 static void fsl_espi_rw_trans(struct spi_message *m,
 364                                 struct fsl_espi_transfer *trans, u8 *rx_buff)
 365 {
 366         struct fsl_espi_transfer *espi_trans = trans;
 367         unsigned int n_tx = espi_trans->n_tx;
 368         unsigned int n_rx = espi_trans->n_rx;
 369         struct spi_transfer *t;
 370         u8 *local_buf;
 371         u8 *rx_buf = rx_buff;
 372         unsigned int trans_len;
 373         unsigned int addr;
 374         int i, pos, loop;
 375
 376         local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
 377         if (!local_buf) {
 378                 espi_trans->status = -ENOMEM;
 379                 return;
 380         }
 381
 382         for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
 383                 trans_len = n_rx - pos;
 384                 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
 385                         trans_len = SPCOM_TRANLEN_MAX - n_tx;
 386
 387                 i = 0;
 388                 list_for_each_entry(t, &m->transfers, transfer_list) {
 389                         if (t->tx_buf) {
 390                                 memcpy(local_buf + i, t->tx_buf, t->len);
 391                                 i += t->len;
 392                         }
 393                 }
 394
 395                 if (pos > 0) {
 396                         addr = fsl_espi_cmd2addr(local_buf);
 397                         addr += pos;
 398                         fsl_espi_addr2cmd(addr, local_buf);
 399                 }
 400
 401                 espi_trans->n_tx = n_tx;
 402                 espi_trans->n_rx = trans_len;
 403                 espi_trans->len = trans_len + n_tx;
 404                 espi_trans->tx_buf = local_buf;
 405                 espi_trans->rx_buf = local_buf + n_tx;
 406                 fsl_espi_do_trans(m, espi_trans);
 407
 408                 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
 409
 410                 if (loop > 0)
 411                         espi_trans->actual_length += espi_trans->len - n_tx;
 412                 else
 413                         espi_trans->actual_length += espi_trans->len;
 414         }
 415
 416         kfree(local_buf);
 417 }
 418
 419 static void fsl_espi_do_one_msg(struct spi_message *m)
 420 {
 421         struct spi_transfer *t;
 422         u8 *rx_buf = NULL;
 423         unsigned int n_tx = 0;
 424         unsigned int n_rx = 0;
 425         struct fsl_espi_transfer espi_trans;
 426
 427         list_for_each_entry(t, &m->transfers, transfer_list) {
 428                 if (t->tx_buf)
 429                         n_tx += t->len;
 430                 if (t->rx_buf) {
 431                         n_rx += t->len;
 432                         rx_buf = t->rx_buf;
 433                 }
 434         }
 435
 436         espi_trans.n_tx = n_tx;
 437         espi_trans.n_rx = n_rx;
 438         espi_trans.len = n_tx + n_rx;
 439         espi_trans.actual_length = 0;
 440         espi_trans.status = 0;
 441
 442         if (!rx_buf)
 443                 fsl_espi_cmd_trans(m, &espi_trans, NULL);
 444         else
 445                 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
 446
 447         m->actual_length = espi_trans.actual_length;
 448         m->status = espi_trans.status;
 449         m->complete(m->context);
 450 }
 451
 452 static int fsl_espi_setup(struct spi_device *spi)
 453 {
 454         struct mpc8xxx_spi *mpc8xxx_spi;
 455         struct fsl_espi_reg *reg_base;
 456         int retval;
 457         u32 hw_mode;
 458         u32 loop_mode;
 459         struct spi_mpc8xxx_cs *cs = spi->controller_state;
 460
 461         if (!spi->max_speed_hz)
 462                 return -EINVAL;
 463
 464         if (!cs) {
 465                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 466                 if (!cs)
 467                         return -ENOMEM;
 468                 spi->controller_state = cs;
 469         }
 470
 471         mpc8xxx_spi = spi_master_get_devdata(spi->master);
 472         reg_base = mpc8xxx_spi->reg_base;
 473
 474         hw_mode = cs->hw_mode; /* Save original settings */
 475         cs->hw_mode = mpc8xxx_spi_read_reg(
 476                         &reg_base->csmode[spi->chip_select]);
 477         /* mask out bits we are going to set */
 478         cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
 479                          | CSMODE_REV);
 480
 481         if (spi->mode & SPI_CPHA)
 482                 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
 483         if (spi->mode & SPI_CPOL)
 484                 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
 485         if (!(spi->mode & SPI_LSB_FIRST))
 486                 cs->hw_mode |= CSMODE_REV;
 487
 488         /* Handle the loop mode */
 489         loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
 490         loop_mode &= ~SPMODE_LOOP;
 491         if (spi->mode & SPI_LOOP)
 492                 loop_mode |= SPMODE_LOOP;
 493         mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
 494
 495         retval = fsl_espi_setup_transfer(spi, NULL);
 496         if (retval < 0) {
 497                 cs->hw_mode = hw_mode; /* Restore settings */
 498                 return retval;
 499         }
 500         return 0;
 501 }
 502
 503 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
 504 {
 505         struct fsl_espi_reg *reg_base = mspi->reg_base;
 506
 507         /* We need handle RX first */
 508         if (events & SPIE_NE) {
 509                 u32 rx_data, tmp;
 510                 u8 rx_data_8;
 511
 512                 /* Spin until RX is done */
 513                 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
 514                         cpu_relax();
 515                         events = mpc8xxx_spi_read_reg(&reg_base->event);
 516                 }
 517
 518                 if (mspi->len >= 4) {
 519                         rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
 520                 } else {
 521                         tmp = mspi->len;
 522                         rx_data = 0;
 523                         while (tmp--) {
 524                                 rx_data_8 = in_8((u8 *)&reg_base->receive);
 525                                 rx_data |= (rx_data_8 << (tmp * 8));
 526                         }
 527
 528                         rx_data <<= (4 - mspi->len) * 8;
 529                 }
 530
 531                 mspi->len -= 4;
 532
 533                 if (mspi->rx)
 534                         mspi->get_rx(rx_data, mspi);
 535         }
 536
 537         if (!(events & SPIE_NF)) {
 538                 int ret;
 539
 540                 /* spin until TX is done */
 541                 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
 542                                 &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
 543                 if (!ret) {
 544                         dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
 545                         return;
 546                 }
 547         }
 548
 549         /* Clear the events */
 550         mpc8xxx_spi_write_reg(&reg_base->event, events);
 551
 552         mspi->count -= 1;
 553         if (mspi->count) {
 554                 u32 word = mspi->get_tx(mspi);
 555
 556                 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
 557         } else {
 558                 complete(&mspi->done);
 559         }
 560 }
 561
 562 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
 563 {
 564         struct mpc8xxx_spi *mspi = context_data;
 565         struct fsl_espi_reg *reg_base = mspi->reg_base;
 566         irqreturn_t ret = IRQ_NONE;
 567         u32 events;
 568
 569         /* Get interrupt events(tx/rx) */
 570         events = mpc8xxx_spi_read_reg(&reg_base->event);
 571         if (events)
 572                 ret = IRQ_HANDLED;
 573
 574         dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
 575
 576         fsl_espi_cpu_irq(mspi, events);
 577
 578         return ret;
 579 }
 580
 581 static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
 582 {
 583         iounmap(mspi->reg_base);
 584 }
 585
 586 static struct spi_master * fsl_espi_probe(struct device *dev,
 587                 struct resource *mem, unsigned int irq)
 588 {
 589         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 590         struct spi_master *master;
 591         struct mpc8xxx_spi *mpc8xxx_spi;
 592         struct fsl_espi_reg *reg_base;
 593         u32 regval;
 594         int i, ret = 0;
 595
 596         master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
 597         if (!master) {
 598                 ret = -ENOMEM;
 599                 goto err;
 600         }
 601
 602         dev_set_drvdata(dev, master);
 603
 604         ret = mpc8xxx_spi_probe(dev, mem, irq);
 605         if (ret)
 606                 goto err_probe;
 607
 608         master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
 609         master->setup = fsl_espi_setup;
 610
 611         mpc8xxx_spi = spi_master_get_devdata(master);
 612         mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
 613         mpc8xxx_spi->spi_remove = fsl_espi_remove;
 614
 615         mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
 616         if (!mpc8xxx_spi->reg_base) {
 617                 ret = -ENOMEM;
 618                 goto err_probe;
 619         }
 620
 621         reg_base = mpc8xxx_spi->reg_base;
 622
 623         /* Register for SPI Interrupt */
 624         ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
 625                           0, "fsl_espi", mpc8xxx_spi);
 626         if (ret)
 627                 goto free_irq;
 628
 629         if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
 630                 mpc8xxx_spi->rx_shift = 16;
 631                 mpc8xxx_spi->tx_shift = 24;
 632         }
 633
 634         /* SPI controller initializations */
 635         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 636         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 637         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 638         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 639
 640         /* Init eSPI CS mode register */
 641         for (i = 0; i < pdata->max_chipselect; i++)
 642                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
 643
 644         /* Enable SPI interface */
 645         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 646
 647         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 648
 649         ret = spi_register_master(master);
 650         if (ret < 0)
 651                 goto unreg_master;
 652
 653         dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
 654
 655         return master;
 656
 657 unreg_master:
 658         free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
 659 free_irq:
 660         iounmap(mpc8xxx_spi->reg_base);
 661 err_probe:
 662         spi_master_put(master);
 663 err:
 664         return ERR_PTR(ret);
 665 }
 666
 667 static int of_fsl_espi_get_chipselects(struct device *dev)
 668 {
 669         struct device_node *np = dev->of_node;
 670         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 671         const u32 *prop;
 672         int len;
 673
 674         prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
 675         if (!prop || len < sizeof(*prop)) {
 676                 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
 677                 return -EINVAL;
 678         }
 679
 680         pdata->max_chipselect = *prop;
 681         pdata->cs_control = NULL;
 682
 683         return 0;
 684 }
 685
 686 static int of_fsl_espi_probe(struct platform_device *ofdev)
 687 {
 688         struct device *dev = &ofdev->dev;
 689         struct device_node *np = ofdev->dev.of_node;
 690         struct spi_master *master;
 691         struct resource mem;
 692         unsigned int irq;
 693         int ret = -ENOMEM;
 694
 695         ret = of_mpc8xxx_spi_probe(ofdev);
 696         if (ret)
 697                 return ret;
 698
 699         ret = of_fsl_espi_get_chipselects(dev);
 700         if (ret)
 701                 goto err;
 702
 703         ret = of_address_to_resource(np, 0, &mem);
 704         if (ret)
 705                 goto err;
 706
 707         irq = irq_of_parse_and_map(np, 0);
 708         if (!irq) {
 709                 ret = -EINVAL;
 710                 goto err;
 711         }
 712
 713         master = fsl_espi_probe(dev, &mem, irq);
 714         if (IS_ERR(master)) {
 715                 ret = PTR_ERR(master);
 716                 goto err;
 717         }
 718
 719         return 0;
 720
 721 err:
 722         return ret;
 723 }
 724
 725 static int of_fsl_espi_remove(struct platform_device *dev)
 726 {
 727         return mpc8xxx_spi_remove(&dev->dev);
 728 }
 729
 730 #ifdef CONFIG_PM_SLEEP
 731 static int of_fsl_espi_suspend(struct device *dev)
 732 {
 733         struct spi_master *master = dev_get_drvdata(dev);
 734         struct mpc8xxx_spi *mpc8xxx_spi;
 735         struct fsl_espi_reg *reg_base;
 736         u32 regval;
 737         int ret;
 738
 739         mpc8xxx_spi = spi_master_get_devdata(master);
 740         reg_base = mpc8xxx_spi->reg_base;
 741
 742         ret = spi_master_suspend(master);
 743         if (ret) {
 744                 dev_warn(dev, "cannot suspend master\n");
 745                 return ret;
 746         }
 747
 748         regval = mpc8xxx_spi_read_reg(&reg_base->mode);
 749         regval &= ~SPMODE_ENABLE;
 750         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 751
 752         return 0;
 753 }
 754
 755 static int of_fsl_espi_resume(struct device *dev)
 756 {
 757         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 758         struct spi_master *master = dev_get_drvdata(dev);
 759         struct mpc8xxx_spi *mpc8xxx_spi;
 760         struct fsl_espi_reg *reg_base;
 761         u32 regval;
 762         int i;
 763
 764         mpc8xxx_spi = spi_master_get_devdata(master);
 765         reg_base = mpc8xxx_spi->reg_base;
 766
 767         /* SPI controller initializations */
 768         mpc8xxx_spi_write_reg(&reg_base->mode, 0);
 769         mpc8xxx_spi_write_reg(&reg_base->mask, 0);
 770         mpc8xxx_spi_write_reg(&reg_base->command, 0);
 771         mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
 772
 773         /* Init eSPI CS mode register */
 774         for (i = 0; i < pdata->max_chipselect; i++)
 775                 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
 776
 777         /* Enable SPI interface */
 778         regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
 779
 780         mpc8xxx_spi_write_reg(&reg_base->mode, regval);
 781
 782         return spi_master_resume(master);
 783 }
 784 #endif /* CONFIG_PM_SLEEP */
 785
 786 static const struct dev_pm_ops espi_pm = {
 787         SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
 788 };
 789
 790 static const struct of_device_id of_fsl_espi_match[] = {
 791         { .compatible = "fsl,mpc8536-espi" },
 792         {}
 793 };
 794 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
 795
 796 static struct platform_driver fsl_espi_driver = {
 797         .driver = {
 798                 .name = "fsl_espi",
 799                 .owner = THIS_MODULE,
 800                 .of_match_table = of_fsl_espi_match,
 801                 .pm = &espi_pm,
 802         },
 803         .probe          = of_fsl_espi_probe,
 804         .remove         = of_fsl_espi_remove,
 805 };
 806 module_platform_driver(fsl_espi_driver);
 807
 808 MODULE_AUTHOR("Mingkai Hu");
 809 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
 810 MODULE_LICENSE("GPL");