2 * Freescale SPI/eSPI controller driver library.
4 * Maintainer: Kumar Gala
6 * Copyright 2010 Freescale Semiconductor, Inc.
7 * Copyright (C) 2006 Polycom, Inc.
9 * CPM SPI and QE buffer descriptors mode support:
10 * Copyright (c) 2009 MontaVista Software, Inc.
11 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 #ifndef __SPI_FSL_LIB_H__
19 #define __SPI_FSL_LIB_H__
23 /* SPI/eSPI Controller driver's private data. */
28 /* rx & tx bufs from the spi_transfer */
31 #ifdef CONFIG_SPI_FSL_ESPI
36 struct spi_pram __iomem
*pram
;
38 struct cpm_buf_desc __iomem
*tx_bd
;
39 struct cpm_buf_desc __iomem
*rx_bd
;
42 struct spi_transfer
*xfer_in_progress
;
44 /* dma addresses for CPM transfers */
50 dma_addr_t dma_dummy_tx
;
51 dma_addr_t dma_dummy_rx
;
53 /* functions to deal with different sized buffers */
54 void (*get_rx
) (u32 rx_data
, struct mpc8xxx_spi
*);
55 u32(*get_tx
) (struct mpc8xxx_spi
*);
57 /* hooks for different controller driver */
58 void (*spi_do_one_msg
) (struct spi_message
*m
);
59 void (*spi_remove
) (struct mpc8xxx_spi
*mspi
);
64 unsigned nsecs
; /* (clock cycle time)/2 */
66 u32 spibrg
; /* SPIBRG input clock */
67 u32 rx_shift
; /* RX data reg shift when in qe mode */
68 u32 tx_shift
; /* TX data reg shift when in qe mode */
72 #ifdef CONFIG_SPI_FSL_SPI
74 int native_chipselects
;
77 void (*set_shifts
)(u32
*rx_shift
, u32
*tx_shift
,
78 int bits_per_word
, int msb_first
);
81 struct workqueue_struct
*workqueue
;
82 struct work_struct work
;
84 struct list_head queue
;
87 struct completion done
;
90 struct spi_mpc8xxx_cs
{
91 /* functions to deal with different sized buffers */
92 void (*get_rx
) (u32 rx_data
, struct mpc8xxx_spi
*);
93 u32 (*get_tx
) (struct mpc8xxx_spi
*);
94 u32 rx_shift
; /* RX data reg shift when in qe mode */
95 u32 tx_shift
; /* TX data reg shift when in qe mode */
96 u32 hw_mode
; /* Holds HW mode register settings */
99 static inline void mpc8xxx_spi_write_reg(__be32 __iomem
*reg
, u32 val
)
101 iowrite32be(val
, reg
);
104 static inline u32
mpc8xxx_spi_read_reg(__be32 __iomem
*reg
)
106 return ioread32be(reg
);
109 struct mpc8xxx_spi_probe_info
{
110 struct fsl_spi_platform_data pdata
;
115 extern u32
mpc8xxx_spi_tx_buf_u8(struct mpc8xxx_spi
*mpc8xxx_spi
);
116 extern u32
mpc8xxx_spi_tx_buf_u16(struct mpc8xxx_spi
*mpc8xxx_spi
);
117 extern u32
mpc8xxx_spi_tx_buf_u32(struct mpc8xxx_spi
*mpc8xxx_spi
);
118 extern void mpc8xxx_spi_rx_buf_u8(u32 data
, struct mpc8xxx_spi
*mpc8xxx_spi
);
119 extern void mpc8xxx_spi_rx_buf_u16(u32 data
, struct mpc8xxx_spi
*mpc8xxx_spi
);
120 extern void mpc8xxx_spi_rx_buf_u32(u32 data
, struct mpc8xxx_spi
*mpc8xxx_spi
);
122 extern struct mpc8xxx_spi_probe_info
*to_of_pinfo(
123 struct fsl_spi_platform_data
*pdata
);
124 extern int mpc8xxx_spi_bufs(struct mpc8xxx_spi
*mspi
,
125 struct spi_transfer
*t
, unsigned int len
);
126 extern int mpc8xxx_spi_transfer(struct spi_device
*spi
, struct spi_message
*m
);
127 extern void mpc8xxx_spi_cleanup(struct spi_device
*spi
);
128 extern const char *mpc8xxx_spi_strmode(unsigned int flags
);
129 extern int mpc8xxx_spi_probe(struct device
*dev
, struct resource
*mem
,
131 extern int mpc8xxx_spi_remove(struct device
*dev
);
132 extern int of_mpc8xxx_spi_probe(struct platform_device
*ofdev
);
134 #endif /* __SPI_FSL_LIB_H__ */