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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / spi / spi-imx.c
bloba5474ef9d2a0cf4ad7367ee1e0399fae2e982145
1 /*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21 #include <linux/clk.h>
22 #include <linux/completion.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/gpio.h>
26 #include <linux/init.h>
27 #include <linux/interrupt.h>
28 #include <linux/io.h>
29 #include <linux/irq.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/platform_device.h>
33 #include <linux/slab.h>
34 #include <linux/spi/spi.h>
35 #include <linux/spi/spi_bitbang.h>
36 #include <linux/types.h>
37 #include <linux/of.h>
38 #include <linux/of_device.h>
39 #include <linux/of_gpio.h>
40
41 #include <linux/platform_data/spi-imx.h>
42
43 #define DRIVER_NAME "spi_imx"
44
45 #define MXC_CSPIRXDATA 0x00
46 #define MXC_CSPITXDATA 0x04
47 #define MXC_CSPICTRL 0x08
48 #define MXC_CSPIINT 0x0c
49 #define MXC_RESET 0x1c
50
51 /* generic defines to abstract from the different register layouts */
52 #define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53 #define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
55 struct spi_imx_config {
56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
59 u8 cs;
60 };
61
62 enum spi_imx_devtype {
63 IMX1_CSPI,
64 IMX21_CSPI,
65 IMX27_CSPI,
66 IMX31_CSPI,
67 IMX35_CSPI, /* CSPI on all i.mx except above */
68 IMX51_ECSPI, /* ECSPI on i.mx51 and later */
69 };
70
71 struct spi_imx_data;
72
73 struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
78 void (*reset)(struct spi_imx_data *);
79 enum spi_imx_devtype devtype;
80 };
81
82 struct spi_imx_data {
83 struct spi_bitbang bitbang;
84
85 struct completion xfer_done;
86 void __iomem *base;
87 int irq;
88 struct clk *clk_per;
89 struct clk *clk_ipg;
90 unsigned long spi_clk;
91
92 unsigned int count;
93 void (*tx)(struct spi_imx_data *);
94 void (*rx)(struct spi_imx_data *);
95 void *rx_buf;
96 const void *tx_buf;
97 unsigned int txfifo; /* number of words pushed in tx FIFO */
98
99 const struct spi_imx_devtype_data *devtype_data;
100 int chipselect[0];
101 };
102
103 static inline int is_imx27_cspi(struct spi_imx_data *d)
104 {
105 return d->devtype_data->devtype == IMX27_CSPI;
106 }
107
108 static inline int is_imx35_cspi(struct spi_imx_data *d)
109 {
110 return d->devtype_data->devtype == IMX35_CSPI;
111 }
112
113 static inline unsigned spi_imx_get_fifosize(struct spi_imx_data *d)
114 {
115 return (d->devtype_data->devtype == IMX51_ECSPI) ? 64 : 8;
116 }
117
118 #define MXC_SPI_BUF_RX(type) \
119 static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
120 { \
121 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
122 \
123 if (spi_imx->rx_buf) { \
124 *(type *)spi_imx->rx_buf = val; \
125 spi_imx->rx_buf += sizeof(type); \
126 } \
127 }
128
129 #define MXC_SPI_BUF_TX(type) \
130 static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
131 { \
132 type val = 0; \
133 \
134 if (spi_imx->tx_buf) { \
135 val = *(type *)spi_imx->tx_buf; \
136 spi_imx->tx_buf += sizeof(type); \
137 } \
138 \
139 spi_imx->count -= sizeof(type); \
140 \
141 writel(val, spi_imx->base + MXC_CSPITXDATA); \
142 }
143
144 MXC_SPI_BUF_RX(u8)
145 MXC_SPI_BUF_TX(u8)
146 MXC_SPI_BUF_RX(u16)
147 MXC_SPI_BUF_TX(u16)
148 MXC_SPI_BUF_RX(u32)
149 MXC_SPI_BUF_TX(u32)
150
151 /* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
152 * (which is currently not the case in this driver)
153 */
154 static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
155 256, 384, 512, 768, 1024};
156
157 /* MX21, MX27 */
158 static unsigned int spi_imx_clkdiv_1(unsigned int fin,
159 unsigned int fspi, unsigned int max)
160 {
161 int i;
162
163 for (i = 2; i < max; i++)
164 if (fspi * mxc_clkdivs[i] >= fin)
165 return i;
166
167 return max;
168 }
169
170 /* MX1, MX31, MX35, MX51 CSPI */
171 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
172 unsigned int fspi)
173 {
174 int i, div = 4;
175
176 for (i = 0; i < 7; i++) {
177 if (fspi * div >= fin)
178 return i;
179 div <<= 1;
180 }
181
182 return 7;
183 }
184
185 #define MX51_ECSPI_CTRL 0x08
186 #define MX51_ECSPI_CTRL_ENABLE (1 << 0)
187 #define MX51_ECSPI_CTRL_XCH (1 << 2)
188 #define MX51_ECSPI_CTRL_MODE_MASK (0xf << 4)
189 #define MX51_ECSPI_CTRL_POSTDIV_OFFSET 8
190 #define MX51_ECSPI_CTRL_PREDIV_OFFSET 12
191 #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18)
192 #define MX51_ECSPI_CTRL_BL_OFFSET 20
193
194 #define MX51_ECSPI_CONFIG 0x0c
195 #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
196 #define MX51_ECSPI_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
197 #define MX51_ECSPI_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
198 #define MX51_ECSPI_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
199 #define MX51_ECSPI_CONFIG_SCLKCTL(cs) (1 << ((cs) + 20))
200
201 #define MX51_ECSPI_INT 0x10
202 #define MX51_ECSPI_INT_TEEN (1 << 0)
203 #define MX51_ECSPI_INT_RREN (1 << 3)
204
205 #define MX51_ECSPI_STAT 0x18
206 #define MX51_ECSPI_STAT_RR (1 << 3)
207
208 /* MX51 eCSPI */
209 static unsigned int mx51_ecspi_clkdiv(unsigned int fin, unsigned int fspi,
210 unsigned int *fres)
211 {
212 /*
213 * there are two 4-bit dividers, the pre-divider divides by
214 * $pre, the post-divider by 2^$post
215 */
216 unsigned int pre, post;
217
218 if (unlikely(fspi > fin))
219 return 0;
220
221 post = fls(fin) - fls(fspi);
222 if (fin > fspi << post)
223 post++;
224
225 /* now we have: (fin <= fspi << post) with post being minimal */
226
227 post = max(4U, post) - 4;
228 if (unlikely(post > 0xf)) {
229 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
230 __func__, fspi, fin);
231 return 0xff;
232 }
233
234 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
235
236 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
237 __func__, fin, fspi, post, pre);
238
239 /* Resulting frequency for the SCLK line. */
240 *fres = (fin / (pre + 1)) >> post;
241
242 return (pre << MX51_ECSPI_CTRL_PREDIV_OFFSET) |
243 (post << MX51_ECSPI_CTRL_POSTDIV_OFFSET);
244 }
245
246 static void __maybe_unused mx51_ecspi_intctrl(struct spi_imx_data *spi_imx, int enable)
247 {
248 unsigned val = 0;
249
250 if (enable & MXC_INT_TE)
251 val |= MX51_ECSPI_INT_TEEN;
252
253 if (enable & MXC_INT_RR)
254 val |= MX51_ECSPI_INT_RREN;
255
256 writel(val, spi_imx->base + MX51_ECSPI_INT);
257 }
258
259 static void __maybe_unused mx51_ecspi_trigger(struct spi_imx_data *spi_imx)
260 {
261 u32 reg;
262
263 reg = readl(spi_imx->base + MX51_ECSPI_CTRL);
264 reg |= MX51_ECSPI_CTRL_XCH;
265 writel(reg, spi_imx->base + MX51_ECSPI_CTRL);
266 }
267
268 static int __maybe_unused mx51_ecspi_config(struct spi_imx_data *spi_imx,
269 struct spi_imx_config *config)
270 {
271 u32 ctrl = MX51_ECSPI_CTRL_ENABLE, cfg = 0;
272 u32 clk = config->speed_hz, delay;
273
274 /*
275 * The hardware seems to have a race condition when changing modes. The
276 * current assumption is that the selection of the channel arrives
277 * earlier in the hardware than the mode bits when they are written at
278 * the same time.
279 * So set master mode for all channels as we do not support slave mode.
280 */
281 ctrl |= MX51_ECSPI_CTRL_MODE_MASK;
282
283 /* set clock speed */
284 ctrl |= mx51_ecspi_clkdiv(spi_imx->spi_clk, config->speed_hz, &clk);
285
286 /* set chip select to use */
287 ctrl |= MX51_ECSPI_CTRL_CS(config->cs);
288
289 ctrl |= (config->bpw - 1) << MX51_ECSPI_CTRL_BL_OFFSET;
290
291 cfg |= MX51_ECSPI_CONFIG_SBBCTRL(config->cs);
292
293 if (config->mode & SPI_CPHA)
294 cfg |= MX51_ECSPI_CONFIG_SCLKPHA(config->cs);
295
296 if (config->mode & SPI_CPOL) {
297 cfg |= MX51_ECSPI_CONFIG_SCLKPOL(config->cs);
298 cfg |= MX51_ECSPI_CONFIG_SCLKCTL(config->cs);
299 }
300 if (config->mode & SPI_CS_HIGH)
301 cfg |= MX51_ECSPI_CONFIG_SSBPOL(config->cs);
302
303 writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL);
304 writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
305
306 /*
307 * Wait until the changes in the configuration register CONFIGREG
308 * propagate into the hardware. It takes exactly one tick of the
309 * SCLK clock, but we will wait two SCLK clock just to be sure. The
310 * effect of the delay it takes for the hardware to apply changes
311 * is noticable if the SCLK clock run very slow. In such a case, if
312 * the polarity of SCLK should be inverted, the GPIO ChipSelect might
313 * be asserted before the SCLK polarity changes, which would disrupt
314 * the SPI communication as the device on the other end would consider
315 * the change of SCLK polarity as a clock tick already.
316 */
317 delay = (2 * 1000000) / clk;
318 if (likely(delay < 10)) /* SCLK is faster than 100 kHz */
319 udelay(delay);
320 else /* SCLK is _very_ slow */
321 usleep_range(delay, delay + 10);
322
323 return 0;
324 }
325
326 static int __maybe_unused mx51_ecspi_rx_available(struct spi_imx_data *spi_imx)
327 {
328 return readl(spi_imx->base + MX51_ECSPI_STAT) & MX51_ECSPI_STAT_RR;
329 }
330
331 static void __maybe_unused mx51_ecspi_reset(struct spi_imx_data *spi_imx)
332 {
333 /* drain receive buffer */
334 while (mx51_ecspi_rx_available(spi_imx))
335 readl(spi_imx->base + MXC_CSPIRXDATA);
336 }
337
338 #define MX31_INTREG_TEEN (1 << 0)
339 #define MX31_INTREG_RREN (1 << 3)
340
341 #define MX31_CSPICTRL_ENABLE (1 << 0)
342 #define MX31_CSPICTRL_MASTER (1 << 1)
343 #define MX31_CSPICTRL_XCH (1 << 2)
344 #define MX31_CSPICTRL_POL (1 << 4)
345 #define MX31_CSPICTRL_PHA (1 << 5)
346 #define MX31_CSPICTRL_SSCTL (1 << 6)
347 #define MX31_CSPICTRL_SSPOL (1 << 7)
348 #define MX31_CSPICTRL_BC_SHIFT 8
349 #define MX35_CSPICTRL_BL_SHIFT 20
350 #define MX31_CSPICTRL_CS_SHIFT 24
351 #define MX35_CSPICTRL_CS_SHIFT 12
352 #define MX31_CSPICTRL_DR_SHIFT 16
353
354 #define MX31_CSPISTATUS 0x14
355 #define MX31_STATUS_RR (1 << 3)
356
357 /* These functions also work for the i.MX35, but be aware that
358 * the i.MX35 has a slightly different register layout for bits
359 * we do not use here.
360 */
361 static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
362 {
363 unsigned int val = 0;
364
365 if (enable & MXC_INT_TE)
366 val |= MX31_INTREG_TEEN;
367 if (enable & MXC_INT_RR)
368 val |= MX31_INTREG_RREN;
369
370 writel(val, spi_imx->base + MXC_CSPIINT);
371 }
372
373 static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
374 {
375 unsigned int reg;
376
377 reg = readl(spi_imx->base + MXC_CSPICTRL);
378 reg |= MX31_CSPICTRL_XCH;
379 writel(reg, spi_imx->base + MXC_CSPICTRL);
380 }
381
382 static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
383 struct spi_imx_config *config)
384 {
385 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
386 int cs = spi_imx->chipselect[config->cs];
387
388 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
389 MX31_CSPICTRL_DR_SHIFT;
390
391 if (is_imx35_cspi(spi_imx)) {
392 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
393 reg |= MX31_CSPICTRL_SSCTL;
394 } else {
395 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
396 }
397
398 if (config->mode & SPI_CPHA)
399 reg |= MX31_CSPICTRL_PHA;
400 if (config->mode & SPI_CPOL)
401 reg |= MX31_CSPICTRL_POL;
402 if (config->mode & SPI_CS_HIGH)
403 reg |= MX31_CSPICTRL_SSPOL;
404 if (cs < 0)
405 reg |= (cs + 32) <<
406 (is_imx35_cspi(spi_imx) ? MX35_CSPICTRL_CS_SHIFT :
407 MX31_CSPICTRL_CS_SHIFT);
408
409 writel(reg, spi_imx->base + MXC_CSPICTRL);
410
411 return 0;
412 }
413
414 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
415 {
416 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
417 }
418
419 static void __maybe_unused mx31_reset(struct spi_imx_data *spi_imx)
420 {
421 /* drain receive buffer */
422 while (readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR)
423 readl(spi_imx->base + MXC_CSPIRXDATA);
424 }
425
426 #define MX21_INTREG_RR (1 << 4)
427 #define MX21_INTREG_TEEN (1 << 9)
428 #define MX21_INTREG_RREN (1 << 13)
429
430 #define MX21_CSPICTRL_POL (1 << 5)
431 #define MX21_CSPICTRL_PHA (1 << 6)
432 #define MX21_CSPICTRL_SSPOL (1 << 8)
433 #define MX21_CSPICTRL_XCH (1 << 9)
434 #define MX21_CSPICTRL_ENABLE (1 << 10)
435 #define MX21_CSPICTRL_MASTER (1 << 11)
436 #define MX21_CSPICTRL_DR_SHIFT 14
437 #define MX21_CSPICTRL_CS_SHIFT 19
438
439 static void __maybe_unused mx21_intctrl(struct spi_imx_data *spi_imx, int enable)
440 {
441 unsigned int val = 0;
442
443 if (enable & MXC_INT_TE)
444 val |= MX21_INTREG_TEEN;
445 if (enable & MXC_INT_RR)
446 val |= MX21_INTREG_RREN;
447
448 writel(val, spi_imx->base + MXC_CSPIINT);
449 }
450
451 static void __maybe_unused mx21_trigger(struct spi_imx_data *spi_imx)
452 {
453 unsigned int reg;
454
455 reg = readl(spi_imx->base + MXC_CSPICTRL);
456 reg |= MX21_CSPICTRL_XCH;
457 writel(reg, spi_imx->base + MXC_CSPICTRL);
458 }
459
460 static int __maybe_unused mx21_config(struct spi_imx_data *spi_imx,
461 struct spi_imx_config *config)
462 {
463 unsigned int reg = MX21_CSPICTRL_ENABLE | MX21_CSPICTRL_MASTER;
464 int cs = spi_imx->chipselect[config->cs];
465 unsigned int max = is_imx27_cspi(spi_imx) ? 16 : 18;
466
467 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz, max) <<
468 MX21_CSPICTRL_DR_SHIFT;
469 reg |= config->bpw - 1;
470
471 if (config->mode & SPI_CPHA)
472 reg |= MX21_CSPICTRL_PHA;
473 if (config->mode & SPI_CPOL)
474 reg |= MX21_CSPICTRL_POL;
475 if (config->mode & SPI_CS_HIGH)
476 reg |= MX21_CSPICTRL_SSPOL;
477 if (cs < 0)
478 reg |= (cs + 32) << MX21_CSPICTRL_CS_SHIFT;
479
480 writel(reg, spi_imx->base + MXC_CSPICTRL);
481
482 return 0;
483 }
484
485 static int __maybe_unused mx21_rx_available(struct spi_imx_data *spi_imx)
486 {
487 return readl(spi_imx->base + MXC_CSPIINT) & MX21_INTREG_RR;
488 }
489
490 static void __maybe_unused mx21_reset(struct spi_imx_data *spi_imx)
491 {
492 writel(1, spi_imx->base + MXC_RESET);
493 }
494
495 #define MX1_INTREG_RR (1 << 3)
496 #define MX1_INTREG_TEEN (1 << 8)
497 #define MX1_INTREG_RREN (1 << 11)
498
499 #define MX1_CSPICTRL_POL (1 << 4)
500 #define MX1_CSPICTRL_PHA (1 << 5)
501 #define MX1_CSPICTRL_XCH (1 << 8)
502 #define MX1_CSPICTRL_ENABLE (1 << 9)
503 #define MX1_CSPICTRL_MASTER (1 << 10)
504 #define MX1_CSPICTRL_DR_SHIFT 13
505
506 static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
507 {
508 unsigned int val = 0;
509
510 if (enable & MXC_INT_TE)
511 val |= MX1_INTREG_TEEN;
512 if (enable & MXC_INT_RR)
513 val |= MX1_INTREG_RREN;
514
515 writel(val, spi_imx->base + MXC_CSPIINT);
516 }
517
518 static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
519 {
520 unsigned int reg;
521
522 reg = readl(spi_imx->base + MXC_CSPICTRL);
523 reg |= MX1_CSPICTRL_XCH;
524 writel(reg, spi_imx->base + MXC_CSPICTRL);
525 }
526
527 static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
528 struct spi_imx_config *config)
529 {
530 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
531
532 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
533 MX1_CSPICTRL_DR_SHIFT;
534 reg |= config->bpw - 1;
535
536 if (config->mode & SPI_CPHA)
537 reg |= MX1_CSPICTRL_PHA;
538 if (config->mode & SPI_CPOL)
539 reg |= MX1_CSPICTRL_POL;
540
541 writel(reg, spi_imx->base + MXC_CSPICTRL);
542
543 return 0;
544 }
545
546 static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
547 {
548 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
549 }
550
551 static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
552 {
553 writel(1, spi_imx->base + MXC_RESET);
554 }
555
556 static struct spi_imx_devtype_data imx1_cspi_devtype_data = {
557 .intctrl = mx1_intctrl,
558 .config = mx1_config,
559 .trigger = mx1_trigger,
560 .rx_available = mx1_rx_available,
561 .reset = mx1_reset,
562 .devtype = IMX1_CSPI,
563 };
564
565 static struct spi_imx_devtype_data imx21_cspi_devtype_data = {
566 .intctrl = mx21_intctrl,
567 .config = mx21_config,
568 .trigger = mx21_trigger,
569 .rx_available = mx21_rx_available,
570 .reset = mx21_reset,
571 .devtype = IMX21_CSPI,
572 };
573
574 static struct spi_imx_devtype_data imx27_cspi_devtype_data = {
575 /* i.mx27 cspi shares the functions with i.mx21 one */
576 .intctrl = mx21_intctrl,
577 .config = mx21_config,
578 .trigger = mx21_trigger,
579 .rx_available = mx21_rx_available,
580 .reset = mx21_reset,
581 .devtype = IMX27_CSPI,
582 };
583
584 static struct spi_imx_devtype_data imx31_cspi_devtype_data = {
585 .intctrl = mx31_intctrl,
586 .config = mx31_config,
587 .trigger = mx31_trigger,
588 .rx_available = mx31_rx_available,
589 .reset = mx31_reset,
590 .devtype = IMX31_CSPI,
591 };
592
593 static struct spi_imx_devtype_data imx35_cspi_devtype_data = {
594 /* i.mx35 and later cspi shares the functions with i.mx31 one */
595 .intctrl = mx31_intctrl,
596 .config = mx31_config,
597 .trigger = mx31_trigger,
598 .rx_available = mx31_rx_available,
599 .reset = mx31_reset,
600 .devtype = IMX35_CSPI,
601 };
602
603 static struct spi_imx_devtype_data imx51_ecspi_devtype_data = {
604 .intctrl = mx51_ecspi_intctrl,
605 .config = mx51_ecspi_config,
606 .trigger = mx51_ecspi_trigger,
607 .rx_available = mx51_ecspi_rx_available,
608 .reset = mx51_ecspi_reset,
609 .devtype = IMX51_ECSPI,
610 };
611
612 static struct platform_device_id spi_imx_devtype[] = {
613 {
614 .name = "imx1-cspi",
615 .driver_data = (kernel_ulong_t) &imx1_cspi_devtype_data,
616 }, {
617 .name = "imx21-cspi",
618 .driver_data = (kernel_ulong_t) &imx21_cspi_devtype_data,
619 }, {
620 .name = "imx27-cspi",
621 .driver_data = (kernel_ulong_t) &imx27_cspi_devtype_data,
622 }, {
623 .name = "imx31-cspi",
624 .driver_data = (kernel_ulong_t) &imx31_cspi_devtype_data,
625 }, {
626 .name = "imx35-cspi",
627 .driver_data = (kernel_ulong_t) &imx35_cspi_devtype_data,
628 }, {
629 .name = "imx51-ecspi",
630 .driver_data = (kernel_ulong_t) &imx51_ecspi_devtype_data,
631 }, {
632 /* sentinel */
633 }
634 };
635
636 static const struct of_device_id spi_imx_dt_ids[] = {
637 { .compatible = "fsl,imx1-cspi", .data = &imx1_cspi_devtype_data, },
638 { .compatible = "fsl,imx21-cspi", .data = &imx21_cspi_devtype_data, },
639 { .compatible = "fsl,imx27-cspi", .data = &imx27_cspi_devtype_data, },
640 { .compatible = "fsl,imx31-cspi", .data = &imx31_cspi_devtype_data, },
641 { .compatible = "fsl,imx35-cspi", .data = &imx35_cspi_devtype_data, },
642 { .compatible = "fsl,imx51-ecspi", .data = &imx51_ecspi_devtype_data, },
643 { /* sentinel */ }
644 };
645 MODULE_DEVICE_TABLE(of, spi_imx_dt_ids);
646
647 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
648 {
649 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
650 int gpio = spi_imx->chipselect[spi->chip_select];
651 int active = is_active != BITBANG_CS_INACTIVE;
652 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
653
654 if (!gpio_is_valid(gpio))
655 return;
656
657 gpio_set_value(gpio, dev_is_lowactive ^ active);
658 }
659
660 static void spi_imx_push(struct spi_imx_data *spi_imx)
661 {
662 while (spi_imx->txfifo < spi_imx_get_fifosize(spi_imx)) {
663 if (!spi_imx->count)
664 break;
665 spi_imx->tx(spi_imx);
666 spi_imx->txfifo++;
667 }
668
669 spi_imx->devtype_data->trigger(spi_imx);
670 }
671
672 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
673 {
674 struct spi_imx_data *spi_imx = dev_id;
675
676 while (spi_imx->devtype_data->rx_available(spi_imx)) {
677 spi_imx->rx(spi_imx);
678 spi_imx->txfifo--;
679 }
680
681 if (spi_imx->count) {
682 spi_imx_push(spi_imx);
683 return IRQ_HANDLED;
684 }
685
686 if (spi_imx->txfifo) {
687 /* No data left to push, but still waiting for rx data,
688 * enable receive data available interrupt.
689 */
690 spi_imx->devtype_data->intctrl(
691 spi_imx, MXC_INT_RR);
692 return IRQ_HANDLED;
693 }
694
695 spi_imx->devtype_data->intctrl(spi_imx, 0);
696 complete(&spi_imx->xfer_done);
697
698 return IRQ_HANDLED;
699 }
700
701 static int spi_imx_setupxfer(struct spi_device *spi,
702 struct spi_transfer *t)
703 {
704 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
705 struct spi_imx_config config;
706
707 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
708 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
709 config.mode = spi->mode;
710 config.cs = spi->chip_select;
711
712 if (!config.speed_hz)
713 config.speed_hz = spi->max_speed_hz;
714 if (!config.bpw)
715 config.bpw = spi->bits_per_word;
716
717 /* Initialize the functions for transfer */
718 if (config.bpw <= 8) {
719 spi_imx->rx = spi_imx_buf_rx_u8;
720 spi_imx->tx = spi_imx_buf_tx_u8;
721 } else if (config.bpw <= 16) {
722 spi_imx->rx = spi_imx_buf_rx_u16;
723 spi_imx->tx = spi_imx_buf_tx_u16;
724 } else {
725 spi_imx->rx = spi_imx_buf_rx_u32;
726 spi_imx->tx = spi_imx_buf_tx_u32;
727 }
728
729 spi_imx->devtype_data->config(spi_imx, &config);
730
731 return 0;
732 }
733
734 static int spi_imx_transfer(struct spi_device *spi,
735 struct spi_transfer *transfer)
736 {
737 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
738
739 spi_imx->tx_buf = transfer->tx_buf;
740 spi_imx->rx_buf = transfer->rx_buf;
741 spi_imx->count = transfer->len;
742 spi_imx->txfifo = 0;
743
744 init_completion(&spi_imx->xfer_done);
745
746 spi_imx_push(spi_imx);
747
748 spi_imx->devtype_data->intctrl(spi_imx, MXC_INT_TE);
749
750 wait_for_completion(&spi_imx->xfer_done);
751
752 return transfer->len;
753 }
754
755 static int spi_imx_setup(struct spi_device *spi)
756 {
757 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
758 int gpio = spi_imx->chipselect[spi->chip_select];
759
760 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
761 spi->mode, spi->bits_per_word, spi->max_speed_hz);
762
763 if (gpio_is_valid(gpio))
764 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
765
766 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
767
768 return 0;
769 }
770
771 static void spi_imx_cleanup(struct spi_device *spi)
772 {
773 }
774
775 static int
776 spi_imx_prepare_message(struct spi_master *master, struct spi_message *msg)
777 {
778 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
779 int ret;
780
781 ret = clk_enable(spi_imx->clk_per);
782 if (ret)
783 return ret;
784
785 ret = clk_enable(spi_imx->clk_ipg);
786 if (ret) {
787 clk_disable(spi_imx->clk_per);
788 return ret;
789 }
790
791 return 0;
792 }
793
794 static int
795 spi_imx_unprepare_message(struct spi_master *master, struct spi_message *msg)
796 {
797 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
798
799 clk_disable(spi_imx->clk_ipg);
800 clk_disable(spi_imx->clk_per);
801 return 0;
802 }
803
804 static int spi_imx_probe(struct platform_device *pdev)
805 {
806 struct device_node *np = pdev->dev.of_node;
807 const struct of_device_id *of_id =
808 of_match_device(spi_imx_dt_ids, &pdev->dev);
809 struct spi_imx_master *mxc_platform_info =
810 dev_get_platdata(&pdev->dev);
811 struct spi_master *master;
812 struct spi_imx_data *spi_imx;
813 struct resource *res;
814 int i, ret, num_cs;
815
816 if (!np && !mxc_platform_info) {
817 dev_err(&pdev->dev, "can't get the platform data\n");
818 return -EINVAL;
819 }
820
821 ret = of_property_read_u32(np, "fsl,spi-num-chipselects", &num_cs);
822 if (ret < 0) {
823 if (mxc_platform_info)
824 num_cs = mxc_platform_info->num_chipselect;
825 else
826 return ret;
827 }
828
829 master = spi_alloc_master(&pdev->dev,
830 sizeof(struct spi_imx_data) + sizeof(int) * num_cs);
831 if (!master)
832 return -ENOMEM;
833
834 platform_set_drvdata(pdev, master);
835
836 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 32);
837 master->bus_num = pdev->id;
838 master->num_chipselect = num_cs;
839
840 spi_imx = spi_master_get_devdata(master);
841 spi_imx->bitbang.master = master;
842
843 for (i = 0; i < master->num_chipselect; i++) {
844 int cs_gpio = of_get_named_gpio(np, "cs-gpios", i);
845 if (!gpio_is_valid(cs_gpio) && mxc_platform_info)
846 cs_gpio = mxc_platform_info->chipselect[i];
847
848 spi_imx->chipselect[i] = cs_gpio;
849 if (!gpio_is_valid(cs_gpio))
850 continue;
851
852 ret = devm_gpio_request(&pdev->dev, spi_imx->chipselect[i],
853 DRIVER_NAME);
854 if (ret) {
855 dev_err(&pdev->dev, "can't get cs gpios\n");
856 goto out_master_put;
857 }
858 }
859
860 spi_imx->bitbang.chipselect = spi_imx_chipselect;
861 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
862 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
863 spi_imx->bitbang.master->setup = spi_imx_setup;
864 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
865 spi_imx->bitbang.master->prepare_message = spi_imx_prepare_message;
866 spi_imx->bitbang.master->unprepare_message = spi_imx_unprepare_message;
867 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
868
869 init_completion(&spi_imx->xfer_done);
870
871 spi_imx->devtype_data = of_id ? of_id->data :
872 (struct spi_imx_devtype_data *) pdev->id_entry->driver_data;
873
874 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
875 spi_imx->base = devm_ioremap_resource(&pdev->dev, res);
876 if (IS_ERR(spi_imx->base)) {
877 ret = PTR_ERR(spi_imx->base);
878 goto out_master_put;
879 }
880
881 spi_imx->irq = platform_get_irq(pdev, 0);
882 if (spi_imx->irq < 0) {
883 ret = -EINVAL;
884 goto out_master_put;
885 }
886
887 ret = devm_request_irq(&pdev->dev, spi_imx->irq, spi_imx_isr, 0,
888 DRIVER_NAME, spi_imx);
889 if (ret) {
890 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
891 goto out_master_put;
892 }
893
894 spi_imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
895 if (IS_ERR(spi_imx->clk_ipg)) {
896 ret = PTR_ERR(spi_imx->clk_ipg);
897 goto out_master_put;
898 }
899
900 spi_imx->clk_per = devm_clk_get(&pdev->dev, "per");
901 if (IS_ERR(spi_imx->clk_per)) {
902 ret = PTR_ERR(spi_imx->clk_per);
903 goto out_master_put;
904 }
905
906 ret = clk_prepare_enable(spi_imx->clk_per);
907 if (ret)
908 goto out_master_put;
909
910 ret = clk_prepare_enable(spi_imx->clk_ipg);
911 if (ret)
912 goto out_put_per;
913
914 spi_imx->spi_clk = clk_get_rate(spi_imx->clk_per);
915
916 spi_imx->devtype_data->reset(spi_imx);
917
918 spi_imx->devtype_data->intctrl(spi_imx, 0);
919
920 master->dev.of_node = pdev->dev.of_node;
921 ret = spi_bitbang_start(&spi_imx->bitbang);
922 if (ret) {
923 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
924 goto out_clk_put;
925 }
926
927 dev_info(&pdev->dev, "probed\n");
928
929 clk_disable(spi_imx->clk_ipg);
930 clk_disable(spi_imx->clk_per);
931 return ret;
932
933 out_clk_put:
934 clk_disable_unprepare(spi_imx->clk_ipg);
935 out_put_per:
936 clk_disable_unprepare(spi_imx->clk_per);
937 out_master_put:
938 spi_master_put(master);
939
940 return ret;
941 }
942
943 static int spi_imx_remove(struct platform_device *pdev)
944 {
945 struct spi_master *master = platform_get_drvdata(pdev);
946 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
947
948 spi_bitbang_stop(&spi_imx->bitbang);
949
950 writel(0, spi_imx->base + MXC_CSPICTRL);
951 clk_disable_unprepare(spi_imx->clk_ipg);
952 clk_disable_unprepare(spi_imx->clk_per);
953 spi_master_put(master);
954
955 return 0;
956 }
957
958 static struct platform_driver spi_imx_driver = {
959 .driver = {
960 .name = DRIVER_NAME,
961 .owner = THIS_MODULE,
962 .of_match_table = spi_imx_dt_ids,
963 },
964 .id_table = spi_imx_devtype,
965 .probe = spi_imx_probe,
966 .remove = spi_imx_remove,
967 };
968 module_platform_driver(spi_imx_driver);
969
970 MODULE_DESCRIPTION("SPI Master Controller driver");
971 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
972 MODULE_LICENSE("GPL");
973 MODULE_ALIAS("platform:" DRIVER_NAME);
Linux with added FPC-III support