drivers/spi/spi-mpc512x-psc.c

   1 /*
   2  * MPC512x PSC in SPI mode driver.
   3  *
   4  * Copyright (C) 2007,2008 Freescale Semiconductor Inc.
   5  * Original port from 52xx driver:
   6  *      Hongjun Chen <hong-jun.chen@freescale.com>
   7  *
   8  * Fork of mpc52xx_psc_spi.c:
   9  *      Copyright (C) 2006 TOPTICA Photonics AG., Dragos Carp
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General  Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of_address.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_platform.h>
  25 #include <linux/completion.h>
  26 #include <linux/io.h>
  27 #include <linux/delay.h>
  28 #include <linux/clk.h>
  29 #include <linux/spi/spi.h>
  30 #include <linux/fsl_devices.h>
  31 #include <linux/gpio.h>
  32 #include <asm/mpc52xx_psc.h>
  33
  34 struct mpc512x_psc_spi {
  35         void (*cs_control)(struct spi_device *spi, bool on);
  36
  37         /* driver internal data */
  38         struct mpc52xx_psc __iomem *psc;
  39         struct mpc512x_psc_fifo __iomem *fifo;
  40         unsigned int irq;
  41         u8 bits_per_word;
  42         struct clk *clk_mclk;
  43         struct clk *clk_ipg;
  44         u32 mclk_rate;
  45
  46         struct completion txisrdone;
  47 };
  48
  49 /* controller state */
  50 struct mpc512x_psc_spi_cs {
  51         int bits_per_word;
  52         int speed_hz;
  53 };
  54
  55 /* set clock freq, clock ramp, bits per work
  56  * if t is NULL then reset the values to the default values
  57  */
  58 static int mpc512x_psc_spi_transfer_setup(struct spi_device *spi,
  59                                           struct spi_transfer *t)
  60 {
  61         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  62
  63         cs->speed_hz = (t && t->speed_hz)
  64             ? t->speed_hz : spi->max_speed_hz;
  65         cs->bits_per_word = (t && t->bits_per_word)
  66             ? t->bits_per_word : spi->bits_per_word;
  67         cs->bits_per_word = ((cs->bits_per_word + 7) / 8) * 8;
  68         return 0;
  69 }
  70
  71 static void mpc512x_psc_spi_activate_cs(struct spi_device *spi)
  72 {
  73         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
  74         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
  75         struct mpc52xx_psc __iomem *psc = mps->psc;
  76         u32 sicr;
  77         u32 ccr;
  78         int speed;
  79         u16 bclkdiv;
  80
  81         sicr = in_be32(&psc->sicr);
  82
  83         /* Set clock phase and polarity */
  84         if (spi->mode & SPI_CPHA)
  85                 sicr |= 0x00001000;
  86         else
  87                 sicr &= ~0x00001000;
  88
  89         if (spi->mode & SPI_CPOL)
  90                 sicr |= 0x00002000;
  91         else
  92                 sicr &= ~0x00002000;
  93
  94         if (spi->mode & SPI_LSB_FIRST)
  95                 sicr |= 0x10000000;
  96         else
  97                 sicr &= ~0x10000000;
  98         out_be32(&psc->sicr, sicr);
  99
 100         ccr = in_be32(&psc->ccr);
 101         ccr &= 0xFF000000;
 102         speed = cs->speed_hz;
 103         if (!speed)
 104                 speed = 1000000;        /* default 1MHz */
 105         bclkdiv = (mps->mclk_rate / speed) - 1;
 106
 107         ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
 108         out_be32(&psc->ccr, ccr);
 109         mps->bits_per_word = cs->bits_per_word;
 110
 111         if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 112                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 1 : 0);
 113 }
 114
 115 static void mpc512x_psc_spi_deactivate_cs(struct spi_device *spi)
 116 {
 117         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 118
 119         if (mps->cs_control && gpio_is_valid(spi->cs_gpio))
 120                 mps->cs_control(spi, (spi->mode & SPI_CS_HIGH) ? 0 : 1);
 121
 122 }
 123
 124 /* extract and scale size field in txsz or rxsz */
 125 #define MPC512x_PSC_FIFO_SZ(sz) ((sz & 0x7ff) << 2);
 126
 127 #define EOFBYTE 1
 128
 129 static int mpc512x_psc_spi_transfer_rxtx(struct spi_device *spi,
 130                                          struct spi_transfer *t)
 131 {
 132         struct mpc512x_psc_spi *mps = spi_master_get_devdata(spi->master);
 133         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 134         size_t tx_len = t->len;
 135         size_t rx_len = t->len;
 136         u8 *tx_buf = (u8 *)t->tx_buf;
 137         u8 *rx_buf = (u8 *)t->rx_buf;
 138
 139         if (!tx_buf && !rx_buf && t->len)
 140                 return -EINVAL;
 141
 142         while (rx_len || tx_len) {
 143                 size_t txcount;
 144                 u8 data;
 145                 size_t fifosz;
 146                 size_t rxcount;
 147                 int rxtries;
 148
 149                 /*
 150                  * send the TX bytes in as large a chunk as possible
 151                  * but neither exceed the TX nor the RX FIFOs
 152                  */
 153                 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->txsz));
 154                 txcount = min(fifosz, tx_len);
 155                 fifosz = MPC512x_PSC_FIFO_SZ(in_be32(&fifo->rxsz));
 156                 fifosz -= in_be32(&fifo->rxcnt) + 1;
 157                 txcount = min(fifosz, txcount);
 158                 if (txcount) {
 159
 160                         /* fill the TX FIFO */
 161                         while (txcount-- > 0) {
 162                                 data = tx_buf ? *tx_buf++ : 0;
 163                                 if (tx_len == EOFBYTE && t->cs_change)
 164                                         setbits32(&fifo->txcmd,
 165                                                   MPC512x_PSC_FIFO_EOF);
 166                                 out_8(&fifo->txdata_8, data);
 167                                 tx_len--;
 168                         }
 169
 170                         /* have the ISR trigger when the TX FIFO is empty */
 171                         reinit_completion(&mps->txisrdone);
 172                         out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
 173                         out_be32(&fifo->tximr, MPC512x_PSC_FIFO_EMPTY);
 174                         wait_for_completion(&mps->txisrdone);
 175                 }
 176
 177                 /*
 178                  * consume as much RX data as the FIFO holds, while we
 179                  * iterate over the transfer's TX data length
 180                  *
 181                  * only insist in draining all the remaining RX bytes
 182                  * when the TX bytes were exhausted (that's at the very
 183                  * end of this transfer, not when still iterating over
 184                  * the transfer's chunks)
 185                  */
 186                 rxtries = 50;
 187                 do {
 188
 189                         /*
 190                          * grab whatever was in the FIFO when we started
 191                          * looking, don't bother fetching what was added to
 192                          * the FIFO while we read from it -- we'll return
 193                          * here eventually and prefer sending out remaining
 194                          * TX data
 195                          */
 196                         fifosz = in_be32(&fifo->rxcnt);
 197                         rxcount = min(fifosz, rx_len);
 198                         while (rxcount-- > 0) {
 199                                 data = in_8(&fifo->rxdata_8);
 200                                 if (rx_buf)
 201                                         *rx_buf++ = data;
 202                                 rx_len--;
 203                         }
 204
 205                         /*
 206                          * come back later if there still is TX data to send,
 207                          * bail out of the RX drain loop if all of the TX data
 208                          * was sent and all of the RX data was received (i.e.
 209                          * when the transmission has completed)
 210                          */
 211                         if (tx_len)
 212                                 break;
 213                         if (!rx_len)
 214                                 break;
 215
 216                         /*
 217                          * TX data transmission has completed while RX data
 218                          * is still pending -- that's a transient situation
 219                          * which depends on wire speed and specific
 220                          * hardware implementation details (buffering) yet
 221                          * should resolve very quickly
 222                          *
 223                          * just yield for a moment to not hog the CPU for
 224                          * too long when running SPI at low speed
 225                          *
 226                          * the timeout range is rather arbitrary and tries
 227                          * to balance throughput against system load; the
 228                          * chosen values result in a minimal timeout of 50
 229                          * times 10us and thus work at speeds as low as
 230                          * some 20kbps, while the maximum timeout at the
 231                          * transfer's end could be 5ms _if_ nothing else
 232                          * ticks in the system _and_ RX data still wasn't
 233                          * received, which only occurs in situations that
 234                          * are exceptional; removing the unpredictability
 235                          * of the timeout either decreases throughput
 236                          * (longer timeouts), or puts more load on the
 237                          * system (fixed short timeouts) or requires the
 238                          * use of a timeout API instead of a counter and an
 239                          * unknown inner delay
 240                          */
 241                         usleep_range(10, 100);
 242
 243                 } while (--rxtries > 0);
 244                 if (!tx_len && rx_len && !rxtries) {
 245                         /*
 246                          * not enough RX bytes even after several retries
 247                          * and the resulting rather long timeout?
 248                          */
 249                         rxcount = in_be32(&fifo->rxcnt);
 250                         dev_warn(&spi->dev,
 251                                  "short xfer, missing %zd RX bytes, FIFO level %zd\n",
 252                                  rx_len, rxcount);
 253                 }
 254
 255                 /*
 256                  * drain and drop RX data which "should not be there" in
 257                  * the first place, for undisturbed transmission this turns
 258                  * into a NOP (except for the FIFO level fetch)
 259                  */
 260                 if (!tx_len && !rx_len) {
 261                         while (in_be32(&fifo->rxcnt))
 262                                 in_8(&fifo->rxdata_8);
 263                 }
 264
 265         }
 266         return 0;
 267 }
 268
 269 static int mpc512x_psc_spi_msg_xfer(struct spi_master *master,
 270                                     struct spi_message *m)
 271 {
 272         struct spi_device *spi;
 273         unsigned cs_change;
 274         int status;
 275         struct spi_transfer *t;
 276
 277         spi = m->spi;
 278         cs_change = 1;
 279         status = 0;
 280         list_for_each_entry(t, &m->transfers, transfer_list) {
 281                 if (t->bits_per_word || t->speed_hz) {
 282                         status = mpc512x_psc_spi_transfer_setup(spi, t);
 283                         if (status < 0)
 284                                 break;
 285                 }
 286
 287                 if (cs_change)
 288                         mpc512x_psc_spi_activate_cs(spi);
 289                 cs_change = t->cs_change;
 290
 291                 status = mpc512x_psc_spi_transfer_rxtx(spi, t);
 292                 if (status)
 293                         break;
 294                 m->actual_length += t->len;
 295
 296                 if (t->delay_usecs)
 297                         udelay(t->delay_usecs);
 298
 299                 if (cs_change)
 300                         mpc512x_psc_spi_deactivate_cs(spi);
 301         }
 302
 303         m->status = status;
 304         m->complete(m->context);
 305
 306         if (status || !cs_change)
 307                 mpc512x_psc_spi_deactivate_cs(spi);
 308
 309         mpc512x_psc_spi_transfer_setup(spi, NULL);
 310
 311         spi_finalize_current_message(master);
 312         return status;
 313 }
 314
 315 static int mpc512x_psc_spi_prep_xfer_hw(struct spi_master *master)
 316 {
 317         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 318         struct mpc52xx_psc __iomem *psc = mps->psc;
 319
 320         dev_dbg(&master->dev, "%s()\n", __func__);
 321
 322         /* Zero MR2 */
 323         in_8(&psc->mode);
 324         out_8(&psc->mode, 0x0);
 325
 326         /* enable transmitter/receiver */
 327         out_8(&psc->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
 328
 329         return 0;
 330 }
 331
 332 static int mpc512x_psc_spi_unprep_xfer_hw(struct spi_master *master)
 333 {
 334         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 335         struct mpc52xx_psc __iomem *psc = mps->psc;
 336         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 337
 338         dev_dbg(&master->dev, "%s()\n", __func__);
 339
 340         /* disable transmitter/receiver and fifo interrupt */
 341         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 342         out_be32(&fifo->tximr, 0);
 343
 344         return 0;
 345 }
 346
 347 static int mpc512x_psc_spi_setup(struct spi_device *spi)
 348 {
 349         struct mpc512x_psc_spi_cs *cs = spi->controller_state;
 350         int ret;
 351
 352         if (spi->bits_per_word % 8)
 353                 return -EINVAL;
 354
 355         if (!cs) {
 356                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 357                 if (!cs)
 358                         return -ENOMEM;
 359
 360                 if (gpio_is_valid(spi->cs_gpio)) {
 361                         ret = gpio_request(spi->cs_gpio, dev_name(&spi->dev));
 362                         if (ret) {
 363                                 dev_err(&spi->dev, "can't get CS gpio: %d\n",
 364                                         ret);
 365                                 kfree(cs);
 366                                 return ret;
 367                         }
 368                         gpio_direction_output(spi->cs_gpio,
 369                                         spi->mode & SPI_CS_HIGH ? 0 : 1);
 370                 }
 371
 372                 spi->controller_state = cs;
 373         }
 374
 375         cs->bits_per_word = spi->bits_per_word;
 376         cs->speed_hz = spi->max_speed_hz;
 377
 378         return 0;
 379 }
 380
 381 static void mpc512x_psc_spi_cleanup(struct spi_device *spi)
 382 {
 383         if (gpio_is_valid(spi->cs_gpio))
 384                 gpio_free(spi->cs_gpio);
 385         kfree(spi->controller_state);
 386 }
 387
 388 static int mpc512x_psc_spi_port_config(struct spi_master *master,
 389                                        struct mpc512x_psc_spi *mps)
 390 {
 391         struct mpc52xx_psc __iomem *psc = mps->psc;
 392         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 393         u32 sicr;
 394         u32 ccr;
 395         int speed;
 396         u16 bclkdiv;
 397
 398         /* Reset the PSC into a known state */
 399         out_8(&psc->command, MPC52xx_PSC_RST_RX);
 400         out_8(&psc->command, MPC52xx_PSC_RST_TX);
 401         out_8(&psc->command, MPC52xx_PSC_TX_DISABLE | MPC52xx_PSC_RX_DISABLE);
 402
 403         /* Disable psc interrupts all useful interrupts are in fifo */
 404         out_be16(&psc->isr_imr.imr, 0);
 405
 406         /* Disable fifo interrupts, will be enabled later */
 407         out_be32(&fifo->tximr, 0);
 408         out_be32(&fifo->rximr, 0);
 409
 410         /* Setup fifo slice address and size */
 411         /*out_be32(&fifo->txsz, 0x0fe00004);*/
 412         /*out_be32(&fifo->rxsz, 0x0ff00004);*/
 413
 414         sicr =  0x01000000 |    /* SIM = 0001 -- 8 bit */
 415                 0x00800000 |    /* GenClk = 1 -- internal clk */
 416                 0x00008000 |    /* SPI = 1 */
 417                 0x00004000 |    /* MSTR = 1   -- SPI master */
 418                 0x00000800;     /* UseEOF = 1 -- SS low until EOF */
 419
 420         out_be32(&psc->sicr, sicr);
 421
 422         ccr = in_be32(&psc->ccr);
 423         ccr &= 0xFF000000;
 424         speed = 1000000;        /* default 1MHz */
 425         bclkdiv = (mps->mclk_rate / speed) - 1;
 426         ccr |= (((bclkdiv & 0xff) << 16) | (((bclkdiv >> 8) & 0xff) << 8));
 427         out_be32(&psc->ccr, ccr);
 428
 429         /* Set 2ms DTL delay */
 430         out_8(&psc->ctur, 0x00);
 431         out_8(&psc->ctlr, 0x82);
 432
 433         /* we don't use the alarms */
 434         out_be32(&fifo->rxalarm, 0xfff);
 435         out_be32(&fifo->txalarm, 0);
 436
 437         /* Enable FIFO slices for Rx/Tx */
 438         out_be32(&fifo->rxcmd,
 439                  MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
 440         out_be32(&fifo->txcmd,
 441                  MPC512x_PSC_FIFO_ENABLE_SLICE | MPC512x_PSC_FIFO_ENABLE_DMA);
 442
 443         mps->bits_per_word = 8;
 444
 445         return 0;
 446 }
 447
 448 static irqreturn_t mpc512x_psc_spi_isr(int irq, void *dev_id)
 449 {
 450         struct mpc512x_psc_spi *mps = (struct mpc512x_psc_spi *)dev_id;
 451         struct mpc512x_psc_fifo __iomem *fifo = mps->fifo;
 452
 453         /* clear interrupt and wake up the rx/tx routine */
 454         if (in_be32(&fifo->txisr) &
 455             in_be32(&fifo->tximr) & MPC512x_PSC_FIFO_EMPTY) {
 456                 out_be32(&fifo->txisr, MPC512x_PSC_FIFO_EMPTY);
 457                 out_be32(&fifo->tximr, 0);
 458                 complete(&mps->txisrdone);
 459                 return IRQ_HANDLED;
 460         }
 461         return IRQ_NONE;
 462 }
 463
 464 static void mpc512x_spi_cs_control(struct spi_device *spi, bool onoff)
 465 {
 466         gpio_set_value(spi->cs_gpio, onoff);
 467 }
 468
 469 /* bus_num is used only for the case dev->platform_data == NULL */
 470 static int mpc512x_psc_spi_do_probe(struct device *dev, u32 regaddr,
 471                                               u32 size, unsigned int irq,
 472                                               s16 bus_num)
 473 {
 474         struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
 475         struct mpc512x_psc_spi *mps;
 476         struct spi_master *master;
 477         int ret;
 478         void *tempp;
 479         struct clk *clk;
 480
 481         master = spi_alloc_master(dev, sizeof *mps);
 482         if (master == NULL)
 483                 return -ENOMEM;
 484
 485         dev_set_drvdata(dev, master);
 486         mps = spi_master_get_devdata(master);
 487         mps->irq = irq;
 488
 489         if (pdata == NULL) {
 490                 mps->cs_control = mpc512x_spi_cs_control;
 491                 master->bus_num = bus_num;
 492         } else {
 493                 mps->cs_control = pdata->cs_control;
 494                 master->bus_num = pdata->bus_num;
 495                 master->num_chipselect = pdata->max_chipselect;
 496         }
 497
 498         master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST;
 499         master->setup = mpc512x_psc_spi_setup;
 500         master->prepare_transfer_hardware = mpc512x_psc_spi_prep_xfer_hw;
 501         master->transfer_one_message = mpc512x_psc_spi_msg_xfer;
 502         master->unprepare_transfer_hardware = mpc512x_psc_spi_unprep_xfer_hw;
 503         master->cleanup = mpc512x_psc_spi_cleanup;
 504         master->dev.of_node = dev->of_node;
 505
 506         tempp = devm_ioremap(dev, regaddr, size);
 507         if (!tempp) {
 508                 dev_err(dev, "could not ioremap I/O port range\n");
 509                 ret = -EFAULT;
 510                 goto free_master;
 511         }
 512         mps->psc = tempp;
 513         mps->fifo =
 514                 (struct mpc512x_psc_fifo *)(tempp + sizeof(struct mpc52xx_psc));
 515         ret = devm_request_irq(dev, mps->irq, mpc512x_psc_spi_isr, IRQF_SHARED,
 516                                 "mpc512x-psc-spi", mps);
 517         if (ret)
 518                 goto free_master;
 519         init_completion(&mps->txisrdone);
 520
 521         clk = devm_clk_get(dev, "mclk");
 522         if (IS_ERR(clk)) {
 523                 ret = PTR_ERR(clk);
 524                 goto free_master;
 525         }
 526         ret = clk_prepare_enable(clk);
 527         if (ret)
 528                 goto free_master;
 529         mps->clk_mclk = clk;
 530         mps->mclk_rate = clk_get_rate(clk);
 531
 532         clk = devm_clk_get(dev, "ipg");
 533         if (IS_ERR(clk)) {
 534                 ret = PTR_ERR(clk);
 535                 goto free_mclk_clock;
 536         }
 537         ret = clk_prepare_enable(clk);
 538         if (ret)
 539                 goto free_mclk_clock;
 540         mps->clk_ipg = clk;
 541
 542         ret = mpc512x_psc_spi_port_config(master, mps);
 543         if (ret < 0)
 544                 goto free_ipg_clock;
 545
 546         ret = devm_spi_register_master(dev, master);
 547         if (ret < 0)
 548                 goto free_ipg_clock;
 549
 550         return ret;
 551
 552 free_ipg_clock:
 553         clk_disable_unprepare(mps->clk_ipg);
 554 free_mclk_clock:
 555         clk_disable_unprepare(mps->clk_mclk);
 556 free_master:
 557         spi_master_put(master);
 558
 559         return ret;
 560 }
 561
 562 static int mpc512x_psc_spi_do_remove(struct device *dev)
 563 {
 564         struct spi_master *master = dev_get_drvdata(dev);
 565         struct mpc512x_psc_spi *mps = spi_master_get_devdata(master);
 566
 567         clk_disable_unprepare(mps->clk_mclk);
 568         clk_disable_unprepare(mps->clk_ipg);
 569
 570         return 0;
 571 }
 572
 573 static int mpc512x_psc_spi_of_probe(struct platform_device *op)
 574 {
 575         const u32 *regaddr_p;
 576         u64 regaddr64, size64;
 577         s16 id = -1;
 578
 579         regaddr_p = of_get_address(op->dev.of_node, 0, &size64, NULL);
 580         if (!regaddr_p) {
 581                 dev_err(&op->dev, "Invalid PSC address\n");
 582                 return -EINVAL;
 583         }
 584         regaddr64 = of_translate_address(op->dev.of_node, regaddr_p);
 585
 586         /* get PSC id (0..11, used by port_config) */
 587         id = of_alias_get_id(op->dev.of_node, "spi");
 588         if (id < 0) {
 589                 dev_err(&op->dev, "no alias id for %s\n",
 590                         op->dev.of_node->full_name);
 591                 return id;
 592         }
 593
 594         return mpc512x_psc_spi_do_probe(&op->dev, (u32) regaddr64, (u32) size64,
 595                                 irq_of_parse_and_map(op->dev.of_node, 0), id);
 596 }
 597
 598 static int mpc512x_psc_spi_of_remove(struct platform_device *op)
 599 {
 600         return mpc512x_psc_spi_do_remove(&op->dev);
 601 }
 602
 603 static struct of_device_id mpc512x_psc_spi_of_match[] = {
 604         { .compatible = "fsl,mpc5121-psc-spi", },
 605         {},
 606 };
 607
 608 MODULE_DEVICE_TABLE(of, mpc512x_psc_spi_of_match);
 609
 610 static struct platform_driver mpc512x_psc_spi_of_driver = {
 611         .probe = mpc512x_psc_spi_of_probe,
 612         .remove = mpc512x_psc_spi_of_remove,
 613         .driver = {
 614                 .name = "mpc512x-psc-spi",
 615                 .owner = THIS_MODULE,
 616                 .of_match_table = mpc512x_psc_spi_of_match,
 617         },
 618 };
 619 module_platform_driver(mpc512x_psc_spi_of_driver);
 620
 621 MODULE_AUTHOR("John Rigby");
 622 MODULE_DESCRIPTION("MPC512x PSC SPI Driver");
 623 MODULE_LICENSE("GPL");