drivers/spi/spi-ppc4xx.c

   1 /*
   2  * SPI_PPC4XX SPI controller driver.
   3  *
   4  * Copyright (C) 2007 Gary Jennejohn <garyj@denx.de>
   5  * Copyright 2008 Stefan Roese <sr@denx.de>, DENX Software Engineering
   6  * Copyright 2009 Harris Corporation, Steven A. Falco <sfalco@harris.com>
   7  *
   8  * Based in part on drivers/spi/spi_s3c24xx.c
   9  *
  10  * Copyright (c) 2006 Ben Dooks
  11  * Copyright (c) 2006 Simtec Electronics
  12  *      Ben Dooks <ben@simtec.co.uk>
  13  *
  14  * This program is free software; you can redistribute  it and/or modify it
  15  * under the terms of the GNU General Public License version 2 as published
  16  * by the Free Software Foundation.
  17  */
  18
  19 /*
  20  * The PPC4xx SPI controller has no FIFO so each sent/received byte will
  21  * generate an interrupt to the CPU. This can cause high CPU utilization.
  22  * This driver allows platforms to reduce the interrupt load on the CPU
  23  * during SPI transfers by setting max_speed_hz via the device tree.
  24  */
  25
  26 #include <linux/module.h>
  27 #include <linux/init.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30 #include <linux/errno.h>
  31 #include <linux/wait.h>
  32 #include <linux/of_address.h>
  33 #include <linux/of_irq.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/of_gpio.h>
  36 #include <linux/interrupt.h>
  37 #include <linux/delay.h>
  38
  39 #include <linux/gpio.h>
  40 #include <linux/spi/spi.h>
  41 #include <linux/spi/spi_bitbang.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/dcr.h>
  45 #include <asm/dcr-regs.h>
  46
  47 /* bits in mode register - bit 0 is MSb */
  48
  49 /*
  50  * SPI_PPC4XX_MODE_SCP = 0 means "data latched on trailing edge of clock"
  51  * SPI_PPC4XX_MODE_SCP = 1 means "data latched on leading edge of clock"
  52  * Note: This is the inverse of CPHA.
  53  */
  54 #define SPI_PPC4XX_MODE_SCP     (0x80 >> 3)
  55
  56 /* SPI_PPC4XX_MODE_SPE = 1 means "port enabled" */
  57 #define SPI_PPC4XX_MODE_SPE     (0x80 >> 4)
  58
  59 /*
  60  * SPI_PPC4XX_MODE_RD = 0 means "MSB first" - this is the normal mode
  61  * SPI_PPC4XX_MODE_RD = 1 means "LSB first" - this is bit-reversed mode
  62  * Note: This is identical to SPI_LSB_FIRST.
  63  */
  64 #define SPI_PPC4XX_MODE_RD      (0x80 >> 5)
  65
  66 /*
  67  * SPI_PPC4XX_MODE_CI = 0 means "clock idles low"
  68  * SPI_PPC4XX_MODE_CI = 1 means "clock idles high"
  69  * Note: This is identical to CPOL.
  70  */
  71 #define SPI_PPC4XX_MODE_CI      (0x80 >> 6)
  72
  73 /*
  74  * SPI_PPC4XX_MODE_IL = 0 means "loopback disable"
  75  * SPI_PPC4XX_MODE_IL = 1 means "loopback enable"
  76  */
  77 #define SPI_PPC4XX_MODE_IL      (0x80 >> 7)
  78
  79 /* bits in control register */
  80 /* starts a transfer when set */
  81 #define SPI_PPC4XX_CR_STR       (0x80 >> 7)
  82
  83 /* bits in status register */
  84 /* port is busy with a transfer */
  85 #define SPI_PPC4XX_SR_BSY       (0x80 >> 6)
  86 /* RxD ready */
  87 #define SPI_PPC4XX_SR_RBR       (0x80 >> 7)
  88
  89 /* clock settings (SCP and CI) for various SPI modes */
  90 #define SPI_CLK_MODE0   (SPI_PPC4XX_MODE_SCP | 0)
  91 #define SPI_CLK_MODE1   (0 | 0)
  92 #define SPI_CLK_MODE2   (SPI_PPC4XX_MODE_SCP | SPI_PPC4XX_MODE_CI)
  93 #define SPI_CLK_MODE3   (0 | SPI_PPC4XX_MODE_CI)
  94
  95 #define DRIVER_NAME     "spi_ppc4xx_of"
  96
  97 struct spi_ppc4xx_regs {
  98         u8 mode;
  99         u8 rxd;
 100         u8 txd;
 101         u8 cr;
 102         u8 sr;
 103         u8 dummy;
 104         /*
 105          * Clock divisor modulus register
 106          * This uses the following formula:
 107          *    SCPClkOut = OPBCLK/(4(CDM + 1))
 108          * or
 109          *    CDM = (OPBCLK/4*SCPClkOut) - 1
 110          * bit 0 is the MSb!
 111          */
 112         u8 cdm;
 113 };
 114
 115 /* SPI Controller driver's private data. */
 116 struct ppc4xx_spi {
 117         /* bitbang has to be first */
 118         struct spi_bitbang bitbang;
 119         struct completion done;
 120
 121         u64 mapbase;
 122         u64 mapsize;
 123         int irqnum;
 124         /* need this to set the SPI clock */
 125         unsigned int opb_freq;
 126
 127         /* for transfers */
 128         int len;
 129         int count;
 130         /* data buffers */
 131         const unsigned char *tx;
 132         unsigned char *rx;
 133
 134         int *gpios;
 135
 136         struct spi_ppc4xx_regs __iomem *regs; /* pointer to the registers */
 137         struct spi_master *master;
 138         struct device *dev;
 139 };
 140
 141 /* need this so we can set the clock in the chipselect routine */
 142 struct spi_ppc4xx_cs {
 143         u8 mode;
 144 };
 145
 146 static int spi_ppc4xx_txrx(struct spi_device *spi, struct spi_transfer *t)
 147 {
 148         struct ppc4xx_spi *hw;
 149         u8 data;
 150
 151         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 152                 t->tx_buf, t->rx_buf, t->len);
 153
 154         hw = spi_master_get_devdata(spi->master);
 155
 156         hw->tx = t->tx_buf;
 157         hw->rx = t->rx_buf;
 158         hw->len = t->len;
 159         hw->count = 0;
 160
 161         /* send the first byte */
 162         data = hw->tx ? hw->tx[0] : 0;
 163         out_8(&hw->regs->txd, data);
 164         out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
 165         wait_for_completion(&hw->done);
 166
 167         return hw->count;
 168 }
 169
 170 static int spi_ppc4xx_setupxfer(struct spi_device *spi, struct spi_transfer *t)
 171 {
 172         struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
 173         struct spi_ppc4xx_cs *cs = spi->controller_state;
 174         int scr;
 175         u8 cdm = 0;
 176         u32 speed;
 177         u8 bits_per_word;
 178
 179         /* Start with the generic configuration for this device. */
 180         bits_per_word = spi->bits_per_word;
 181         speed = spi->max_speed_hz;
 182
 183         /*
 184          * Modify the configuration if the transfer overrides it.  Do not allow
 185          * the transfer to overwrite the generic configuration with zeros.
 186          */
 187         if (t) {
 188                 if (t->bits_per_word)
 189                         bits_per_word = t->bits_per_word;
 190
 191                 if (t->speed_hz)
 192                         speed = min(t->speed_hz, spi->max_speed_hz);
 193         }
 194
 195         if (!speed || (speed > spi->max_speed_hz)) {
 196                 dev_err(&spi->dev, "invalid speed_hz (%d)\n", speed);
 197                 return -EINVAL;
 198         }
 199
 200         /* Write new configuration */
 201         out_8(&hw->regs->mode, cs->mode);
 202
 203         /* Set the clock */
 204         /* opb_freq was already divided by 4 */
 205         scr = (hw->opb_freq / speed) - 1;
 206         if (scr > 0)
 207                 cdm = min(scr, 0xff);
 208
 209         dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", cdm, speed);
 210
 211         if (in_8(&hw->regs->cdm) != cdm)
 212                 out_8(&hw->regs->cdm, cdm);
 213
 214         spin_lock(&hw->bitbang.lock);
 215         if (!hw->bitbang.busy) {
 216                 hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
 217                 /* Need to ndelay here? */
 218         }
 219         spin_unlock(&hw->bitbang.lock);
 220
 221         return 0;
 222 }
 223
 224 static int spi_ppc4xx_setup(struct spi_device *spi)
 225 {
 226         struct spi_ppc4xx_cs *cs = spi->controller_state;
 227
 228         if (!spi->max_speed_hz) {
 229                 dev_err(&spi->dev, "invalid max_speed_hz (must be non-zero)\n");
 230                 return -EINVAL;
 231         }
 232
 233         if (cs == NULL) {
 234                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 235                 if (!cs)
 236                         return -ENOMEM;
 237                 spi->controller_state = cs;
 238         }
 239
 240         /*
 241          * We set all bits of the SPI0_MODE register, so,
 242          * no need to read-modify-write
 243          */
 244         cs->mode = SPI_PPC4XX_MODE_SPE;
 245
 246         switch (spi->mode & (SPI_CPHA | SPI_CPOL)) {
 247         case SPI_MODE_0:
 248                 cs->mode |= SPI_CLK_MODE0;
 249                 break;
 250         case SPI_MODE_1:
 251                 cs->mode |= SPI_CLK_MODE1;
 252                 break;
 253         case SPI_MODE_2:
 254                 cs->mode |= SPI_CLK_MODE2;
 255                 break;
 256         case SPI_MODE_3:
 257                 cs->mode |= SPI_CLK_MODE3;
 258                 break;
 259         }
 260
 261         if (spi->mode & SPI_LSB_FIRST)
 262                 cs->mode |= SPI_PPC4XX_MODE_RD;
 263
 264         return 0;
 265 }
 266
 267 static void spi_ppc4xx_chipsel(struct spi_device *spi, int value)
 268 {
 269         struct ppc4xx_spi *hw = spi_master_get_devdata(spi->master);
 270         unsigned int cs = spi->chip_select;
 271         unsigned int cspol;
 272
 273         /*
 274          * If there are no chip selects at all, or if this is the special
 275          * case of a non-existent (dummy) chip select, do nothing.
 276          */
 277
 278         if (!hw->master->num_chipselect || hw->gpios[cs] == -EEXIST)
 279                 return;
 280
 281         cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 282         if (value == BITBANG_CS_INACTIVE)
 283                 cspol = !cspol;
 284
 285         gpio_set_value(hw->gpios[cs], cspol);
 286 }
 287
 288 static irqreturn_t spi_ppc4xx_int(int irq, void *dev_id)
 289 {
 290         struct ppc4xx_spi *hw;
 291         u8 status;
 292         u8 data;
 293         unsigned int count;
 294
 295         hw = (struct ppc4xx_spi *)dev_id;
 296
 297         status = in_8(&hw->regs->sr);
 298         if (!status)
 299                 return IRQ_NONE;
 300
 301         /*
 302          * BSY de-asserts one cycle after the transfer is complete.  The
 303          * interrupt is asserted after the transfer is complete.  The exact
 304          * relationship is not documented, hence this code.
 305          */
 306
 307         if (unlikely(status & SPI_PPC4XX_SR_BSY)) {
 308                 u8 lstatus;
 309                 int cnt = 0;
 310
 311                 dev_dbg(hw->dev, "got interrupt but spi still busy?\n");
 312                 do {
 313                         ndelay(10);
 314                         lstatus = in_8(&hw->regs->sr);
 315                 } while (++cnt < 100 && lstatus & SPI_PPC4XX_SR_BSY);
 316
 317                 if (cnt >= 100) {
 318                         dev_err(hw->dev, "busywait: too many loops!\n");
 319                         complete(&hw->done);
 320                         return IRQ_HANDLED;
 321                 } else {
 322                         /* status is always 1 (RBR) here */
 323                         status = in_8(&hw->regs->sr);
 324                         dev_dbg(hw->dev, "loops %d status %x\n", cnt, status);
 325                 }
 326         }
 327
 328         count = hw->count;
 329         hw->count++;
 330
 331         /* RBR triggered this interrupt.  Therefore, data must be ready. */
 332         data = in_8(&hw->regs->rxd);
 333         if (hw->rx)
 334                 hw->rx[count] = data;
 335
 336         count++;
 337
 338         if (count < hw->len) {
 339                 data = hw->tx ? hw->tx[count] : 0;
 340                 out_8(&hw->regs->txd, data);
 341                 out_8(&hw->regs->cr, SPI_PPC4XX_CR_STR);
 342         } else {
 343                 complete(&hw->done);
 344         }
 345
 346         return IRQ_HANDLED;
 347 }
 348
 349 static void spi_ppc4xx_cleanup(struct spi_device *spi)
 350 {
 351         kfree(spi->controller_state);
 352 }
 353
 354 static void spi_ppc4xx_enable(struct ppc4xx_spi *hw)
 355 {
 356         /*
 357          * On all 4xx PPC's the SPI bus is shared/multiplexed with
 358          * the 2nd I2C bus. We need to enable the the SPI bus before
 359          * using it.
 360          */
 361
 362         /* need to clear bit 14 to enable SPC */
 363         dcri_clrset(SDR0, SDR0_PFC1, 0x80000000 >> 14, 0);
 364 }
 365
 366 static void free_gpios(struct ppc4xx_spi *hw)
 367 {
 368         if (hw->master->num_chipselect) {
 369                 int i;
 370                 for (i = 0; i < hw->master->num_chipselect; i++)
 371                         if (gpio_is_valid(hw->gpios[i]))
 372                                 gpio_free(hw->gpios[i]);
 373
 374                 kfree(hw->gpios);
 375                 hw->gpios = NULL;
 376         }
 377 }
 378
 379 /*
 380  * platform_device layer stuff...
 381  */
 382 static int spi_ppc4xx_of_probe(struct platform_device *op)
 383 {
 384         struct ppc4xx_spi *hw;
 385         struct spi_master *master;
 386         struct spi_bitbang *bbp;
 387         struct resource resource;
 388         struct device_node *np = op->dev.of_node;
 389         struct device *dev = &op->dev;
 390         struct device_node *opbnp;
 391         int ret;
 392         int num_gpios;
 393         const unsigned int *clk;
 394
 395         master = spi_alloc_master(dev, sizeof *hw);
 396         if (master == NULL)
 397                 return -ENOMEM;
 398         master->dev.of_node = np;
 399         platform_set_drvdata(op, master);
 400         hw = spi_master_get_devdata(master);
 401         hw->master = master;
 402         hw->dev = dev;
 403
 404         init_completion(&hw->done);
 405
 406         /*
 407          * A count of zero implies a single SPI device without any chip-select.
 408          * Note that of_gpio_count counts all gpios assigned to this spi master.
 409          * This includes both "null" gpio's and real ones.
 410          */
 411         num_gpios = of_gpio_count(np);
 412         if (num_gpios > 0) {
 413                 int i;
 414
 415                 hw->gpios = kzalloc(sizeof(int) * num_gpios, GFP_KERNEL);
 416                 if (!hw->gpios) {
 417                         ret = -ENOMEM;
 418                         goto free_master;
 419                 }
 420
 421                 for (i = 0; i < num_gpios; i++) {
 422                         int gpio;
 423                         enum of_gpio_flags flags;
 424
 425                         gpio = of_get_gpio_flags(np, i, &flags);
 426                         hw->gpios[i] = gpio;
 427
 428                         if (gpio_is_valid(gpio)) {
 429                                 /* Real CS - set the initial state. */
 430                                 ret = gpio_request(gpio, np->name);
 431                                 if (ret < 0) {
 432                                         dev_err(dev, "can't request gpio "
 433                                                         "#%d: %d\n", i, ret);
 434                                         goto free_gpios;
 435                                 }
 436
 437                                 gpio_direction_output(gpio,
 438                                                 !!(flags & OF_GPIO_ACTIVE_LOW));
 439                         } else if (gpio == -EEXIST) {
 440                                 ; /* No CS, but that's OK. */
 441                         } else {
 442                                 dev_err(dev, "invalid gpio #%d: %d\n", i, gpio);
 443                                 ret = -EINVAL;
 444                                 goto free_gpios;
 445                         }
 446                 }
 447         }
 448
 449         /* Setup the state for the bitbang driver */
 450         bbp = &hw->bitbang;
 451         bbp->master = hw->master;
 452         bbp->setup_transfer = spi_ppc4xx_setupxfer;
 453         bbp->chipselect = spi_ppc4xx_chipsel;
 454         bbp->txrx_bufs = spi_ppc4xx_txrx;
 455         bbp->use_dma = 0;
 456         bbp->master->setup = spi_ppc4xx_setup;
 457         bbp->master->cleanup = spi_ppc4xx_cleanup;
 458         bbp->master->bits_per_word_mask = SPI_BPW_MASK(8);
 459
 460         /* the spi->mode bits understood by this driver: */
 461         bbp->master->mode_bits =
 462                 SPI_CPHA | SPI_CPOL | SPI_CS_HIGH | SPI_LSB_FIRST;
 463
 464         /* this many pins in all GPIO controllers */
 465         bbp->master->num_chipselect = num_gpios > 0 ? num_gpios : 0;
 466
 467         /* Get the clock for the OPB */
 468         opbnp = of_find_compatible_node(NULL, NULL, "ibm,opb");
 469         if (opbnp == NULL) {
 470                 dev_err(dev, "OPB: cannot find node\n");
 471                 ret = -ENODEV;
 472                 goto free_gpios;
 473         }
 474         /* Get the clock (Hz) for the OPB */
 475         clk = of_get_property(opbnp, "clock-frequency", NULL);
 476         if (clk == NULL) {
 477                 dev_err(dev, "OPB: no clock-frequency property set\n");
 478                 of_node_put(opbnp);
 479                 ret = -ENODEV;
 480                 goto free_gpios;
 481         }
 482         hw->opb_freq = *clk;
 483         hw->opb_freq >>= 2;
 484         of_node_put(opbnp);
 485
 486         ret = of_address_to_resource(np, 0, &resource);
 487         if (ret) {
 488                 dev_err(dev, "error while parsing device node resource\n");
 489                 goto free_gpios;
 490         }
 491         hw->mapbase = resource.start;
 492         hw->mapsize = resource_size(&resource);
 493
 494         /* Sanity check */
 495         if (hw->mapsize < sizeof(struct spi_ppc4xx_regs)) {
 496                 dev_err(dev, "too small to map registers\n");
 497                 ret = -EINVAL;
 498                 goto free_gpios;
 499         }
 500
 501         /* Request IRQ */
 502         hw->irqnum = irq_of_parse_and_map(np, 0);
 503         ret = request_irq(hw->irqnum, spi_ppc4xx_int,
 504                           0, "spi_ppc4xx_of", (void *)hw);
 505         if (ret) {
 506                 dev_err(dev, "unable to allocate interrupt\n");
 507                 goto free_gpios;
 508         }
 509
 510         if (!request_mem_region(hw->mapbase, hw->mapsize, DRIVER_NAME)) {
 511                 dev_err(dev, "resource unavailable\n");
 512                 ret = -EBUSY;
 513                 goto request_mem_error;
 514         }
 515
 516         hw->regs = ioremap(hw->mapbase, sizeof(struct spi_ppc4xx_regs));
 517
 518         if (!hw->regs) {
 519                 dev_err(dev, "unable to memory map registers\n");
 520                 ret = -ENXIO;
 521                 goto map_io_error;
 522         }
 523
 524         spi_ppc4xx_enable(hw);
 525
 526         /* Finally register our spi controller */
 527         dev->dma_mask = 0;
 528         ret = spi_bitbang_start(bbp);
 529         if (ret) {
 530                 dev_err(dev, "failed to register SPI master\n");
 531                 goto unmap_regs;
 532         }
 533
 534         dev_info(dev, "driver initialized\n");
 535
 536         return 0;
 537
 538 unmap_regs:
 539         iounmap(hw->regs);
 540 map_io_error:
 541         release_mem_region(hw->mapbase, hw->mapsize);
 542 request_mem_error:
 543         free_irq(hw->irqnum, hw);
 544 free_gpios:
 545         free_gpios(hw);
 546 free_master:
 547         spi_master_put(master);
 548
 549         dev_err(dev, "initialization failed\n");
 550         return ret;
 551 }
 552
 553 static int spi_ppc4xx_of_remove(struct platform_device *op)
 554 {
 555         struct spi_master *master = platform_get_drvdata(op);
 556         struct ppc4xx_spi *hw = spi_master_get_devdata(master);
 557
 558         spi_bitbang_stop(&hw->bitbang);
 559         release_mem_region(hw->mapbase, hw->mapsize);
 560         free_irq(hw->irqnum, hw);
 561         iounmap(hw->regs);
 562         free_gpios(hw);
 563         spi_master_put(master);
 564         return 0;
 565 }
 566
 567 static const struct of_device_id spi_ppc4xx_of_match[] = {
 568         { .compatible = "ibm,ppc4xx-spi", },
 569         {},
 570 };
 571
 572 MODULE_DEVICE_TABLE(of, spi_ppc4xx_of_match);
 573
 574 static struct platform_driver spi_ppc4xx_of_driver = {
 575         .probe = spi_ppc4xx_of_probe,
 576         .remove = spi_ppc4xx_of_remove,
 577         .driver = {
 578                 .name = DRIVER_NAME,
 579                 .owner = THIS_MODULE,
 580                 .of_match_table = spi_ppc4xx_of_match,
 581         },
 582 };
 583 module_platform_driver(spi_ppc4xx_of_driver);
 584
 585 MODULE_AUTHOR("Gary Jennejohn & Stefan Roese");
 586 MODULE_DESCRIPTION("Simple PPC4xx SPI Driver");
 587 MODULE_LICENSE("GPL");