drivers/spi/spi-tegra20-sflash.c

   1 /*
   2  * SPI driver for Nvidia's Tegra20 Serial Flash Controller.
   3  *
   4  * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   5  *
   6  * Author: Laxman Dewangan <ldewangan@nvidia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <linux/clk.h>
  22 #include <linux/completion.h>
  23 #include <linux/delay.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/io.h>
  28 #include <linux/kernel.h>
  29 #include <linux/kthread.h>
  30 #include <linux/module.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/of.h>
  34 #include <linux/of_device.h>
  35 #include <linux/reset.h>
  36 #include <linux/spi/spi.h>
  37
  38 #define SPI_COMMAND                             0x000
  39 #define SPI_GO                                  BIT(30)
  40 #define SPI_M_S                                 BIT(28)
  41 #define SPI_ACTIVE_SCLK_MASK                    (0x3 << 26)
  42 #define SPI_ACTIVE_SCLK_DRIVE_LOW               (0 << 26)
  43 #define SPI_ACTIVE_SCLK_DRIVE_HIGH              (1 << 26)
  44 #define SPI_ACTIVE_SCLK_PULL_LOW                (2 << 26)
  45 #define SPI_ACTIVE_SCLK_PULL_HIGH               (3 << 26)
  46
  47 #define SPI_CK_SDA_FALLING                      (1 << 21)
  48 #define SPI_CK_SDA_RISING                       (0 << 21)
  49 #define SPI_CK_SDA_MASK                         (1 << 21)
  50 #define SPI_ACTIVE_SDA                          (0x3 << 18)
  51 #define SPI_ACTIVE_SDA_DRIVE_LOW                (0 << 18)
  52 #define SPI_ACTIVE_SDA_DRIVE_HIGH               (1 << 18)
  53 #define SPI_ACTIVE_SDA_PULL_LOW                 (2 << 18)
  54 #define SPI_ACTIVE_SDA_PULL_HIGH                (3 << 18)
  55
  56 #define SPI_CS_POL_INVERT                       BIT(16)
  57 #define SPI_TX_EN                               BIT(15)
  58 #define SPI_RX_EN                               BIT(14)
  59 #define SPI_CS_VAL_HIGH                         BIT(13)
  60 #define SPI_CS_VAL_LOW                          0x0
  61 #define SPI_CS_SW                               BIT(12)
  62 #define SPI_CS_HW                               0x0
  63 #define SPI_CS_DELAY_MASK                       (7 << 9)
  64 #define SPI_CS3_EN                              BIT(8)
  65 #define SPI_CS2_EN                              BIT(7)
  66 #define SPI_CS1_EN                              BIT(6)
  67 #define SPI_CS0_EN                              BIT(5)
  68
  69 #define SPI_CS_MASK                     (SPI_CS3_EN | SPI_CS2_EN |      \
  70                                         SPI_CS1_EN | SPI_CS0_EN)
  71 #define SPI_BIT_LENGTH(x)               (((x) & 0x1f) << 0)
  72
  73 #define SPI_MODES                       (SPI_ACTIVE_SCLK_MASK | SPI_CK_SDA_MASK)
  74
  75 #define SPI_STATUS                      0x004
  76 #define SPI_BSY                         BIT(31)
  77 #define SPI_RDY                         BIT(30)
  78 #define SPI_TXF_FLUSH                   BIT(29)
  79 #define SPI_RXF_FLUSH                   BIT(28)
  80 #define SPI_RX_UNF                      BIT(27)
  81 #define SPI_TX_OVF                      BIT(26)
  82 #define SPI_RXF_EMPTY                   BIT(25)
  83 #define SPI_RXF_FULL                    BIT(24)
  84 #define SPI_TXF_EMPTY                   BIT(23)
  85 #define SPI_TXF_FULL                    BIT(22)
  86 #define SPI_BLK_CNT(count)              (((count) & 0xffff) + 1)
  87
  88 #define SPI_FIFO_ERROR                  (SPI_RX_UNF | SPI_TX_OVF)
  89 #define SPI_FIFO_EMPTY                  (SPI_TX_EMPTY | SPI_RX_EMPTY)
  90
  91 #define SPI_RX_CMP                      0x8
  92 #define SPI_DMA_CTL                     0x0C
  93 #define SPI_DMA_EN                      BIT(31)
  94 #define SPI_IE_RXC                      BIT(27)
  95 #define SPI_IE_TXC                      BIT(26)
  96 #define SPI_PACKED                      BIT(20)
  97 #define SPI_RX_TRIG_MASK                (0x3 << 18)
  98 #define SPI_RX_TRIG_1W                  (0x0 << 18)
  99 #define SPI_RX_TRIG_4W                  (0x1 << 18)
 100 #define SPI_TX_TRIG_MASK                (0x3 << 16)
 101 #define SPI_TX_TRIG_1W                  (0x0 << 16)
 102 #define SPI_TX_TRIG_4W                  (0x1 << 16)
 103 #define SPI_DMA_BLK_COUNT(count)        (((count) - 1) & 0xFFFF);
 104
 105 #define SPI_TX_FIFO                     0x10
 106 #define SPI_RX_FIFO                     0x20
 107
 108 #define DATA_DIR_TX                     (1 << 0)
 109 #define DATA_DIR_RX                     (1 << 1)
 110
 111 #define MAX_CHIP_SELECT                 4
 112 #define SPI_FIFO_DEPTH                  4
 113 #define SPI_DMA_TIMEOUT               (msecs_to_jiffies(1000))
 114
 115 struct tegra_sflash_data {
 116         struct device                           *dev;
 117         struct spi_master                       *master;
 118         spinlock_t                              lock;
 119
 120         struct clk                              *clk;
 121         struct reset_control                    *rst;
 122         void __iomem                            *base;
 123         unsigned                                irq;
 124         u32                                     spi_max_frequency;
 125         u32                                     cur_speed;
 126
 127         struct spi_device                       *cur_spi;
 128         unsigned                                cur_pos;
 129         unsigned                                cur_len;
 130         unsigned                                bytes_per_word;
 131         unsigned                                cur_direction;
 132         unsigned                                curr_xfer_words;
 133
 134         unsigned                                cur_rx_pos;
 135         unsigned                                cur_tx_pos;
 136
 137         u32                                     tx_status;
 138         u32                                     rx_status;
 139         u32                                     status_reg;
 140
 141         u32                                     def_command_reg;
 142         u32                                     command_reg;
 143         u32                                     dma_control_reg;
 144
 145         struct completion                       xfer_completion;
 146         struct spi_transfer                     *curr_xfer;
 147 };
 148
 149 static int tegra_sflash_runtime_suspend(struct device *dev);
 150 static int tegra_sflash_runtime_resume(struct device *dev);
 151
 152 static inline u32 tegra_sflash_readl(struct tegra_sflash_data *tsd,
 153                 unsigned long reg)
 154 {
 155         return readl(tsd->base + reg);
 156 }
 157
 158 static inline void tegra_sflash_writel(struct tegra_sflash_data *tsd,
 159                 u32 val, unsigned long reg)
 160 {
 161         writel(val, tsd->base + reg);
 162 }
 163
 164 static void tegra_sflash_clear_status(struct tegra_sflash_data *tsd)
 165 {
 166         /* Write 1 to clear status register */
 167         tegra_sflash_writel(tsd, SPI_RDY | SPI_FIFO_ERROR, SPI_STATUS);
 168 }
 169
 170 static unsigned tegra_sflash_calculate_curr_xfer_param(
 171         struct spi_device *spi, struct tegra_sflash_data *tsd,
 172         struct spi_transfer *t)
 173 {
 174         unsigned remain_len = t->len - tsd->cur_pos;
 175         unsigned max_word;
 176
 177         tsd->bytes_per_word = DIV_ROUND_UP(t->bits_per_word, 8);
 178         max_word = remain_len / tsd->bytes_per_word;
 179         if (max_word > SPI_FIFO_DEPTH)
 180                 max_word = SPI_FIFO_DEPTH;
 181         tsd->curr_xfer_words = max_word;
 182         return max_word;
 183 }
 184
 185 static unsigned tegra_sflash_fill_tx_fifo_from_client_txbuf(
 186         struct tegra_sflash_data *tsd, struct spi_transfer *t)
 187 {
 188         unsigned nbytes;
 189         u32 status;
 190         unsigned max_n_32bit = tsd->curr_xfer_words;
 191         u8 *tx_buf = (u8 *)t->tx_buf + tsd->cur_tx_pos;
 192
 193         if (max_n_32bit > SPI_FIFO_DEPTH)
 194                 max_n_32bit = SPI_FIFO_DEPTH;
 195         nbytes = max_n_32bit * tsd->bytes_per_word;
 196
 197         status = tegra_sflash_readl(tsd, SPI_STATUS);
 198         while (!(status & SPI_TXF_FULL)) {
 199                 int i;
 200                 u32 x = 0;
 201
 202                 for (i = 0; nbytes && (i < tsd->bytes_per_word);
 203                                                         i++, nbytes--)
 204                         x |= (u32)(*tx_buf++) << (i * 8);
 205                 tegra_sflash_writel(tsd, x, SPI_TX_FIFO);
 206                 if (!nbytes)
 207                         break;
 208
 209                 status = tegra_sflash_readl(tsd, SPI_STATUS);
 210         }
 211         tsd->cur_tx_pos += max_n_32bit * tsd->bytes_per_word;
 212         return max_n_32bit;
 213 }
 214
 215 static int tegra_sflash_read_rx_fifo_to_client_rxbuf(
 216                 struct tegra_sflash_data *tsd, struct spi_transfer *t)
 217 {
 218         u32 status;
 219         unsigned int read_words = 0;
 220         u8 *rx_buf = (u8 *)t->rx_buf + tsd->cur_rx_pos;
 221
 222         status = tegra_sflash_readl(tsd, SPI_STATUS);
 223         while (!(status & SPI_RXF_EMPTY)) {
 224                 int i;
 225                 u32 x = tegra_sflash_readl(tsd, SPI_RX_FIFO);
 226                 for (i = 0; (i < tsd->bytes_per_word); i++)
 227                         *rx_buf++ = (x >> (i*8)) & 0xFF;
 228                 read_words++;
 229                 status = tegra_sflash_readl(tsd, SPI_STATUS);
 230         }
 231         tsd->cur_rx_pos += read_words * tsd->bytes_per_word;
 232         return 0;
 233 }
 234
 235 static int tegra_sflash_start_cpu_based_transfer(
 236                 struct tegra_sflash_data *tsd, struct spi_transfer *t)
 237 {
 238         u32 val = 0;
 239         unsigned cur_words;
 240
 241         if (tsd->cur_direction & DATA_DIR_TX)
 242                 val |= SPI_IE_TXC;
 243
 244         if (tsd->cur_direction & DATA_DIR_RX)
 245                 val |= SPI_IE_RXC;
 246
 247         tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
 248         tsd->dma_control_reg = val;
 249
 250         if (tsd->cur_direction & DATA_DIR_TX)
 251                 cur_words = tegra_sflash_fill_tx_fifo_from_client_txbuf(tsd, t);
 252         else
 253                 cur_words = tsd->curr_xfer_words;
 254         val |= SPI_DMA_BLK_COUNT(cur_words);
 255         tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
 256         tsd->dma_control_reg = val;
 257         val |= SPI_DMA_EN;
 258         tegra_sflash_writel(tsd, val, SPI_DMA_CTL);
 259         return 0;
 260 }
 261
 262 static int tegra_sflash_start_transfer_one(struct spi_device *spi,
 263                 struct spi_transfer *t, bool is_first_of_msg,
 264                 bool is_single_xfer)
 265 {
 266         struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
 267         u32 speed;
 268         u32 command;
 269
 270         speed = t->speed_hz;
 271         if (speed != tsd->cur_speed) {
 272                 clk_set_rate(tsd->clk, speed);
 273                 tsd->cur_speed = speed;
 274         }
 275
 276         tsd->cur_spi = spi;
 277         tsd->cur_pos = 0;
 278         tsd->cur_rx_pos = 0;
 279         tsd->cur_tx_pos = 0;
 280         tsd->curr_xfer = t;
 281         tegra_sflash_calculate_curr_xfer_param(spi, tsd, t);
 282         if (is_first_of_msg) {
 283                 command = tsd->def_command_reg;
 284                 command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
 285                 command |= SPI_CS_VAL_HIGH;
 286
 287                 command &= ~SPI_MODES;
 288                 if (spi->mode & SPI_CPHA)
 289                         command |= SPI_CK_SDA_FALLING;
 290
 291                 if (spi->mode & SPI_CPOL)
 292                         command |= SPI_ACTIVE_SCLK_DRIVE_HIGH;
 293                 else
 294                         command |= SPI_ACTIVE_SCLK_DRIVE_LOW;
 295                 command |= SPI_CS0_EN << spi->chip_select;
 296         } else {
 297                 command = tsd->command_reg;
 298                 command &= ~SPI_BIT_LENGTH(~0);
 299                 command |= SPI_BIT_LENGTH(t->bits_per_word - 1);
 300                 command &= ~(SPI_RX_EN | SPI_TX_EN);
 301         }
 302
 303         tsd->cur_direction = 0;
 304         if (t->rx_buf) {
 305                 command |= SPI_RX_EN;
 306                 tsd->cur_direction |= DATA_DIR_RX;
 307         }
 308         if (t->tx_buf) {
 309                 command |= SPI_TX_EN;
 310                 tsd->cur_direction |= DATA_DIR_TX;
 311         }
 312         tegra_sflash_writel(tsd, command, SPI_COMMAND);
 313         tsd->command_reg = command;
 314
 315         return tegra_sflash_start_cpu_based_transfer(tsd, t);
 316 }
 317
 318 static int tegra_sflash_setup(struct spi_device *spi)
 319 {
 320         struct tegra_sflash_data *tsd = spi_master_get_devdata(spi->master);
 321
 322         /* Set speed to the spi max fequency if spi device has not set */
 323         spi->max_speed_hz = spi->max_speed_hz ? : tsd->spi_max_frequency;
 324         return 0;
 325 }
 326
 327 static int tegra_sflash_transfer_one_message(struct spi_master *master,
 328                         struct spi_message *msg)
 329 {
 330         bool is_first_msg = true;
 331         int single_xfer;
 332         struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 333         struct spi_transfer *xfer;
 334         struct spi_device *spi = msg->spi;
 335         int ret;
 336
 337         msg->status = 0;
 338         msg->actual_length = 0;
 339         single_xfer = list_is_singular(&msg->transfers);
 340         list_for_each_entry(xfer, &msg->transfers, transfer_list) {
 341                 reinit_completion(&tsd->xfer_completion);
 342                 ret = tegra_sflash_start_transfer_one(spi, xfer,
 343                                         is_first_msg, single_xfer);
 344                 if (ret < 0) {
 345                         dev_err(tsd->dev,
 346                                 "spi can not start transfer, err %d\n", ret);
 347                         goto exit;
 348                 }
 349                 is_first_msg = false;
 350                 ret = wait_for_completion_timeout(&tsd->xfer_completion,
 351                                                 SPI_DMA_TIMEOUT);
 352                 if (WARN_ON(ret == 0)) {
 353                         dev_err(tsd->dev,
 354                                 "spi trasfer timeout, err %d\n", ret);
 355                         ret = -EIO;
 356                         goto exit;
 357                 }
 358
 359                 if (tsd->tx_status ||  tsd->rx_status) {
 360                         dev_err(tsd->dev, "Error in Transfer\n");
 361                         ret = -EIO;
 362                         goto exit;
 363                 }
 364                 msg->actual_length += xfer->len;
 365                 if (xfer->cs_change && xfer->delay_usecs) {
 366                         tegra_sflash_writel(tsd, tsd->def_command_reg,
 367                                         SPI_COMMAND);
 368                         udelay(xfer->delay_usecs);
 369                 }
 370         }
 371         ret = 0;
 372 exit:
 373         tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
 374         msg->status = ret;
 375         spi_finalize_current_message(master);
 376         return ret;
 377 }
 378
 379 static irqreturn_t handle_cpu_based_xfer(struct tegra_sflash_data *tsd)
 380 {
 381         struct spi_transfer *t = tsd->curr_xfer;
 382         unsigned long flags;
 383
 384         spin_lock_irqsave(&tsd->lock, flags);
 385         if (tsd->tx_status || tsd->rx_status || (tsd->status_reg & SPI_BSY)) {
 386                 dev_err(tsd->dev,
 387                         "CpuXfer ERROR bit set 0x%x\n", tsd->status_reg);
 388                 dev_err(tsd->dev,
 389                         "CpuXfer 0x%08x:0x%08x\n", tsd->command_reg,
 390                                 tsd->dma_control_reg);
 391                 reset_control_assert(tsd->rst);
 392                 udelay(2);
 393                 reset_control_deassert(tsd->rst);
 394                 complete(&tsd->xfer_completion);
 395                 goto exit;
 396         }
 397
 398         if (tsd->cur_direction & DATA_DIR_RX)
 399                 tegra_sflash_read_rx_fifo_to_client_rxbuf(tsd, t);
 400
 401         if (tsd->cur_direction & DATA_DIR_TX)
 402                 tsd->cur_pos = tsd->cur_tx_pos;
 403         else
 404                 tsd->cur_pos = tsd->cur_rx_pos;
 405
 406         if (tsd->cur_pos == t->len) {
 407                 complete(&tsd->xfer_completion);
 408                 goto exit;
 409         }
 410
 411         tegra_sflash_calculate_curr_xfer_param(tsd->cur_spi, tsd, t);
 412         tegra_sflash_start_cpu_based_transfer(tsd, t);
 413 exit:
 414         spin_unlock_irqrestore(&tsd->lock, flags);
 415         return IRQ_HANDLED;
 416 }
 417
 418 static irqreturn_t tegra_sflash_isr(int irq, void *context_data)
 419 {
 420         struct tegra_sflash_data *tsd = context_data;
 421
 422         tsd->status_reg = tegra_sflash_readl(tsd, SPI_STATUS);
 423         if (tsd->cur_direction & DATA_DIR_TX)
 424                 tsd->tx_status = tsd->status_reg & SPI_TX_OVF;
 425
 426         if (tsd->cur_direction & DATA_DIR_RX)
 427                 tsd->rx_status = tsd->status_reg & SPI_RX_UNF;
 428         tegra_sflash_clear_status(tsd);
 429
 430         return handle_cpu_based_xfer(tsd);
 431 }
 432
 433 static void tegra_sflash_parse_dt(struct tegra_sflash_data *tsd)
 434 {
 435         struct device_node *np = tsd->dev->of_node;
 436
 437         if (of_property_read_u32(np, "spi-max-frequency",
 438                                         &tsd->spi_max_frequency))
 439                 tsd->spi_max_frequency = 25000000; /* 25MHz */
 440 }
 441
 442 static struct of_device_id tegra_sflash_of_match[] = {
 443         { .compatible = "nvidia,tegra20-sflash", },
 444         {}
 445 };
 446 MODULE_DEVICE_TABLE(of, tegra_sflash_of_match);
 447
 448 static int tegra_sflash_probe(struct platform_device *pdev)
 449 {
 450         struct spi_master       *master;
 451         struct tegra_sflash_data        *tsd;
 452         struct resource         *r;
 453         int ret;
 454         const struct of_device_id *match;
 455
 456         match = of_match_device(tegra_sflash_of_match, &pdev->dev);
 457         if (!match) {
 458                 dev_err(&pdev->dev, "Error: No device match found\n");
 459                 return -ENODEV;
 460         }
 461
 462         master = spi_alloc_master(&pdev->dev, sizeof(*tsd));
 463         if (!master) {
 464                 dev_err(&pdev->dev, "master allocation failed\n");
 465                 return -ENOMEM;
 466         }
 467
 468         /* the spi->mode bits understood by this driver: */
 469         master->mode_bits = SPI_CPOL | SPI_CPHA;
 470         master->setup = tegra_sflash_setup;
 471         master->transfer_one_message = tegra_sflash_transfer_one_message;
 472         master->auto_runtime_pm = true;
 473         master->num_chipselect = MAX_CHIP_SELECT;
 474         master->bus_num = -1;
 475
 476         platform_set_drvdata(pdev, master);
 477         tsd = spi_master_get_devdata(master);
 478         tsd->master = master;
 479         tsd->dev = &pdev->dev;
 480         spin_lock_init(&tsd->lock);
 481
 482         tegra_sflash_parse_dt(tsd);
 483
 484         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 485         tsd->base = devm_ioremap_resource(&pdev->dev, r);
 486         if (IS_ERR(tsd->base)) {
 487                 ret = PTR_ERR(tsd->base);
 488                 goto exit_free_master;
 489         }
 490
 491         tsd->irq = platform_get_irq(pdev, 0);
 492         ret = request_irq(tsd->irq, tegra_sflash_isr, 0,
 493                         dev_name(&pdev->dev), tsd);
 494         if (ret < 0) {
 495                 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
 496                                         tsd->irq);
 497                 goto exit_free_master;
 498         }
 499
 500         tsd->clk = devm_clk_get(&pdev->dev, NULL);
 501         if (IS_ERR(tsd->clk)) {
 502                 dev_err(&pdev->dev, "can not get clock\n");
 503                 ret = PTR_ERR(tsd->clk);
 504                 goto exit_free_irq;
 505         }
 506
 507         tsd->rst = devm_reset_control_get(&pdev->dev, "spi");
 508         if (IS_ERR(tsd->rst)) {
 509                 dev_err(&pdev->dev, "can not get reset\n");
 510                 ret = PTR_ERR(tsd->rst);
 511                 goto exit_free_irq;
 512         }
 513
 514         init_completion(&tsd->xfer_completion);
 515         pm_runtime_enable(&pdev->dev);
 516         if (!pm_runtime_enabled(&pdev->dev)) {
 517                 ret = tegra_sflash_runtime_resume(&pdev->dev);
 518                 if (ret)
 519                         goto exit_pm_disable;
 520         }
 521
 522         ret = pm_runtime_get_sync(&pdev->dev);
 523         if (ret < 0) {
 524                 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
 525                 goto exit_pm_disable;
 526         }
 527
 528         /* Reset controller */
 529         reset_control_assert(tsd->rst);
 530         udelay(2);
 531         reset_control_deassert(tsd->rst);
 532
 533         tsd->def_command_reg  = SPI_M_S | SPI_CS_SW;
 534         tegra_sflash_writel(tsd, tsd->def_command_reg, SPI_COMMAND);
 535         pm_runtime_put(&pdev->dev);
 536
 537         master->dev.of_node = pdev->dev.of_node;
 538         ret = devm_spi_register_master(&pdev->dev, master);
 539         if (ret < 0) {
 540                 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
 541                 goto exit_pm_disable;
 542         }
 543         return ret;
 544
 545 exit_pm_disable:
 546         pm_runtime_disable(&pdev->dev);
 547         if (!pm_runtime_status_suspended(&pdev->dev))
 548                 tegra_sflash_runtime_suspend(&pdev->dev);
 549 exit_free_irq:
 550         free_irq(tsd->irq, tsd);
 551 exit_free_master:
 552         spi_master_put(master);
 553         return ret;
 554 }
 555
 556 static int tegra_sflash_remove(struct platform_device *pdev)
 557 {
 558         struct spi_master *master = platform_get_drvdata(pdev);
 559         struct tegra_sflash_data        *tsd = spi_master_get_devdata(master);
 560
 561         free_irq(tsd->irq, tsd);
 562
 563         pm_runtime_disable(&pdev->dev);
 564         if (!pm_runtime_status_suspended(&pdev->dev))
 565                 tegra_sflash_runtime_suspend(&pdev->dev);
 566
 567         return 0;
 568 }
 569
 570 #ifdef CONFIG_PM_SLEEP
 571 static int tegra_sflash_suspend(struct device *dev)
 572 {
 573         struct spi_master *master = dev_get_drvdata(dev);
 574
 575         return spi_master_suspend(master);
 576 }
 577
 578 static int tegra_sflash_resume(struct device *dev)
 579 {
 580         struct spi_master *master = dev_get_drvdata(dev);
 581         struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 582         int ret;
 583
 584         ret = pm_runtime_get_sync(dev);
 585         if (ret < 0) {
 586                 dev_err(dev, "pm runtime failed, e = %d\n", ret);
 587                 return ret;
 588         }
 589         tegra_sflash_writel(tsd, tsd->command_reg, SPI_COMMAND);
 590         pm_runtime_put(dev);
 591
 592         return spi_master_resume(master);
 593 }
 594 #endif
 595
 596 static int tegra_sflash_runtime_suspend(struct device *dev)
 597 {
 598         struct spi_master *master = dev_get_drvdata(dev);
 599         struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 600
 601         /* Flush all write which are in PPSB queue by reading back */
 602         tegra_sflash_readl(tsd, SPI_COMMAND);
 603
 604         clk_disable_unprepare(tsd->clk);
 605         return 0;
 606 }
 607
 608 static int tegra_sflash_runtime_resume(struct device *dev)
 609 {
 610         struct spi_master *master = dev_get_drvdata(dev);
 611         struct tegra_sflash_data *tsd = spi_master_get_devdata(master);
 612         int ret;
 613
 614         ret = clk_prepare_enable(tsd->clk);
 615         if (ret < 0) {
 616                 dev_err(tsd->dev, "clk_prepare failed: %d\n", ret);
 617                 return ret;
 618         }
 619         return 0;
 620 }
 621
 622 static const struct dev_pm_ops slink_pm_ops = {
 623         SET_RUNTIME_PM_OPS(tegra_sflash_runtime_suspend,
 624                 tegra_sflash_runtime_resume, NULL)
 625         SET_SYSTEM_SLEEP_PM_OPS(tegra_sflash_suspend, tegra_sflash_resume)
 626 };
 627 static struct platform_driver tegra_sflash_driver = {
 628         .driver = {
 629                 .name           = "spi-tegra-sflash",
 630                 .owner          = THIS_MODULE,
 631                 .pm             = &slink_pm_ops,
 632                 .of_match_table = tegra_sflash_of_match,
 633         },
 634         .probe =        tegra_sflash_probe,
 635         .remove =       tegra_sflash_remove,
 636 };
 637 module_platform_driver(tegra_sflash_driver);
 638
 639 MODULE_ALIAS("platform:spi-tegra-sflash");
 640 MODULE_DESCRIPTION("NVIDIA Tegra20 Serial Flash Controller Driver");
 641 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
 642 MODULE_LICENSE("GPL v2");