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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / staging / rts5208 / ms.c
blobedf979f18a6c983c411a73a7cb05b419ee7b956f
1 /* Driver for Realtek PCI-Express card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
8 * later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
17 *
18 * Author:
19 * Wei WANG (wei_wang@realsil.com.cn)
20 * Micky Ching (micky_ching@realsil.com.cn)
21 */
22
23 #include <linux/blkdev.h>
24 #include <linux/kthread.h>
25 #include <linux/sched.h>
26 #include <linux/vmalloc.h>
27
28 #include "rtsx.h"
29 #include "rtsx_transport.h"
30 #include "rtsx_scsi.h"
31 #include "rtsx_card.h"
32 #include "ms.h"
33
34 static inline void ms_set_err_code(struct rtsx_chip *chip, u8 err_code)
35 {
36 struct ms_info *ms_card = &(chip->ms_card);
37
38 ms_card->err_code = err_code;
39 }
40
41 static inline int ms_check_err_code(struct rtsx_chip *chip, u8 err_code)
42 {
43 struct ms_info *ms_card = &(chip->ms_card);
44
45 return (ms_card->err_code == err_code);
46 }
47
48 static int ms_parse_err_code(struct rtsx_chip *chip)
49 {
50 TRACE_RET(chip, STATUS_FAIL);
51 }
52
53 static int ms_transfer_tpc(struct rtsx_chip *chip, u8 trans_mode,
54 u8 tpc, u8 cnt, u8 cfg)
55 {
56 struct ms_info *ms_card = &(chip->ms_card);
57 int retval;
58 u8 *ptr;
59
60 RTSX_DEBUGP("ms_transfer_tpc: tpc = 0x%x\n", tpc);
61
62 rtsx_init_cmd(chip);
63
64 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
65 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
66 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
67 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
68 0x01, PINGPONG_BUFFER);
69
70 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER,
71 0xFF, MS_TRANSFER_START | trans_mode);
72 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
73 MS_TRANSFER_END, MS_TRANSFER_END);
74
75 rtsx_add_cmd(chip, READ_REG_CMD, MS_TRANS_CFG, 0, 0);
76
77 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
78 if (retval < 0) {
79 rtsx_clear_ms_error(chip);
80 ms_set_err_code(chip, MS_TO_ERROR);
81 TRACE_RET(chip, ms_parse_err_code(chip));
82 }
83
84 ptr = rtsx_get_cmd_data(chip) + 1;
85
86 if (!(tpc & 0x08)) { /* Read Packet */
87 if (*ptr & MS_CRC16_ERR) {
88 ms_set_err_code(chip, MS_CRC16_ERROR);
89 TRACE_RET(chip, ms_parse_err_code(chip));
90 }
91 } else { /* Write Packet */
92 if (CHK_MSPRO(ms_card) && !(*ptr & 0x80)) {
93 if (*ptr & (MS_INT_ERR | MS_INT_CMDNK)) {
94 ms_set_err_code(chip, MS_CMD_NK);
95 TRACE_RET(chip, ms_parse_err_code(chip));
96 }
97 }
98 }
99
100 if (*ptr & MS_RDY_TIMEOUT) {
101 rtsx_clear_ms_error(chip);
102 ms_set_err_code(chip, MS_TO_ERROR);
103 TRACE_RET(chip, ms_parse_err_code(chip));
104 }
105
106 return STATUS_SUCCESS;
107 }
108
109 static int ms_transfer_data(struct rtsx_chip *chip, u8 trans_mode,
110 u8 tpc, u16 sec_cnt, u8 cfg, int mode_2k,
111 int use_sg, void *buf, int buf_len)
112 {
113 int retval;
114 u8 val, err_code = 0;
115 enum dma_data_direction dir;
116
117 if (!buf || !buf_len)
118 TRACE_RET(chip, STATUS_FAIL);
119
120 if (trans_mode == MS_TM_AUTO_READ) {
121 dir = DMA_FROM_DEVICE;
122 err_code = MS_FLASH_READ_ERROR;
123 } else if (trans_mode == MS_TM_AUTO_WRITE) {
124 dir = DMA_TO_DEVICE;
125 err_code = MS_FLASH_WRITE_ERROR;
126 } else {
127 TRACE_RET(chip, STATUS_FAIL);
128 }
129
130 rtsx_init_cmd(chip);
131
132 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
133 rtsx_add_cmd(chip, WRITE_REG_CMD,
134 MS_SECTOR_CNT_H, 0xFF, (u8)(sec_cnt >> 8));
135 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_SECTOR_CNT_L, 0xFF, (u8)sec_cnt);
136 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
137
138 if (mode_2k) {
139 rtsx_add_cmd(chip, WRITE_REG_CMD,
140 MS_CFG, MS_2K_SECTOR_MODE, MS_2K_SECTOR_MODE);
141 } else {
142 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_CFG, MS_2K_SECTOR_MODE, 0);
143 }
144
145 trans_dma_enable(dir, chip, sec_cnt * 512, DMA_512);
146
147 rtsx_add_cmd(chip, WRITE_REG_CMD,
148 MS_TRANSFER, 0xFF, MS_TRANSFER_START | trans_mode);
149 rtsx_add_cmd(chip, CHECK_REG_CMD,
150 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
151
152 rtsx_send_cmd_no_wait(chip);
153
154 retval = rtsx_transfer_data(chip, MS_CARD, buf, buf_len,
155 use_sg, dir, chip->mspro_timeout);
156 if (retval < 0) {
157 ms_set_err_code(chip, err_code);
158 if (retval == -ETIMEDOUT)
159 retval = STATUS_TIMEDOUT;
160 else
161 retval = STATUS_FAIL;
162
163 TRACE_RET(chip, retval);
164 }
165
166 RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
167 if (val & (MS_INT_CMDNK | MS_INT_ERR | MS_CRC16_ERR | MS_RDY_TIMEOUT))
168 TRACE_RET(chip, STATUS_FAIL);
169
170 return STATUS_SUCCESS;
171 }
172
173 static int ms_write_bytes(struct rtsx_chip *chip,
174 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
175 {
176 struct ms_info *ms_card = &(chip->ms_card);
177 int retval, i;
178
179 if (!data || (data_len < cnt))
180 TRACE_RET(chip, STATUS_ERROR);
181
182 rtsx_init_cmd(chip);
183
184 for (i = 0; i < cnt; i++) {
185 rtsx_add_cmd(chip, WRITE_REG_CMD,
186 PPBUF_BASE2 + i, 0xFF, data[i]);
187 }
188 if (cnt % 2)
189 rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2 + i, 0xFF, 0xFF);
190
191 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
192 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
193 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
194 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
195 0x01, PINGPONG_BUFFER);
196
197 rtsx_add_cmd(chip, WRITE_REG_CMD,
198 MS_TRANSFER, 0xFF, MS_TRANSFER_START | MS_TM_WRITE_BYTES);
199 rtsx_add_cmd(chip, CHECK_REG_CMD,
200 MS_TRANSFER, MS_TRANSFER_END, MS_TRANSFER_END);
201
202 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
203 if (retval < 0) {
204 u8 val = 0;
205
206 rtsx_read_register(chip, MS_TRANS_CFG, &val);
207 RTSX_DEBUGP("MS_TRANS_CFG: 0x%02x\n", val);
208
209 rtsx_clear_ms_error(chip);
210
211 if (!(tpc & 0x08)) {
212 if (val & MS_CRC16_ERR) {
213 ms_set_err_code(chip, MS_CRC16_ERROR);
214 TRACE_RET(chip, ms_parse_err_code(chip));
215 }
216 } else {
217 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
218 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
219 ms_set_err_code(chip, MS_CMD_NK);
220 TRACE_RET(chip,
221 ms_parse_err_code(chip));
222 }
223 }
224 }
225
226 if (val & MS_RDY_TIMEOUT) {
227 ms_set_err_code(chip, MS_TO_ERROR);
228 TRACE_RET(chip, ms_parse_err_code(chip));
229 }
230
231 ms_set_err_code(chip, MS_TO_ERROR);
232 TRACE_RET(chip, ms_parse_err_code(chip));
233 }
234
235 return STATUS_SUCCESS;
236 }
237
238 static int ms_read_bytes(struct rtsx_chip *chip,
239 u8 tpc, u8 cnt, u8 cfg, u8 *data, int data_len)
240 {
241 struct ms_info *ms_card = &(chip->ms_card);
242 int retval, i;
243 u8 *ptr;
244
245 if (!data)
246 TRACE_RET(chip, STATUS_ERROR);
247
248 rtsx_init_cmd(chip);
249
250 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, tpc);
251 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_BYTE_CNT, 0xFF, cnt);
252 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, cfg);
253 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
254 0x01, PINGPONG_BUFFER);
255
256 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
257 MS_TRANSFER_START | MS_TM_READ_BYTES);
258 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
259 MS_TRANSFER_END, MS_TRANSFER_END);
260
261 for (i = 0; i < data_len - 1; i++)
262 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + i, 0, 0);
263
264 if (data_len % 2)
265 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len, 0, 0);
266 else
267 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + data_len - 1,
268 0, 0);
269
270 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
271 if (retval < 0) {
272 u8 val = 0;
273
274 rtsx_read_register(chip, MS_TRANS_CFG, &val);
275 rtsx_clear_ms_error(chip);
276
277 if (!(tpc & 0x08)) {
278 if (val & MS_CRC16_ERR) {
279 ms_set_err_code(chip, MS_CRC16_ERROR);
280 TRACE_RET(chip, ms_parse_err_code(chip));
281 }
282 } else {
283 if (CHK_MSPRO(ms_card) && !(val & 0x80)) {
284 if (val & (MS_INT_ERR | MS_INT_CMDNK)) {
285 ms_set_err_code(chip, MS_CMD_NK);
286 TRACE_RET(chip,
287 ms_parse_err_code(chip));
288 }
289 }
290 }
291
292 if (val & MS_RDY_TIMEOUT) {
293 ms_set_err_code(chip, MS_TO_ERROR);
294 TRACE_RET(chip, ms_parse_err_code(chip));
295 }
296
297 ms_set_err_code(chip, MS_TO_ERROR);
298 TRACE_RET(chip, ms_parse_err_code(chip));
299 }
300
301 ptr = rtsx_get_cmd_data(chip) + 1;
302
303 for (i = 0; i < data_len; i++)
304 data[i] = ptr[i];
305
306 if ((tpc == PRO_READ_SHORT_DATA) && (data_len == 8)) {
307 RTSX_DEBUGP("Read format progress:\n");
308 RTSX_DUMP(ptr, cnt);
309 }
310
311 return STATUS_SUCCESS;
312 }
313
314 static int ms_set_rw_reg_addr(struct rtsx_chip *chip,
315 u8 read_start, u8 read_cnt, u8 write_start, u8 write_cnt)
316 {
317 int retval, i;
318 u8 data[4];
319
320 data[0] = read_start;
321 data[1] = read_cnt;
322 data[2] = write_start;
323 data[3] = write_cnt;
324
325 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
326 retval = ms_write_bytes(chip, SET_RW_REG_ADRS, 4,
327 NO_WAIT_INT, data, 4);
328 if (retval == STATUS_SUCCESS)
329 return STATUS_SUCCESS;
330 rtsx_clear_ms_error(chip);
331 }
332
333 TRACE_RET(chip, STATUS_FAIL);
334 }
335
336 static int ms_send_cmd(struct rtsx_chip *chip, u8 cmd, u8 cfg)
337 {
338 u8 data[2];
339
340 data[0] = cmd;
341 data[1] = 0;
342
343 return ms_write_bytes(chip, PRO_SET_CMD, 1, cfg, data, 1);
344 }
345
346 static int ms_set_init_para(struct rtsx_chip *chip)
347 {
348 struct ms_info *ms_card = &(chip->ms_card);
349 int retval;
350
351 if (CHK_HG8BIT(ms_card)) {
352 if (chip->asic_code)
353 ms_card->ms_clock = chip->asic_ms_hg_clk;
354 else
355 ms_card->ms_clock = chip->fpga_ms_hg_clk;
356
357 } else if (CHK_MSPRO(ms_card) || CHK_MS4BIT(ms_card)) {
358 if (chip->asic_code)
359 ms_card->ms_clock = chip->asic_ms_4bit_clk;
360 else
361 ms_card->ms_clock = chip->fpga_ms_4bit_clk;
362
363 } else {
364 if (chip->asic_code)
365 ms_card->ms_clock = chip->asic_ms_1bit_clk;
366 else
367 ms_card->ms_clock = chip->fpga_ms_1bit_clk;
368 }
369
370 retval = switch_clock(chip, ms_card->ms_clock);
371 if (retval != STATUS_SUCCESS)
372 TRACE_RET(chip, STATUS_FAIL);
373
374 retval = select_card(chip, MS_CARD);
375 if (retval != STATUS_SUCCESS)
376 TRACE_RET(chip, STATUS_FAIL);
377
378 return STATUS_SUCCESS;
379 }
380
381 static int ms_switch_clock(struct rtsx_chip *chip)
382 {
383 struct ms_info *ms_card = &(chip->ms_card);
384 int retval;
385
386 retval = select_card(chip, MS_CARD);
387 if (retval != STATUS_SUCCESS)
388 TRACE_RET(chip, STATUS_FAIL);
389
390 retval = switch_clock(chip, ms_card->ms_clock);
391 if (retval != STATUS_SUCCESS)
392 TRACE_RET(chip, STATUS_FAIL);
393
394 return STATUS_SUCCESS;
395 }
396
397 static int ms_pull_ctl_disable(struct rtsx_chip *chip)
398 {
399 if (CHECK_PID(chip, 0x5208)) {
400 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF,
401 MS_D1_PD | MS_D2_PD | MS_CLK_PD | MS_D6_PD);
402 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF,
403 MS_D3_PD | MS_D0_PD | MS_BS_PD | XD_D4_PD);
404 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF,
405 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
406 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF,
407 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
408 RTSX_WRITE_REG(chip, CARD_PULL_CTL5, 0xFF,
409 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
410 RTSX_WRITE_REG(chip, CARD_PULL_CTL6, 0xFF,
411 MS_D5_PD | MS_D4_PD);
412 } else if (CHECK_PID(chip, 0x5288)) {
413 if (CHECK_BARO_PKG(chip, QFN)) {
414 RTSX_WRITE_REG(chip, CARD_PULL_CTL1, 0xFF, 0x55);
415 RTSX_WRITE_REG(chip, CARD_PULL_CTL2, 0xFF, 0x55);
416 RTSX_WRITE_REG(chip, CARD_PULL_CTL3, 0xFF, 0x4B);
417 RTSX_WRITE_REG(chip, CARD_PULL_CTL4, 0xFF, 0x69);
418 }
419 }
420
421 return STATUS_SUCCESS;
422 }
423
424 static int ms_pull_ctl_enable(struct rtsx_chip *chip)
425 {
426 int retval;
427
428 rtsx_init_cmd(chip);
429
430 if (CHECK_PID(chip, 0x5208)) {
431 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
432 MS_D1_PD | MS_D2_PD | MS_CLK_NP | MS_D6_PD);
433 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
434 MS_D3_PD | MS_D0_PD | MS_BS_NP | XD_D4_PD);
435 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
436 MS_D7_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
437 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
438 XD_RDY_PD | SD_D3_PD | SD_D2_PD | XD_ALE_PD);
439 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
440 MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
441 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
442 MS_D5_PD | MS_D4_PD);
443 } else if (CHECK_PID(chip, 0x5288)) {
444 if (CHECK_BARO_PKG(chip, QFN)) {
445 rtsx_add_cmd(chip, WRITE_REG_CMD,
446 CARD_PULL_CTL1, 0xFF, 0x55);
447 rtsx_add_cmd(chip, WRITE_REG_CMD,
448 CARD_PULL_CTL2, 0xFF, 0x45);
449 rtsx_add_cmd(chip, WRITE_REG_CMD,
450 CARD_PULL_CTL3, 0xFF, 0x4B);
451 rtsx_add_cmd(chip, WRITE_REG_CMD,
452 CARD_PULL_CTL4, 0xFF, 0x29);
453 }
454 }
455
456 retval = rtsx_send_cmd(chip, MS_CARD, 100);
457 if (retval < 0)
458 TRACE_RET(chip, STATUS_FAIL);
459
460 return STATUS_SUCCESS;
461 }
462
463 static int ms_prepare_reset(struct rtsx_chip *chip)
464 {
465 struct ms_info *ms_card = &(chip->ms_card);
466 int retval;
467 u8 oc_mask = 0;
468
469 ms_card->ms_type = 0;
470 ms_card->check_ms_flow = 0;
471 ms_card->switch_8bit_fail = 0;
472 ms_card->delay_write.delay_write_flag = 0;
473
474 ms_card->pro_under_formatting = 0;
475
476 retval = ms_power_off_card3v3(chip);
477 if (retval != STATUS_SUCCESS)
478 TRACE_RET(chip, STATUS_FAIL);
479
480 if (!chip->ft2_fast_mode)
481 wait_timeout(250);
482
483 retval = enable_card_clock(chip, MS_CARD);
484 if (retval != STATUS_SUCCESS)
485 TRACE_RET(chip, STATUS_FAIL);
486
487 if (chip->asic_code) {
488 retval = ms_pull_ctl_enable(chip);
489 if (retval != STATUS_SUCCESS)
490 TRACE_RET(chip, STATUS_FAIL);
491 } else {
492 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
493 FPGA_MS_PULL_CTL_BIT | 0x20, 0);
494 }
495
496 if (!chip->ft2_fast_mode) {
497 retval = card_power_on(chip, MS_CARD);
498 if (retval != STATUS_SUCCESS)
499 TRACE_RET(chip, STATUS_FAIL);
500
501 wait_timeout(150);
502
503 #ifdef SUPPORT_OCP
504 if (CHECK_LUN_MODE(chip, SD_MS_2LUN))
505 oc_mask = MS_OC_NOW | MS_OC_EVER;
506 else
507 oc_mask = SD_OC_NOW | SD_OC_EVER;
508
509 if (chip->ocp_stat & oc_mask) {
510 RTSX_DEBUGP("Over current, OCPSTAT is 0x%x\n",
511 chip->ocp_stat);
512 TRACE_RET(chip, STATUS_FAIL);
513 }
514 #endif
515 }
516
517 RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, MS_OUTPUT_EN);
518
519 if (chip->asic_code) {
520 RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
521 SAMPLE_TIME_RISING | PUSH_TIME_DEFAULT |
522 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
523 } else {
524 RTSX_WRITE_REG(chip, MS_CFG, 0xFF,
525 SAMPLE_TIME_FALLING | PUSH_TIME_DEFAULT |
526 NO_EXTEND_TOGGLE | MS_BUS_WIDTH_1);
527 }
528 RTSX_WRITE_REG(chip, MS_TRANS_CFG,
529 0xFF, NO_WAIT_INT | NO_AUTO_READ_INT_REG);
530 RTSX_WRITE_REG(chip, CARD_STOP,
531 MS_STOP | MS_CLR_ERR, MS_STOP | MS_CLR_ERR);
532
533 retval = ms_set_init_para(chip);
534 if (retval != STATUS_SUCCESS)
535 TRACE_RET(chip, STATUS_FAIL);
536
537 return STATUS_SUCCESS;
538 }
539
540 static int ms_identify_media_type(struct rtsx_chip *chip, int switch_8bit_bus)
541 {
542 struct ms_info *ms_card = &(chip->ms_card);
543 int retval, i;
544 u8 val;
545
546 retval = ms_set_rw_reg_addr(chip, Pro_StatusReg, 6, SystemParm, 1);
547 if (retval != STATUS_SUCCESS)
548 TRACE_RET(chip, STATUS_FAIL);
549
550 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
551 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, READ_REG,
552 6, NO_WAIT_INT);
553 if (retval == STATUS_SUCCESS)
554 break;
555 }
556 if (i == MS_MAX_RETRY_COUNT)
557 TRACE_RET(chip, STATUS_FAIL);
558
559 RTSX_READ_REG(chip, PPBUF_BASE2 + 2, &val);
560 RTSX_DEBUGP("Type register: 0x%x\n", val);
561 if (val != 0x01) {
562 if (val != 0x02)
563 ms_card->check_ms_flow = 1;
564
565 TRACE_RET(chip, STATUS_FAIL);
566 }
567
568 RTSX_READ_REG(chip, PPBUF_BASE2 + 4, &val);
569 RTSX_DEBUGP("Category register: 0x%x\n", val);
570 if (val != 0) {
571 ms_card->check_ms_flow = 1;
572 TRACE_RET(chip, STATUS_FAIL);
573 }
574
575 RTSX_READ_REG(chip, PPBUF_BASE2 + 5, &val);
576 RTSX_DEBUGP("Class register: 0x%x\n", val);
577 if (val == 0) {
578 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
579 if (val & WRT_PRTCT)
580 chip->card_wp |= MS_CARD;
581 else
582 chip->card_wp &= ~MS_CARD;
583
584 } else if ((val == 0x01) || (val == 0x02) || (val == 0x03)) {
585 chip->card_wp |= MS_CARD;
586 } else {
587 ms_card->check_ms_flow = 1;
588 TRACE_RET(chip, STATUS_FAIL);
589 }
590
591 ms_card->ms_type |= TYPE_MSPRO;
592
593 RTSX_READ_REG(chip, PPBUF_BASE2 + 3, &val);
594 RTSX_DEBUGP("IF Mode register: 0x%x\n", val);
595 if (val == 0) {
596 ms_card->ms_type &= 0x0F;
597 } else if (val == 7) {
598 if (switch_8bit_bus)
599 ms_card->ms_type |= MS_HG;
600 else
601 ms_card->ms_type &= 0x0F;
602
603 } else {
604 TRACE_RET(chip, STATUS_FAIL);
605 }
606
607 return STATUS_SUCCESS;
608 }
609
610 static int ms_confirm_cpu_startup(struct rtsx_chip *chip)
611 {
612 int retval, i, k;
613 u8 val;
614
615 /* Confirm CPU StartUp */
616 k = 0;
617 do {
618 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
619 ms_set_err_code(chip, MS_NO_CARD);
620 TRACE_RET(chip, STATUS_FAIL);
621 }
622
623 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
624 retval = ms_read_bytes(chip, GET_INT, 1,
625 NO_WAIT_INT, &val, 1);
626 if (retval == STATUS_SUCCESS)
627 break;
628 }
629 if (i == MS_MAX_RETRY_COUNT)
630 TRACE_RET(chip, STATUS_FAIL);
631
632 if (k > 100)
633 TRACE_RET(chip, STATUS_FAIL);
634
635 k++;
636 wait_timeout(100);
637 } while (!(val & INT_REG_CED));
638
639 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
640 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
641 if (retval == STATUS_SUCCESS)
642 break;
643 }
644 if (i == MS_MAX_RETRY_COUNT)
645 TRACE_RET(chip, STATUS_FAIL);
646
647 if (val & INT_REG_ERR) {
648 if (val & INT_REG_CMDNK)
649 chip->card_wp |= (MS_CARD);
650 else
651 TRACE_RET(chip, STATUS_FAIL);
652 }
653 /* -- end confirm CPU startup */
654
655 return STATUS_SUCCESS;
656 }
657
658 static int ms_switch_parallel_bus(struct rtsx_chip *chip)
659 {
660 int retval, i;
661 u8 data[2];
662
663 data[0] = PARALLEL_4BIT_IF;
664 data[1] = 0;
665 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
666 retval = ms_write_bytes(chip, WRITE_REG, 1, NO_WAIT_INT,
667 data, 2);
668 if (retval == STATUS_SUCCESS)
669 break;
670 }
671 if (retval != STATUS_SUCCESS)
672 TRACE_RET(chip, STATUS_FAIL);
673
674 return STATUS_SUCCESS;
675 }
676
677 static int ms_switch_8bit_bus(struct rtsx_chip *chip)
678 {
679 struct ms_info *ms_card = &(chip->ms_card);
680 int retval, i;
681 u8 data[2];
682
683 data[0] = PARALLEL_8BIT_IF;
684 data[1] = 0;
685 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
686 retval = ms_write_bytes(chip, WRITE_REG, 1,
687 NO_WAIT_INT, data, 2);
688 if (retval == STATUS_SUCCESS)
689 break;
690 }
691 if (retval != STATUS_SUCCESS)
692 TRACE_RET(chip, STATUS_FAIL);
693
694 RTSX_WRITE_REG(chip, MS_CFG, 0x98,
695 MS_BUS_WIDTH_8 | SAMPLE_TIME_FALLING);
696 ms_card->ms_type |= MS_8BIT;
697 retval = ms_set_init_para(chip);
698 if (retval != STATUS_SUCCESS)
699 TRACE_RET(chip, STATUS_FAIL);
700
701 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
702 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT,
703 1, NO_WAIT_INT);
704 if (retval != STATUS_SUCCESS)
705 TRACE_RET(chip, STATUS_FAIL);
706 }
707
708 return STATUS_SUCCESS;
709 }
710
711 static int ms_pro_reset_flow(struct rtsx_chip *chip, int switch_8bit_bus)
712 {
713 struct ms_info *ms_card = &(chip->ms_card);
714 int retval, i;
715
716 for (i = 0; i < 3; i++) {
717 retval = ms_prepare_reset(chip);
718 if (retval != STATUS_SUCCESS)
719 TRACE_RET(chip, STATUS_FAIL);
720
721 retval = ms_identify_media_type(chip, switch_8bit_bus);
722 if (retval != STATUS_SUCCESS)
723 TRACE_RET(chip, STATUS_FAIL);
724
725 retval = ms_confirm_cpu_startup(chip);
726 if (retval != STATUS_SUCCESS)
727 TRACE_RET(chip, STATUS_FAIL);
728
729 retval = ms_switch_parallel_bus(chip);
730 if (retval != STATUS_SUCCESS) {
731 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
732 ms_set_err_code(chip, MS_NO_CARD);
733 TRACE_RET(chip, STATUS_FAIL);
734 }
735 continue;
736 } else {
737 break;
738 }
739 }
740
741 if (retval != STATUS_SUCCESS)
742 TRACE_RET(chip, STATUS_FAIL);
743
744 /* Switch MS-PRO into Parallel mode */
745 RTSX_WRITE_REG(chip, MS_CFG, 0x18, MS_BUS_WIDTH_4);
746 RTSX_WRITE_REG(chip, MS_CFG, PUSH_TIME_ODD, PUSH_TIME_ODD);
747
748 retval = ms_set_init_para(chip);
749 if (retval != STATUS_SUCCESS)
750 TRACE_RET(chip, STATUS_FAIL);
751
752 /* If MSPro HG Card, We shall try to switch to 8-bit bus */
753 if (CHK_MSHG(ms_card) && chip->support_ms_8bit && switch_8bit_bus) {
754 retval = ms_switch_8bit_bus(chip);
755 if (retval != STATUS_SUCCESS) {
756 ms_card->switch_8bit_fail = 1;
757 TRACE_RET(chip, STATUS_FAIL);
758 }
759 }
760
761 return STATUS_SUCCESS;
762 }
763
764 #ifdef XC_POWERCLASS
765 static int msxc_change_power(struct rtsx_chip *chip, u8 mode)
766 {
767 int retval;
768 u8 buf[6];
769
770 ms_cleanup_work(chip);
771
772 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
773 if (retval != STATUS_SUCCESS)
774 TRACE_RET(chip, STATUS_FAIL);
775
776 buf[0] = 0;
777 buf[1] = mode;
778 buf[2] = 0;
779 buf[3] = 0;
780 buf[4] = 0;
781 buf[5] = 0;
782
783 retval = ms_write_bytes(chip, PRO_WRITE_REG , 6, NO_WAIT_INT, buf, 6);
784 if (retval != STATUS_SUCCESS)
785 TRACE_RET(chip, STATUS_FAIL);
786
787 retval = ms_send_cmd(chip, XC_CHG_POWER, WAIT_INT);
788 if (retval != STATUS_SUCCESS)
789 TRACE_RET(chip, STATUS_FAIL);
790
791 RTSX_READ_REG(chip, MS_TRANS_CFG, buf);
792 if (buf[0] & (MS_INT_CMDNK | MS_INT_ERR))
793 TRACE_RET(chip, STATUS_FAIL);
794
795 return STATUS_SUCCESS;
796 }
797 #endif
798
799 static int ms_read_attribute_info(struct rtsx_chip *chip)
800 {
801 struct ms_info *ms_card = &(chip->ms_card);
802 int retval, i;
803 u8 val, *buf, class_code, device_type, sub_class, data[16];
804 u16 total_blk = 0, blk_size = 0;
805 #ifdef SUPPORT_MSXC
806 u32 xc_total_blk = 0, xc_blk_size = 0;
807 #endif
808 u32 sys_info_addr = 0, sys_info_size;
809 #ifdef SUPPORT_PCGL_1P18
810 u32 model_name_addr = 0, model_name_size;
811 int found_sys_info = 0, found_model_name = 0;
812 #endif
813
814 retval = ms_set_rw_reg_addr(chip, Pro_IntReg, 2, Pro_SystemParm, 7);
815 if (retval != STATUS_SUCCESS)
816 TRACE_RET(chip, STATUS_FAIL);
817
818 if (CHK_MS8BIT(ms_card))
819 data[0] = PARALLEL_8BIT_IF;
820 else
821 data[0] = PARALLEL_4BIT_IF;
822
823 data[1] = 0;
824
825 data[2] = 0x40;
826 data[3] = 0;
827 data[4] = 0;
828 data[5] = 0;
829 data[6] = 0;
830 data[7] = 0;
831
832 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
833 retval = ms_write_bytes(chip, PRO_WRITE_REG, 7, NO_WAIT_INT,
834 data, 8);
835 if (retval == STATUS_SUCCESS)
836 break;
837 }
838 if (retval != STATUS_SUCCESS)
839 TRACE_RET(chip, STATUS_FAIL);
840
841 buf = kmalloc(64 * 512, GFP_KERNEL);
842 if (buf == NULL)
843 TRACE_RET(chip, STATUS_ERROR);
844
845 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
846 retval = ms_send_cmd(chip, PRO_READ_ATRB, WAIT_INT);
847 if (retval != STATUS_SUCCESS)
848 continue;
849
850 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
851 if (retval != STATUS_SUCCESS) {
852 kfree(buf);
853 TRACE_RET(chip, STATUS_FAIL);
854 }
855 if (!(val & MS_INT_BREQ)) {
856 kfree(buf);
857 TRACE_RET(chip, STATUS_FAIL);
858 }
859 retval = ms_transfer_data(chip, MS_TM_AUTO_READ,
860 PRO_READ_LONG_DATA, 0x40, WAIT_INT,
861 0, 0, buf, 64 * 512);
862 if (retval == STATUS_SUCCESS)
863 break;
864 else
865 rtsx_clear_ms_error(chip);
866 }
867 if (retval != STATUS_SUCCESS) {
868 kfree(buf);
869 TRACE_RET(chip, STATUS_FAIL);
870 }
871
872 i = 0;
873 do {
874 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
875 if (retval != STATUS_SUCCESS) {
876 kfree(buf);
877 TRACE_RET(chip, STATUS_FAIL);
878 }
879
880 if ((val & MS_INT_CED) || !(val & MS_INT_BREQ))
881 break;
882
883 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ,
884 PRO_READ_LONG_DATA, 0, WAIT_INT);
885 if (retval != STATUS_SUCCESS) {
886 kfree(buf);
887 TRACE_RET(chip, STATUS_FAIL);
888 }
889
890 i++;
891 } while (i < 1024);
892
893 if (retval != STATUS_SUCCESS) {
894 kfree(buf);
895 TRACE_RET(chip, STATUS_FAIL);
896 }
897
898 if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
899 /* Signature code is wrong */
900 kfree(buf);
901 TRACE_RET(chip, STATUS_FAIL);
902 }
903
904 if ((buf[4] < 1) || (buf[4] > 12)) {
905 kfree(buf);
906 TRACE_RET(chip, STATUS_FAIL);
907 }
908
909 for (i = 0; i < buf[4]; i++) {
910 int cur_addr_off = 16 + i * 12;
911
912 #ifdef SUPPORT_MSXC
913 if ((buf[cur_addr_off + 8] == 0x10) ||
914 (buf[cur_addr_off + 8] == 0x13))
915 #else
916 if (buf[cur_addr_off + 8] == 0x10)
917 #endif
918 {
919 sys_info_addr = ((u32)buf[cur_addr_off + 0] << 24) |
920 ((u32)buf[cur_addr_off + 1] << 16) |
921 ((u32)buf[cur_addr_off + 2] << 8) |
922 buf[cur_addr_off + 3];
923 sys_info_size = ((u32)buf[cur_addr_off + 4] << 24) |
924 ((u32)buf[cur_addr_off + 5] << 16) |
925 ((u32)buf[cur_addr_off + 6] << 8) |
926 buf[cur_addr_off + 7];
927 RTSX_DEBUGP("sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
928 sys_info_addr, sys_info_size);
929 if (sys_info_size != 96) {
930 kfree(buf);
931 TRACE_RET(chip, STATUS_FAIL);
932 }
933 if (sys_info_addr < 0x1A0) {
934 kfree(buf);
935 TRACE_RET(chip, STATUS_FAIL);
936 }
937 if ((sys_info_size + sys_info_addr) > 0x8000) {
938 kfree(buf);
939 TRACE_RET(chip, STATUS_FAIL);
940 }
941
942 #ifdef SUPPORT_MSXC
943 if (buf[cur_addr_off + 8] == 0x13)
944 ms_card->ms_type |= MS_XC;
945 #endif
946 #ifdef SUPPORT_PCGL_1P18
947 found_sys_info = 1;
948 #else
949 break;
950 #endif
951 }
952 #ifdef SUPPORT_PCGL_1P18
953 if (buf[cur_addr_off + 8] == 0x15) {
954 model_name_addr = ((u32)buf[cur_addr_off + 0] << 24) |
955 ((u32)buf[cur_addr_off + 1] << 16) |
956 ((u32)buf[cur_addr_off + 2] << 8) |
957 buf[cur_addr_off + 3];
958 model_name_size = ((u32)buf[cur_addr_off + 4] << 24) |
959 ((u32)buf[cur_addr_off + 5] << 16) |
960 ((u32)buf[cur_addr_off + 6] << 8) |
961 buf[cur_addr_off + 7];
962 RTSX_DEBUGP("model_name_addr = 0x%x, model_name_size = 0x%x\n",
963 model_name_addr, model_name_size);
964 if (model_name_size != 48) {
965 kfree(buf);
966 TRACE_RET(chip, STATUS_FAIL);
967 }
968 if (model_name_addr < 0x1A0) {
969 kfree(buf);
970 TRACE_RET(chip, STATUS_FAIL);
971 }
972 if ((model_name_size + model_name_addr) > 0x8000) {
973 kfree(buf);
974 TRACE_RET(chip, STATUS_FAIL);
975 }
976
977 found_model_name = 1;
978 }
979
980 if (found_sys_info && found_model_name)
981 break;
982 #endif
983 }
984
985 if (i == buf[4]) {
986 kfree(buf);
987 TRACE_RET(chip, STATUS_FAIL);
988 }
989
990 class_code = buf[sys_info_addr + 0];
991 device_type = buf[sys_info_addr + 56];
992 sub_class = buf[sys_info_addr + 46];
993 #ifdef SUPPORT_MSXC
994 if (CHK_MSXC(ms_card)) {
995 xc_total_blk = ((u32)buf[sys_info_addr + 6] << 24) |
996 ((u32)buf[sys_info_addr + 7] << 16) |
997 ((u32)buf[sys_info_addr + 8] << 8) |
998 buf[sys_info_addr + 9];
999 xc_blk_size = ((u32)buf[sys_info_addr + 32] << 24) |
1000 ((u32)buf[sys_info_addr + 33] << 16) |
1001 ((u32)buf[sys_info_addr + 34] << 8) |
1002 buf[sys_info_addr + 35];
1003 RTSX_DEBUGP("xc_total_blk = 0x%x, xc_blk_size = 0x%x\n",
1004 xc_total_blk, xc_blk_size);
1005 } else {
1006 total_blk = ((u16)buf[sys_info_addr + 6] << 8) |
1007 buf[sys_info_addr + 7];
1008 blk_size = ((u16)buf[sys_info_addr + 2] << 8) |
1009 buf[sys_info_addr + 3];
1010 RTSX_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n",
1011 total_blk, blk_size);
1012 }
1013 #else
1014 total_blk = ((u16)buf[sys_info_addr + 6] << 8) | buf[sys_info_addr + 7];
1015 blk_size = ((u16)buf[sys_info_addr + 2] << 8) | buf[sys_info_addr + 3];
1016 RTSX_DEBUGP("total_blk = 0x%x, blk_size = 0x%x\n", total_blk, blk_size);
1017 #endif
1018
1019 RTSX_DEBUGP("class_code = 0x%x, device_type = 0x%x, sub_class = 0x%x\n",
1020 class_code, device_type, sub_class);
1021
1022 memcpy(ms_card->raw_sys_info, buf + sys_info_addr, 96);
1023 #ifdef SUPPORT_PCGL_1P18
1024 memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
1025 #endif
1026
1027 kfree(buf);
1028
1029 #ifdef SUPPORT_MSXC
1030 if (CHK_MSXC(ms_card)) {
1031 if (class_code != 0x03)
1032 TRACE_RET(chip, STATUS_FAIL);
1033 } else {
1034 if (class_code != 0x02)
1035 TRACE_RET(chip, STATUS_FAIL);
1036 }
1037 #else
1038 if (class_code != 0x02)
1039 TRACE_RET(chip, STATUS_FAIL);
1040 #endif
1041
1042 if (device_type != 0x00) {
1043 if ((device_type == 0x01) || (device_type == 0x02) ||
1044 (device_type == 0x03)) {
1045 chip->card_wp |= MS_CARD;
1046 } else {
1047 TRACE_RET(chip, STATUS_FAIL);
1048 }
1049 }
1050
1051 if (sub_class & 0xC0)
1052 TRACE_RET(chip, STATUS_FAIL);
1053
1054 RTSX_DEBUGP("class_code: 0x%x, device_type: 0x%x, sub_class: 0x%x\n",
1055 class_code, device_type, sub_class);
1056
1057 #ifdef SUPPORT_MSXC
1058 if (CHK_MSXC(ms_card)) {
1059 chip->capacity[chip->card2lun[MS_CARD]] =
1060 ms_card->capacity = xc_total_blk * xc_blk_size;
1061 } else {
1062 chip->capacity[chip->card2lun[MS_CARD]] =
1063 ms_card->capacity = total_blk * blk_size;
1064 }
1065 #else
1066 ms_card->capacity = total_blk * blk_size;
1067 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1068 #endif
1069
1070 return STATUS_SUCCESS;
1071 }
1072
1073 #ifdef SUPPORT_MAGIC_GATE
1074 static int mg_set_tpc_para_sub(struct rtsx_chip *chip,
1075 int type, u8 mg_entry_num);
1076 #endif
1077
1078 static int reset_ms_pro(struct rtsx_chip *chip)
1079 {
1080 struct ms_info *ms_card = &(chip->ms_card);
1081 int retval;
1082 #ifdef XC_POWERCLASS
1083 u8 change_power_class;
1084
1085 if (chip->ms_power_class_en & 0x02)
1086 change_power_class = 2;
1087 else if (chip->ms_power_class_en & 0x01)
1088 change_power_class = 1;
1089 else
1090 change_power_class = 0;
1091 #endif
1092
1093 #ifdef XC_POWERCLASS
1094 Retry:
1095 #endif
1096 retval = ms_pro_reset_flow(chip, 1);
1097 if (retval != STATUS_SUCCESS) {
1098 if (ms_card->switch_8bit_fail) {
1099 retval = ms_pro_reset_flow(chip, 0);
1100 if (retval != STATUS_SUCCESS)
1101 TRACE_RET(chip, STATUS_FAIL);
1102 } else {
1103 TRACE_RET(chip, STATUS_FAIL);
1104 }
1105 }
1106
1107 retval = ms_read_attribute_info(chip);
1108 if (retval != STATUS_SUCCESS)
1109 TRACE_RET(chip, STATUS_FAIL);
1110
1111 #ifdef XC_POWERCLASS
1112 if (CHK_HG8BIT(ms_card))
1113 change_power_class = 0;
1114
1115 if (change_power_class && CHK_MSXC(ms_card)) {
1116 u8 power_class_en = chip->ms_power_class_en;
1117
1118 RTSX_DEBUGP("power_class_en = 0x%x\n", power_class_en);
1119 RTSX_DEBUGP("change_power_class = %d\n", change_power_class);
1120
1121 if (change_power_class)
1122 power_class_en &= (1 << (change_power_class - 1));
1123 else
1124 power_class_en = 0;
1125
1126 if (power_class_en) {
1127 u8 power_class_mode =
1128 (ms_card->raw_sys_info[46] & 0x18) >> 3;
1129 RTSX_DEBUGP("power_class_mode = 0x%x",
1130 power_class_mode);
1131 if (change_power_class > power_class_mode)
1132 change_power_class = power_class_mode;
1133 if (change_power_class) {
1134 retval = msxc_change_power(chip,
1135 change_power_class);
1136 if (retval != STATUS_SUCCESS) {
1137 change_power_class--;
1138 goto Retry;
1139 }
1140 }
1141 }
1142 }
1143 #endif
1144
1145 #ifdef SUPPORT_MAGIC_GATE
1146 retval = mg_set_tpc_para_sub(chip, 0, 0);
1147 if (retval != STATUS_SUCCESS)
1148 TRACE_RET(chip, STATUS_FAIL);
1149 #endif
1150
1151 if (CHK_HG8BIT(ms_card))
1152 chip->card_bus_width[chip->card2lun[MS_CARD]] = 8;
1153 else
1154 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1155
1156 return STATUS_SUCCESS;
1157 }
1158
1159 static int ms_read_status_reg(struct rtsx_chip *chip)
1160 {
1161 int retval;
1162 u8 val[2];
1163
1164 retval = ms_set_rw_reg_addr(chip, StatusReg0, 2, 0, 0);
1165 if (retval != STATUS_SUCCESS)
1166 TRACE_RET(chip, STATUS_FAIL);
1167
1168 retval = ms_read_bytes(chip, READ_REG, 2, NO_WAIT_INT, val, 2);
1169 if (retval != STATUS_SUCCESS)
1170 TRACE_RET(chip, STATUS_FAIL);
1171
1172 if (val[1] & (STS_UCDT | STS_UCEX | STS_UCFG)) {
1173 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1174 TRACE_RET(chip, STATUS_FAIL);
1175 }
1176
1177 return STATUS_SUCCESS;
1178 }
1179
1180
1181 static int ms_read_extra_data(struct rtsx_chip *chip,
1182 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1183 {
1184 struct ms_info *ms_card = &(chip->ms_card);
1185 int retval, i;
1186 u8 val, data[10];
1187
1188 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1189 SystemParm, 6);
1190 if (retval != STATUS_SUCCESS)
1191 TRACE_RET(chip, STATUS_FAIL);
1192
1193 if (CHK_MS4BIT(ms_card)) {
1194 /* Parallel interface */
1195 data[0] = 0x88;
1196 } else {
1197 /* Serial interface */
1198 data[0] = 0x80;
1199 }
1200 data[1] = 0;
1201 data[2] = (u8)(block_addr >> 8);
1202 data[3] = (u8)block_addr;
1203 data[4] = 0x40;
1204 data[5] = page_num;
1205
1206 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1207 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
1208 data, 6);
1209 if (retval == STATUS_SUCCESS)
1210 break;
1211 }
1212 if (i == MS_MAX_RETRY_COUNT)
1213 TRACE_RET(chip, STATUS_FAIL);
1214
1215 ms_set_err_code(chip, MS_NO_ERROR);
1216
1217 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
1218 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1219 if (retval == STATUS_SUCCESS)
1220 break;
1221 }
1222 if (i == MS_MAX_RETRY_COUNT)
1223 TRACE_RET(chip, STATUS_FAIL);
1224
1225 ms_set_err_code(chip, MS_NO_ERROR);
1226 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1227 if (retval != STATUS_SUCCESS)
1228 TRACE_RET(chip, STATUS_FAIL);
1229
1230 if (val & INT_REG_CMDNK) {
1231 ms_set_err_code(chip, MS_CMD_NK);
1232 TRACE_RET(chip, STATUS_FAIL);
1233 }
1234 if (val & INT_REG_CED) {
1235 if (val & INT_REG_ERR) {
1236 retval = ms_read_status_reg(chip);
1237 if (retval != STATUS_SUCCESS)
1238 TRACE_RET(chip, STATUS_FAIL);
1239
1240 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1241 MS_EXTRA_SIZE, SystemParm, 6);
1242 if (retval != STATUS_SUCCESS)
1243 TRACE_RET(chip, STATUS_FAIL);
1244 }
1245 }
1246
1247 retval = ms_read_bytes(chip, READ_REG, MS_EXTRA_SIZE, NO_WAIT_INT,
1248 data, MS_EXTRA_SIZE);
1249 if (retval != STATUS_SUCCESS)
1250 TRACE_RET(chip, STATUS_FAIL);
1251
1252 if (buf && buf_len) {
1253 if (buf_len > MS_EXTRA_SIZE)
1254 buf_len = MS_EXTRA_SIZE;
1255 memcpy(buf, data, buf_len);
1256 }
1257
1258 return STATUS_SUCCESS;
1259 }
1260
1261 static int ms_write_extra_data(struct rtsx_chip *chip,
1262 u16 block_addr, u8 page_num, u8 *buf, int buf_len)
1263 {
1264 struct ms_info *ms_card = &(chip->ms_card);
1265 int retval, i;
1266 u8 val, data[16];
1267
1268 if (!buf || (buf_len < MS_EXTRA_SIZE))
1269 TRACE_RET(chip, STATUS_FAIL);
1270
1271 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1272 SystemParm, 6 + MS_EXTRA_SIZE);
1273 if (retval != STATUS_SUCCESS)
1274 TRACE_RET(chip, STATUS_FAIL);
1275
1276 if (CHK_MS4BIT(ms_card))
1277 data[0] = 0x88;
1278 else
1279 data[0] = 0x80;
1280
1281 data[1] = 0;
1282 data[2] = (u8)(block_addr >> 8);
1283 data[3] = (u8)block_addr;
1284 data[4] = 0x40;
1285 data[5] = page_num;
1286
1287 for (i = 6; i < MS_EXTRA_SIZE + 6; i++)
1288 data[i] = buf[i - 6];
1289
1290 retval = ms_write_bytes(chip, WRITE_REG , (6+MS_EXTRA_SIZE),
1291 NO_WAIT_INT, data, 16);
1292 if (retval != STATUS_SUCCESS)
1293 TRACE_RET(chip, STATUS_FAIL);
1294
1295 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1296 if (retval != STATUS_SUCCESS)
1297 TRACE_RET(chip, STATUS_FAIL);
1298
1299 ms_set_err_code(chip, MS_NO_ERROR);
1300 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1301 if (retval != STATUS_SUCCESS)
1302 TRACE_RET(chip, STATUS_FAIL);
1303
1304 if (val & INT_REG_CMDNK) {
1305 ms_set_err_code(chip, MS_CMD_NK);
1306 TRACE_RET(chip, STATUS_FAIL);
1307 }
1308 if (val & INT_REG_CED) {
1309 if (val & INT_REG_ERR) {
1310 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1311 TRACE_RET(chip, STATUS_FAIL);
1312 }
1313 }
1314
1315 return STATUS_SUCCESS;
1316 }
1317
1318
1319 static int ms_read_page(struct rtsx_chip *chip, u16 block_addr, u8 page_num)
1320 {
1321 struct ms_info *ms_card = &(chip->ms_card);
1322 int retval;
1323 u8 val, data[6];
1324
1325 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1326 SystemParm, 6);
1327 if (retval != STATUS_SUCCESS)
1328 TRACE_RET(chip, STATUS_FAIL);
1329
1330 if (CHK_MS4BIT(ms_card))
1331 data[0] = 0x88;
1332 else
1333 data[0] = 0x80;
1334
1335 data[1] = 0;
1336 data[2] = (u8)(block_addr >> 8);
1337 data[3] = (u8)block_addr;
1338 data[4] = 0x20;
1339 data[5] = page_num;
1340
1341 retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT, data, 6);
1342 if (retval != STATUS_SUCCESS)
1343 TRACE_RET(chip, STATUS_FAIL);
1344
1345 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1346 if (retval != STATUS_SUCCESS)
1347 TRACE_RET(chip, STATUS_FAIL);
1348
1349 ms_set_err_code(chip, MS_NO_ERROR);
1350 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1351 if (retval != STATUS_SUCCESS)
1352 TRACE_RET(chip, STATUS_FAIL);
1353
1354 if (val & INT_REG_CMDNK) {
1355 ms_set_err_code(chip, MS_CMD_NK);
1356 TRACE_RET(chip, STATUS_FAIL);
1357 }
1358
1359 if (val & INT_REG_CED) {
1360 if (val & INT_REG_ERR) {
1361 if (!(val & INT_REG_BREQ)) {
1362 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
1363 TRACE_RET(chip, STATUS_FAIL);
1364 }
1365 retval = ms_read_status_reg(chip);
1366 if (retval != STATUS_SUCCESS)
1367 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1368
1369 } else {
1370 if (!(val & INT_REG_BREQ)) {
1371 ms_set_err_code(chip, MS_BREQ_ERROR);
1372 TRACE_RET(chip, STATUS_FAIL);
1373 }
1374 }
1375 }
1376
1377 retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, READ_PAGE_DATA,
1378 0, NO_WAIT_INT);
1379 if (retval != STATUS_SUCCESS)
1380 TRACE_RET(chip, STATUS_FAIL);
1381
1382 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR))
1383 TRACE_RET(chip, STATUS_FAIL);
1384
1385 return STATUS_SUCCESS;
1386 }
1387
1388
1389 static int ms_set_bad_block(struct rtsx_chip *chip, u16 phy_blk)
1390 {
1391 struct ms_info *ms_card = &(chip->ms_card);
1392 int retval;
1393 u8 val, data[8], extra[MS_EXTRA_SIZE];
1394
1395 retval = ms_read_extra_data(chip, phy_blk, 0, extra, MS_EXTRA_SIZE);
1396 if (retval != STATUS_SUCCESS)
1397 TRACE_RET(chip, STATUS_FAIL);
1398
1399 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1400 SystemParm, 7);
1401 if (retval != STATUS_SUCCESS)
1402 TRACE_RET(chip, STATUS_FAIL);
1403
1404 ms_set_err_code(chip, MS_NO_ERROR);
1405
1406 if (CHK_MS4BIT(ms_card))
1407 data[0] = 0x88;
1408 else
1409 data[0] = 0x80;
1410
1411 data[1] = 0;
1412 data[2] = (u8)(phy_blk >> 8);
1413 data[3] = (u8)phy_blk;
1414 data[4] = 0x80;
1415 data[5] = 0;
1416 data[6] = extra[0] & 0x7F;
1417 data[7] = 0xFF;
1418
1419 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT, data, 7);
1420 if (retval != STATUS_SUCCESS)
1421 TRACE_RET(chip, STATUS_FAIL);
1422
1423 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1424 if (retval != STATUS_SUCCESS)
1425 TRACE_RET(chip, STATUS_FAIL);
1426
1427 ms_set_err_code(chip, MS_NO_ERROR);
1428 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1429 if (retval != STATUS_SUCCESS)
1430 TRACE_RET(chip, STATUS_FAIL);
1431
1432 if (val & INT_REG_CMDNK) {
1433 ms_set_err_code(chip, MS_CMD_NK);
1434 TRACE_RET(chip, STATUS_FAIL);
1435 }
1436
1437 if (val & INT_REG_CED) {
1438 if (val & INT_REG_ERR) {
1439 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1440 TRACE_RET(chip, STATUS_FAIL);
1441 }
1442 }
1443
1444 return STATUS_SUCCESS;
1445 }
1446
1447
1448 static int ms_erase_block(struct rtsx_chip *chip, u16 phy_blk)
1449 {
1450 struct ms_info *ms_card = &(chip->ms_card);
1451 int retval, i = 0;
1452 u8 val, data[6];
1453
1454 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
1455 SystemParm, 6);
1456 if (retval != STATUS_SUCCESS)
1457 TRACE_RET(chip, STATUS_FAIL);
1458
1459 ms_set_err_code(chip, MS_NO_ERROR);
1460
1461 if (CHK_MS4BIT(ms_card))
1462 data[0] = 0x88;
1463 else
1464 data[0] = 0x80;
1465
1466 data[1] = 0;
1467 data[2] = (u8)(phy_blk >> 8);
1468 data[3] = (u8)phy_blk;
1469 data[4] = 0;
1470 data[5] = 0;
1471
1472 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT, data, 6);
1473 if (retval != STATUS_SUCCESS)
1474 TRACE_RET(chip, STATUS_FAIL);
1475
1476 ERASE_RTY:
1477 retval = ms_send_cmd(chip, BLOCK_ERASE, WAIT_INT);
1478 if (retval != STATUS_SUCCESS)
1479 TRACE_RET(chip, STATUS_FAIL);
1480
1481 ms_set_err_code(chip, MS_NO_ERROR);
1482 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1483 if (retval != STATUS_SUCCESS)
1484 TRACE_RET(chip, STATUS_FAIL);
1485
1486 if (val & INT_REG_CMDNK) {
1487 if (i < 3) {
1488 i++;
1489 goto ERASE_RTY;
1490 }
1491
1492 ms_set_err_code(chip, MS_CMD_NK);
1493 ms_set_bad_block(chip, phy_blk);
1494 TRACE_RET(chip, STATUS_FAIL);
1495 }
1496
1497 if (val & INT_REG_CED) {
1498 if (val & INT_REG_ERR) {
1499 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1500 TRACE_RET(chip, STATUS_FAIL);
1501 }
1502 }
1503
1504 return STATUS_SUCCESS;
1505 }
1506
1507
1508 static void ms_set_page_status(u16 log_blk, u8 type, u8 *extra, int extra_len)
1509 {
1510 if (!extra || (extra_len < MS_EXTRA_SIZE))
1511 return;
1512
1513 memset(extra, 0xFF, MS_EXTRA_SIZE);
1514
1515 if (type == setPS_NG) {
1516 /* set page status as 1:NG,and block status keep 1:OK */
1517 extra[0] = 0xB8;
1518 } else {
1519 /* set page status as 0:Data Error,and block status keep 1:OK */
1520 extra[0] = 0x98;
1521 }
1522
1523 extra[2] = (u8)(log_blk >> 8);
1524 extra[3] = (u8)log_blk;
1525 }
1526
1527 static int ms_init_page(struct rtsx_chip *chip, u16 phy_blk, u16 log_blk,
1528 u8 start_page, u8 end_page)
1529 {
1530 int retval;
1531 u8 extra[MS_EXTRA_SIZE], i;
1532
1533 memset(extra, 0xff, MS_EXTRA_SIZE);
1534
1535 extra[0] = 0xf8; /* Block, page OK, data erased */
1536 extra[1] = 0xff;
1537 extra[2] = (u8)(log_blk >> 8);
1538 extra[3] = (u8)log_blk;
1539
1540 for (i = start_page; i < end_page; i++) {
1541 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1542 ms_set_err_code(chip, MS_NO_CARD);
1543 TRACE_RET(chip, STATUS_FAIL);
1544 }
1545
1546 retval = ms_write_extra_data(chip, phy_blk, i,
1547 extra, MS_EXTRA_SIZE);
1548 if (retval != STATUS_SUCCESS)
1549 TRACE_RET(chip, STATUS_FAIL);
1550 }
1551
1552 return STATUS_SUCCESS;
1553 }
1554
1555 static int ms_copy_page(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
1556 u16 log_blk, u8 start_page, u8 end_page)
1557 {
1558 struct ms_info *ms_card = &(chip->ms_card);
1559 int retval, rty_cnt, uncorrect_flag = 0;
1560 u8 extra[MS_EXTRA_SIZE], val, i, j, data[16];
1561
1562 RTSX_DEBUGP("Copy page from 0x%x to 0x%x, logical block is 0x%x\n",
1563 old_blk, new_blk, log_blk);
1564 RTSX_DEBUGP("start_page = %d, end_page = %d\n", start_page, end_page);
1565
1566 retval = ms_read_extra_data(chip, new_blk, 0, extra, MS_EXTRA_SIZE);
1567 if (retval != STATUS_SUCCESS)
1568 TRACE_RET(chip, STATUS_FAIL);
1569
1570 retval = ms_read_status_reg(chip);
1571 if (retval != STATUS_SUCCESS)
1572 TRACE_RET(chip, STATUS_FAIL);
1573
1574 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1575
1576 if (val & BUF_FULL) {
1577 retval = ms_send_cmd(chip, CLEAR_BUF, WAIT_INT);
1578 if (retval != STATUS_SUCCESS)
1579 TRACE_RET(chip, STATUS_FAIL);
1580
1581 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1582 if (retval != STATUS_SUCCESS)
1583 TRACE_RET(chip, STATUS_FAIL);
1584
1585 if (!(val & INT_REG_CED)) {
1586 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1587 TRACE_RET(chip, STATUS_FAIL);
1588 }
1589 }
1590
1591 for (i = start_page; i < end_page; i++) {
1592 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1593 ms_set_err_code(chip, MS_NO_CARD);
1594 TRACE_RET(chip, STATUS_FAIL);
1595 }
1596
1597 ms_read_extra_data(chip, old_blk, i, extra, MS_EXTRA_SIZE);
1598
1599 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1600 MS_EXTRA_SIZE, SystemParm, 6);
1601 if (retval != STATUS_SUCCESS)
1602 TRACE_RET(chip, STATUS_FAIL);
1603
1604 ms_set_err_code(chip, MS_NO_ERROR);
1605
1606 if (CHK_MS4BIT(ms_card))
1607 data[0] = 0x88;
1608 else
1609 data[0] = 0x80;
1610
1611 data[1] = 0;
1612 data[2] = (u8)(old_blk >> 8);
1613 data[3] = (u8)old_blk;
1614 data[4] = 0x20;
1615 data[5] = i;
1616
1617 retval = ms_write_bytes(chip, WRITE_REG , 6, NO_WAIT_INT,
1618 data, 6);
1619 if (retval != STATUS_SUCCESS)
1620 TRACE_RET(chip, STATUS_FAIL);
1621
1622 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
1623 if (retval != STATUS_SUCCESS)
1624 TRACE_RET(chip, STATUS_FAIL);
1625
1626 ms_set_err_code(chip, MS_NO_ERROR);
1627 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1628 if (retval != STATUS_SUCCESS)
1629 TRACE_RET(chip, STATUS_FAIL);
1630
1631 if (val & INT_REG_CMDNK) {
1632 ms_set_err_code(chip, MS_CMD_NK);
1633 TRACE_RET(chip, STATUS_FAIL);
1634 }
1635
1636 if (val & INT_REG_CED) {
1637 if (val & INT_REG_ERR) {
1638 retval = ms_read_status_reg(chip);
1639 if (retval != STATUS_SUCCESS) {
1640 uncorrect_flag = 1;
1641 RTSX_DEBUGP("Uncorrectable error\n");
1642 } else {
1643 uncorrect_flag = 0;
1644 }
1645
1646 retval = ms_transfer_tpc(chip,
1647 MS_TM_NORMAL_READ,
1648 READ_PAGE_DATA,
1649 0, NO_WAIT_INT);
1650 if (retval != STATUS_SUCCESS)
1651 TRACE_RET(chip, STATUS_FAIL);
1652
1653 if (uncorrect_flag) {
1654 ms_set_page_status(log_blk, setPS_NG,
1655 extra, MS_EXTRA_SIZE);
1656 if (i == 0)
1657 extra[0] &= 0xEF;
1658
1659 ms_write_extra_data(chip, old_blk, i,
1660 extra, MS_EXTRA_SIZE);
1661 RTSX_DEBUGP("page %d : extra[0] = 0x%x\n", i, extra[0]);
1662 MS_SET_BAD_BLOCK_FLG(ms_card);
1663
1664 ms_set_page_status(log_blk, setPS_Error,
1665 extra, MS_EXTRA_SIZE);
1666 ms_write_extra_data(chip, new_blk, i,
1667 extra, MS_EXTRA_SIZE);
1668 continue;
1669 }
1670
1671 for (rty_cnt = 0; rty_cnt < MS_MAX_RETRY_COUNT;
1672 rty_cnt++) {
1673 retval = ms_transfer_tpc(
1674 chip,
1675 MS_TM_NORMAL_WRITE,
1676 WRITE_PAGE_DATA,
1677 0, NO_WAIT_INT);
1678 if (retval == STATUS_SUCCESS)
1679 break;
1680 }
1681 if (rty_cnt == MS_MAX_RETRY_COUNT)
1682 TRACE_RET(chip, STATUS_FAIL);
1683 }
1684
1685 if (!(val & INT_REG_BREQ)) {
1686 ms_set_err_code(chip, MS_BREQ_ERROR);
1687 TRACE_RET(chip, STATUS_FAIL);
1688 }
1689 }
1690
1691 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1692 MS_EXTRA_SIZE, SystemParm, (6+MS_EXTRA_SIZE));
1693
1694 ms_set_err_code(chip, MS_NO_ERROR);
1695
1696 if (CHK_MS4BIT(ms_card))
1697 data[0] = 0x88;
1698 else
1699 data[0] = 0x80;
1700
1701 data[1] = 0;
1702 data[2] = (u8)(new_blk >> 8);
1703 data[3] = (u8)new_blk;
1704 data[4] = 0x20;
1705 data[5] = i;
1706
1707 if ((extra[0] & 0x60) != 0x60)
1708 data[6] = extra[0];
1709 else
1710 data[6] = 0xF8;
1711
1712 data[6 + 1] = 0xFF;
1713 data[6 + 2] = (u8)(log_blk >> 8);
1714 data[6 + 3] = (u8)log_blk;
1715
1716 for (j = 4; j <= MS_EXTRA_SIZE; j++)
1717 data[6 + j] = 0xFF;
1718
1719 retval = ms_write_bytes(chip, WRITE_REG, (6 + MS_EXTRA_SIZE),
1720 NO_WAIT_INT, data, 16);
1721 if (retval != STATUS_SUCCESS)
1722 TRACE_RET(chip, STATUS_FAIL);
1723
1724 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1725 if (retval != STATUS_SUCCESS)
1726 TRACE_RET(chip, STATUS_FAIL);
1727
1728 ms_set_err_code(chip, MS_NO_ERROR);
1729 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
1730 if (retval != STATUS_SUCCESS)
1731 TRACE_RET(chip, STATUS_FAIL);
1732
1733 if (val & INT_REG_CMDNK) {
1734 ms_set_err_code(chip, MS_CMD_NK);
1735 TRACE_RET(chip, STATUS_FAIL);
1736 }
1737
1738 if (val & INT_REG_CED) {
1739 if (val & INT_REG_ERR) {
1740 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
1741 TRACE_RET(chip, STATUS_FAIL);
1742 }
1743 }
1744
1745 if (i == 0) {
1746 retval = ms_set_rw_reg_addr(chip, OverwriteFlag,
1747 MS_EXTRA_SIZE, SystemParm, 7);
1748 if (retval != STATUS_SUCCESS)
1749 TRACE_RET(chip, STATUS_FAIL);
1750
1751 ms_set_err_code(chip, MS_NO_ERROR);
1752
1753 if (CHK_MS4BIT(ms_card))
1754 data[0] = 0x88;
1755 else
1756 data[0] = 0x80;
1757
1758 data[1] = 0;
1759 data[2] = (u8)(old_blk >> 8);
1760 data[3] = (u8)old_blk;
1761 data[4] = 0x80;
1762 data[5] = 0;
1763 data[6] = 0xEF;
1764 data[7] = 0xFF;
1765
1766 retval = ms_write_bytes(chip, WRITE_REG, 7,
1767 NO_WAIT_INT, data, 8);
1768 if (retval != STATUS_SUCCESS)
1769 TRACE_RET(chip, STATUS_FAIL);
1770
1771 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
1772 if (retval != STATUS_SUCCESS)
1773 TRACE_RET(chip, STATUS_FAIL);
1774
1775 ms_set_err_code(chip, MS_NO_ERROR);
1776 retval = ms_read_bytes(chip, GET_INT, 1,
1777 NO_WAIT_INT, &val, 1);
1778 if (retval != STATUS_SUCCESS)
1779 TRACE_RET(chip, STATUS_FAIL);
1780
1781 if (val & INT_REG_CMDNK) {
1782 ms_set_err_code(chip, MS_CMD_NK);
1783 TRACE_RET(chip, STATUS_FAIL);
1784 }
1785
1786 if (val & INT_REG_CED) {
1787 if (val & INT_REG_ERR) {
1788 ms_set_err_code(chip,
1789 MS_FLASH_WRITE_ERROR);
1790 TRACE_RET(chip, STATUS_FAIL);
1791 }
1792 }
1793 }
1794 }
1795
1796 return STATUS_SUCCESS;
1797 }
1798
1799
1800 static int reset_ms(struct rtsx_chip *chip)
1801 {
1802 struct ms_info *ms_card = &(chip->ms_card);
1803 int retval;
1804 u16 i, reg_addr, block_size;
1805 u8 val, extra[MS_EXTRA_SIZE], j, *ptr;
1806 #ifndef SUPPORT_MAGIC_GATE
1807 u16 eblock_cnt;
1808 #endif
1809
1810 retval = ms_prepare_reset(chip);
1811 if (retval != STATUS_SUCCESS)
1812 TRACE_RET(chip, STATUS_FAIL);
1813
1814 ms_card->ms_type |= TYPE_MS;
1815
1816 retval = ms_send_cmd(chip, MS_RESET, NO_WAIT_INT);
1817 if (retval != STATUS_SUCCESS)
1818 TRACE_RET(chip, STATUS_FAIL);
1819
1820 retval = ms_read_status_reg(chip);
1821 if (retval != STATUS_SUCCESS)
1822 TRACE_RET(chip, STATUS_FAIL);
1823
1824 RTSX_READ_REG(chip, PPBUF_BASE2, &val);
1825 if (val & WRT_PRTCT)
1826 chip->card_wp |= MS_CARD;
1827 else
1828 chip->card_wp &= ~MS_CARD;
1829
1830 i = 0;
1831
1832 RE_SEARCH:
1833 /* Search Boot Block */
1834 while (i < (MAX_DEFECTIVE_BLOCK + 2)) {
1835 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
1836 ms_set_err_code(chip, MS_NO_CARD);
1837 TRACE_RET(chip, STATUS_FAIL);
1838 }
1839
1840 retval = ms_read_extra_data(chip, i, 0, extra, MS_EXTRA_SIZE);
1841 if (retval != STATUS_SUCCESS) {
1842 i++;
1843 continue;
1844 }
1845
1846 if (extra[0] & BLOCK_OK) {
1847 if (!(extra[1] & NOT_BOOT_BLOCK)) {
1848 ms_card->boot_block = i;
1849 break;
1850 }
1851 }
1852 i++;
1853 }
1854
1855 if (i == (MAX_DEFECTIVE_BLOCK + 2)) {
1856 RTSX_DEBUGP("No boot block found!");
1857 TRACE_RET(chip, STATUS_FAIL);
1858 }
1859
1860 for (j = 0; j < 3; j++) {
1861 retval = ms_read_page(chip, ms_card->boot_block, j);
1862 if (retval != STATUS_SUCCESS) {
1863 if (ms_check_err_code(chip, MS_FLASH_WRITE_ERROR)) {
1864 i = ms_card->boot_block + 1;
1865 ms_set_err_code(chip, MS_NO_ERROR);
1866 goto RE_SEARCH;
1867 }
1868 }
1869 }
1870
1871 retval = ms_read_page(chip, ms_card->boot_block, 0);
1872 if (retval != STATUS_SUCCESS)
1873 TRACE_RET(chip, STATUS_FAIL);
1874
1875 /* Read MS system information as sys_info */
1876 rtsx_init_cmd(chip);
1877
1878 for (i = 0; i < 96; i++)
1879 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + 0x1A0 + i, 0, 0);
1880
1881 retval = rtsx_send_cmd(chip, MS_CARD, 100);
1882 if (retval < 0)
1883 TRACE_RET(chip, STATUS_FAIL);
1884
1885 ptr = rtsx_get_cmd_data(chip);
1886 memcpy(ms_card->raw_sys_info, ptr, 96);
1887
1888 /* Read useful block contents */
1889 rtsx_init_cmd(chip);
1890
1891 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID0, 0, 0);
1892 rtsx_add_cmd(chip, READ_REG_CMD, HEADER_ID1, 0, 0);
1893
1894 for (reg_addr = DISABLED_BLOCK0; reg_addr <= DISABLED_BLOCK3;
1895 reg_addr++)
1896 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1897
1898 for (reg_addr = BLOCK_SIZE_0; reg_addr <= PAGE_SIZE_1; reg_addr++)
1899 rtsx_add_cmd(chip, READ_REG_CMD, reg_addr, 0, 0);
1900
1901 rtsx_add_cmd(chip, READ_REG_CMD, MS_Device_Type, 0, 0);
1902 rtsx_add_cmd(chip, READ_REG_CMD, MS_4bit_Support, 0, 0);
1903
1904 retval = rtsx_send_cmd(chip, MS_CARD, 100);
1905 if (retval < 0)
1906 TRACE_RET(chip, STATUS_FAIL);
1907
1908 ptr = rtsx_get_cmd_data(chip);
1909
1910 RTSX_DEBUGP("Boot block data:\n");
1911 RTSX_DUMP(ptr, 16);
1912
1913 /* Block ID error
1914 * HEADER_ID0, HEADER_ID1
1915 */
1916 if (ptr[0] != 0x00 || ptr[1] != 0x01) {
1917 i = ms_card->boot_block + 1;
1918 goto RE_SEARCH;
1919 }
1920
1921 /* Page size error
1922 * PAGE_SIZE_0, PAGE_SIZE_1
1923 */
1924 if (ptr[12] != 0x02 || ptr[13] != 0x00) {
1925 i = ms_card->boot_block + 1;
1926 goto RE_SEARCH;
1927 }
1928
1929 if ((ptr[14] == 1) || (ptr[14] == 3))
1930 chip->card_wp |= MS_CARD;
1931
1932 /* BLOCK_SIZE_0, BLOCK_SIZE_1 */
1933 block_size = ((u16)ptr[6] << 8) | ptr[7];
1934 if (block_size == 0x0010) {
1935 /* Block size 16KB */
1936 ms_card->block_shift = 5;
1937 ms_card->page_off = 0x1F;
1938 } else if (block_size == 0x0008) {
1939 /* Block size 8KB */
1940 ms_card->block_shift = 4;
1941 ms_card->page_off = 0x0F;
1942 }
1943
1944 /* BLOCK_COUNT_0, BLOCK_COUNT_1 */
1945 ms_card->total_block = ((u16)ptr[8] << 8) | ptr[9];
1946
1947 #ifdef SUPPORT_MAGIC_GATE
1948 j = ptr[10];
1949
1950 if (ms_card->block_shift == 4) { /* 4MB or 8MB */
1951 if (j < 2) { /* Effective block for 4MB: 0x1F0 */
1952 ms_card->capacity = 0x1EE0;
1953 } else { /* Effective block for 8MB: 0x3E0 */
1954 ms_card->capacity = 0x3DE0;
1955 }
1956 } else { /* 16MB, 32MB, 64MB or 128MB */
1957 if (j < 5) { /* Effective block for 16MB: 0x3E0 */
1958 ms_card->capacity = 0x7BC0;
1959 } else if (j < 0xA) { /* Effective block for 32MB: 0x7C0 */
1960 ms_card->capacity = 0xF7C0;
1961 } else if (j < 0x11) { /* Effective block for 64MB: 0xF80 */
1962 ms_card->capacity = 0x1EF80;
1963 } else { /* Effective block for 128MB: 0x1F00 */
1964 ms_card->capacity = 0x3DF00;
1965 }
1966 }
1967 #else
1968 /* EBLOCK_COUNT_0, EBLOCK_COUNT_1 */
1969 eblock_cnt = ((u16)ptr[10] << 8) | ptr[11];
1970
1971 ms_card->capacity = ((u32)eblock_cnt - 2) << ms_card->block_shift;
1972 #endif
1973
1974 chip->capacity[chip->card2lun[MS_CARD]] = ms_card->capacity;
1975
1976 /* Switch I/F Mode */
1977 if (ptr[15]) {
1978 retval = ms_set_rw_reg_addr(chip, 0, 0, SystemParm, 1);
1979 if (retval != STATUS_SUCCESS)
1980 TRACE_RET(chip, STATUS_FAIL);
1981
1982 RTSX_WRITE_REG(chip, PPBUF_BASE2, 0xFF, 0x88);
1983 RTSX_WRITE_REG(chip, PPBUF_BASE2 + 1, 0xFF, 0);
1984
1985 retval = ms_transfer_tpc(chip, MS_TM_WRITE_BYTES, WRITE_REG , 1,
1986 NO_WAIT_INT);
1987 if (retval != STATUS_SUCCESS)
1988 TRACE_RET(chip, STATUS_FAIL);
1989
1990 RTSX_WRITE_REG(chip, MS_CFG, 0x58 | MS_NO_CHECK_INT,
1991 MS_BUS_WIDTH_4 | PUSH_TIME_ODD | MS_NO_CHECK_INT);
1992
1993 ms_card->ms_type |= MS_4BIT;
1994 }
1995
1996 if (CHK_MS4BIT(ms_card))
1997 chip->card_bus_width[chip->card2lun[MS_CARD]] = 4;
1998 else
1999 chip->card_bus_width[chip->card2lun[MS_CARD]] = 1;
2000
2001 return STATUS_SUCCESS;
2002 }
2003
2004 static int ms_init_l2p_tbl(struct rtsx_chip *chip)
2005 {
2006 struct ms_info *ms_card = &(chip->ms_card);
2007 int size, i, seg_no, retval;
2008 u16 defect_block, reg_addr;
2009 u8 val1, val2;
2010
2011 ms_card->segment_cnt = ms_card->total_block >> 9;
2012 RTSX_DEBUGP("ms_card->segment_cnt = %d\n", ms_card->segment_cnt);
2013
2014 size = ms_card->segment_cnt * sizeof(struct zone_entry);
2015 ms_card->segment = vzalloc(size);
2016 if (ms_card->segment == NULL)
2017 TRACE_RET(chip, STATUS_FAIL);
2018
2019 retval = ms_read_page(chip, ms_card->boot_block, 1);
2020 if (retval != STATUS_SUCCESS)
2021 TRACE_GOTO(chip, INIT_FAIL);
2022
2023 reg_addr = PPBUF_BASE2;
2024 for (i = 0; i < (((ms_card->total_block >> 9) * 10) + 1); i++) {
2025 retval = rtsx_read_register(chip, reg_addr++, &val1);
2026 if (retval != STATUS_SUCCESS)
2027 TRACE_GOTO(chip, INIT_FAIL);
2028
2029 retval = rtsx_read_register(chip, reg_addr++, &val2);
2030 if (retval != STATUS_SUCCESS)
2031 TRACE_GOTO(chip, INIT_FAIL);
2032
2033 defect_block = ((u16)val1 << 8) | val2;
2034 if (defect_block == 0xFFFF)
2035 break;
2036
2037 seg_no = defect_block / 512;
2038 ms_card->segment[seg_no].defect_list[ms_card->segment[seg_no].disable_count++] = defect_block;
2039 }
2040
2041 for (i = 0; i < ms_card->segment_cnt; i++) {
2042 ms_card->segment[i].build_flag = 0;
2043 ms_card->segment[i].l2p_table = NULL;
2044 ms_card->segment[i].free_table = NULL;
2045 ms_card->segment[i].get_index = 0;
2046 ms_card->segment[i].set_index = 0;
2047 ms_card->segment[i].unused_blk_cnt = 0;
2048
2049 RTSX_DEBUGP("defective block count of segment %d is %d\n",
2050 i, ms_card->segment[i].disable_count);
2051 }
2052
2053 return STATUS_SUCCESS;
2054
2055 INIT_FAIL:
2056 if (ms_card->segment) {
2057 vfree(ms_card->segment);
2058 ms_card->segment = NULL;
2059 }
2060
2061 return STATUS_FAIL;
2062 }
2063
2064 static u16 ms_get_l2p_tbl(struct rtsx_chip *chip, int seg_no, u16 log_off)
2065 {
2066 struct ms_info *ms_card = &(chip->ms_card);
2067 struct zone_entry *segment;
2068
2069 if (ms_card->segment == NULL)
2070 return 0xFFFF;
2071
2072 segment = &(ms_card->segment[seg_no]);
2073
2074 if (segment->l2p_table)
2075 return segment->l2p_table[log_off];
2076
2077 return 0xFFFF;
2078 }
2079
2080 static void ms_set_l2p_tbl(struct rtsx_chip *chip,
2081 int seg_no, u16 log_off, u16 phy_blk)
2082 {
2083 struct ms_info *ms_card = &(chip->ms_card);
2084 struct zone_entry *segment;
2085
2086 if (ms_card->segment == NULL)
2087 return;
2088
2089 segment = &(ms_card->segment[seg_no]);
2090 if (segment->l2p_table)
2091 segment->l2p_table[log_off] = phy_blk;
2092 }
2093
2094 static void ms_set_unused_block(struct rtsx_chip *chip, u16 phy_blk)
2095 {
2096 struct ms_info *ms_card = &(chip->ms_card);
2097 struct zone_entry *segment;
2098 int seg_no;
2099
2100 seg_no = (int)phy_blk >> 9;
2101 segment = &(ms_card->segment[seg_no]);
2102
2103 segment->free_table[segment->set_index++] = phy_blk;
2104 if (segment->set_index >= MS_FREE_TABLE_CNT)
2105 segment->set_index = 0;
2106
2107 segment->unused_blk_cnt++;
2108 }
2109
2110 static u16 ms_get_unused_block(struct rtsx_chip *chip, int seg_no)
2111 {
2112 struct ms_info *ms_card = &(chip->ms_card);
2113 struct zone_entry *segment;
2114 u16 phy_blk;
2115
2116 segment = &(ms_card->segment[seg_no]);
2117
2118 if (segment->unused_blk_cnt <= 0)
2119 return 0xFFFF;
2120
2121 phy_blk = segment->free_table[segment->get_index];
2122 segment->free_table[segment->get_index++] = 0xFFFF;
2123 if (segment->get_index >= MS_FREE_TABLE_CNT)
2124 segment->get_index = 0;
2125
2126 segment->unused_blk_cnt--;
2127
2128 return phy_blk;
2129 }
2130
2131 static const unsigned short ms_start_idx[] = {0, 494, 990, 1486, 1982, 2478,
2132 2974, 3470, 3966, 4462, 4958,
2133 5454, 5950, 6446, 6942, 7438,
2134 7934};
2135
2136 static int ms_arbitrate_l2p(struct rtsx_chip *chip, u16 phy_blk,
2137 u16 log_off, u8 us1, u8 us2)
2138 {
2139 struct ms_info *ms_card = &(chip->ms_card);
2140 struct zone_entry *segment;
2141 int seg_no;
2142 u16 tmp_blk;
2143
2144 seg_no = (int)phy_blk >> 9;
2145 segment = &(ms_card->segment[seg_no]);
2146 tmp_blk = segment->l2p_table[log_off];
2147
2148 if (us1 != us2) {
2149 if (us1 == 0) {
2150 if (!(chip->card_wp & MS_CARD))
2151 ms_erase_block(chip, tmp_blk);
2152
2153 ms_set_unused_block(chip, tmp_blk);
2154 segment->l2p_table[log_off] = phy_blk;
2155 } else {
2156 if (!(chip->card_wp & MS_CARD))
2157 ms_erase_block(chip, phy_blk);
2158
2159 ms_set_unused_block(chip, phy_blk);
2160 }
2161 } else {
2162 if (phy_blk < tmp_blk) {
2163 if (!(chip->card_wp & MS_CARD))
2164 ms_erase_block(chip, phy_blk);
2165
2166 ms_set_unused_block(chip, phy_blk);
2167 } else {
2168 if (!(chip->card_wp & MS_CARD))
2169 ms_erase_block(chip, tmp_blk);
2170
2171 ms_set_unused_block(chip, tmp_blk);
2172 segment->l2p_table[log_off] = phy_blk;
2173 }
2174 }
2175
2176 return STATUS_SUCCESS;
2177 }
2178
2179 static int ms_build_l2p_tbl(struct rtsx_chip *chip, int seg_no)
2180 {
2181 struct ms_info *ms_card = &(chip->ms_card);
2182 struct zone_entry *segment;
2183 int retval, table_size, disable_cnt, defect_flag, i;
2184 u16 start, end, phy_blk, log_blk, tmp_blk;
2185 u8 extra[MS_EXTRA_SIZE], us1, us2;
2186
2187 RTSX_DEBUGP("ms_build_l2p_tbl: %d\n", seg_no);
2188
2189 if (ms_card->segment == NULL) {
2190 retval = ms_init_l2p_tbl(chip);
2191 if (retval != STATUS_SUCCESS)
2192 TRACE_RET(chip, retval);
2193 }
2194
2195 if (ms_card->segment[seg_no].build_flag) {
2196 RTSX_DEBUGP("l2p table of segment %d has been built\n", seg_no);
2197 return STATUS_SUCCESS;
2198 }
2199
2200 if (seg_no == 0)
2201 table_size = 494;
2202 else
2203 table_size = 496;
2204
2205 segment = &(ms_card->segment[seg_no]);
2206
2207 if (segment->l2p_table == NULL) {
2208 segment->l2p_table = vmalloc(table_size * 2);
2209 if (segment->l2p_table == NULL)
2210 TRACE_GOTO(chip, BUILD_FAIL);
2211 }
2212 memset((u8 *)(segment->l2p_table), 0xff, table_size * 2);
2213
2214 if (segment->free_table == NULL) {
2215 segment->free_table = vmalloc(MS_FREE_TABLE_CNT * 2);
2216 if (segment->free_table == NULL)
2217 TRACE_GOTO(chip, BUILD_FAIL);
2218 }
2219 memset((u8 *)(segment->free_table), 0xff, MS_FREE_TABLE_CNT * 2);
2220
2221 start = (u16)seg_no << 9;
2222 end = (u16)(seg_no + 1) << 9;
2223
2224 disable_cnt = segment->disable_count;
2225
2226 segment->get_index = segment->set_index = 0;
2227 segment->unused_blk_cnt = 0;
2228
2229 for (phy_blk = start; phy_blk < end; phy_blk++) {
2230 if (disable_cnt) {
2231 defect_flag = 0;
2232 for (i = 0; i < segment->disable_count; i++) {
2233 if (phy_blk == segment->defect_list[i]) {
2234 defect_flag = 1;
2235 break;
2236 }
2237 }
2238 if (defect_flag) {
2239 disable_cnt--;
2240 continue;
2241 }
2242 }
2243
2244 retval = ms_read_extra_data(chip, phy_blk, 0,
2245 extra, MS_EXTRA_SIZE);
2246 if (retval != STATUS_SUCCESS) {
2247 RTSX_DEBUGP("read extra data fail\n");
2248 ms_set_bad_block(chip, phy_blk);
2249 continue;
2250 }
2251
2252 if (seg_no == ms_card->segment_cnt - 1) {
2253 if (!(extra[1] & NOT_TRANSLATION_TABLE)) {
2254 if (!(chip->card_wp & MS_CARD)) {
2255 retval = ms_erase_block(chip, phy_blk);
2256 if (retval != STATUS_SUCCESS)
2257 continue;
2258 extra[2] = 0xff;
2259 extra[3] = 0xff;
2260 }
2261 }
2262 }
2263
2264 if (!(extra[0] & BLOCK_OK))
2265 continue;
2266 if (!(extra[1] & NOT_BOOT_BLOCK))
2267 continue;
2268 if ((extra[0] & PAGE_OK) != PAGE_OK)
2269 continue;
2270
2271 log_blk = ((u16)extra[2] << 8) | extra[3];
2272
2273 if (log_blk == 0xFFFF) {
2274 if (!(chip->card_wp & MS_CARD)) {
2275 retval = ms_erase_block(chip, phy_blk);
2276 if (retval != STATUS_SUCCESS)
2277 continue;
2278 }
2279 ms_set_unused_block(chip, phy_blk);
2280 continue;
2281 }
2282
2283 if ((log_blk < ms_start_idx[seg_no]) ||
2284 (log_blk >= ms_start_idx[seg_no+1])) {
2285 if (!(chip->card_wp & MS_CARD)) {
2286 retval = ms_erase_block(chip, phy_blk);
2287 if (retval != STATUS_SUCCESS)
2288 continue;
2289 }
2290 ms_set_unused_block(chip, phy_blk);
2291 continue;
2292 }
2293
2294 if (segment->l2p_table[log_blk - ms_start_idx[seg_no]] == 0xFFFF) {
2295 segment->l2p_table[log_blk - ms_start_idx[seg_no]] = phy_blk;
2296 continue;
2297 }
2298
2299 us1 = extra[0] & 0x10;
2300 tmp_blk = segment->l2p_table[log_blk - ms_start_idx[seg_no]];
2301 retval = ms_read_extra_data(chip, tmp_blk, 0,
2302 extra, MS_EXTRA_SIZE);
2303 if (retval != STATUS_SUCCESS)
2304 continue;
2305 us2 = extra[0] & 0x10;
2306
2307 (void)ms_arbitrate_l2p(chip, phy_blk,
2308 log_blk-ms_start_idx[seg_no], us1, us2);
2309 continue;
2310 }
2311
2312 segment->build_flag = 1;
2313
2314 RTSX_DEBUGP("unused block count: %d\n", segment->unused_blk_cnt);
2315
2316 /* Logical Address Confirmation Process */
2317 if (seg_no == ms_card->segment_cnt - 1) {
2318 if (segment->unused_blk_cnt < 2)
2319 chip->card_wp |= MS_CARD;
2320 } else {
2321 if (segment->unused_blk_cnt < 1)
2322 chip->card_wp |= MS_CARD;
2323 }
2324
2325 if (chip->card_wp & MS_CARD)
2326 return STATUS_SUCCESS;
2327
2328 for (log_blk = ms_start_idx[seg_no];
2329 log_blk < ms_start_idx[seg_no + 1]; log_blk++) {
2330 if (segment->l2p_table[log_blk-ms_start_idx[seg_no]] == 0xFFFF) {
2331 phy_blk = ms_get_unused_block(chip, seg_no);
2332 if (phy_blk == 0xFFFF) {
2333 chip->card_wp |= MS_CARD;
2334 return STATUS_SUCCESS;
2335 }
2336 retval = ms_init_page(chip, phy_blk, log_blk, 0, 1);
2337 if (retval != STATUS_SUCCESS)
2338 TRACE_GOTO(chip, BUILD_FAIL);
2339
2340 segment->l2p_table[log_blk-ms_start_idx[seg_no]] = phy_blk;
2341 if (seg_no == ms_card->segment_cnt - 1) {
2342 if (segment->unused_blk_cnt < 2) {
2343 chip->card_wp |= MS_CARD;
2344 return STATUS_SUCCESS;
2345 }
2346 } else {
2347 if (segment->unused_blk_cnt < 1) {
2348 chip->card_wp |= MS_CARD;
2349 return STATUS_SUCCESS;
2350 }
2351 }
2352 }
2353 }
2354
2355 /* Make boot block be the first normal block */
2356 if (seg_no == 0) {
2357 for (log_blk = 0; log_blk < 494; log_blk++) {
2358 tmp_blk = segment->l2p_table[log_blk];
2359 if (tmp_blk < ms_card->boot_block) {
2360 RTSX_DEBUGP("Boot block is not the first normal block.\n");
2361
2362 if (chip->card_wp & MS_CARD)
2363 break;
2364
2365 phy_blk = ms_get_unused_block(chip, 0);
2366 retval = ms_copy_page(chip, tmp_blk, phy_blk,
2367 log_blk, 0, ms_card->page_off + 1);
2368 if (retval != STATUS_SUCCESS)
2369 TRACE_RET(chip, STATUS_FAIL);
2370
2371 segment->l2p_table[log_blk] = phy_blk;
2372
2373 retval = ms_set_bad_block(chip, tmp_blk);
2374 if (retval != STATUS_SUCCESS)
2375 TRACE_RET(chip, STATUS_FAIL);
2376 }
2377 }
2378 }
2379
2380 return STATUS_SUCCESS;
2381
2382 BUILD_FAIL:
2383 segment->build_flag = 0;
2384 if (segment->l2p_table) {
2385 vfree(segment->l2p_table);
2386 segment->l2p_table = NULL;
2387 }
2388 if (segment->free_table) {
2389 vfree(segment->free_table);
2390 segment->free_table = NULL;
2391 }
2392
2393 return STATUS_FAIL;
2394 }
2395
2396
2397 int reset_ms_card(struct rtsx_chip *chip)
2398 {
2399 struct ms_info *ms_card = &(chip->ms_card);
2400 int retval;
2401
2402 memset(ms_card, 0, sizeof(struct ms_info));
2403
2404 retval = enable_card_clock(chip, MS_CARD);
2405 if (retval != STATUS_SUCCESS)
2406 TRACE_RET(chip, STATUS_FAIL);
2407
2408 retval = select_card(chip, MS_CARD);
2409 if (retval != STATUS_SUCCESS)
2410 TRACE_RET(chip, STATUS_FAIL);
2411
2412 ms_card->ms_type = 0;
2413
2414 retval = reset_ms_pro(chip);
2415 if (retval != STATUS_SUCCESS) {
2416 if (ms_card->check_ms_flow) {
2417 retval = reset_ms(chip);
2418 if (retval != STATUS_SUCCESS)
2419 TRACE_RET(chip, STATUS_FAIL);
2420 } else {
2421 TRACE_RET(chip, STATUS_FAIL);
2422 }
2423 }
2424
2425 retval = ms_set_init_para(chip);
2426 if (retval != STATUS_SUCCESS)
2427 TRACE_RET(chip, STATUS_FAIL);
2428
2429 if (!CHK_MSPRO(ms_card)) {
2430 /* Build table for the last segment,
2431 * to check if L2P table block exists, erasing it
2432 */
2433 retval = ms_build_l2p_tbl(chip, ms_card->total_block / 512 - 1);
2434 if (retval != STATUS_SUCCESS)
2435 TRACE_RET(chip, STATUS_FAIL);
2436 }
2437
2438 RTSX_DEBUGP("ms_card->ms_type = 0x%x\n", ms_card->ms_type);
2439
2440 return STATUS_SUCCESS;
2441 }
2442
2443 static int mspro_set_rw_cmd(struct rtsx_chip *chip,
2444 u32 start_sec, u16 sec_cnt, u8 cmd)
2445 {
2446 int retval, i;
2447 u8 data[8];
2448
2449 data[0] = cmd;
2450 data[1] = (u8)(sec_cnt >> 8);
2451 data[2] = (u8)sec_cnt;
2452 data[3] = (u8)(start_sec >> 24);
2453 data[4] = (u8)(start_sec >> 16);
2454 data[5] = (u8)(start_sec >> 8);
2455 data[6] = (u8)start_sec;
2456 data[7] = 0;
2457
2458 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2459 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7,
2460 WAIT_INT, data, 8);
2461 if (retval == STATUS_SUCCESS)
2462 break;
2463 }
2464 if (i == MS_MAX_RETRY_COUNT)
2465 TRACE_RET(chip, STATUS_FAIL);
2466
2467 return STATUS_SUCCESS;
2468 }
2469
2470
2471 void mspro_stop_seq_mode(struct rtsx_chip *chip)
2472 {
2473 struct ms_info *ms_card = &(chip->ms_card);
2474 int retval;
2475
2476 RTSX_DEBUGP("--%s--\n", __func__);
2477
2478 if (ms_card->seq_mode) {
2479 retval = ms_switch_clock(chip);
2480 if (retval != STATUS_SUCCESS)
2481 return;
2482
2483 ms_card->seq_mode = 0;
2484 ms_card->total_sec_cnt = 0;
2485 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2486
2487 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2488 }
2489 }
2490
2491 static inline int ms_auto_tune_clock(struct rtsx_chip *chip)
2492 {
2493 struct ms_info *ms_card = &(chip->ms_card);
2494 int retval;
2495
2496 RTSX_DEBUGP("--%s--\n", __func__);
2497
2498 if (chip->asic_code) {
2499 if (ms_card->ms_clock > 30)
2500 ms_card->ms_clock -= 20;
2501 } else {
2502 if (ms_card->ms_clock == CLK_80)
2503 ms_card->ms_clock = CLK_60;
2504 else if (ms_card->ms_clock == CLK_60)
2505 ms_card->ms_clock = CLK_40;
2506 }
2507
2508 retval = ms_switch_clock(chip);
2509 if (retval != STATUS_SUCCESS)
2510 TRACE_RET(chip, STATUS_FAIL);
2511
2512 return STATUS_SUCCESS;
2513 }
2514
2515 static int mspro_rw_multi_sector(struct scsi_cmnd *srb,
2516 struct rtsx_chip *chip, u32 start_sector,
2517 u16 sector_cnt)
2518 {
2519 struct ms_info *ms_card = &(chip->ms_card);
2520 int retval, mode_2k = 0;
2521 u16 count;
2522 u8 val, trans_mode, rw_tpc, rw_cmd;
2523
2524 ms_set_err_code(chip, MS_NO_ERROR);
2525
2526 ms_card->cleanup_counter = 0;
2527
2528 if (CHK_MSHG(ms_card)) {
2529 if ((start_sector % 4) || (sector_cnt % 4)) {
2530 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2531 rw_tpc = PRO_READ_LONG_DATA;
2532 rw_cmd = PRO_READ_DATA;
2533 } else {
2534 rw_tpc = PRO_WRITE_LONG_DATA;
2535 rw_cmd = PRO_WRITE_DATA;
2536 }
2537 } else {
2538 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2539 rw_tpc = PRO_READ_QUAD_DATA;
2540 rw_cmd = PRO_READ_2K_DATA;
2541 } else {
2542 rw_tpc = PRO_WRITE_QUAD_DATA;
2543 rw_cmd = PRO_WRITE_2K_DATA;
2544 }
2545 mode_2k = 1;
2546 }
2547 } else {
2548 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2549 rw_tpc = PRO_READ_LONG_DATA;
2550 rw_cmd = PRO_READ_DATA;
2551 } else {
2552 rw_tpc = PRO_WRITE_LONG_DATA;
2553 rw_cmd = PRO_WRITE_DATA;
2554 }
2555 }
2556
2557 retval = ms_switch_clock(chip);
2558 if (retval != STATUS_SUCCESS)
2559 TRACE_RET(chip, STATUS_FAIL);
2560
2561 if (srb->sc_data_direction == DMA_FROM_DEVICE)
2562 trans_mode = MS_TM_AUTO_READ;
2563 else
2564 trans_mode = MS_TM_AUTO_WRITE;
2565
2566 RTSX_READ_REG(chip, MS_TRANS_CFG, &val);
2567
2568 if (ms_card->seq_mode) {
2569 if ((ms_card->pre_dir != srb->sc_data_direction)
2570 || ((ms_card->pre_sec_addr + ms_card->pre_sec_cnt) != start_sector)
2571 || (mode_2k && (ms_card->seq_mode & MODE_512_SEQ))
2572 || (!mode_2k && (ms_card->seq_mode & MODE_2K_SEQ))
2573 || !(val & MS_INT_BREQ)
2574 || ((ms_card->total_sec_cnt + sector_cnt) > 0xFE00)) {
2575 ms_card->seq_mode = 0;
2576 ms_card->total_sec_cnt = 0;
2577 if (val & MS_INT_BREQ) {
2578 retval = ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2579 if (retval != STATUS_SUCCESS)
2580 TRACE_RET(chip, STATUS_FAIL);
2581
2582 rtsx_write_register(chip, RBCTL, RB_FLUSH, RB_FLUSH);
2583 }
2584 }
2585 }
2586
2587 if (!ms_card->seq_mode) {
2588 ms_card->total_sec_cnt = 0;
2589 if (sector_cnt >= SEQ_START_CRITERIA) {
2590 if ((ms_card->capacity - start_sector) > 0xFE00)
2591 count = 0xFE00;
2592 else
2593 count = (u16)(ms_card->capacity - start_sector);
2594
2595 if (count > sector_cnt) {
2596 if (mode_2k)
2597 ms_card->seq_mode |= MODE_2K_SEQ;
2598 else
2599 ms_card->seq_mode |= MODE_512_SEQ;
2600 }
2601 } else {
2602 count = sector_cnt;
2603 }
2604 retval = mspro_set_rw_cmd(chip, start_sector, count, rw_cmd);
2605 if (retval != STATUS_SUCCESS) {
2606 ms_card->seq_mode = 0;
2607 TRACE_RET(chip, STATUS_FAIL);
2608 }
2609 }
2610
2611 retval = ms_transfer_data(chip, trans_mode, rw_tpc, sector_cnt,
2612 WAIT_INT, mode_2k, scsi_sg_count(srb),
2613 scsi_sglist(srb), scsi_bufflen(srb));
2614 if (retval != STATUS_SUCCESS) {
2615 ms_card->seq_mode = 0;
2616 rtsx_read_register(chip, MS_TRANS_CFG, &val);
2617 rtsx_clear_ms_error(chip);
2618
2619 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2620 chip->rw_need_retry = 0;
2621 RTSX_DEBUGP("No card exist, exit mspro_rw_multi_sector\n");
2622 TRACE_RET(chip, STATUS_FAIL);
2623 }
2624
2625 if (val & MS_INT_BREQ)
2626 ms_send_cmd(chip, PRO_STOP, WAIT_INT);
2627
2628 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
2629 RTSX_DEBUGP("MSPro CRC error, tune clock!\n");
2630 chip->rw_need_retry = 1;
2631 ms_auto_tune_clock(chip);
2632 }
2633
2634 TRACE_RET(chip, retval);
2635 }
2636
2637 if (ms_card->seq_mode) {
2638 ms_card->pre_sec_addr = start_sector;
2639 ms_card->pre_sec_cnt = sector_cnt;
2640 ms_card->pre_dir = srb->sc_data_direction;
2641 ms_card->total_sec_cnt += sector_cnt;
2642 }
2643
2644 return STATUS_SUCCESS;
2645 }
2646
2647 static int mspro_read_format_progress(struct rtsx_chip *chip,
2648 const int short_data_len)
2649 {
2650 struct ms_info *ms_card = &(chip->ms_card);
2651 int retval, i;
2652 u32 total_progress, cur_progress;
2653 u8 cnt, tmp;
2654 u8 data[8];
2655
2656 RTSX_DEBUGP("mspro_read_format_progress, short_data_len = %d\n",
2657 short_data_len);
2658
2659 retval = ms_switch_clock(chip);
2660 if (retval != STATUS_SUCCESS) {
2661 ms_card->format_status = FORMAT_FAIL;
2662 TRACE_RET(chip, STATUS_FAIL);
2663 }
2664
2665 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2666 if (retval != STATUS_SUCCESS) {
2667 ms_card->format_status = FORMAT_FAIL;
2668 TRACE_RET(chip, STATUS_FAIL);
2669 }
2670
2671 if (!(tmp & MS_INT_BREQ)) {
2672 if ((tmp & (MS_INT_CED | MS_INT_BREQ | MS_INT_CMDNK | MS_INT_ERR)) == MS_INT_CED) {
2673 ms_card->format_status = FORMAT_SUCCESS;
2674 return STATUS_SUCCESS;
2675 }
2676 ms_card->format_status = FORMAT_FAIL;
2677 TRACE_RET(chip, STATUS_FAIL);
2678 }
2679
2680 if (short_data_len >= 256)
2681 cnt = 0;
2682 else
2683 cnt = (u8)short_data_len;
2684
2685 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT,
2686 MS_NO_CHECK_INT);
2687 if (retval != STATUS_SUCCESS) {
2688 ms_card->format_status = FORMAT_FAIL;
2689 TRACE_RET(chip, STATUS_FAIL);
2690 }
2691
2692 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, cnt, WAIT_INT,
2693 data, 8);
2694 if (retval != STATUS_SUCCESS) {
2695 ms_card->format_status = FORMAT_FAIL;
2696 TRACE_RET(chip, STATUS_FAIL);
2697 }
2698
2699 total_progress = (data[0] << 24) | (data[1] << 16) |
2700 (data[2] << 8) | data[3];
2701 cur_progress = (data[4] << 24) | (data[5] << 16) |
2702 (data[6] << 8) | data[7];
2703
2704 RTSX_DEBUGP("total_progress = %d, cur_progress = %d\n",
2705 total_progress, cur_progress);
2706
2707 if (total_progress == 0) {
2708 ms_card->progress = 0;
2709 } else {
2710 u64 ulltmp = (u64)cur_progress * (u64)65535;
2711 do_div(ulltmp, total_progress);
2712 ms_card->progress = (u16)ulltmp;
2713 }
2714 RTSX_DEBUGP("progress = %d\n", ms_card->progress);
2715
2716 for (i = 0; i < 5000; i++) {
2717 retval = rtsx_read_register(chip, MS_TRANS_CFG, &tmp);
2718 if (retval != STATUS_SUCCESS) {
2719 ms_card->format_status = FORMAT_FAIL;
2720 TRACE_RET(chip, STATUS_FAIL);
2721 }
2722 if (tmp & (MS_INT_CED | MS_INT_CMDNK |
2723 MS_INT_BREQ | MS_INT_ERR))
2724 break;
2725
2726 wait_timeout(1);
2727 }
2728
2729 retval = rtsx_write_register(chip, MS_CFG, MS_NO_CHECK_INT, 0);
2730 if (retval != STATUS_SUCCESS) {
2731 ms_card->format_status = FORMAT_FAIL;
2732 TRACE_RET(chip, STATUS_FAIL);
2733 }
2734
2735 if (i == 5000) {
2736 ms_card->format_status = FORMAT_FAIL;
2737 TRACE_RET(chip, STATUS_FAIL);
2738 }
2739
2740 if (tmp & (MS_INT_CMDNK | MS_INT_ERR)) {
2741 ms_card->format_status = FORMAT_FAIL;
2742 TRACE_RET(chip, STATUS_FAIL);
2743 }
2744
2745 if (tmp & MS_INT_CED) {
2746 ms_card->format_status = FORMAT_SUCCESS;
2747 ms_card->pro_under_formatting = 0;
2748 } else if (tmp & MS_INT_BREQ) {
2749 ms_card->format_status = FORMAT_IN_PROGRESS;
2750 } else {
2751 ms_card->format_status = FORMAT_FAIL;
2752 ms_card->pro_under_formatting = 0;
2753 TRACE_RET(chip, STATUS_FAIL);
2754 }
2755
2756 return STATUS_SUCCESS;
2757 }
2758
2759 void mspro_polling_format_status(struct rtsx_chip *chip)
2760 {
2761 struct ms_info *ms_card = &(chip->ms_card);
2762 int i;
2763
2764 if (ms_card->pro_under_formatting &&
2765 (rtsx_get_stat(chip) != RTSX_STAT_SS)) {
2766 rtsx_set_stat(chip, RTSX_STAT_RUN);
2767
2768 for (i = 0; i < 65535; i++) {
2769 mspro_read_format_progress(chip, MS_SHORT_DATA_LEN);
2770 if (ms_card->format_status != FORMAT_IN_PROGRESS)
2771 break;
2772 }
2773 }
2774
2775 return;
2776 }
2777
2778 int mspro_format(struct scsi_cmnd *srb, struct rtsx_chip *chip,
2779 int short_data_len, int quick_format)
2780 {
2781 struct ms_info *ms_card = &(chip->ms_card);
2782 int retval, i;
2783 u8 buf[8], tmp;
2784 u16 para;
2785
2786 RTSX_DEBUGP("--%s--\n", __func__);
2787
2788 retval = ms_switch_clock(chip);
2789 if (retval != STATUS_SUCCESS)
2790 TRACE_RET(chip, STATUS_FAIL);
2791
2792 retval = ms_set_rw_reg_addr(chip, 0x00, 0x00, Pro_TPCParm, 0x01);
2793 if (retval != STATUS_SUCCESS)
2794 TRACE_RET(chip, STATUS_FAIL);
2795
2796 memset(buf, 0, 2);
2797 switch (short_data_len) {
2798 case 32:
2799 buf[0] = 0;
2800 break;
2801 case 64:
2802 buf[0] = 1;
2803 break;
2804 case 128:
2805 buf[0] = 2;
2806 break;
2807 case 256:
2808 default:
2809 buf[0] = 3;
2810 break;
2811 }
2812
2813 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2814 retval = ms_write_bytes(chip, PRO_WRITE_REG, 1,
2815 NO_WAIT_INT, buf, 2);
2816 if (retval == STATUS_SUCCESS)
2817 break;
2818 }
2819 if (i == MS_MAX_RETRY_COUNT)
2820 TRACE_RET(chip, STATUS_FAIL);
2821
2822 if (quick_format)
2823 para = 0x0000;
2824 else
2825 para = 0x0001;
2826
2827 retval = mspro_set_rw_cmd(chip, 0, para, PRO_FORMAT);
2828 if (retval != STATUS_SUCCESS)
2829 TRACE_RET(chip, STATUS_FAIL);
2830
2831 RTSX_READ_REG(chip, MS_TRANS_CFG, &tmp);
2832
2833 if (tmp & (MS_INT_CMDNK | MS_INT_ERR))
2834 TRACE_RET(chip, STATUS_FAIL);
2835
2836 if ((tmp & (MS_INT_BREQ | MS_INT_CED)) == MS_INT_BREQ) {
2837 ms_card->pro_under_formatting = 1;
2838 ms_card->progress = 0;
2839 ms_card->format_status = FORMAT_IN_PROGRESS;
2840 return STATUS_SUCCESS;
2841 }
2842
2843 if (tmp & MS_INT_CED) {
2844 ms_card->pro_under_formatting = 0;
2845 ms_card->progress = 0;
2846 ms_card->format_status = FORMAT_SUCCESS;
2847 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_NO_SENSE);
2848 return STATUS_SUCCESS;
2849 }
2850
2851 TRACE_RET(chip, STATUS_FAIL);
2852 }
2853
2854
2855 static int ms_read_multiple_pages(struct rtsx_chip *chip, u16 phy_blk,
2856 u16 log_blk, u8 start_page, u8 end_page,
2857 u8 *buf, unsigned int *index,
2858 unsigned int *offset)
2859 {
2860 struct ms_info *ms_card = &(chip->ms_card);
2861 int retval, i;
2862 u8 extra[MS_EXTRA_SIZE], page_addr, val, trans_cfg, data[6];
2863 u8 *ptr;
2864
2865 retval = ms_read_extra_data(chip, phy_blk, start_page,
2866 extra, MS_EXTRA_SIZE);
2867 if (retval == STATUS_SUCCESS) {
2868 if ((extra[1] & 0x30) != 0x30) {
2869 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2870 TRACE_RET(chip, STATUS_FAIL);
2871 }
2872 }
2873
2874 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
2875 SystemParm, 6);
2876 if (retval != STATUS_SUCCESS)
2877 TRACE_RET(chip, STATUS_FAIL);
2878
2879 if (CHK_MS4BIT(ms_card))
2880 data[0] = 0x88;
2881 else
2882 data[0] = 0x80;
2883
2884 data[1] = 0;
2885 data[2] = (u8)(phy_blk >> 8);
2886 data[3] = (u8)phy_blk;
2887 data[4] = 0;
2888 data[5] = start_page;
2889
2890 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
2891 retval = ms_write_bytes(chip, WRITE_REG, 6, NO_WAIT_INT,
2892 data, 6);
2893 if (retval == STATUS_SUCCESS)
2894 break;
2895 }
2896 if (i == MS_MAX_RETRY_COUNT)
2897 TRACE_RET(chip, STATUS_FAIL);
2898
2899 ms_set_err_code(chip, MS_NO_ERROR);
2900
2901 retval = ms_send_cmd(chip, BLOCK_READ, WAIT_INT);
2902 if (retval != STATUS_SUCCESS)
2903 TRACE_RET(chip, STATUS_FAIL);
2904
2905 ptr = buf;
2906
2907 for (page_addr = start_page; page_addr < end_page; page_addr++) {
2908 ms_set_err_code(chip, MS_NO_ERROR);
2909
2910 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
2911 ms_set_err_code(chip, MS_NO_CARD);
2912 TRACE_RET(chip, STATUS_FAIL);
2913 }
2914
2915 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
2916 if (retval != STATUS_SUCCESS)
2917 TRACE_RET(chip, STATUS_FAIL);
2918
2919 if (val & INT_REG_CMDNK) {
2920 ms_set_err_code(chip, MS_CMD_NK);
2921 TRACE_RET(chip, STATUS_FAIL);
2922 }
2923 if (val & INT_REG_ERR) {
2924 if (val & INT_REG_BREQ) {
2925 retval = ms_read_status_reg(chip);
2926 if (retval != STATUS_SUCCESS) {
2927 if (!(chip->card_wp & MS_CARD)) {
2928 reset_ms(chip);
2929 ms_set_page_status(log_blk, setPS_NG, extra, MS_EXTRA_SIZE);
2930 ms_write_extra_data(chip, phy_blk,
2931 page_addr, extra, MS_EXTRA_SIZE);
2932 }
2933 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2934 TRACE_RET(chip, STATUS_FAIL);
2935 }
2936 } else {
2937 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2938 TRACE_RET(chip, STATUS_FAIL);
2939 }
2940 } else {
2941 if (!(val & INT_REG_BREQ)) {
2942 ms_set_err_code(chip, MS_BREQ_ERROR);
2943 TRACE_RET(chip, STATUS_FAIL);
2944 }
2945 }
2946
2947 if (page_addr == (end_page - 1)) {
2948 if (!(val & INT_REG_CED)) {
2949 retval = ms_send_cmd(chip, BLOCK_END, WAIT_INT);
2950 if (retval != STATUS_SUCCESS)
2951 TRACE_RET(chip, STATUS_FAIL);
2952 }
2953
2954 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT,
2955 &val, 1);
2956 if (retval != STATUS_SUCCESS)
2957 TRACE_RET(chip, STATUS_FAIL);
2958
2959 if (!(val & INT_REG_CED)) {
2960 ms_set_err_code(chip, MS_FLASH_READ_ERROR);
2961 TRACE_RET(chip, STATUS_FAIL);
2962 }
2963
2964 trans_cfg = NO_WAIT_INT;
2965 } else {
2966 trans_cfg = WAIT_INT;
2967 }
2968
2969 rtsx_init_cmd(chip);
2970
2971 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC, 0xFF, READ_PAGE_DATA);
2972 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
2973 0xFF, trans_cfg);
2974 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
2975 0x01, RING_BUFFER);
2976
2977 trans_dma_enable(DMA_FROM_DEVICE, chip, 512, DMA_512);
2978
2979 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
2980 MS_TRANSFER_START | MS_TM_NORMAL_READ);
2981 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
2982 MS_TRANSFER_END, MS_TRANSFER_END);
2983
2984 rtsx_send_cmd_no_wait(chip);
2985
2986 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
2987 512, scsi_sg_count(chip->srb),
2988 index, offset, DMA_FROM_DEVICE,
2989 chip->ms_timeout);
2990 if (retval < 0) {
2991 if (retval == -ETIMEDOUT) {
2992 ms_set_err_code(chip, MS_TO_ERROR);
2993 rtsx_clear_ms_error(chip);
2994 TRACE_RET(chip, STATUS_TIMEDOUT);
2995 }
2996
2997 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
2998 if (retval != STATUS_SUCCESS) {
2999 ms_set_err_code(chip, MS_TO_ERROR);
3000 rtsx_clear_ms_error(chip);
3001 TRACE_RET(chip, STATUS_TIMEDOUT);
3002 }
3003 if (val & (MS_CRC16_ERR | MS_RDY_TIMEOUT)) {
3004 ms_set_err_code(chip, MS_CRC16_ERROR);
3005 rtsx_clear_ms_error(chip);
3006 TRACE_RET(chip, STATUS_FAIL);
3007 }
3008 }
3009
3010 if (scsi_sg_count(chip->srb) == 0)
3011 ptr += 512;
3012 }
3013
3014 return STATUS_SUCCESS;
3015 }
3016
3017 static int ms_write_multiple_pages(struct rtsx_chip *chip, u16 old_blk,
3018 u16 new_blk, u16 log_blk, u8 start_page,
3019 u8 end_page, u8 *buf, unsigned int *index,
3020 unsigned int *offset)
3021 {
3022 struct ms_info *ms_card = &(chip->ms_card);
3023 int retval, i;
3024 u8 page_addr, val, data[16];
3025 u8 *ptr;
3026
3027 if (!start_page) {
3028 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3029 SystemParm, 7);
3030 if (retval != STATUS_SUCCESS)
3031 TRACE_RET(chip, STATUS_FAIL);
3032
3033 if (CHK_MS4BIT(ms_card))
3034 data[0] = 0x88;
3035 else
3036 data[0] = 0x80;
3037
3038 data[1] = 0;
3039 data[2] = (u8)(old_blk >> 8);
3040 data[3] = (u8)old_blk;
3041 data[4] = 0x80;
3042 data[5] = 0;
3043 data[6] = 0xEF;
3044 data[7] = 0xFF;
3045
3046 retval = ms_write_bytes(chip, WRITE_REG, 7, NO_WAIT_INT,
3047 data, 8);
3048 if (retval != STATUS_SUCCESS)
3049 TRACE_RET(chip, STATUS_FAIL);
3050
3051 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3052 if (retval != STATUS_SUCCESS)
3053 TRACE_RET(chip, STATUS_FAIL);
3054
3055 ms_set_err_code(chip, MS_NO_ERROR);
3056 retval = ms_transfer_tpc(chip, MS_TM_READ_BYTES, GET_INT, 1,
3057 NO_WAIT_INT);
3058 if (retval != STATUS_SUCCESS)
3059 TRACE_RET(chip, STATUS_FAIL);
3060 }
3061
3062 retval = ms_set_rw_reg_addr(chip, OverwriteFlag, MS_EXTRA_SIZE,
3063 SystemParm, (6 + MS_EXTRA_SIZE));
3064 if (retval != STATUS_SUCCESS)
3065 TRACE_RET(chip, STATUS_FAIL);
3066
3067 ms_set_err_code(chip, MS_NO_ERROR);
3068
3069 if (CHK_MS4BIT(ms_card))
3070 data[0] = 0x88;
3071 else
3072 data[0] = 0x80;
3073
3074 data[1] = 0;
3075 data[2] = (u8)(new_blk >> 8);
3076 data[3] = (u8)new_blk;
3077 if ((end_page - start_page) == 1)
3078 data[4] = 0x20;
3079 else
3080 data[4] = 0;
3081
3082 data[5] = start_page;
3083 data[6] = 0xF8;
3084 data[7] = 0xFF;
3085 data[8] = (u8)(log_blk >> 8);
3086 data[9] = (u8)log_blk;
3087
3088 for (i = 0x0A; i < 0x10; i++)
3089 data[i] = 0xFF;
3090
3091 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3092 retval = ms_write_bytes(chip, WRITE_REG, 6 + MS_EXTRA_SIZE,
3093 NO_WAIT_INT, data, 16);
3094 if (retval == STATUS_SUCCESS)
3095 break;
3096 }
3097 if (i == MS_MAX_RETRY_COUNT)
3098 TRACE_RET(chip, STATUS_FAIL);
3099
3100 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3101 retval = ms_send_cmd(chip, BLOCK_WRITE, WAIT_INT);
3102 if (retval == STATUS_SUCCESS)
3103 break;
3104 }
3105 if (i == MS_MAX_RETRY_COUNT)
3106 TRACE_RET(chip, STATUS_FAIL);
3107
3108 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3109 if (retval != STATUS_SUCCESS)
3110 TRACE_RET(chip, STATUS_FAIL);
3111
3112 ptr = buf;
3113 for (page_addr = start_page; page_addr < end_page; page_addr++) {
3114 ms_set_err_code(chip, MS_NO_ERROR);
3115
3116 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3117 ms_set_err_code(chip, MS_NO_CARD);
3118 TRACE_RET(chip, STATUS_FAIL);
3119 }
3120
3121 if (val & INT_REG_CMDNK) {
3122 ms_set_err_code(chip, MS_CMD_NK);
3123 TRACE_RET(chip, STATUS_FAIL);
3124 }
3125 if (val & INT_REG_ERR) {
3126 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3127 TRACE_RET(chip, STATUS_FAIL);
3128 }
3129 if (!(val & INT_REG_BREQ)) {
3130 ms_set_err_code(chip, MS_BREQ_ERROR);
3131 TRACE_RET(chip, STATUS_FAIL);
3132 }
3133
3134 udelay(30);
3135
3136 rtsx_init_cmd(chip);
3137
3138 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
3139 0xFF, WRITE_PAGE_DATA);
3140 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG,
3141 0xFF, WAIT_INT);
3142 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
3143 0x01, RING_BUFFER);
3144
3145 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
3146
3147 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
3148 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
3149 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
3150 MS_TRANSFER_END, MS_TRANSFER_END);
3151
3152 rtsx_send_cmd_no_wait(chip);
3153
3154 retval = rtsx_transfer_data_partial(chip, MS_CARD, ptr,
3155 512, scsi_sg_count(chip->srb),
3156 index, offset, DMA_TO_DEVICE,
3157 chip->ms_timeout);
3158 if (retval < 0) {
3159 ms_set_err_code(chip, MS_TO_ERROR);
3160 rtsx_clear_ms_error(chip);
3161
3162 if (retval == -ETIMEDOUT)
3163 TRACE_RET(chip, STATUS_TIMEDOUT);
3164 else
3165 TRACE_RET(chip, STATUS_FAIL);
3166 }
3167
3168 retval = ms_read_bytes(chip, GET_INT, 1, NO_WAIT_INT, &val, 1);
3169 if (retval != STATUS_SUCCESS)
3170 TRACE_RET(chip, STATUS_FAIL);
3171
3172 if ((end_page - start_page) == 1) {
3173 if (!(val & INT_REG_CED)) {
3174 ms_set_err_code(chip, MS_FLASH_WRITE_ERROR);
3175 TRACE_RET(chip, STATUS_FAIL);
3176 }
3177 } else {
3178 if (page_addr == (end_page - 1)) {
3179 if (!(val & INT_REG_CED)) {
3180 retval = ms_send_cmd(chip, BLOCK_END,
3181 WAIT_INT);
3182 if (retval != STATUS_SUCCESS)
3183 TRACE_RET(chip, STATUS_FAIL);
3184 }
3185
3186 retval = ms_read_bytes(chip, GET_INT, 1,
3187 NO_WAIT_INT, &val, 1);
3188 if (retval != STATUS_SUCCESS)
3189 TRACE_RET(chip, STATUS_FAIL);
3190 }
3191
3192 if ((page_addr == (end_page - 1)) ||
3193 (page_addr == ms_card->page_off)) {
3194 if (!(val & INT_REG_CED)) {
3195 ms_set_err_code(chip,
3196 MS_FLASH_WRITE_ERROR);
3197 TRACE_RET(chip, STATUS_FAIL);
3198 }
3199 }
3200 }
3201
3202 if (scsi_sg_count(chip->srb) == 0)
3203 ptr += 512;
3204 }
3205
3206 return STATUS_SUCCESS;
3207 }
3208
3209
3210 static int ms_finish_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3211 u16 log_blk, u8 page_off)
3212 {
3213 struct ms_info *ms_card = &(chip->ms_card);
3214 int retval, seg_no;
3215
3216 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3217 page_off, ms_card->page_off + 1);
3218 if (retval != STATUS_SUCCESS)
3219 TRACE_RET(chip, STATUS_FAIL);
3220
3221 seg_no = old_blk >> 9;
3222
3223 if (MS_TST_BAD_BLOCK_FLG(ms_card)) {
3224 MS_CLR_BAD_BLOCK_FLG(ms_card);
3225 ms_set_bad_block(chip, old_blk);
3226 } else {
3227 retval = ms_erase_block(chip, old_blk);
3228 if (retval == STATUS_SUCCESS)
3229 ms_set_unused_block(chip, old_blk);
3230 }
3231
3232 ms_set_l2p_tbl(chip, seg_no, log_blk - ms_start_idx[seg_no], new_blk);
3233
3234 return STATUS_SUCCESS;
3235 }
3236
3237 static int ms_prepare_write(struct rtsx_chip *chip, u16 old_blk, u16 new_blk,
3238 u16 log_blk, u8 start_page)
3239 {
3240 int retval;
3241
3242 if (start_page) {
3243 retval = ms_copy_page(chip, old_blk, new_blk, log_blk,
3244 0, start_page);
3245 if (retval != STATUS_SUCCESS)
3246 TRACE_RET(chip, STATUS_FAIL);
3247 }
3248
3249 return STATUS_SUCCESS;
3250 }
3251
3252 #ifdef MS_DELAY_WRITE
3253 int ms_delay_write(struct rtsx_chip *chip)
3254 {
3255 struct ms_info *ms_card = &(chip->ms_card);
3256 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3257 int retval;
3258
3259 if (delay_write->delay_write_flag) {
3260 retval = ms_set_init_para(chip);
3261 if (retval != STATUS_SUCCESS)
3262 TRACE_RET(chip, STATUS_FAIL);
3263
3264 delay_write->delay_write_flag = 0;
3265 retval = ms_finish_write(chip,
3266 delay_write->old_phyblock,
3267 delay_write->new_phyblock,
3268 delay_write->logblock,
3269 delay_write->pageoff);
3270 if (retval != STATUS_SUCCESS)
3271 TRACE_RET(chip, STATUS_FAIL);
3272 }
3273
3274 return STATUS_SUCCESS;
3275 }
3276 #endif
3277
3278 static inline void ms_rw_fail(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3279 {
3280 if (srb->sc_data_direction == DMA_FROM_DEVICE)
3281 set_sense_type(chip, SCSI_LUN(srb),
3282 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3283 else
3284 set_sense_type(chip, SCSI_LUN(srb), SENSE_TYPE_MEDIA_WRITE_ERR);
3285 }
3286
3287 static int ms_rw_multi_sector(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3288 u32 start_sector, u16 sector_cnt)
3289 {
3290 struct ms_info *ms_card = &(chip->ms_card);
3291 unsigned int lun = SCSI_LUN(srb);
3292 int retval, seg_no;
3293 unsigned int index = 0, offset = 0;
3294 u16 old_blk = 0, new_blk = 0, log_blk, total_sec_cnt = sector_cnt;
3295 u8 start_page, end_page = 0, page_cnt;
3296 u8 *ptr;
3297 #ifdef MS_DELAY_WRITE
3298 struct ms_delay_write_tag *delay_write = &(ms_card->delay_write);
3299 #endif
3300
3301 ms_set_err_code(chip, MS_NO_ERROR);
3302
3303 ms_card->cleanup_counter = 0;
3304
3305 ptr = (u8 *)scsi_sglist(srb);
3306
3307 retval = ms_switch_clock(chip);
3308 if (retval != STATUS_SUCCESS) {
3309 ms_rw_fail(srb, chip);
3310 TRACE_RET(chip, STATUS_FAIL);
3311 }
3312
3313 log_blk = (u16)(start_sector >> ms_card->block_shift);
3314 start_page = (u8)(start_sector & ms_card->page_off);
3315
3316 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1; seg_no++) {
3317 if (log_blk < ms_start_idx[seg_no+1])
3318 break;
3319 }
3320
3321 if (ms_card->segment[seg_no].build_flag == 0) {
3322 retval = ms_build_l2p_tbl(chip, seg_no);
3323 if (retval != STATUS_SUCCESS) {
3324 chip->card_fail |= MS_CARD;
3325 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
3326 TRACE_RET(chip, STATUS_FAIL);
3327 }
3328 }
3329
3330 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3331 #ifdef MS_DELAY_WRITE
3332 if (delay_write->delay_write_flag &&
3333 (delay_write->logblock == log_blk) &&
3334 (start_page > delay_write->pageoff)) {
3335 delay_write->delay_write_flag = 0;
3336 retval = ms_copy_page(chip,
3337 delay_write->old_phyblock,
3338 delay_write->new_phyblock, log_blk,
3339 delay_write->pageoff, start_page);
3340 if (retval != STATUS_SUCCESS) {
3341 set_sense_type(chip, lun,
3342 SENSE_TYPE_MEDIA_WRITE_ERR);
3343 TRACE_RET(chip, STATUS_FAIL);
3344 }
3345 old_blk = delay_write->old_phyblock;
3346 new_blk = delay_write->new_phyblock;
3347 } else if (delay_write->delay_write_flag &&
3348 (delay_write->logblock == log_blk) &&
3349 (start_page == delay_write->pageoff)) {
3350 delay_write->delay_write_flag = 0;
3351 old_blk = delay_write->old_phyblock;
3352 new_blk = delay_write->new_phyblock;
3353 } else {
3354 retval = ms_delay_write(chip);
3355 if (retval != STATUS_SUCCESS) {
3356 set_sense_type(chip, lun,
3357 SENSE_TYPE_MEDIA_WRITE_ERR);
3358 TRACE_RET(chip, STATUS_FAIL);
3359 }
3360 #endif
3361 old_blk = ms_get_l2p_tbl(chip, seg_no,
3362 log_blk - ms_start_idx[seg_no]);
3363 new_blk = ms_get_unused_block(chip, seg_no);
3364 if ((old_blk == 0xFFFF) || (new_blk == 0xFFFF)) {
3365 set_sense_type(chip, lun,
3366 SENSE_TYPE_MEDIA_WRITE_ERR);
3367 TRACE_RET(chip, STATUS_FAIL);
3368 }
3369
3370 retval = ms_prepare_write(chip, old_blk, new_blk,
3371 log_blk, start_page);
3372 if (retval != STATUS_SUCCESS) {
3373 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3374 set_sense_type(chip, lun,
3375 SENSE_TYPE_MEDIA_NOT_PRESENT);
3376 TRACE_RET(chip, STATUS_FAIL);
3377 }
3378 set_sense_type(chip, lun,
3379 SENSE_TYPE_MEDIA_WRITE_ERR);
3380 TRACE_RET(chip, STATUS_FAIL);
3381 }
3382 #ifdef MS_DELAY_WRITE
3383 }
3384 #endif
3385 } else {
3386 #ifdef MS_DELAY_WRITE
3387 retval = ms_delay_write(chip);
3388 if (retval != STATUS_SUCCESS) {
3389 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3390 set_sense_type(chip, lun,
3391 SENSE_TYPE_MEDIA_NOT_PRESENT);
3392 TRACE_RET(chip, STATUS_FAIL);
3393 }
3394 set_sense_type(chip, lun,
3395 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3396 TRACE_RET(chip, STATUS_FAIL);
3397 }
3398 #endif
3399 old_blk = ms_get_l2p_tbl(chip, seg_no,
3400 log_blk - ms_start_idx[seg_no]);
3401 if (old_blk == 0xFFFF) {
3402 set_sense_type(chip, lun,
3403 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
3404 TRACE_RET(chip, STATUS_FAIL);
3405 }
3406 }
3407
3408 RTSX_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3409 seg_no, old_blk, new_blk);
3410
3411 while (total_sec_cnt) {
3412 if ((start_page + total_sec_cnt) > (ms_card->page_off + 1))
3413 end_page = ms_card->page_off + 1;
3414 else
3415 end_page = start_page + (u8)total_sec_cnt;
3416
3417 page_cnt = end_page - start_page;
3418
3419 RTSX_DEBUGP("start_page = %d, end_page = %d, page_cnt = %d\n",
3420 start_page, end_page, page_cnt);
3421
3422 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
3423 retval = ms_read_multiple_pages(chip,
3424 old_blk, log_blk, start_page, end_page,
3425 ptr, &index, &offset);
3426 } else {
3427 retval = ms_write_multiple_pages(chip, old_blk,
3428 new_blk, log_blk, start_page, end_page,
3429 ptr, &index, &offset);
3430 }
3431
3432 if (retval != STATUS_SUCCESS) {
3433 toggle_gpio(chip, 1);
3434 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3435 set_sense_type(chip, lun,
3436 SENSE_TYPE_MEDIA_NOT_PRESENT);
3437 TRACE_RET(chip, STATUS_FAIL);
3438 }
3439 ms_rw_fail(srb, chip);
3440 TRACE_RET(chip, STATUS_FAIL);
3441 }
3442
3443 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3444 if (end_page == (ms_card->page_off + 1)) {
3445 retval = ms_erase_block(chip, old_blk);
3446 if (retval == STATUS_SUCCESS)
3447 ms_set_unused_block(chip, old_blk);
3448
3449 ms_set_l2p_tbl(chip, seg_no,
3450 log_blk - ms_start_idx[seg_no],
3451 new_blk);
3452 }
3453 }
3454
3455 total_sec_cnt -= page_cnt;
3456 if (scsi_sg_count(srb) == 0)
3457 ptr += page_cnt * 512;
3458
3459 if (total_sec_cnt == 0)
3460 break;
3461
3462 log_blk++;
3463
3464 for (seg_no = 0; seg_no < ARRAY_SIZE(ms_start_idx) - 1;
3465 seg_no++) {
3466 if (log_blk < ms_start_idx[seg_no+1])
3467 break;
3468 }
3469
3470 if (ms_card->segment[seg_no].build_flag == 0) {
3471 retval = ms_build_l2p_tbl(chip, seg_no);
3472 if (retval != STATUS_SUCCESS) {
3473 chip->card_fail |= MS_CARD;
3474 set_sense_type(chip, lun,
3475 SENSE_TYPE_MEDIA_NOT_PRESENT);
3476 TRACE_RET(chip, STATUS_FAIL);
3477 }
3478 }
3479
3480 old_blk = ms_get_l2p_tbl(chip, seg_no,
3481 log_blk - ms_start_idx[seg_no]);
3482 if (old_blk == 0xFFFF) {
3483 ms_rw_fail(srb, chip);
3484 TRACE_RET(chip, STATUS_FAIL);
3485 }
3486
3487 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3488 new_blk = ms_get_unused_block(chip, seg_no);
3489 if (new_blk == 0xFFFF) {
3490 ms_rw_fail(srb, chip);
3491 TRACE_RET(chip, STATUS_FAIL);
3492 }
3493 }
3494
3495 RTSX_DEBUGP("seg_no = %d, old_blk = 0x%x, new_blk = 0x%x\n",
3496 seg_no, old_blk, new_blk);
3497
3498 start_page = 0;
3499 }
3500
3501 if (srb->sc_data_direction == DMA_TO_DEVICE) {
3502 if (end_page < (ms_card->page_off + 1)) {
3503 #ifdef MS_DELAY_WRITE
3504 delay_write->delay_write_flag = 1;
3505 delay_write->old_phyblock = old_blk;
3506 delay_write->new_phyblock = new_blk;
3507 delay_write->logblock = log_blk;
3508 delay_write->pageoff = end_page;
3509 #else
3510 retval = ms_finish_write(chip, old_blk, new_blk,
3511 log_blk, end_page);
3512 if (retval != STATUS_SUCCESS) {
3513 if (detect_card_cd(chip, MS_CARD) != STATUS_SUCCESS) {
3514 set_sense_type(chip, lun,
3515 SENSE_TYPE_MEDIA_NOT_PRESENT);
3516 TRACE_RET(chip, STATUS_FAIL);
3517 }
3518
3519 ms_rw_fail(srb, chip);
3520 TRACE_RET(chip, STATUS_FAIL);
3521 }
3522 #endif
3523 }
3524 }
3525
3526 scsi_set_resid(srb, 0);
3527
3528 return STATUS_SUCCESS;
3529 }
3530
3531 int ms_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
3532 u32 start_sector, u16 sector_cnt)
3533 {
3534 struct ms_info *ms_card = &(chip->ms_card);
3535 int retval;
3536
3537 if (CHK_MSPRO(ms_card))
3538 retval = mspro_rw_multi_sector(srb, chip, start_sector,
3539 sector_cnt);
3540 else
3541 retval = ms_rw_multi_sector(srb, chip, start_sector,
3542 sector_cnt);
3543
3544 return retval;
3545 }
3546
3547
3548 void ms_free_l2p_tbl(struct rtsx_chip *chip)
3549 {
3550 struct ms_info *ms_card = &(chip->ms_card);
3551 int i = 0;
3552
3553 if (ms_card->segment != NULL) {
3554 for (i = 0; i < ms_card->segment_cnt; i++) {
3555 if (ms_card->segment[i].l2p_table != NULL) {
3556 vfree(ms_card->segment[i].l2p_table);
3557 ms_card->segment[i].l2p_table = NULL;
3558 }
3559 if (ms_card->segment[i].free_table != NULL) {
3560 vfree(ms_card->segment[i].free_table);
3561 ms_card->segment[i].free_table = NULL;
3562 }
3563 }
3564 vfree(ms_card->segment);
3565 ms_card->segment = NULL;
3566 }
3567 }
3568
3569 #ifdef SUPPORT_MAGIC_GATE
3570
3571 #ifdef READ_BYTES_WAIT_INT
3572 static int ms_poll_int(struct rtsx_chip *chip)
3573 {
3574 int retval;
3575 u8 val;
3576
3577 rtsx_init_cmd(chip);
3578
3579 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANS_CFG, MS_INT_CED, MS_INT_CED);
3580
3581 retval = rtsx_send_cmd(chip, MS_CARD, 5000);
3582 if (retval != STATUS_SUCCESS)
3583 TRACE_RET(chip, STATUS_FAIL);
3584
3585 val = *rtsx_get_cmd_data(chip);
3586 if (val & MS_INT_ERR)
3587 TRACE_RET(chip, STATUS_FAIL);
3588
3589 return STATUS_SUCCESS;
3590 }
3591 #endif
3592
3593 #ifdef MS_SAMPLE_INT_ERR
3594 static int check_ms_err(struct rtsx_chip *chip)
3595 {
3596 int retval;
3597 u8 val;
3598
3599 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3600 if (retval != STATUS_SUCCESS)
3601 return 1;
3602 if (val & MS_TRANSFER_ERR)
3603 return 1;
3604
3605 retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
3606 if (retval != STATUS_SUCCESS)
3607 return 1;
3608
3609 if (val & (MS_INT_ERR | MS_INT_CMDNK))
3610 return 1;
3611
3612 return 0;
3613 }
3614 #else
3615 static int check_ms_err(struct rtsx_chip *chip)
3616 {
3617 int retval;
3618 u8 val;
3619
3620 retval = rtsx_read_register(chip, MS_TRANSFER, &val);
3621 if (retval != STATUS_SUCCESS)
3622 return 1;
3623 if (val & MS_TRANSFER_ERR)
3624 return 1;
3625
3626 return 0;
3627 }
3628 #endif
3629
3630 static int mg_send_ex_cmd(struct rtsx_chip *chip, u8 cmd, u8 entry_num)
3631 {
3632 int retval, i;
3633 u8 data[8];
3634
3635 data[0] = cmd;
3636 data[1] = 0;
3637 data[2] = 0;
3638 data[3] = 0;
3639 data[4] = 0;
3640 data[5] = 0;
3641 data[6] = entry_num;
3642 data[7] = 0;
3643
3644 for (i = 0; i < MS_MAX_RETRY_COUNT; i++) {
3645 retval = ms_write_bytes(chip, PRO_EX_SET_CMD, 7, WAIT_INT,
3646 data, 8);
3647 if (retval == STATUS_SUCCESS)
3648 break;
3649 }
3650 if (i == MS_MAX_RETRY_COUNT)
3651 TRACE_RET(chip, STATUS_FAIL);
3652
3653 if (check_ms_err(chip)) {
3654 rtsx_clear_ms_error(chip);
3655 TRACE_RET(chip, STATUS_FAIL);
3656 }
3657
3658 return STATUS_SUCCESS;
3659 }
3660
3661 static int mg_set_tpc_para_sub(struct rtsx_chip *chip, int type,
3662 u8 mg_entry_num)
3663 {
3664 int retval;
3665 u8 buf[6];
3666
3667 RTSX_DEBUGP("--%s--\n", __func__);
3668
3669 if (type == 0)
3670 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_TPCParm, 1);
3671 else
3672 retval = ms_set_rw_reg_addr(chip, 0, 0, Pro_DataCount1, 6);
3673
3674 if (retval != STATUS_SUCCESS)
3675 TRACE_RET(chip, STATUS_FAIL);
3676
3677 buf[0] = 0;
3678 buf[1] = 0;
3679 if (type == 1) {
3680 buf[2] = 0;
3681 buf[3] = 0;
3682 buf[4] = 0;
3683 buf[5] = mg_entry_num;
3684 }
3685 retval = ms_write_bytes(chip, PRO_WRITE_REG, (type == 0) ? 1 : 6,
3686 NO_WAIT_INT, buf, 6);
3687 if (retval != STATUS_SUCCESS)
3688 TRACE_RET(chip, STATUS_FAIL);
3689
3690 return STATUS_SUCCESS;
3691 }
3692
3693 int mg_set_leaf_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3694 {
3695 int retval;
3696 int i;
3697 unsigned int lun = SCSI_LUN(srb);
3698 u8 buf1[32], buf2[12];
3699
3700 RTSX_DEBUGP("--%s--\n", __func__);
3701
3702 if (scsi_bufflen(srb) < 12) {
3703 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_INVALID_CMD_FIELD);
3704 TRACE_RET(chip, STATUS_FAIL);
3705 }
3706
3707 ms_cleanup_work(chip);
3708
3709 retval = ms_switch_clock(chip);
3710 if (retval != STATUS_SUCCESS)
3711 TRACE_RET(chip, STATUS_FAIL);
3712
3713 retval = mg_send_ex_cmd(chip, MG_SET_LID, 0);
3714 if (retval != STATUS_SUCCESS) {
3715 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3716 TRACE_RET(chip, STATUS_FAIL);
3717 }
3718
3719 memset(buf1, 0, 32);
3720 rtsx_stor_get_xfer_buf(buf2, min_t(int, 12, scsi_bufflen(srb)), srb);
3721 for (i = 0; i < 8; i++)
3722 buf1[8+i] = buf2[4+i];
3723
3724 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
3725 buf1, 32);
3726 if (retval != STATUS_SUCCESS) {
3727 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3728 TRACE_RET(chip, STATUS_FAIL);
3729 }
3730 if (check_ms_err(chip)) {
3731 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
3732 rtsx_clear_ms_error(chip);
3733 TRACE_RET(chip, STATUS_FAIL);
3734 }
3735
3736 return STATUS_SUCCESS;
3737 }
3738
3739 int mg_get_local_EKB(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3740 {
3741 int retval = STATUS_FAIL;
3742 int bufflen;
3743 unsigned int lun = SCSI_LUN(srb);
3744 u8 *buf = NULL;
3745
3746 RTSX_DEBUGP("--%s--\n", __func__);
3747
3748 ms_cleanup_work(chip);
3749
3750 retval = ms_switch_clock(chip);
3751 if (retval != STATUS_SUCCESS)
3752 TRACE_RET(chip, STATUS_FAIL);
3753
3754 buf = kmalloc(1540, GFP_KERNEL);
3755 if (!buf)
3756 TRACE_RET(chip, STATUS_ERROR);
3757
3758 buf[0] = 0x04;
3759 buf[1] = 0x1A;
3760 buf[2] = 0x00;
3761 buf[3] = 0x00;
3762
3763 retval = mg_send_ex_cmd(chip, MG_GET_LEKB, 0);
3764 if (retval != STATUS_SUCCESS) {
3765 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3766 TRACE_GOTO(chip, GetEKBFinish);
3767 }
3768
3769 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
3770 3, WAIT_INT, 0, 0, buf + 4, 1536);
3771 if (retval != STATUS_SUCCESS) {
3772 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3773 rtsx_clear_ms_error(chip);
3774 TRACE_GOTO(chip, GetEKBFinish);
3775 }
3776 if (check_ms_err(chip)) {
3777 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3778 rtsx_clear_ms_error(chip);
3779 TRACE_RET(chip, STATUS_FAIL);
3780 }
3781
3782 bufflen = min_t(int, 1052, scsi_bufflen(srb));
3783 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
3784
3785 GetEKBFinish:
3786 kfree(buf);
3787 return retval;
3788 }
3789
3790 int mg_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3791 {
3792 struct ms_info *ms_card = &(chip->ms_card);
3793 int retval;
3794 int bufflen;
3795 int i;
3796 unsigned int lun = SCSI_LUN(srb);
3797 u8 buf[32];
3798
3799 RTSX_DEBUGP("--%s--\n", __func__);
3800
3801 ms_cleanup_work(chip);
3802
3803 retval = ms_switch_clock(chip);
3804 if (retval != STATUS_SUCCESS)
3805 TRACE_RET(chip, STATUS_FAIL);
3806
3807 retval = mg_send_ex_cmd(chip, MG_GET_ID, 0);
3808 if (retval != STATUS_SUCCESS) {
3809 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3810 TRACE_RET(chip, STATUS_FAIL);
3811 }
3812
3813 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
3814 buf, 32);
3815 if (retval != STATUS_SUCCESS) {
3816 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3817 TRACE_RET(chip, STATUS_FAIL);
3818 }
3819 if (check_ms_err(chip)) {
3820 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3821 rtsx_clear_ms_error(chip);
3822 TRACE_RET(chip, STATUS_FAIL);
3823 }
3824
3825 memcpy(ms_card->magic_gate_id, buf, 16);
3826
3827 #ifdef READ_BYTES_WAIT_INT
3828 retval = ms_poll_int(chip);
3829 if (retval != STATUS_SUCCESS) {
3830 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3831 TRACE_RET(chip, STATUS_FAIL);
3832 }
3833 #endif
3834
3835 retval = mg_send_ex_cmd(chip, MG_SET_RD, 0);
3836 if (retval != STATUS_SUCCESS) {
3837 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3838 TRACE_RET(chip, STATUS_FAIL);
3839 }
3840
3841 bufflen = min_t(int, 12, scsi_bufflen(srb));
3842 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3843
3844 for (i = 0; i < 8; i++)
3845 buf[i] = buf[4+i];
3846
3847 for (i = 0; i < 24; i++)
3848 buf[8+i] = 0;
3849
3850 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA,
3851 32, WAIT_INT, buf, 32);
3852 if (retval != STATUS_SUCCESS) {
3853 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3854 TRACE_RET(chip, STATUS_FAIL);
3855 }
3856 if (check_ms_err(chip)) {
3857 set_sense_type(chip, lun, SENSE_TYPE_MG_INCOMPATIBLE_MEDIUM);
3858 rtsx_clear_ms_error(chip);
3859 TRACE_RET(chip, STATUS_FAIL);
3860 }
3861
3862 ms_card->mg_auth = 0;
3863
3864 return STATUS_SUCCESS;
3865 }
3866
3867 int mg_get_rsp_chg(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3868 {
3869 struct ms_info *ms_card = &(chip->ms_card);
3870 int retval;
3871 int bufflen;
3872 unsigned int lun = SCSI_LUN(srb);
3873 u8 buf1[32], buf2[36];
3874
3875 RTSX_DEBUGP("--%s--\n", __func__);
3876
3877 ms_cleanup_work(chip);
3878
3879 retval = ms_switch_clock(chip);
3880 if (retval != STATUS_SUCCESS)
3881 TRACE_RET(chip, STATUS_FAIL);
3882
3883 retval = mg_send_ex_cmd(chip, MG_MAKE_RMS, 0);
3884 if (retval != STATUS_SUCCESS) {
3885 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3886 TRACE_RET(chip, STATUS_FAIL);
3887 }
3888
3889 retval = ms_read_bytes(chip, PRO_READ_SHORT_DATA, 32, WAIT_INT,
3890 buf1, 32);
3891 if (retval != STATUS_SUCCESS) {
3892 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3893 TRACE_RET(chip, STATUS_FAIL);
3894 }
3895 if (check_ms_err(chip)) {
3896 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3897 rtsx_clear_ms_error(chip);
3898 TRACE_RET(chip, STATUS_FAIL);
3899 }
3900
3901 buf2[0] = 0x00;
3902 buf2[1] = 0x22;
3903 buf2[2] = 0x00;
3904 buf2[3] = 0x00;
3905
3906 memcpy(buf2 + 4, ms_card->magic_gate_id, 16);
3907 memcpy(buf2 + 20, buf1, 16);
3908
3909 bufflen = min_t(int, 36, scsi_bufflen(srb));
3910 rtsx_stor_set_xfer_buf(buf2, bufflen, srb);
3911
3912 #ifdef READ_BYTES_WAIT_INT
3913 retval = ms_poll_int(chip);
3914 if (retval != STATUS_SUCCESS) {
3915 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3916 TRACE_RET(chip, STATUS_FAIL);
3917 }
3918 #endif
3919
3920 return STATUS_SUCCESS;
3921 }
3922
3923 int mg_rsp(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3924 {
3925 struct ms_info *ms_card = &(chip->ms_card);
3926 int retval;
3927 int i;
3928 int bufflen;
3929 unsigned int lun = SCSI_LUN(srb);
3930 u8 buf[32];
3931
3932 RTSX_DEBUGP("--%s--\n", __func__);
3933
3934 ms_cleanup_work(chip);
3935
3936 retval = ms_switch_clock(chip);
3937 if (retval != STATUS_SUCCESS)
3938 TRACE_RET(chip, STATUS_FAIL);
3939
3940 retval = mg_send_ex_cmd(chip, MG_MAKE_KSE, 0);
3941 if (retval != STATUS_SUCCESS) {
3942 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3943 TRACE_RET(chip, STATUS_FAIL);
3944 }
3945
3946 bufflen = min_t(int, 12, scsi_bufflen(srb));
3947 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
3948
3949 for (i = 0; i < 8; i++)
3950 buf[i] = buf[4+i];
3951
3952 for (i = 0; i < 24; i++)
3953 buf[8+i] = 0;
3954
3955 retval = ms_write_bytes(chip, PRO_WRITE_SHORT_DATA, 32, WAIT_INT,
3956 buf, 32);
3957 if (retval != STATUS_SUCCESS) {
3958 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3959 TRACE_RET(chip, STATUS_FAIL);
3960 }
3961 if (check_ms_err(chip)) {
3962 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_AUTHEN);
3963 rtsx_clear_ms_error(chip);
3964 TRACE_RET(chip, STATUS_FAIL);
3965 }
3966
3967 ms_card->mg_auth = 1;
3968
3969 return STATUS_SUCCESS;
3970 }
3971
3972 int mg_get_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
3973 {
3974 struct ms_info *ms_card = &(chip->ms_card);
3975 int retval;
3976 int bufflen;
3977 unsigned int lun = SCSI_LUN(srb);
3978 u8 *buf = NULL;
3979
3980 RTSX_DEBUGP("--%s--\n", __func__);
3981
3982 ms_cleanup_work(chip);
3983
3984 retval = ms_switch_clock(chip);
3985 if (retval != STATUS_SUCCESS)
3986 TRACE_RET(chip, STATUS_FAIL);
3987
3988 buf = kmalloc(1028, GFP_KERNEL);
3989 if (!buf)
3990 TRACE_RET(chip, STATUS_ERROR);
3991
3992 buf[0] = 0x04;
3993 buf[1] = 0x02;
3994 buf[2] = 0x00;
3995 buf[3] = 0x00;
3996
3997 retval = mg_send_ex_cmd(chip, MG_GET_IBD, ms_card->mg_entry_num);
3998 if (retval != STATUS_SUCCESS) {
3999 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4000 TRACE_GOTO(chip, GetICVFinish);
4001 }
4002
4003 retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
4004 2, WAIT_INT, 0, 0, buf + 4, 1024);
4005 if (retval != STATUS_SUCCESS) {
4006 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4007 rtsx_clear_ms_error(chip);
4008 TRACE_GOTO(chip, GetICVFinish);
4009 }
4010 if (check_ms_err(chip)) {
4011 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
4012 rtsx_clear_ms_error(chip);
4013 TRACE_RET(chip, STATUS_FAIL);
4014 }
4015
4016 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4017 rtsx_stor_set_xfer_buf(buf, bufflen, srb);
4018
4019 GetICVFinish:
4020 kfree(buf);
4021 return retval;
4022 }
4023
4024 int mg_set_ICV(struct scsi_cmnd *srb, struct rtsx_chip *chip)
4025 {
4026 struct ms_info *ms_card = &(chip->ms_card);
4027 int retval;
4028 int bufflen;
4029 #ifdef MG_SET_ICV_SLOW
4030 int i;
4031 #endif
4032 unsigned int lun = SCSI_LUN(srb);
4033 u8 *buf = NULL;
4034
4035 RTSX_DEBUGP("--%s--\n", __func__);
4036
4037 ms_cleanup_work(chip);
4038
4039 retval = ms_switch_clock(chip);
4040 if (retval != STATUS_SUCCESS)
4041 TRACE_RET(chip, STATUS_FAIL);
4042
4043 buf = kmalloc(1028, GFP_KERNEL);
4044 if (!buf)
4045 TRACE_RET(chip, STATUS_ERROR);
4046
4047 bufflen = min_t(int, 1028, scsi_bufflen(srb));
4048 rtsx_stor_get_xfer_buf(buf, bufflen, srb);
4049
4050 retval = mg_send_ex_cmd(chip, MG_SET_IBD, ms_card->mg_entry_num);
4051 if (retval != STATUS_SUCCESS) {
4052 if (ms_card->mg_auth == 0) {
4053 if ((buf[5] & 0xC0) != 0)
4054 set_sense_type(chip, lun,
4055 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4056 else
4057 set_sense_type(chip, lun,
4058 SENSE_TYPE_MG_WRITE_ERR);
4059 } else {
4060 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4061 }
4062 TRACE_GOTO(chip, SetICVFinish);
4063 }
4064
4065 #ifdef MG_SET_ICV_SLOW
4066 for (i = 0; i < 2; i++) {
4067 udelay(50);
4068
4069 rtsx_init_cmd(chip);
4070
4071 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TPC,
4072 0xFF, PRO_WRITE_LONG_DATA);
4073 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANS_CFG, 0xFF, WAIT_INT);
4074 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
4075 0x01, RING_BUFFER);
4076
4077 trans_dma_enable(DMA_TO_DEVICE, chip, 512, DMA_512);
4078
4079 rtsx_add_cmd(chip, WRITE_REG_CMD, MS_TRANSFER, 0xFF,
4080 MS_TRANSFER_START | MS_TM_NORMAL_WRITE);
4081 rtsx_add_cmd(chip, CHECK_REG_CMD, MS_TRANSFER,
4082 MS_TRANSFER_END, MS_TRANSFER_END);
4083
4084 rtsx_send_cmd_no_wait(chip);
4085
4086 retval = rtsx_transfer_data(chip, MS_CARD, buf + 4 + i*512,
4087 512, 0, DMA_TO_DEVICE, 3000);
4088 if ((retval < 0) || check_ms_err(chip)) {
4089 rtsx_clear_ms_error(chip);
4090 if (ms_card->mg_auth == 0) {
4091 if ((buf[5] & 0xC0) != 0)
4092 set_sense_type(chip, lun, SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4093 else
4094 set_sense_type(chip, lun,
4095 SENSE_TYPE_MG_WRITE_ERR);
4096 } else {
4097 set_sense_type(chip, lun,
4098 SENSE_TYPE_MG_WRITE_ERR);
4099 }
4100 retval = STATUS_FAIL;
4101 TRACE_GOTO(chip, SetICVFinish);
4102 }
4103 }
4104 #else
4105 retval = ms_transfer_data(chip, MS_TM_AUTO_WRITE, PRO_WRITE_LONG_DATA,
4106 2, WAIT_INT, 0, 0, buf + 4, 1024);
4107 if ((retval != STATUS_SUCCESS) || check_ms_err(chip)) {
4108 rtsx_clear_ms_error(chip);
4109 if (ms_card->mg_auth == 0) {
4110 if ((buf[5] & 0xC0) != 0)
4111 set_sense_type(chip, lun,
4112 SENSE_TYPE_MG_KEY_FAIL_NOT_ESTAB);
4113 else
4114 set_sense_type(chip, lun,
4115 SENSE_TYPE_MG_WRITE_ERR);
4116 } else {
4117 set_sense_type(chip, lun, SENSE_TYPE_MG_WRITE_ERR);
4118 }
4119 TRACE_GOTO(chip, SetICVFinish);
4120 }
4121 #endif
4122
4123 SetICVFinish:
4124 kfree(buf);
4125 return retval;
4126 }
4127
4128 #endif /* SUPPORT_MAGIC_GATE */
4129
4130 void ms_cleanup_work(struct rtsx_chip *chip)
4131 {
4132 struct ms_info *ms_card = &(chip->ms_card);
4133
4134 if (CHK_MSPRO(ms_card)) {
4135 if (ms_card->seq_mode) {
4136 RTSX_DEBUGP("MS Pro: stop transmission\n");
4137 mspro_stop_seq_mode(chip);
4138 ms_card->cleanup_counter = 0;
4139 }
4140 if (CHK_MSHG(ms_card)) {
4141 rtsx_write_register(chip, MS_CFG,
4142 MS_2K_SECTOR_MODE, 0x00);
4143 }
4144 }
4145 #ifdef MS_DELAY_WRITE
4146 else if ((!CHK_MSPRO(ms_card)) && ms_card->delay_write.delay_write_flag) {
4147 RTSX_DEBUGP("MS: delay write\n");
4148 ms_delay_write(chip);
4149 ms_card->cleanup_counter = 0;
4150 }
4151 #endif
4152 }
4153
4154 int ms_power_off_card3v3(struct rtsx_chip *chip)
4155 {
4156 int retval;
4157
4158 retval = disable_card_clock(chip, MS_CARD);
4159 if (retval != STATUS_SUCCESS)
4160 TRACE_RET(chip, STATUS_FAIL);
4161
4162 if (chip->asic_code) {
4163 retval = ms_pull_ctl_disable(chip);
4164 if (retval != STATUS_SUCCESS)
4165 TRACE_RET(chip, STATUS_FAIL);
4166 } else {
4167 RTSX_WRITE_REG(chip, FPGA_PULL_CTL,
4168 FPGA_MS_PULL_CTL_BIT | 0x20, FPGA_MS_PULL_CTL_BIT);
4169 }
4170 RTSX_WRITE_REG(chip, CARD_OE, MS_OUTPUT_EN, 0);
4171 if (!chip->ft2_fast_mode) {
4172 retval = card_power_off(chip, MS_CARD);
4173 if (retval != STATUS_SUCCESS)
4174 TRACE_RET(chip, STATUS_FAIL);
4175 }
4176
4177 return STATUS_SUCCESS;
4178 }
4179
4180 int release_ms_card(struct rtsx_chip *chip)
4181 {
4182 struct ms_info *ms_card = &(chip->ms_card);
4183 int retval;
4184
4185 RTSX_DEBUGP("release_ms_card\n");
4186
4187 #ifdef MS_DELAY_WRITE
4188 ms_card->delay_write.delay_write_flag = 0;
4189 #endif
4190 ms_card->pro_under_formatting = 0;
4191
4192 chip->card_ready &= ~MS_CARD;
4193 chip->card_fail &= ~MS_CARD;
4194 chip->card_wp &= ~MS_CARD;
4195
4196 ms_free_l2p_tbl(chip);
4197
4198 memset(ms_card->raw_sys_info, 0, 96);
4199 #ifdef SUPPORT_PCGL_1P18
4200 memset(ms_card->raw_model_name, 0, 48);
4201 #endif
4202
4203 retval = ms_power_off_card3v3(chip);
4204 if (retval != STATUS_SUCCESS)
4205 TRACE_RET(chip, STATUS_FAIL);
4206
4207 return STATUS_SUCCESS;
4208 }
Linux with added FPC-III support