drivers/staging/rts5208/spi.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26
  27 #include "rtsx.h"
  28 #include "rtsx_transport.h"
  29 #include "rtsx_scsi.h"
  30 #include "rtsx_card.h"
  31 #include "spi.h"
  32
  33 static inline void spi_set_err_code(struct rtsx_chip *chip, u8 err_code)
  34 {
  35         struct spi_info *spi = &(chip->spi);
  36
  37         spi->err_code = err_code;
  38 }
  39
  40 static int spi_init(struct rtsx_chip *chip)
  41 {
  42         RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF,
  43                 CS_POLARITY_LOW | DTO_MSB_FIRST | SPI_MASTER | SPI_MODE0 |
  44                 SPI_AUTO);
  45         RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF);
  46
  47         return STATUS_SUCCESS;
  48 }
  49
  50 static int spi_set_init_para(struct rtsx_chip *chip)
  51 {
  52         struct spi_info *spi = &(chip->spi);
  53         int retval;
  54
  55         RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, (u8)(spi->clk_div >> 8));
  56         RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, (u8)(spi->clk_div));
  57
  58         retval = switch_clock(chip, spi->spi_clock);
  59         if (retval != STATUS_SUCCESS)
  60                 TRACE_RET(chip, STATUS_FAIL);
  61
  62         retval = select_card(chip, SPI_CARD);
  63         if (retval != STATUS_SUCCESS)
  64                 TRACE_RET(chip, STATUS_FAIL);
  65
  66         RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN);
  67         RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN);
  68
  69         wait_timeout(10);
  70
  71         retval = spi_init(chip);
  72         if (retval != STATUS_SUCCESS)
  73                 TRACE_RET(chip, STATUS_FAIL);
  74
  75         return STATUS_SUCCESS;
  76 }
  77
  78 static int sf_polling_status(struct rtsx_chip *chip, int msec)
  79 {
  80         int retval;
  81
  82         rtsx_init_cmd(chip);
  83
  84         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, SPI_RDSR);
  85         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
  86                 SPI_TRANSFER0_START | SPI_POLLING_MODE0);
  87         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
  88                 SPI_TRANSFER0_END);
  89
  90         retval = rtsx_send_cmd(chip, 0, msec);
  91         if (retval < 0) {
  92                 rtsx_clear_spi_error(chip);
  93                 spi_set_err_code(chip, SPI_BUSY_ERR);
  94                 TRACE_RET(chip, STATUS_FAIL);
  95         }
  96
  97         return STATUS_SUCCESS;
  98 }
  99
 100 static int sf_enable_write(struct rtsx_chip *chip, u8 ins)
 101 {
 102         struct spi_info *spi = &(chip->spi);
 103         int retval;
 104
 105         if (!spi->write_en)
 106                 return STATUS_SUCCESS;
 107
 108         rtsx_init_cmd(chip);
 109
 110         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 111         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 112                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 113         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 114                 SPI_TRANSFER0_START | SPI_C_MODE0);
 115         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 116                 SPI_TRANSFER0_END);
 117
 118         retval = rtsx_send_cmd(chip, 0, 100);
 119         if (retval < 0) {
 120                 rtsx_clear_spi_error(chip);
 121                 spi_set_err_code(chip, SPI_HW_ERR);
 122                 TRACE_RET(chip, STATUS_FAIL);
 123         }
 124
 125         return STATUS_SUCCESS;
 126 }
 127
 128 static int sf_disable_write(struct rtsx_chip *chip, u8 ins)
 129 {
 130         struct spi_info *spi = &(chip->spi);
 131         int retval;
 132
 133         if (!spi->write_en)
 134                 return STATUS_SUCCESS;
 135
 136         rtsx_init_cmd(chip);
 137
 138         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 139         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 140                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 141         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 142                 SPI_TRANSFER0_START | SPI_C_MODE0);
 143         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 144                 SPI_TRANSFER0_END);
 145
 146         retval = rtsx_send_cmd(chip, 0, 100);
 147         if (retval < 0) {
 148                 rtsx_clear_spi_error(chip);
 149                 spi_set_err_code(chip, SPI_HW_ERR);
 150                 TRACE_RET(chip, STATUS_FAIL);
 151         }
 152
 153         return STATUS_SUCCESS;
 154 }
 155
 156 static void sf_program(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr,
 157                 u16 len)
 158 {
 159         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 160         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 161                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 162         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, (u8)len);
 163         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, (u8)(len >> 8));
 164         if (addr_mode) {
 165                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 166                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 167                         (u8)(addr >> 8));
 168                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 169                         (u8)(addr >> 16));
 170                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 171                         SPI_TRANSFER0_START | SPI_CADO_MODE0);
 172         } else {
 173                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 174                         SPI_TRANSFER0_START | SPI_CDO_MODE0);
 175         }
 176         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 177                 SPI_TRANSFER0_END);
 178 }
 179
 180 static int sf_erase(struct rtsx_chip *chip, u8 ins, u8 addr_mode, u32 addr)
 181 {
 182         int retval;
 183
 184         rtsx_init_cmd(chip);
 185
 186         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 187         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 188                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 189         if (addr_mode) {
 190                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 191                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 192                         (u8)(addr >> 8));
 193                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 194                         (u8)(addr >> 16));
 195                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 196                         SPI_TRANSFER0_START | SPI_CA_MODE0);
 197         } else {
 198                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 199                         SPI_TRANSFER0_START | SPI_C_MODE0);
 200         }
 201         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 202                 SPI_TRANSFER0_END);
 203
 204         retval = rtsx_send_cmd(chip, 0, 100);
 205         if (retval < 0) {
 206                 rtsx_clear_spi_error(chip);
 207                 spi_set_err_code(chip, SPI_HW_ERR);
 208                 TRACE_RET(chip, STATUS_FAIL);
 209         }
 210
 211         return STATUS_SUCCESS;
 212 }
 213
 214 static int spi_init_eeprom(struct rtsx_chip *chip)
 215 {
 216         int retval;
 217         int clk;
 218
 219         if (chip->asic_code)
 220                 clk = 30;
 221         else
 222                 clk = CLK_30;
 223
 224         RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER1, 0xFF, 0x00);
 225         RTSX_WRITE_REG(chip, SPI_CLK_DIVIDER0, 0xFF, 0x27);
 226
 227         retval = switch_clock(chip, clk);
 228         if (retval != STATUS_SUCCESS)
 229                 TRACE_RET(chip, STATUS_FAIL);
 230
 231         retval = select_card(chip, SPI_CARD);
 232         if (retval != STATUS_SUCCESS)
 233                 TRACE_RET(chip, STATUS_FAIL);
 234
 235         RTSX_WRITE_REG(chip, CARD_CLK_EN, SPI_CLK_EN, SPI_CLK_EN);
 236         RTSX_WRITE_REG(chip, CARD_OE, SPI_OUTPUT_EN, SPI_OUTPUT_EN);
 237
 238         wait_timeout(10);
 239
 240         RTSX_WRITE_REG(chip, SPI_CONTROL, 0xFF,
 241                 CS_POLARITY_HIGH | SPI_EEPROM_AUTO);
 242         RTSX_WRITE_REG(chip, SPI_TCTL, EDO_TIMING_MASK, SAMPLE_DELAY_HALF);
 243
 244         return STATUS_SUCCESS;
 245 }
 246
 247 static int spi_eeprom_program_enable(struct rtsx_chip *chip)
 248 {
 249         int retval;
 250
 251         rtsx_init_cmd(chip);
 252
 253         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x86);
 254         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x13);
 255         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 256                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 257         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 258                 SPI_TRANSFER0_END);
 259
 260         retval = rtsx_send_cmd(chip, 0, 100);
 261         if (retval < 0)
 262                 TRACE_RET(chip, STATUS_FAIL);
 263
 264         return STATUS_SUCCESS;
 265 }
 266
 267 int spi_erase_eeprom_chip(struct rtsx_chip *chip)
 268 {
 269         int retval;
 270
 271         retval = spi_init_eeprom(chip);
 272         if (retval != STATUS_SUCCESS)
 273                 TRACE_RET(chip, STATUS_FAIL);
 274
 275         retval = spi_eeprom_program_enable(chip);
 276         if (retval != STATUS_SUCCESS)
 277                 TRACE_RET(chip, STATUS_FAIL);
 278
 279         rtsx_init_cmd(chip);
 280
 281         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 282         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 283         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x12);
 284         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x84);
 285         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 286                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 287         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 288                 SPI_TRANSFER0_END);
 289
 290         retval = rtsx_send_cmd(chip, 0, 100);
 291         if (retval < 0)
 292                 TRACE_RET(chip, STATUS_FAIL);
 293
 294         RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
 295
 296         return STATUS_SUCCESS;
 297 }
 298
 299 int spi_erase_eeprom_byte(struct rtsx_chip *chip, u16 addr)
 300 {
 301         int retval;
 302
 303         retval = spi_init_eeprom(chip);
 304         if (retval != STATUS_SUCCESS)
 305                 TRACE_RET(chip, STATUS_FAIL);
 306
 307         retval = spi_eeprom_program_enable(chip);
 308         if (retval != STATUS_SUCCESS)
 309                 TRACE_RET(chip, STATUS_FAIL);
 310
 311         rtsx_init_cmd(chip);
 312
 313         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 314         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 315         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x07);
 316         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 317         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
 318         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
 319         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 320                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 321         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 322                 SPI_TRANSFER0_END);
 323
 324         retval = rtsx_send_cmd(chip, 0, 100);
 325         if (retval < 0)
 326                 TRACE_RET(chip, STATUS_FAIL);
 327
 328         RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
 329
 330         return STATUS_SUCCESS;
 331 }
 332
 333
 334 int spi_read_eeprom(struct rtsx_chip *chip, u16 addr, u8 *val)
 335 {
 336         int retval;
 337         u8 data;
 338
 339         retval = spi_init_eeprom(chip);
 340         if (retval != STATUS_SUCCESS)
 341                 TRACE_RET(chip, STATUS_FAIL);
 342
 343         rtsx_init_cmd(chip);
 344
 345         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 346         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 347         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x06);
 348         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, (u8)addr);
 349         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)(addr >> 8));
 350         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x46);
 351         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
 352         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 353                 SPI_TRANSFER0_START | SPI_CADI_MODE0);
 354         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 355                 SPI_TRANSFER0_END);
 356
 357         retval = rtsx_send_cmd(chip, 0, 100);
 358         if (retval < 0)
 359                 TRACE_RET(chip, STATUS_FAIL);
 360
 361         wait_timeout(5);
 362         RTSX_READ_REG(chip, SPI_DATA, &data);
 363
 364         if (val)
 365                 *val = data;
 366
 367         RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
 368
 369         return STATUS_SUCCESS;
 370 }
 371
 372 int spi_write_eeprom(struct rtsx_chip *chip, u16 addr, u8 val)
 373 {
 374         int retval;
 375
 376         retval = spi_init_eeprom(chip);
 377         if (retval != STATUS_SUCCESS)
 378                 TRACE_RET(chip, STATUS_FAIL);
 379
 380         retval = spi_eeprom_program_enable(chip);
 381         if (retval != STATUS_SUCCESS)
 382                 TRACE_RET(chip, STATUS_FAIL);
 383
 384         rtsx_init_cmd(chip);
 385
 386         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_GPIO_DIR, 0x01, 0);
 387         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
 388         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, 0x05);
 389         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, val);
 390         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, (u8)addr);
 391         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, (u8)(addr >> 8));
 392         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF, 0x4E);
 393         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 394                 SPI_TRANSFER0_START | SPI_CA_MODE0);
 395         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 396                 SPI_TRANSFER0_END);
 397
 398         retval = rtsx_send_cmd(chip, 0, 100);
 399         if (retval < 0)
 400                 TRACE_RET(chip, STATUS_FAIL);
 401
 402         RTSX_WRITE_REG(chip, CARD_GPIO_DIR, 0x01, 0x01);
 403
 404         return STATUS_SUCCESS;
 405 }
 406
 407
 408 int spi_get_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 409 {
 410         struct spi_info *spi = &(chip->spi);
 411
 412         RTSX_DEBUGP("spi_get_status: err_code = 0x%x\n", spi->err_code);
 413         rtsx_stor_set_xfer_buf(&(spi->err_code),
 414                         min_t(int, scsi_bufflen(srb), 1), srb);
 415         scsi_set_resid(srb, scsi_bufflen(srb) - 1);
 416
 417         return STATUS_SUCCESS;
 418 }
 419
 420 int spi_set_parameter(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 421 {
 422         struct spi_info *spi = &(chip->spi);
 423
 424         spi_set_err_code(chip, SPI_NO_ERR);
 425
 426         if (chip->asic_code)
 427                 spi->spi_clock = ((u16)(srb->cmnd[8]) << 8) | srb->cmnd[9];
 428         else
 429                 spi->spi_clock = srb->cmnd[3];
 430
 431         spi->clk_div = ((u16)(srb->cmnd[4]) << 8) | srb->cmnd[5];
 432         spi->write_en = srb->cmnd[6];
 433
 434         RTSX_DEBUGP("spi_set_parameter: spi_clock = %d, clk_div = %d, write_en = %d\n",
 435                      spi->spi_clock, spi->clk_div, spi->write_en);
 436
 437         return STATUS_SUCCESS;
 438 }
 439
 440 int spi_read_flash_id(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 441 {
 442         int retval;
 443         u16 len;
 444         u8 *buf;
 445
 446         spi_set_err_code(chip, SPI_NO_ERR);
 447
 448         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 449         if (len > 512) {
 450                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 451                 TRACE_RET(chip, STATUS_FAIL);
 452         }
 453
 454         retval = spi_set_init_para(chip);
 455         if (retval != STATUS_SUCCESS) {
 456                 spi_set_err_code(chip, SPI_HW_ERR);
 457                 TRACE_RET(chip, STATUS_FAIL);
 458         }
 459
 460         rtsx_init_cmd(chip);
 461
 462         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 463                 PINGPONG_BUFFER);
 464
 465         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, srb->cmnd[3]);
 466         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF, srb->cmnd[4]);
 467         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF, srb->cmnd[5]);
 468         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF, srb->cmnd[6]);
 469         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 470                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 471         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, srb->cmnd[7]);
 472         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, srb->cmnd[8]);
 473
 474         if (len == 0) {
 475                 if (srb->cmnd[9]) {
 476                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
 477                                       0xFF, SPI_TRANSFER0_START | SPI_CA_MODE0);
 478                 } else {
 479                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0,
 480                                       0xFF, SPI_TRANSFER0_START | SPI_C_MODE0);
 481                 }
 482         } else {
 483                 if (srb->cmnd[9]) {
 484                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 485                                 SPI_TRANSFER0_START | SPI_CADI_MODE0);
 486                 } else {
 487                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 488                                 SPI_TRANSFER0_START | SPI_CDI_MODE0);
 489                 }
 490         }
 491
 492         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 493                 SPI_TRANSFER0_END);
 494
 495         retval = rtsx_send_cmd(chip, 0, 100);
 496         if (retval < 0) {
 497                 rtsx_clear_spi_error(chip);
 498                 spi_set_err_code(chip, SPI_HW_ERR);
 499                 TRACE_RET(chip, STATUS_FAIL);
 500         }
 501
 502         if (len) {
 503                 buf = kmalloc(len, GFP_KERNEL);
 504                 if (!buf)
 505                         TRACE_RET(chip, STATUS_ERROR);
 506
 507                 retval = rtsx_read_ppbuf(chip, buf, len);
 508                 if (retval != STATUS_SUCCESS) {
 509                         spi_set_err_code(chip, SPI_READ_ERR);
 510                         kfree(buf);
 511                         TRACE_RET(chip, STATUS_FAIL);
 512                 }
 513
 514                 rtsx_stor_set_xfer_buf(buf, scsi_bufflen(srb), srb);
 515                 scsi_set_resid(srb, 0);
 516
 517                 kfree(buf);
 518         }
 519
 520         return STATUS_SUCCESS;
 521 }
 522
 523 int spi_read_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 524 {
 525         int retval;
 526         unsigned int index = 0, offset = 0;
 527         u8 ins, slow_read;
 528         u32 addr;
 529         u16 len;
 530         u8 *buf;
 531
 532         spi_set_err_code(chip, SPI_NO_ERR);
 533
 534         ins = srb->cmnd[3];
 535         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 536                                         << 8) | srb->cmnd[6];
 537         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 538         slow_read = srb->cmnd[9];
 539
 540         retval = spi_set_init_para(chip);
 541         if (retval != STATUS_SUCCESS) {
 542                 spi_set_err_code(chip, SPI_HW_ERR);
 543                 TRACE_RET(chip, STATUS_FAIL);
 544         }
 545
 546         buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
 547         if (buf == NULL)
 548                 TRACE_RET(chip, STATUS_ERROR);
 549
 550         while (len) {
 551                 u16 pagelen = SF_PAGE_LEN - (u8)addr;
 552
 553                 if (pagelen > len)
 554                         pagelen = len;
 555
 556                 rtsx_init_cmd(chip);
 557
 558                 trans_dma_enable(DMA_FROM_DEVICE, chip, 256, DMA_256);
 559
 560                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 561
 562                 if (slow_read) {
 563                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR0, 0xFF,
 564                                 (u8)addr);
 565                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 566                                 (u8)(addr >> 8));
 567                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 568                                 (u8)(addr >> 16));
 569                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 570                                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 571                 } else {
 572                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR1, 0xFF,
 573                                 (u8)addr);
 574                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR2, 0xFF,
 575                                 (u8)(addr >> 8));
 576                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_ADDR3, 0xFF,
 577                                 (u8)(addr >> 16));
 578                         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 579                                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_32);
 580                 }
 581
 582                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF,
 583                         (u8)(pagelen >> 8));
 584                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF,
 585                         (u8)pagelen);
 586
 587                 rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 588                         SPI_TRANSFER0_START | SPI_CADI_MODE0);
 589                 rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0,
 590                         SPI_TRANSFER0_END, SPI_TRANSFER0_END);
 591
 592                 rtsx_send_cmd_no_wait(chip);
 593
 594                 retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
 595                                         DMA_FROM_DEVICE, 10000);
 596                 if (retval < 0) {
 597                         kfree(buf);
 598                         rtsx_clear_spi_error(chip);
 599                         spi_set_err_code(chip, SPI_HW_ERR);
 600                         TRACE_RET(chip, STATUS_FAIL);
 601                 }
 602
 603                 rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index, &offset,
 604                                         TO_XFER_BUF);
 605
 606                 addr += pagelen;
 607                 len -= pagelen;
 608         }
 609
 610         scsi_set_resid(srb, 0);
 611         kfree(buf);
 612
 613         return STATUS_SUCCESS;
 614 }
 615
 616 int spi_write_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 617 {
 618         int retval;
 619         u8 ins, program_mode;
 620         u32 addr;
 621         u16 len;
 622         u8 *buf;
 623         unsigned int index = 0, offset = 0;
 624
 625         spi_set_err_code(chip, SPI_NO_ERR);
 626
 627         ins = srb->cmnd[3];
 628         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 629                                         << 8) | srb->cmnd[6];
 630         len = ((u16)(srb->cmnd[7]) << 8) | srb->cmnd[8];
 631         program_mode = srb->cmnd[9];
 632
 633         retval = spi_set_init_para(chip);
 634         if (retval != STATUS_SUCCESS) {
 635                 spi_set_err_code(chip, SPI_HW_ERR);
 636                 TRACE_RET(chip, STATUS_FAIL);
 637         }
 638
 639         if (program_mode == BYTE_PROGRAM) {
 640                 buf = kmalloc(4, GFP_KERNEL);
 641                 if (!buf)
 642                         TRACE_RET(chip, STATUS_ERROR);
 643
 644                 while (len) {
 645                         retval = sf_enable_write(chip, SPI_WREN);
 646                         if (retval != STATUS_SUCCESS) {
 647                                 kfree(buf);
 648                                 TRACE_RET(chip, STATUS_FAIL);
 649                         }
 650
 651                         rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
 652                                                 FROM_XFER_BUF);
 653
 654                         rtsx_init_cmd(chip);
 655
 656                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 657                                 0x01, PINGPONG_BUFFER);
 658                         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
 659                                 buf[0]);
 660                         sf_program(chip, ins, 1, addr, 1);
 661
 662                         retval = rtsx_send_cmd(chip, 0, 100);
 663                         if (retval < 0) {
 664                                 kfree(buf);
 665                                 rtsx_clear_spi_error(chip);
 666                                 spi_set_err_code(chip, SPI_HW_ERR);
 667                                 TRACE_RET(chip, STATUS_FAIL);
 668                         }
 669
 670                         retval = sf_polling_status(chip, 100);
 671                         if (retval != STATUS_SUCCESS) {
 672                                 kfree(buf);
 673                                 TRACE_RET(chip, STATUS_FAIL);
 674                         }
 675
 676                         addr++;
 677                         len--;
 678                 }
 679
 680                 kfree(buf);
 681
 682         } else if (program_mode == AAI_PROGRAM) {
 683                 int first_byte = 1;
 684
 685                 retval = sf_enable_write(chip, SPI_WREN);
 686                 if (retval != STATUS_SUCCESS)
 687                         TRACE_RET(chip, STATUS_FAIL);
 688
 689                 buf = kmalloc(4, GFP_KERNEL);
 690                 if (!buf)
 691                         TRACE_RET(chip, STATUS_ERROR);
 692
 693                 while (len) {
 694                         rtsx_stor_access_xfer_buf(buf, 1, srb, &index, &offset,
 695                                                 FROM_XFER_BUF);
 696
 697                         rtsx_init_cmd(chip);
 698
 699                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 700                                 0x01, PINGPONG_BUFFER);
 701                         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF,
 702                                 buf[0]);
 703                         if (first_byte) {
 704                                 sf_program(chip, ins, 1, addr, 1);
 705                                 first_byte = 0;
 706                         } else {
 707                                 sf_program(chip, ins, 0, 0, 1);
 708                         }
 709
 710                         retval = rtsx_send_cmd(chip, 0, 100);
 711                         if (retval < 0) {
 712                                 kfree(buf);
 713                                 rtsx_clear_spi_error(chip);
 714                                 spi_set_err_code(chip, SPI_HW_ERR);
 715                                 TRACE_RET(chip, STATUS_FAIL);
 716                         }
 717
 718                         retval = sf_polling_status(chip, 100);
 719                         if (retval != STATUS_SUCCESS) {
 720                                 kfree(buf);
 721                                 TRACE_RET(chip, STATUS_FAIL);
 722                         }
 723
 724                         len--;
 725                 }
 726
 727                 kfree(buf);
 728
 729                 retval = sf_disable_write(chip, SPI_WRDI);
 730                 if (retval != STATUS_SUCCESS)
 731                         TRACE_RET(chip, STATUS_FAIL);
 732
 733                 retval = sf_polling_status(chip, 100);
 734                 if (retval != STATUS_SUCCESS)
 735                         TRACE_RET(chip, STATUS_FAIL);
 736         } else if (program_mode == PAGE_PROGRAM) {
 737                 buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
 738                 if (!buf)
 739                         TRACE_RET(chip, STATUS_NOMEM);
 740
 741                 while (len) {
 742                         u16 pagelen = SF_PAGE_LEN - (u8)addr;
 743
 744                         if (pagelen > len)
 745                                 pagelen = len;
 746
 747                         retval = sf_enable_write(chip, SPI_WREN);
 748                         if (retval != STATUS_SUCCESS) {
 749                                 kfree(buf);
 750                                 TRACE_RET(chip, STATUS_FAIL);
 751                         }
 752
 753                         rtsx_init_cmd(chip);
 754
 755                         trans_dma_enable(DMA_TO_DEVICE, chip, 256, DMA_256);
 756                         sf_program(chip, ins, 1, addr, pagelen);
 757
 758                         rtsx_send_cmd_no_wait(chip);
 759
 760                         rtsx_stor_access_xfer_buf(buf, pagelen, srb, &index,
 761                                                 &offset, FROM_XFER_BUF);
 762
 763                         retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0,
 764                                                 DMA_TO_DEVICE, 100);
 765                         if (retval < 0) {
 766                                 kfree(buf);
 767                                 rtsx_clear_spi_error(chip);
 768                                 spi_set_err_code(chip, SPI_HW_ERR);
 769                                 TRACE_RET(chip, STATUS_FAIL);
 770                         }
 771
 772                         retval = sf_polling_status(chip, 100);
 773                         if (retval != STATUS_SUCCESS) {
 774                                 kfree(buf);
 775                                 TRACE_RET(chip, STATUS_FAIL);
 776                         }
 777
 778                         addr += pagelen;
 779                         len -= pagelen;
 780                 }
 781
 782                 kfree(buf);
 783         } else {
 784                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 785                 TRACE_RET(chip, STATUS_FAIL);
 786         }
 787
 788         return STATUS_SUCCESS;
 789 }
 790
 791 int spi_erase_flash(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 792 {
 793         int retval;
 794         u8 ins, erase_mode;
 795         u32 addr;
 796
 797         spi_set_err_code(chip, SPI_NO_ERR);
 798
 799         ins = srb->cmnd[3];
 800         addr = ((u32)(srb->cmnd[4]) << 16) | ((u32)(srb->cmnd[5])
 801                                         << 8) | srb->cmnd[6];
 802         erase_mode = srb->cmnd[9];
 803
 804         retval = spi_set_init_para(chip);
 805         if (retval != STATUS_SUCCESS) {
 806                 spi_set_err_code(chip, SPI_HW_ERR);
 807                 TRACE_RET(chip, STATUS_FAIL);
 808         }
 809
 810         if (erase_mode == PAGE_ERASE) {
 811                 retval = sf_enable_write(chip, SPI_WREN);
 812                 if (retval != STATUS_SUCCESS)
 813                         TRACE_RET(chip, STATUS_FAIL);
 814
 815                 retval = sf_erase(chip, ins, 1, addr);
 816                 if (retval != STATUS_SUCCESS)
 817                         TRACE_RET(chip, STATUS_FAIL);
 818         } else if (erase_mode == CHIP_ERASE) {
 819                 retval = sf_enable_write(chip, SPI_WREN);
 820                 if (retval != STATUS_SUCCESS)
 821                         TRACE_RET(chip, STATUS_FAIL);
 822
 823                 retval = sf_erase(chip, ins, 0, 0);
 824                 if (retval != STATUS_SUCCESS)
 825                         TRACE_RET(chip, STATUS_FAIL);
 826         } else {
 827                 spi_set_err_code(chip, SPI_INVALID_COMMAND);
 828                 TRACE_RET(chip, STATUS_FAIL);
 829         }
 830
 831         return STATUS_SUCCESS;
 832 }
 833
 834 int spi_write_flash_status(struct scsi_cmnd *srb, struct rtsx_chip *chip)
 835 {
 836         int retval;
 837         u8 ins, status, ewsr;
 838
 839         ins = srb->cmnd[3];
 840         status = srb->cmnd[4];
 841         ewsr = srb->cmnd[5];
 842
 843         retval = spi_set_init_para(chip);
 844         if (retval != STATUS_SUCCESS) {
 845                 spi_set_err_code(chip, SPI_HW_ERR);
 846                 TRACE_RET(chip, STATUS_FAIL);
 847         }
 848
 849         retval = sf_enable_write(chip, ewsr);
 850         if (retval != STATUS_SUCCESS)
 851                 TRACE_RET(chip, STATUS_FAIL);
 852
 853         rtsx_init_cmd(chip);
 854
 855         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
 856                 PINGPONG_BUFFER);
 857
 858         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_COMMAND, 0xFF, ins);
 859         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_CA_NUMBER, 0xFF,
 860                 SPI_COMMAND_BIT_8 | SPI_ADDRESS_BIT_24);
 861         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH1, 0xFF, 0);
 862         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_LENGTH0, 0xFF, 1);
 863         rtsx_add_cmd(chip, WRITE_REG_CMD, PPBUF_BASE2, 0xFF, status);
 864         rtsx_add_cmd(chip, WRITE_REG_CMD, SPI_TRANSFER0, 0xFF,
 865                 SPI_TRANSFER0_START | SPI_CDO_MODE0);
 866         rtsx_add_cmd(chip, CHECK_REG_CMD, SPI_TRANSFER0, SPI_TRANSFER0_END,
 867                 SPI_TRANSFER0_END);
 868
 869         retval = rtsx_send_cmd(chip, 0, 100);
 870         if (retval != STATUS_SUCCESS) {
 871                 rtsx_clear_spi_error(chip);
 872                 spi_set_err_code(chip, SPI_HW_ERR);
 873                 TRACE_RET(chip, STATUS_FAIL);
 874         }
 875
 876         return STATUS_SUCCESS;
 877 }