drivers/thermal/samsung/exynos_tmu_data.h

   1 /*
   2  * exynos_tmu_data.h - Samsung EXYNOS tmu data header file
   3  *
   4  *  Copyright (C) 2013 Samsung Electronics
   5  *  Amit Daniel Kachhap <amit.daniel@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  *
  21  */
  22
  23 #ifndef _EXYNOS_TMU_DATA_H
  24 #define _EXYNOS_TMU_DATA_H
  25
  26 /* Exynos generic registers */
  27 #define EXYNOS_TMU_REG_TRIMINFO         0x0
  28 #define EXYNOS_TMU_REG_CONTROL          0x20
  29 #define EXYNOS_TMU_REG_STATUS           0x28
  30 #define EXYNOS_TMU_REG_CURRENT_TEMP     0x40
  31 #define EXYNOS_TMU_REG_INTEN            0x70
  32 #define EXYNOS_TMU_REG_INTSTAT          0x74
  33 #define EXYNOS_TMU_REG_INTCLEAR         0x78
  34
  35 #define EXYNOS_TMU_TEMP_MASK            0xff
  36 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT    24
  37 #define EXYNOS_TMU_REF_VOLTAGE_MASK     0x1f
  38 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK   0xf
  39 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT  8
  40 #define EXYNOS_TMU_CORE_EN_SHIFT        0
  41
  42 /* Exynos4210 specific registers */
  43 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP       0x44
  44 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0  0x50
  45 #define EXYNOS4210_TMU_REG_TRIG_LEVEL1  0x54
  46 #define EXYNOS4210_TMU_REG_TRIG_LEVEL2  0x58
  47 #define EXYNOS4210_TMU_REG_TRIG_LEVEL3  0x5C
  48 #define EXYNOS4210_TMU_REG_PAST_TEMP0   0x60
  49 #define EXYNOS4210_TMU_REG_PAST_TEMP1   0x64
  50 #define EXYNOS4210_TMU_REG_PAST_TEMP2   0x68
  51 #define EXYNOS4210_TMU_REG_PAST_TEMP3   0x6C
  52
  53 #define EXYNOS4210_TMU_TRIG_LEVEL0_MASK 0x1
  54 #define EXYNOS4210_TMU_TRIG_LEVEL1_MASK 0x10
  55 #define EXYNOS4210_TMU_TRIG_LEVEL2_MASK 0x100
  56 #define EXYNOS4210_TMU_TRIG_LEVEL3_MASK 0x1000
  57 #define EXYNOS4210_TMU_TRIG_LEVEL_MASK  0x1111
  58 #define EXYNOS4210_TMU_INTCLEAR_VAL     0x1111
  59
  60 /* Exynos5250 and Exynos4412 specific registers */
  61 #define EXYNOS_TMU_TRIMINFO_CON 0x14
  62 #define EXYNOS_THD_TEMP_RISE            0x50
  63 #define EXYNOS_THD_TEMP_FALL            0x54
  64 #define EXYNOS_EMUL_CON         0x80
  65
  66 #define EXYNOS_TRIMINFO_RELOAD_SHIFT    1
  67 #define EXYNOS_TRIMINFO_25_SHIFT        0
  68 #define EXYNOS_TRIMINFO_85_SHIFT        8
  69 #define EXYNOS_TMU_RISE_INT_MASK        0x111
  70 #define EXYNOS_TMU_RISE_INT_SHIFT       0
  71 #define EXYNOS_TMU_FALL_INT_MASK        0x111
  72 #define EXYNOS_TMU_FALL_INT_SHIFT       12
  73 #define EXYNOS_TMU_CLEAR_RISE_INT       0x111
  74 #define EXYNOS_TMU_CLEAR_FALL_INT       (0x111 << 12)
  75 #define EXYNOS_TMU_TRIP_MODE_SHIFT      13
  76 #define EXYNOS_TMU_TRIP_MODE_MASK       0x7
  77 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT  12
  78 #define EXYNOS_TMU_CALIB_MODE_SHIFT     4
  79 #define EXYNOS_TMU_CALIB_MODE_MASK      0x3
  80
  81 #define EXYNOS_TMU_INTEN_RISE0_SHIFT    0
  82 #define EXYNOS_TMU_INTEN_RISE1_SHIFT    4
  83 #define EXYNOS_TMU_INTEN_RISE2_SHIFT    8
  84 #define EXYNOS_TMU_INTEN_RISE3_SHIFT    12
  85 #define EXYNOS_TMU_INTEN_FALL0_SHIFT    16
  86 #define EXYNOS_TMU_INTEN_FALL1_SHIFT    20
  87 #define EXYNOS_TMU_INTEN_FALL2_SHIFT    24
  88
  89 #define EXYNOS_EMUL_TIME        0x57F0
  90 #define EXYNOS_EMUL_TIME_MASK   0xffff
  91 #define EXYNOS_EMUL_TIME_SHIFT  16
  92 #define EXYNOS_EMUL_DATA_SHIFT  8
  93 #define EXYNOS_EMUL_DATA_MASK   0xFF
  94 #define EXYNOS_EMUL_ENABLE      0x1
  95
  96 #define EXYNOS_MAX_TRIGGER_PER_REG      4
  97
  98 /* Exynos4412 specific */
  99 #define EXYNOS4412_MUX_ADDR_VALUE          6
 100 #define EXYNOS4412_MUX_ADDR_SHIFT          20
 101
 102 /*exynos5440 specific registers*/
 103 #define EXYNOS5440_TMU_S0_7_TRIM                0x000
 104 #define EXYNOS5440_TMU_S0_7_CTRL                0x020
 105 #define EXYNOS5440_TMU_S0_7_DEBUG               0x040
 106 #define EXYNOS5440_TMU_S0_7_STATUS              0x060
 107 #define EXYNOS5440_TMU_S0_7_TEMP                0x0f0
 108 #define EXYNOS5440_TMU_S0_7_TH0                 0x110
 109 #define EXYNOS5440_TMU_S0_7_TH1                 0x130
 110 #define EXYNOS5440_TMU_S0_7_TH2                 0x150
 111 #define EXYNOS5440_TMU_S0_7_EVTEN               0x1F0
 112 #define EXYNOS5440_TMU_S0_7_IRQEN               0x210
 113 #define EXYNOS5440_TMU_S0_7_IRQ                 0x230
 114 /* exynos5440 common registers */
 115 #define EXYNOS5440_TMU_IRQ_STATUS               0x000
 116 #define EXYNOS5440_TMU_PMIN                     0x004
 117 #define EXYNOS5440_TMU_TEMP                     0x008
 118
 119 #define EXYNOS5440_TMU_RISE_INT_MASK            0xf
 120 #define EXYNOS5440_TMU_RISE_INT_SHIFT           0
 121 #define EXYNOS5440_TMU_FALL_INT_MASK            0xf
 122 #define EXYNOS5440_TMU_FALL_INT_SHIFT           4
 123 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT        0
 124 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT        1
 125 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT        2
 126 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT        3
 127 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT        4
 128 #define EXYNOS5440_TMU_INTEN_FALL1_SHIFT        5
 129 #define EXYNOS5440_TMU_INTEN_FALL2_SHIFT        6
 130 #define EXYNOS5440_TMU_INTEN_FALL3_SHIFT        7
 131 #define EXYNOS5440_TMU_TH_RISE0_SHIFT           0
 132 #define EXYNOS5440_TMU_TH_RISE1_SHIFT           8
 133 #define EXYNOS5440_TMU_TH_RISE2_SHIFT           16
 134 #define EXYNOS5440_TMU_TH_RISE3_SHIFT           24
 135 #define EXYNOS5440_TMU_TH_RISE4_SHIFT           24
 136 #define EXYNOS5440_EFUSE_SWAP_OFFSET            8
 137
 138 #if defined(CONFIG_CPU_EXYNOS4210)
 139 extern struct exynos_tmu_init_data const exynos4210_default_tmu_data;
 140 #define EXYNOS4210_TMU_DRV_DATA (&exynos4210_default_tmu_data)
 141 #else
 142 #define EXYNOS4210_TMU_DRV_DATA (NULL)
 143 #endif
 144
 145 #if defined(CONFIG_SOC_EXYNOS4412)
 146 extern struct exynos_tmu_init_data const exynos4412_default_tmu_data;
 147 #define EXYNOS4412_TMU_DRV_DATA (&exynos4412_default_tmu_data)
 148 #else
 149 #define EXYNOS4412_TMU_DRV_DATA (NULL)
 150 #endif
 151
 152 #if defined(CONFIG_SOC_EXYNOS5250)
 153 extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 154 #define EXYNOS5250_TMU_DRV_DATA (&exynos5250_default_tmu_data)
 155 #else
 156 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 157 #endif
 158
 159 #if defined(CONFIG_SOC_EXYNOS5440)
 160 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 161 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
 162 #else
 163 #define EXYNOS5440_TMU_DRV_DATA (NULL)
 164 #endif
 165
 166 #endif /*_EXYNOS_TMU_DATA_H*/