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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / tty / serial / imx.c
blobd799140e53b6a649b51ace8129b8846ed695a824
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/io.h>
51 #include <linux/dma-mapping.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
56
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76 /* UART Control Register Bit Fields.*/
77 #define URXD_CHARRDY (1<<15)
78 #define URXD_ERR (1<<14)
79 #define URXD_OVRRUN (1<<13)
80 #define URXD_FRMERR (1<<12)
81 #define URXD_BRK (1<<11)
82 #define URXD_PRERR (1<<10)
83 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
84 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
85 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
86 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
87 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
88 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
89 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
90 #define UCR1_IREN (1<<7) /* Infrared interface enable */
91 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
92 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
93 #define UCR1_SNDBRK (1<<4) /* Send break */
94 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
95 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
96 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
97 #define UCR1_DOZE (1<<1) /* Doze */
98 #define UCR1_UARTEN (1<<0) /* UART enabled */
99 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
100 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
101 #define UCR2_CTSC (1<<13) /* CTS pin control */
102 #define UCR2_CTS (1<<12) /* Clear to send */
103 #define UCR2_ESCEN (1<<11) /* Escape enable */
104 #define UCR2_PREN (1<<8) /* Parity enable */
105 #define UCR2_PROE (1<<7) /* Parity odd/even */
106 #define UCR2_STPB (1<<6) /* Stop */
107 #define UCR2_WS (1<<5) /* Word size */
108 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
109 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
110 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
111 #define UCR2_RXEN (1<<1) /* Receiver enabled */
112 #define UCR2_SRST (1<<0) /* SW reset */
113 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
114 #define UCR3_PARERREN (1<<12) /* Parity enable */
115 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
116 #define UCR3_DSR (1<<10) /* Data set ready */
117 #define UCR3_DCD (1<<9) /* Data carrier detect */
118 #define UCR3_RI (1<<8) /* Ring indicator */
119 #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */
120 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
121 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
122 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
123 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
124 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
125 #define UCR3_BPEN (1<<0) /* Preset registers enable */
126 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
127 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
128 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
129 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
130 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
131 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
132 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
133 #define UCR4_IRSC (1<<5) /* IR special case */
134 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
135 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
136 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
137 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
138 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
139 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
140 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
141 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
142 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
143 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
144 #define USR1_RTSS (1<<14) /* RTS pin status */
145 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
146 #define USR1_RTSD (1<<12) /* RTS delta */
147 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
148 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
149 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
150 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
151 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
152 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
153 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
154 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
155 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
156 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
157 #define USR2_IDLE (1<<12) /* Idle condition */
158 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
159 #define USR2_WAKE (1<<7) /* Wake */
160 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
161 #define USR2_TXDC (1<<3) /* Transmitter complete */
162 #define USR2_BRCD (1<<2) /* Break condition */
163 #define USR2_ORE (1<<1) /* Overrun error */
164 #define USR2_RDR (1<<0) /* Recv data ready */
165 #define UTS_FRCPERR (1<<13) /* Force parity error */
166 #define UTS_LOOP (1<<12) /* Loop tx and rx */
167 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
168 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
169 #define UTS_TXFULL (1<<4) /* TxFIFO full */
170 #define UTS_RXFULL (1<<3) /* RxFIFO full */
171 #define UTS_SOFTRST (1<<0) /* Software reset */
172
173 /* We've been assigned a range on the "Low-density serial ports" major */
174 #define SERIAL_IMX_MAJOR 207
175 #define MINOR_START 16
176 #define DEV_NAME "ttymxc"
177
178 /*
179 * This determines how often we check the modem status signals
180 * for any change. They generally aren't connected to an IRQ
181 * so we have to poll them. We also check immediately before
182 * filling the TX fifo incase CTS has been dropped.
183 */
184 #define MCTRL_TIMEOUT (250*HZ/1000)
185
186 #define DRIVER_NAME "IMX-uart"
187
188 #define UART_NR 8
189
190 /* i.mx21 type uart runs on all i.mx except i.mx1 */
191 enum imx_uart_type {
192 IMX1_UART,
193 IMX21_UART,
194 IMX6Q_UART,
195 };
196
197 /* device type dependent stuff */
198 struct imx_uart_data {
199 unsigned uts_reg;
200 enum imx_uart_type devtype;
201 };
202
203 struct imx_port {
204 struct uart_port port;
205 struct timer_list timer;
206 unsigned int old_status;
207 int txirq, rxirq, rtsirq;
208 unsigned int have_rtscts:1;
209 unsigned int dte_mode:1;
210 unsigned int use_irda:1;
211 unsigned int irda_inv_rx:1;
212 unsigned int irda_inv_tx:1;
213 unsigned short trcv_delay; /* transceiver delay */
214 struct clk *clk_ipg;
215 struct clk *clk_per;
216 const struct imx_uart_data *devdata;
217
218 /* DMA fields */
219 unsigned int dma_is_inited:1;
220 unsigned int dma_is_enabled:1;
221 unsigned int dma_is_rxing:1;
222 unsigned int dma_is_txing:1;
223 struct dma_chan *dma_chan_rx, *dma_chan_tx;
224 struct scatterlist rx_sgl, tx_sgl[2];
225 void *rx_buf;
226 unsigned int tx_bytes;
227 unsigned int dma_tx_nents;
228 wait_queue_head_t dma_wait;
229 };
230
231 struct imx_port_ucrs {
232 unsigned int ucr1;
233 unsigned int ucr2;
234 unsigned int ucr3;
235 };
236
237 #ifdef CONFIG_IRDA
238 #define USE_IRDA(sport) ((sport)->use_irda)
239 #else
240 #define USE_IRDA(sport) (0)
241 #endif
242
243 static struct imx_uart_data imx_uart_devdata[] = {
244 [IMX1_UART] = {
245 .uts_reg = IMX1_UTS,
246 .devtype = IMX1_UART,
247 },
248 [IMX21_UART] = {
249 .uts_reg = IMX21_UTS,
250 .devtype = IMX21_UART,
251 },
252 [IMX6Q_UART] = {
253 .uts_reg = IMX21_UTS,
254 .devtype = IMX6Q_UART,
255 },
256 };
257
258 static struct platform_device_id imx_uart_devtype[] = {
259 {
260 .name = "imx1-uart",
261 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
262 }, {
263 .name = "imx21-uart",
264 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
265 }, {
266 .name = "imx6q-uart",
267 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
268 }, {
269 /* sentinel */
270 }
271 };
272 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
273
274 static struct of_device_id imx_uart_dt_ids[] = {
275 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
276 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
277 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
278 { /* sentinel */ }
279 };
280 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
281
282 static inline unsigned uts_reg(struct imx_port *sport)
283 {
284 return sport->devdata->uts_reg;
285 }
286
287 static inline int is_imx1_uart(struct imx_port *sport)
288 {
289 return sport->devdata->devtype == IMX1_UART;
290 }
291
292 static inline int is_imx21_uart(struct imx_port *sport)
293 {
294 return sport->devdata->devtype == IMX21_UART;
295 }
296
297 static inline int is_imx6q_uart(struct imx_port *sport)
298 {
299 return sport->devdata->devtype == IMX6Q_UART;
300 }
301 /*
302 * Save and restore functions for UCR1, UCR2 and UCR3 registers
303 */
304 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_IMX_CONSOLE)
305 static void imx_port_ucrs_save(struct uart_port *port,
306 struct imx_port_ucrs *ucr)
307 {
308 /* save control registers */
309 ucr->ucr1 = readl(port->membase + UCR1);
310 ucr->ucr2 = readl(port->membase + UCR2);
311 ucr->ucr3 = readl(port->membase + UCR3);
312 }
313
314 static void imx_port_ucrs_restore(struct uart_port *port,
315 struct imx_port_ucrs *ucr)
316 {
317 /* restore control registers */
318 writel(ucr->ucr1, port->membase + UCR1);
319 writel(ucr->ucr2, port->membase + UCR2);
320 writel(ucr->ucr3, port->membase + UCR3);
321 }
322 #endif
323
324 /*
325 * Handle any change of modem status signal since we were last called.
326 */
327 static void imx_mctrl_check(struct imx_port *sport)
328 {
329 unsigned int status, changed;
330
331 status = sport->port.ops->get_mctrl(&sport->port);
332 changed = status ^ sport->old_status;
333
334 if (changed == 0)
335 return;
336
337 sport->old_status = status;
338
339 if (changed & TIOCM_RI)
340 sport->port.icount.rng++;
341 if (changed & TIOCM_DSR)
342 sport->port.icount.dsr++;
343 if (changed & TIOCM_CAR)
344 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
345 if (changed & TIOCM_CTS)
346 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
347
348 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
349 }
350
351 /*
352 * This is our per-port timeout handler, for checking the
353 * modem status signals.
354 */
355 static void imx_timeout(unsigned long data)
356 {
357 struct imx_port *sport = (struct imx_port *)data;
358 unsigned long flags;
359
360 if (sport->port.state) {
361 spin_lock_irqsave(&sport->port.lock, flags);
362 imx_mctrl_check(sport);
363 spin_unlock_irqrestore(&sport->port.lock, flags);
364
365 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
366 }
367 }
368
369 /*
370 * interrupts disabled on entry
371 */
372 static void imx_stop_tx(struct uart_port *port)
373 {
374 struct imx_port *sport = (struct imx_port *)port;
375 unsigned long temp;
376
377 if (USE_IRDA(sport)) {
378 /* half duplex - wait for end of transmission */
379 int n = 256;
380 while ((--n > 0) &&
381 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
382 udelay(5);
383 barrier();
384 }
385 /*
386 * irda transceiver - wait a bit more to avoid
387 * cutoff, hardware dependent
388 */
389 udelay(sport->trcv_delay);
390
391 /*
392 * half duplex - reactivate receive mode,
393 * flush receive pipe echo crap
394 */
395 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
396 temp = readl(sport->port.membase + UCR1);
397 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
398 writel(temp, sport->port.membase + UCR1);
399
400 temp = readl(sport->port.membase + UCR4);
401 temp &= ~(UCR4_TCEN);
402 writel(temp, sport->port.membase + UCR4);
403
404 while (readl(sport->port.membase + URXD0) &
405 URXD_CHARRDY)
406 barrier();
407
408 temp = readl(sport->port.membase + UCR1);
409 temp |= UCR1_RRDYEN;
410 writel(temp, sport->port.membase + UCR1);
411
412 temp = readl(sport->port.membase + UCR4);
413 temp |= UCR4_DREN;
414 writel(temp, sport->port.membase + UCR4);
415 }
416 return;
417 }
418
419 /*
420 * We are maybe in the SMP context, so if the DMA TX thread is running
421 * on other cpu, we have to wait for it to finish.
422 */
423 if (sport->dma_is_enabled && sport->dma_is_txing)
424 return;
425
426 temp = readl(sport->port.membase + UCR1);
427 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
428 }
429
430 /*
431 * interrupts disabled on entry
432 */
433 static void imx_stop_rx(struct uart_port *port)
434 {
435 struct imx_port *sport = (struct imx_port *)port;
436 unsigned long temp;
437
438 /*
439 * We are maybe in the SMP context, so if the DMA TX thread is running
440 * on other cpu, we have to wait for it to finish.
441 */
442 if (sport->dma_is_enabled && sport->dma_is_rxing)
443 return;
444
445 temp = readl(sport->port.membase + UCR2);
446 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
447 }
448
449 /*
450 * Set the modem control timer to fire immediately.
451 */
452 static void imx_enable_ms(struct uart_port *port)
453 {
454 struct imx_port *sport = (struct imx_port *)port;
455
456 mod_timer(&sport->timer, jiffies);
457 }
458
459 static inline void imx_transmit_buffer(struct imx_port *sport)
460 {
461 struct circ_buf *xmit = &sport->port.state->xmit;
462
463 while (!uart_circ_empty(xmit) &&
464 !(readl(sport->port.membase + uts_reg(sport))
465 & UTS_TXFULL)) {
466 /* send xmit->buf[xmit->tail]
467 * out the port here */
468 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
469 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
470 sport->port.icount.tx++;
471 }
472
473 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
474 uart_write_wakeup(&sport->port);
475
476 if (uart_circ_empty(xmit))
477 imx_stop_tx(&sport->port);
478 }
479
480 static void dma_tx_callback(void *data)
481 {
482 struct imx_port *sport = data;
483 struct scatterlist *sgl = &sport->tx_sgl[0];
484 struct circ_buf *xmit = &sport->port.state->xmit;
485 unsigned long flags;
486
487 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
488
489 sport->dma_is_txing = 0;
490
491 /* update the stat */
492 spin_lock_irqsave(&sport->port.lock, flags);
493 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
494 sport->port.icount.tx += sport->tx_bytes;
495 spin_unlock_irqrestore(&sport->port.lock, flags);
496
497 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
498
499 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
500 uart_write_wakeup(&sport->port);
501
502 if (waitqueue_active(&sport->dma_wait)) {
503 wake_up(&sport->dma_wait);
504 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
505 return;
506 }
507 }
508
509 static void imx_dma_tx(struct imx_port *sport)
510 {
511 struct circ_buf *xmit = &sport->port.state->xmit;
512 struct scatterlist *sgl = sport->tx_sgl;
513 struct dma_async_tx_descriptor *desc;
514 struct dma_chan *chan = sport->dma_chan_tx;
515 struct device *dev = sport->port.dev;
516 enum dma_status status;
517 int ret;
518
519 status = dmaengine_tx_status(chan, (dma_cookie_t)0, NULL);
520 if (DMA_IN_PROGRESS == status)
521 return;
522
523 sport->tx_bytes = uart_circ_chars_pending(xmit);
524
525 if (xmit->tail > xmit->head && xmit->head > 0) {
526 sport->dma_tx_nents = 2;
527 sg_init_table(sgl, 2);
528 sg_set_buf(sgl, xmit->buf + xmit->tail,
529 UART_XMIT_SIZE - xmit->tail);
530 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
531 } else {
532 sport->dma_tx_nents = 1;
533 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
534 }
535
536 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
537 if (ret == 0) {
538 dev_err(dev, "DMA mapping error for TX.\n");
539 return;
540 }
541 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
542 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
543 if (!desc) {
544 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
545 return;
546 }
547 desc->callback = dma_tx_callback;
548 desc->callback_param = sport;
549
550 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
551 uart_circ_chars_pending(xmit));
552 /* fire it */
553 sport->dma_is_txing = 1;
554 dmaengine_submit(desc);
555 dma_async_issue_pending(chan);
556 return;
557 }
558
559 /*
560 * interrupts disabled on entry
561 */
562 static void imx_start_tx(struct uart_port *port)
563 {
564 struct imx_port *sport = (struct imx_port *)port;
565 unsigned long temp;
566
567 if (USE_IRDA(sport)) {
568 /* half duplex in IrDA mode; have to disable receive mode */
569 temp = readl(sport->port.membase + UCR4);
570 temp &= ~(UCR4_DREN);
571 writel(temp, sport->port.membase + UCR4);
572
573 temp = readl(sport->port.membase + UCR1);
574 temp &= ~(UCR1_RRDYEN);
575 writel(temp, sport->port.membase + UCR1);
576 }
577 /* Clear any pending ORE flag before enabling interrupt */
578 temp = readl(sport->port.membase + USR2);
579 writel(temp | USR2_ORE, sport->port.membase + USR2);
580
581 temp = readl(sport->port.membase + UCR4);
582 temp |= UCR4_OREN;
583 writel(temp, sport->port.membase + UCR4);
584
585 if (!sport->dma_is_enabled) {
586 temp = readl(sport->port.membase + UCR1);
587 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
588 }
589
590 if (USE_IRDA(sport)) {
591 temp = readl(sport->port.membase + UCR1);
592 temp |= UCR1_TRDYEN;
593 writel(temp, sport->port.membase + UCR1);
594
595 temp = readl(sport->port.membase + UCR4);
596 temp |= UCR4_TCEN;
597 writel(temp, sport->port.membase + UCR4);
598 }
599
600 if (sport->dma_is_enabled) {
601 imx_dma_tx(sport);
602 return;
603 }
604
605 if (readl(sport->port.membase + uts_reg(sport)) & UTS_TXEMPTY)
606 imx_transmit_buffer(sport);
607 }
608
609 static irqreturn_t imx_rtsint(int irq, void *dev_id)
610 {
611 struct imx_port *sport = dev_id;
612 unsigned int val;
613 unsigned long flags;
614
615 spin_lock_irqsave(&sport->port.lock, flags);
616
617 writel(USR1_RTSD, sport->port.membase + USR1);
618 val = readl(sport->port.membase + USR1) & USR1_RTSS;
619 uart_handle_cts_change(&sport->port, !!val);
620 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
621
622 spin_unlock_irqrestore(&sport->port.lock, flags);
623 return IRQ_HANDLED;
624 }
625
626 static irqreturn_t imx_txint(int irq, void *dev_id)
627 {
628 struct imx_port *sport = dev_id;
629 struct circ_buf *xmit = &sport->port.state->xmit;
630 unsigned long flags;
631
632 spin_lock_irqsave(&sport->port.lock, flags);
633 if (sport->port.x_char) {
634 /* Send next char */
635 writel(sport->port.x_char, sport->port.membase + URTX0);
636 goto out;
637 }
638
639 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
640 imx_stop_tx(&sport->port);
641 goto out;
642 }
643
644 imx_transmit_buffer(sport);
645
646 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
647 uart_write_wakeup(&sport->port);
648
649 out:
650 spin_unlock_irqrestore(&sport->port.lock, flags);
651 return IRQ_HANDLED;
652 }
653
654 static irqreturn_t imx_rxint(int irq, void *dev_id)
655 {
656 struct imx_port *sport = dev_id;
657 unsigned int rx, flg, ignored = 0;
658 struct tty_port *port = &sport->port.state->port;
659 unsigned long flags, temp;
660
661 spin_lock_irqsave(&sport->port.lock, flags);
662
663 while (readl(sport->port.membase + USR2) & USR2_RDR) {
664 flg = TTY_NORMAL;
665 sport->port.icount.rx++;
666
667 rx = readl(sport->port.membase + URXD0);
668
669 temp = readl(sport->port.membase + USR2);
670 if (temp & USR2_BRCD) {
671 writel(USR2_BRCD, sport->port.membase + USR2);
672 if (uart_handle_break(&sport->port))
673 continue;
674 }
675
676 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
677 continue;
678
679 if (unlikely(rx & URXD_ERR)) {
680 if (rx & URXD_BRK)
681 sport->port.icount.brk++;
682 else if (rx & URXD_PRERR)
683 sport->port.icount.parity++;
684 else if (rx & URXD_FRMERR)
685 sport->port.icount.frame++;
686 if (rx & URXD_OVRRUN)
687 sport->port.icount.overrun++;
688
689 if (rx & sport->port.ignore_status_mask) {
690 if (++ignored > 100)
691 goto out;
692 continue;
693 }
694
695 rx &= sport->port.read_status_mask;
696
697 if (rx & URXD_BRK)
698 flg = TTY_BREAK;
699 else if (rx & URXD_PRERR)
700 flg = TTY_PARITY;
701 else if (rx & URXD_FRMERR)
702 flg = TTY_FRAME;
703 if (rx & URXD_OVRRUN)
704 flg = TTY_OVERRUN;
705
706 #ifdef SUPPORT_SYSRQ
707 sport->port.sysrq = 0;
708 #endif
709 }
710
711 tty_insert_flip_char(port, rx, flg);
712 }
713
714 out:
715 spin_unlock_irqrestore(&sport->port.lock, flags);
716 tty_flip_buffer_push(port);
717 return IRQ_HANDLED;
718 }
719
720 static int start_rx_dma(struct imx_port *sport);
721 /*
722 * If the RXFIFO is filled with some data, and then we
723 * arise a DMA operation to receive them.
724 */
725 static void imx_dma_rxint(struct imx_port *sport)
726 {
727 unsigned long temp;
728
729 temp = readl(sport->port.membase + USR2);
730 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
731 sport->dma_is_rxing = 1;
732
733 /* disable the `Recerver Ready Interrrupt` */
734 temp = readl(sport->port.membase + UCR1);
735 temp &= ~(UCR1_RRDYEN);
736 writel(temp, sport->port.membase + UCR1);
737
738 /* tell the DMA to receive the data. */
739 start_rx_dma(sport);
740 }
741 }
742
743 static irqreturn_t imx_int(int irq, void *dev_id)
744 {
745 struct imx_port *sport = dev_id;
746 unsigned int sts;
747 unsigned int sts2;
748
749 sts = readl(sport->port.membase + USR1);
750
751 if (sts & USR1_RRDY) {
752 if (sport->dma_is_enabled)
753 imx_dma_rxint(sport);
754 else
755 imx_rxint(irq, dev_id);
756 }
757
758 if (sts & USR1_TRDY &&
759 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
760 imx_txint(irq, dev_id);
761
762 if (sts & USR1_RTSD)
763 imx_rtsint(irq, dev_id);
764
765 if (sts & USR1_AWAKE)
766 writel(USR1_AWAKE, sport->port.membase + USR1);
767
768 sts2 = readl(sport->port.membase + USR2);
769 if (sts2 & USR2_ORE) {
770 dev_err(sport->port.dev, "Rx FIFO overrun\n");
771 sport->port.icount.overrun++;
772 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
773 }
774
775 return IRQ_HANDLED;
776 }
777
778 /*
779 * Return TIOCSER_TEMT when transmitter is not busy.
780 */
781 static unsigned int imx_tx_empty(struct uart_port *port)
782 {
783 struct imx_port *sport = (struct imx_port *)port;
784 unsigned int ret;
785
786 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
787
788 /* If the TX DMA is working, return 0. */
789 if (sport->dma_is_enabled && sport->dma_is_txing)
790 ret = 0;
791
792 return ret;
793 }
794
795 /*
796 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
797 */
798 static unsigned int imx_get_mctrl(struct uart_port *port)
799 {
800 struct imx_port *sport = (struct imx_port *)port;
801 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
802
803 if (readl(sport->port.membase + USR1) & USR1_RTSS)
804 tmp |= TIOCM_CTS;
805
806 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
807 tmp |= TIOCM_RTS;
808
809 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
810 tmp |= TIOCM_LOOP;
811
812 return tmp;
813 }
814
815 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
816 {
817 struct imx_port *sport = (struct imx_port *)port;
818 unsigned long temp;
819
820 temp = readl(sport->port.membase + UCR2) & ~UCR2_CTS;
821
822 if (mctrl & TIOCM_RTS)
823 if (!sport->dma_is_enabled)
824 temp |= UCR2_CTS;
825
826 writel(temp, sport->port.membase + UCR2);
827
828 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
829 if (mctrl & TIOCM_LOOP)
830 temp |= UTS_LOOP;
831 writel(temp, sport->port.membase + uts_reg(sport));
832 }
833
834 /*
835 * Interrupts always disabled.
836 */
837 static void imx_break_ctl(struct uart_port *port, int break_state)
838 {
839 struct imx_port *sport = (struct imx_port *)port;
840 unsigned long flags, temp;
841
842 spin_lock_irqsave(&sport->port.lock, flags);
843
844 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
845
846 if (break_state != 0)
847 temp |= UCR1_SNDBRK;
848
849 writel(temp, sport->port.membase + UCR1);
850
851 spin_unlock_irqrestore(&sport->port.lock, flags);
852 }
853
854 #define TXTL 2 /* reset default */
855 #define RXTL 1 /* reset default */
856
857 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
858 {
859 unsigned int val;
860
861 /* set receiver / transmitter trigger level */
862 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
863 val |= TXTL << UFCR_TXTL_SHF | RXTL;
864 writel(val, sport->port.membase + UFCR);
865 return 0;
866 }
867
868 #define RX_BUF_SIZE (PAGE_SIZE)
869 static void imx_rx_dma_done(struct imx_port *sport)
870 {
871 unsigned long temp;
872
873 /* Enable this interrupt when the RXFIFO is empty. */
874 temp = readl(sport->port.membase + UCR1);
875 temp |= UCR1_RRDYEN;
876 writel(temp, sport->port.membase + UCR1);
877
878 sport->dma_is_rxing = 0;
879
880 /* Is the shutdown waiting for us? */
881 if (waitqueue_active(&sport->dma_wait))
882 wake_up(&sport->dma_wait);
883 }
884
885 /*
886 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
887 * [1] the RX DMA buffer is full.
888 * [2] the Aging timer expires(wait for 8 bytes long)
889 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
890 *
891 * The [2] is trigger when a character was been sitting in the FIFO
892 * meanwhile [3] can wait for 32 bytes long when the RX line is
893 * on IDLE state and RxFIFO is empty.
894 */
895 static void dma_rx_callback(void *data)
896 {
897 struct imx_port *sport = data;
898 struct dma_chan *chan = sport->dma_chan_rx;
899 struct scatterlist *sgl = &sport->rx_sgl;
900 struct tty_port *port = &sport->port.state->port;
901 struct dma_tx_state state;
902 enum dma_status status;
903 unsigned int count;
904
905 /* unmap it first */
906 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
907
908 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
909 count = RX_BUF_SIZE - state.residue;
910 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
911
912 if (count) {
913 tty_insert_flip_string(port, sport->rx_buf, count);
914 tty_flip_buffer_push(port);
915
916 start_rx_dma(sport);
917 } else
918 imx_rx_dma_done(sport);
919 }
920
921 static int start_rx_dma(struct imx_port *sport)
922 {
923 struct scatterlist *sgl = &sport->rx_sgl;
924 struct dma_chan *chan = sport->dma_chan_rx;
925 struct device *dev = sport->port.dev;
926 struct dma_async_tx_descriptor *desc;
927 int ret;
928
929 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
930 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
931 if (ret == 0) {
932 dev_err(dev, "DMA mapping error for RX.\n");
933 return -EINVAL;
934 }
935 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
936 DMA_PREP_INTERRUPT);
937 if (!desc) {
938 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
939 return -EINVAL;
940 }
941 desc->callback = dma_rx_callback;
942 desc->callback_param = sport;
943
944 dev_dbg(dev, "RX: prepare for the DMA.\n");
945 dmaengine_submit(desc);
946 dma_async_issue_pending(chan);
947 return 0;
948 }
949
950 static void imx_uart_dma_exit(struct imx_port *sport)
951 {
952 if (sport->dma_chan_rx) {
953 dma_release_channel(sport->dma_chan_rx);
954 sport->dma_chan_rx = NULL;
955
956 kfree(sport->rx_buf);
957 sport->rx_buf = NULL;
958 }
959
960 if (sport->dma_chan_tx) {
961 dma_release_channel(sport->dma_chan_tx);
962 sport->dma_chan_tx = NULL;
963 }
964
965 sport->dma_is_inited = 0;
966 }
967
968 static int imx_uart_dma_init(struct imx_port *sport)
969 {
970 struct dma_slave_config slave_config = {};
971 struct device *dev = sport->port.dev;
972 int ret;
973
974 /* Prepare for RX : */
975 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
976 if (!sport->dma_chan_rx) {
977 dev_dbg(dev, "cannot get the DMA channel.\n");
978 ret = -EINVAL;
979 goto err;
980 }
981
982 slave_config.direction = DMA_DEV_TO_MEM;
983 slave_config.src_addr = sport->port.mapbase + URXD0;
984 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
985 slave_config.src_maxburst = RXTL;
986 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
987 if (ret) {
988 dev_err(dev, "error in RX dma configuration.\n");
989 goto err;
990 }
991
992 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
993 if (!sport->rx_buf) {
994 dev_err(dev, "cannot alloc DMA buffer.\n");
995 ret = -ENOMEM;
996 goto err;
997 }
998
999 /* Prepare for TX : */
1000 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1001 if (!sport->dma_chan_tx) {
1002 dev_err(dev, "cannot get the TX DMA channel!\n");
1003 ret = -EINVAL;
1004 goto err;
1005 }
1006
1007 slave_config.direction = DMA_MEM_TO_DEV;
1008 slave_config.dst_addr = sport->port.mapbase + URTX0;
1009 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1010 slave_config.dst_maxburst = TXTL;
1011 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1012 if (ret) {
1013 dev_err(dev, "error in TX dma configuration.");
1014 goto err;
1015 }
1016
1017 sport->dma_is_inited = 1;
1018
1019 return 0;
1020 err:
1021 imx_uart_dma_exit(sport);
1022 return ret;
1023 }
1024
1025 static void imx_enable_dma(struct imx_port *sport)
1026 {
1027 unsigned long temp;
1028
1029 init_waitqueue_head(&sport->dma_wait);
1030
1031 /* set UCR1 */
1032 temp = readl(sport->port.membase + UCR1);
1033 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1034 /* wait for 32 idle frames for IDDMA interrupt */
1035 UCR1_ICD_REG(3);
1036 writel(temp, sport->port.membase + UCR1);
1037
1038 /* set UCR4 */
1039 temp = readl(sport->port.membase + UCR4);
1040 temp |= UCR4_IDDMAEN;
1041 writel(temp, sport->port.membase + UCR4);
1042
1043 sport->dma_is_enabled = 1;
1044 }
1045
1046 static void imx_disable_dma(struct imx_port *sport)
1047 {
1048 unsigned long temp;
1049
1050 /* clear UCR1 */
1051 temp = readl(sport->port.membase + UCR1);
1052 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1053 writel(temp, sport->port.membase + UCR1);
1054
1055 /* clear UCR2 */
1056 temp = readl(sport->port.membase + UCR2);
1057 temp &= ~(UCR2_CTSC | UCR2_CTS);
1058 writel(temp, sport->port.membase + UCR2);
1059
1060 /* clear UCR4 */
1061 temp = readl(sport->port.membase + UCR4);
1062 temp &= ~UCR4_IDDMAEN;
1063 writel(temp, sport->port.membase + UCR4);
1064
1065 sport->dma_is_enabled = 0;
1066 }
1067
1068 /* half the RX buffer size */
1069 #define CTSTL 16
1070
1071 static int imx_startup(struct uart_port *port)
1072 {
1073 struct imx_port *sport = (struct imx_port *)port;
1074 int retval;
1075 unsigned long flags, temp;
1076
1077 retval = clk_prepare_enable(sport->clk_per);
1078 if (retval)
1079 goto error_out1;
1080 retval = clk_prepare_enable(sport->clk_ipg);
1081 if (retval) {
1082 clk_disable_unprepare(sport->clk_per);
1083 goto error_out1;
1084 }
1085
1086 imx_setup_ufcr(sport, 0);
1087
1088 /* disable the DREN bit (Data Ready interrupt enable) before
1089 * requesting IRQs
1090 */
1091 temp = readl(sport->port.membase + UCR4);
1092
1093 if (USE_IRDA(sport))
1094 temp |= UCR4_IRSC;
1095
1096 /* set the trigger level for CTS */
1097 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1098 temp |= CTSTL << UCR4_CTSTL_SHF;
1099
1100 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1101
1102 if (USE_IRDA(sport)) {
1103 /* reset fifo's and state machines */
1104 int i = 100;
1105 temp = readl(sport->port.membase + UCR2);
1106 temp &= ~UCR2_SRST;
1107 writel(temp, sport->port.membase + UCR2);
1108 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) &&
1109 (--i > 0)) {
1110 udelay(1);
1111 }
1112 }
1113
1114 /*
1115 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1116 * chips only have one interrupt.
1117 */
1118 if (sport->txirq > 0) {
1119 retval = request_irq(sport->rxirq, imx_rxint, 0,
1120 DRIVER_NAME, sport);
1121 if (retval)
1122 goto error_out1;
1123
1124 retval = request_irq(sport->txirq, imx_txint, 0,
1125 DRIVER_NAME, sport);
1126 if (retval)
1127 goto error_out2;
1128
1129 /* do not use RTS IRQ on IrDA */
1130 if (!USE_IRDA(sport)) {
1131 retval = request_irq(sport->rtsirq, imx_rtsint, 0,
1132 DRIVER_NAME, sport);
1133 if (retval)
1134 goto error_out3;
1135 }
1136 } else {
1137 retval = request_irq(sport->port.irq, imx_int, 0,
1138 DRIVER_NAME, sport);
1139 if (retval) {
1140 free_irq(sport->port.irq, sport);
1141 goto error_out1;
1142 }
1143 }
1144
1145 spin_lock_irqsave(&sport->port.lock, flags);
1146 /*
1147 * Finally, clear and enable interrupts
1148 */
1149 writel(USR1_RTSD, sport->port.membase + USR1);
1150
1151 temp = readl(sport->port.membase + UCR1);
1152 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1153
1154 if (USE_IRDA(sport)) {
1155 temp |= UCR1_IREN;
1156 temp &= ~(UCR1_RTSDEN);
1157 }
1158
1159 writel(temp, sport->port.membase + UCR1);
1160
1161 temp = readl(sport->port.membase + UCR2);
1162 temp |= (UCR2_RXEN | UCR2_TXEN);
1163 if (!sport->have_rtscts)
1164 temp |= UCR2_IRTS;
1165 writel(temp, sport->port.membase + UCR2);
1166
1167 if (USE_IRDA(sport)) {
1168 /* clear RX-FIFO */
1169 int i = 64;
1170 while ((--i > 0) &&
1171 (readl(sport->port.membase + URXD0) & URXD_CHARRDY)) {
1172 barrier();
1173 }
1174 }
1175
1176 if (!is_imx1_uart(sport)) {
1177 temp = readl(sport->port.membase + UCR3);
1178 temp |= IMX21_UCR3_RXDMUXSEL;
1179 writel(temp, sport->port.membase + UCR3);
1180 }
1181
1182 if (USE_IRDA(sport)) {
1183 temp = readl(sport->port.membase + UCR4);
1184 if (sport->irda_inv_rx)
1185 temp |= UCR4_INVR;
1186 else
1187 temp &= ~(UCR4_INVR);
1188 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1189
1190 temp = readl(sport->port.membase + UCR3);
1191 if (sport->irda_inv_tx)
1192 temp |= UCR3_INVT;
1193 else
1194 temp &= ~(UCR3_INVT);
1195 writel(temp, sport->port.membase + UCR3);
1196 }
1197
1198 /*
1199 * Enable modem status interrupts
1200 */
1201 imx_enable_ms(&sport->port);
1202 spin_unlock_irqrestore(&sport->port.lock, flags);
1203
1204 if (USE_IRDA(sport)) {
1205 struct imxuart_platform_data *pdata;
1206 pdata = dev_get_platdata(sport->port.dev);
1207 sport->irda_inv_rx = pdata->irda_inv_rx;
1208 sport->irda_inv_tx = pdata->irda_inv_tx;
1209 sport->trcv_delay = pdata->transceiver_delay;
1210 if (pdata->irda_enable)
1211 pdata->irda_enable(1);
1212 }
1213
1214 return 0;
1215
1216 error_out3:
1217 if (sport->txirq)
1218 free_irq(sport->txirq, sport);
1219 error_out2:
1220 if (sport->rxirq)
1221 free_irq(sport->rxirq, sport);
1222 error_out1:
1223 return retval;
1224 }
1225
1226 static void imx_shutdown(struct uart_port *port)
1227 {
1228 struct imx_port *sport = (struct imx_port *)port;
1229 unsigned long temp;
1230 unsigned long flags;
1231
1232 if (sport->dma_is_enabled) {
1233 /* We have to wait for the DMA to finish. */
1234 wait_event(sport->dma_wait,
1235 !sport->dma_is_rxing && !sport->dma_is_txing);
1236 imx_stop_rx(port);
1237 imx_disable_dma(sport);
1238 imx_uart_dma_exit(sport);
1239 }
1240
1241 spin_lock_irqsave(&sport->port.lock, flags);
1242 temp = readl(sport->port.membase + UCR2);
1243 temp &= ~(UCR2_TXEN);
1244 writel(temp, sport->port.membase + UCR2);
1245 spin_unlock_irqrestore(&sport->port.lock, flags);
1246
1247 if (USE_IRDA(sport)) {
1248 struct imxuart_platform_data *pdata;
1249 pdata = dev_get_platdata(sport->port.dev);
1250 if (pdata->irda_enable)
1251 pdata->irda_enable(0);
1252 }
1253
1254 /*
1255 * Stop our timer.
1256 */
1257 del_timer_sync(&sport->timer);
1258
1259 /*
1260 * Free the interrupts
1261 */
1262 if (sport->txirq > 0) {
1263 if (!USE_IRDA(sport))
1264 free_irq(sport->rtsirq, sport);
1265 free_irq(sport->txirq, sport);
1266 free_irq(sport->rxirq, sport);
1267 } else
1268 free_irq(sport->port.irq, sport);
1269
1270 /*
1271 * Disable all interrupts, port and break condition.
1272 */
1273
1274 spin_lock_irqsave(&sport->port.lock, flags);
1275 temp = readl(sport->port.membase + UCR1);
1276 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1277 if (USE_IRDA(sport))
1278 temp &= ~(UCR1_IREN);
1279
1280 writel(temp, sport->port.membase + UCR1);
1281 spin_unlock_irqrestore(&sport->port.lock, flags);
1282
1283 clk_disable_unprepare(sport->clk_per);
1284 clk_disable_unprepare(sport->clk_ipg);
1285 }
1286
1287 static void imx_flush_buffer(struct uart_port *port)
1288 {
1289 struct imx_port *sport = (struct imx_port *)port;
1290
1291 if (sport->dma_is_enabled) {
1292 sport->tx_bytes = 0;
1293 dmaengine_terminate_all(sport->dma_chan_tx);
1294 }
1295 }
1296
1297 static void
1298 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1299 struct ktermios *old)
1300 {
1301 struct imx_port *sport = (struct imx_port *)port;
1302 unsigned long flags;
1303 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1304 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1305 unsigned int div, ufcr;
1306 unsigned long num, denom;
1307 uint64_t tdiv64;
1308
1309 /*
1310 * If we don't support modem control lines, don't allow
1311 * these to be set.
1312 */
1313 if (0) {
1314 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1315 termios->c_cflag |= CLOCAL;
1316 }
1317
1318 /*
1319 * We only support CS7 and CS8.
1320 */
1321 while ((termios->c_cflag & CSIZE) != CS7 &&
1322 (termios->c_cflag & CSIZE) != CS8) {
1323 termios->c_cflag &= ~CSIZE;
1324 termios->c_cflag |= old_csize;
1325 old_csize = CS8;
1326 }
1327
1328 if ((termios->c_cflag & CSIZE) == CS8)
1329 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1330 else
1331 ucr2 = UCR2_SRST | UCR2_IRTS;
1332
1333 if (termios->c_cflag & CRTSCTS) {
1334 if (sport->have_rtscts) {
1335 ucr2 &= ~UCR2_IRTS;
1336 ucr2 |= UCR2_CTSC;
1337
1338 /* Can we enable the DMA support? */
1339 if (is_imx6q_uart(sport) && !uart_console(port)
1340 && !sport->dma_is_inited)
1341 imx_uart_dma_init(sport);
1342 } else {
1343 termios->c_cflag &= ~CRTSCTS;
1344 }
1345 }
1346
1347 if (termios->c_cflag & CSTOPB)
1348 ucr2 |= UCR2_STPB;
1349 if (termios->c_cflag & PARENB) {
1350 ucr2 |= UCR2_PREN;
1351 if (termios->c_cflag & PARODD)
1352 ucr2 |= UCR2_PROE;
1353 }
1354
1355 del_timer_sync(&sport->timer);
1356
1357 /*
1358 * Ask the core to calculate the divisor for us.
1359 */
1360 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1361 quot = uart_get_divisor(port, baud);
1362
1363 spin_lock_irqsave(&sport->port.lock, flags);
1364
1365 sport->port.read_status_mask = 0;
1366 if (termios->c_iflag & INPCK)
1367 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1368 if (termios->c_iflag & (BRKINT | PARMRK))
1369 sport->port.read_status_mask |= URXD_BRK;
1370
1371 /*
1372 * Characters to ignore
1373 */
1374 sport->port.ignore_status_mask = 0;
1375 if (termios->c_iflag & IGNPAR)
1376 sport->port.ignore_status_mask |= URXD_PRERR;
1377 if (termios->c_iflag & IGNBRK) {
1378 sport->port.ignore_status_mask |= URXD_BRK;
1379 /*
1380 * If we're ignoring parity and break indicators,
1381 * ignore overruns too (for real raw support).
1382 */
1383 if (termios->c_iflag & IGNPAR)
1384 sport->port.ignore_status_mask |= URXD_OVRRUN;
1385 }
1386
1387 /*
1388 * Update the per-port timeout.
1389 */
1390 uart_update_timeout(port, termios->c_cflag, baud);
1391
1392 /*
1393 * disable interrupts and drain transmitter
1394 */
1395 old_ucr1 = readl(sport->port.membase + UCR1);
1396 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1397 sport->port.membase + UCR1);
1398
1399 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1400 barrier();
1401
1402 /* then, disable everything */
1403 old_txrxen = readl(sport->port.membase + UCR2);
1404 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1405 sport->port.membase + UCR2);
1406 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1407
1408 if (USE_IRDA(sport)) {
1409 /*
1410 * use maximum available submodule frequency to
1411 * avoid missing short pulses due to low sampling rate
1412 */
1413 div = 1;
1414 } else {
1415 /* custom-baudrate handling */
1416 div = sport->port.uartclk / (baud * 16);
1417 if (baud == 38400 && quot != div)
1418 baud = sport->port.uartclk / (quot * 16);
1419
1420 div = sport->port.uartclk / (baud * 16);
1421 if (div > 7)
1422 div = 7;
1423 if (!div)
1424 div = 1;
1425 }
1426
1427 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1428 1 << 16, 1 << 16, &num, &denom);
1429
1430 tdiv64 = sport->port.uartclk;
1431 tdiv64 *= num;
1432 do_div(tdiv64, denom * 16 * div);
1433 tty_termios_encode_baud_rate(termios,
1434 (speed_t)tdiv64, (speed_t)tdiv64);
1435
1436 num -= 1;
1437 denom -= 1;
1438
1439 ufcr = readl(sport->port.membase + UFCR);
1440 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1441 if (sport->dte_mode)
1442 ufcr |= UFCR_DCEDTE;
1443 writel(ufcr, sport->port.membase + UFCR);
1444
1445 writel(num, sport->port.membase + UBIR);
1446 writel(denom, sport->port.membase + UBMR);
1447
1448 if (!is_imx1_uart(sport))
1449 writel(sport->port.uartclk / div / 1000,
1450 sport->port.membase + IMX21_ONEMS);
1451
1452 writel(old_ucr1, sport->port.membase + UCR1);
1453
1454 /* set the parity, stop bits and data size */
1455 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1456
1457 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1458 imx_enable_ms(&sport->port);
1459
1460 if (sport->dma_is_inited && !sport->dma_is_enabled)
1461 imx_enable_dma(sport);
1462 spin_unlock_irqrestore(&sport->port.lock, flags);
1463 }
1464
1465 static const char *imx_type(struct uart_port *port)
1466 {
1467 struct imx_port *sport = (struct imx_port *)port;
1468
1469 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1470 }
1471
1472 /*
1473 * Release the memory region(s) being used by 'port'.
1474 */
1475 static void imx_release_port(struct uart_port *port)
1476 {
1477 struct platform_device *pdev = to_platform_device(port->dev);
1478 struct resource *mmres;
1479
1480 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1481 release_mem_region(mmres->start, resource_size(mmres));
1482 }
1483
1484 /*
1485 * Request the memory region(s) being used by 'port'.
1486 */
1487 static int imx_request_port(struct uart_port *port)
1488 {
1489 struct platform_device *pdev = to_platform_device(port->dev);
1490 struct resource *mmres;
1491 void *ret;
1492
1493 mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1494 if (!mmres)
1495 return -ENODEV;
1496
1497 ret = request_mem_region(mmres->start, resource_size(mmres), "imx-uart");
1498
1499 return ret ? 0 : -EBUSY;
1500 }
1501
1502 /*
1503 * Configure/autoconfigure the port.
1504 */
1505 static void imx_config_port(struct uart_port *port, int flags)
1506 {
1507 struct imx_port *sport = (struct imx_port *)port;
1508
1509 if (flags & UART_CONFIG_TYPE &&
1510 imx_request_port(&sport->port) == 0)
1511 sport->port.type = PORT_IMX;
1512 }
1513
1514 /*
1515 * Verify the new serial_struct (for TIOCSSERIAL).
1516 * The only change we allow are to the flags and type, and
1517 * even then only between PORT_IMX and PORT_UNKNOWN
1518 */
1519 static int
1520 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1521 {
1522 struct imx_port *sport = (struct imx_port *)port;
1523 int ret = 0;
1524
1525 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1526 ret = -EINVAL;
1527 if (sport->port.irq != ser->irq)
1528 ret = -EINVAL;
1529 if (ser->io_type != UPIO_MEM)
1530 ret = -EINVAL;
1531 if (sport->port.uartclk / 16 != ser->baud_base)
1532 ret = -EINVAL;
1533 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1534 ret = -EINVAL;
1535 if (sport->port.iobase != ser->port)
1536 ret = -EINVAL;
1537 if (ser->hub6 != 0)
1538 ret = -EINVAL;
1539 return ret;
1540 }
1541
1542 #if defined(CONFIG_CONSOLE_POLL)
1543 static int imx_poll_get_char(struct uart_port *port)
1544 {
1545 struct imx_port_ucrs old_ucr;
1546 unsigned int status;
1547 unsigned char c;
1548
1549 /* save control registers */
1550 imx_port_ucrs_save(port, &old_ucr);
1551
1552 /* disable interrupts */
1553 writel(UCR1_UARTEN, port->membase + UCR1);
1554 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1555 port->membase + UCR2);
1556 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1557 port->membase + UCR3);
1558
1559 /* poll */
1560 do {
1561 status = readl(port->membase + USR2);
1562 } while (~status & USR2_RDR);
1563
1564 /* read */
1565 c = readl(port->membase + URXD0);
1566
1567 /* restore control registers */
1568 imx_port_ucrs_restore(port, &old_ucr);
1569
1570 return c;
1571 }
1572
1573 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1574 {
1575 struct imx_port_ucrs old_ucr;
1576 unsigned int status;
1577
1578 /* save control registers */
1579 imx_port_ucrs_save(port, &old_ucr);
1580
1581 /* disable interrupts */
1582 writel(UCR1_UARTEN, port->membase + UCR1);
1583 writel(old_ucr.ucr2 & ~(UCR2_ATEN | UCR2_RTSEN | UCR2_ESCI),
1584 port->membase + UCR2);
1585 writel(old_ucr.ucr3 & ~(UCR3_DCD | UCR3_RI | UCR3_DTREN),
1586 port->membase + UCR3);
1587
1588 /* drain */
1589 do {
1590 status = readl(port->membase + USR1);
1591 } while (~status & USR1_TRDY);
1592
1593 /* write */
1594 writel(c, port->membase + URTX0);
1595
1596 /* flush */
1597 do {
1598 status = readl(port->membase + USR2);
1599 } while (~status & USR2_TXDC);
1600
1601 /* restore control registers */
1602 imx_port_ucrs_restore(port, &old_ucr);
1603 }
1604 #endif
1605
1606 static struct uart_ops imx_pops = {
1607 .tx_empty = imx_tx_empty,
1608 .set_mctrl = imx_set_mctrl,
1609 .get_mctrl = imx_get_mctrl,
1610 .stop_tx = imx_stop_tx,
1611 .start_tx = imx_start_tx,
1612 .stop_rx = imx_stop_rx,
1613 .enable_ms = imx_enable_ms,
1614 .break_ctl = imx_break_ctl,
1615 .startup = imx_startup,
1616 .shutdown = imx_shutdown,
1617 .flush_buffer = imx_flush_buffer,
1618 .set_termios = imx_set_termios,
1619 .type = imx_type,
1620 .release_port = imx_release_port,
1621 .request_port = imx_request_port,
1622 .config_port = imx_config_port,
1623 .verify_port = imx_verify_port,
1624 #if defined(CONFIG_CONSOLE_POLL)
1625 .poll_get_char = imx_poll_get_char,
1626 .poll_put_char = imx_poll_put_char,
1627 #endif
1628 };
1629
1630 static struct imx_port *imx_ports[UART_NR];
1631
1632 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1633 static void imx_console_putchar(struct uart_port *port, int ch)
1634 {
1635 struct imx_port *sport = (struct imx_port *)port;
1636
1637 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1638 barrier();
1639
1640 writel(ch, sport->port.membase + URTX0);
1641 }
1642
1643 /*
1644 * Interrupts are disabled on entering
1645 */
1646 static void
1647 imx_console_write(struct console *co, const char *s, unsigned int count)
1648 {
1649 struct imx_port *sport = imx_ports[co->index];
1650 struct imx_port_ucrs old_ucr;
1651 unsigned int ucr1;
1652 unsigned long flags = 0;
1653 int locked = 1;
1654 int retval;
1655
1656 retval = clk_enable(sport->clk_per);
1657 if (retval)
1658 return;
1659 retval = clk_enable(sport->clk_ipg);
1660 if (retval) {
1661 clk_disable(sport->clk_per);
1662 return;
1663 }
1664
1665 if (sport->port.sysrq)
1666 locked = 0;
1667 else if (oops_in_progress)
1668 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1669 else
1670 spin_lock_irqsave(&sport->port.lock, flags);
1671
1672 /*
1673 * First, save UCR1/2/3 and then disable interrupts
1674 */
1675 imx_port_ucrs_save(&sport->port, &old_ucr);
1676 ucr1 = old_ucr.ucr1;
1677
1678 if (is_imx1_uart(sport))
1679 ucr1 |= IMX1_UCR1_UARTCLKEN;
1680 ucr1 |= UCR1_UARTEN;
1681 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1682
1683 writel(ucr1, sport->port.membase + UCR1);
1684
1685 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1686
1687 uart_console_write(&sport->port, s, count, imx_console_putchar);
1688
1689 /*
1690 * Finally, wait for transmitter to become empty
1691 * and restore UCR1/2/3
1692 */
1693 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1694
1695 imx_port_ucrs_restore(&sport->port, &old_ucr);
1696
1697 if (locked)
1698 spin_unlock_irqrestore(&sport->port.lock, flags);
1699
1700 clk_disable(sport->clk_ipg);
1701 clk_disable(sport->clk_per);
1702 }
1703
1704 /*
1705 * If the port was already initialised (eg, by a boot loader),
1706 * try to determine the current setup.
1707 */
1708 static void __init
1709 imx_console_get_options(struct imx_port *sport, int *baud,
1710 int *parity, int *bits)
1711 {
1712
1713 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1714 /* ok, the port was enabled */
1715 unsigned int ucr2, ubir, ubmr, uartclk;
1716 unsigned int baud_raw;
1717 unsigned int ucfr_rfdiv;
1718
1719 ucr2 = readl(sport->port.membase + UCR2);
1720
1721 *parity = 'n';
1722 if (ucr2 & UCR2_PREN) {
1723 if (ucr2 & UCR2_PROE)
1724 *parity = 'o';
1725 else
1726 *parity = 'e';
1727 }
1728
1729 if (ucr2 & UCR2_WS)
1730 *bits = 8;
1731 else
1732 *bits = 7;
1733
1734 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1735 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1736
1737 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1738 if (ucfr_rfdiv == 6)
1739 ucfr_rfdiv = 7;
1740 else
1741 ucfr_rfdiv = 6 - ucfr_rfdiv;
1742
1743 uartclk = clk_get_rate(sport->clk_per);
1744 uartclk /= ucfr_rfdiv;
1745
1746 { /*
1747 * The next code provides exact computation of
1748 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1749 * without need of float support or long long division,
1750 * which would be required to prevent 32bit arithmetic overflow
1751 */
1752 unsigned int mul = ubir + 1;
1753 unsigned int div = 16 * (ubmr + 1);
1754 unsigned int rem = uartclk % div;
1755
1756 baud_raw = (uartclk / div) * mul;
1757 baud_raw += (rem * mul + div / 2) / div;
1758 *baud = (baud_raw + 50) / 100 * 100;
1759 }
1760
1761 if (*baud != baud_raw)
1762 pr_info("Console IMX rounded baud rate from %d to %d\n",
1763 baud_raw, *baud);
1764 }
1765 }
1766
1767 static int __init
1768 imx_console_setup(struct console *co, char *options)
1769 {
1770 struct imx_port *sport;
1771 int baud = 9600;
1772 int bits = 8;
1773 int parity = 'n';
1774 int flow = 'n';
1775 int retval;
1776
1777 /*
1778 * Check whether an invalid uart number has been specified, and
1779 * if so, search for the first available port that does have
1780 * console support.
1781 */
1782 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1783 co->index = 0;
1784 sport = imx_ports[co->index];
1785 if (sport == NULL)
1786 return -ENODEV;
1787
1788 /* For setting the registers, we only need to enable the ipg clock. */
1789 retval = clk_prepare_enable(sport->clk_ipg);
1790 if (retval)
1791 goto error_console;
1792
1793 if (options)
1794 uart_parse_options(options, &baud, &parity, &bits, &flow);
1795 else
1796 imx_console_get_options(sport, &baud, &parity, &bits);
1797
1798 imx_setup_ufcr(sport, 0);
1799
1800 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1801
1802 clk_disable(sport->clk_ipg);
1803 if (retval) {
1804 clk_unprepare(sport->clk_ipg);
1805 goto error_console;
1806 }
1807
1808 retval = clk_prepare(sport->clk_per);
1809 if (retval)
1810 clk_disable_unprepare(sport->clk_ipg);
1811
1812 error_console:
1813 return retval;
1814 }
1815
1816 static struct uart_driver imx_reg;
1817 static struct console imx_console = {
1818 .name = DEV_NAME,
1819 .write = imx_console_write,
1820 .device = uart_console_device,
1821 .setup = imx_console_setup,
1822 .flags = CON_PRINTBUFFER,
1823 .index = -1,
1824 .data = &imx_reg,
1825 };
1826
1827 #define IMX_CONSOLE &imx_console
1828 #else
1829 #define IMX_CONSOLE NULL
1830 #endif
1831
1832 static struct uart_driver imx_reg = {
1833 .owner = THIS_MODULE,
1834 .driver_name = DRIVER_NAME,
1835 .dev_name = DEV_NAME,
1836 .major = SERIAL_IMX_MAJOR,
1837 .minor = MINOR_START,
1838 .nr = ARRAY_SIZE(imx_ports),
1839 .cons = IMX_CONSOLE,
1840 };
1841
1842 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1843 {
1844 struct imx_port *sport = platform_get_drvdata(dev);
1845 unsigned int val;
1846
1847 /* enable wakeup from i.MX UART */
1848 val = readl(sport->port.membase + UCR3);
1849 val |= UCR3_AWAKEN;
1850 writel(val, sport->port.membase + UCR3);
1851
1852 uart_suspend_port(&imx_reg, &sport->port);
1853
1854 return 0;
1855 }
1856
1857 static int serial_imx_resume(struct platform_device *dev)
1858 {
1859 struct imx_port *sport = platform_get_drvdata(dev);
1860 unsigned int val;
1861
1862 /* disable wakeup from i.MX UART */
1863 val = readl(sport->port.membase + UCR3);
1864 val &= ~UCR3_AWAKEN;
1865 writel(val, sport->port.membase + UCR3);
1866
1867 uart_resume_port(&imx_reg, &sport->port);
1868
1869 return 0;
1870 }
1871
1872 #ifdef CONFIG_OF
1873 /*
1874 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1875 * could successfully get all information from dt or a negative errno.
1876 */
1877 static int serial_imx_probe_dt(struct imx_port *sport,
1878 struct platform_device *pdev)
1879 {
1880 struct device_node *np = pdev->dev.of_node;
1881 const struct of_device_id *of_id =
1882 of_match_device(imx_uart_dt_ids, &pdev->dev);
1883 int ret;
1884
1885 if (!np)
1886 /* no device tree device */
1887 return 1;
1888
1889 ret = of_alias_get_id(np, "serial");
1890 if (ret < 0) {
1891 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1892 return ret;
1893 }
1894 sport->port.line = ret;
1895
1896 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1897 sport->have_rtscts = 1;
1898
1899 if (of_get_property(np, "fsl,irda-mode", NULL))
1900 sport->use_irda = 1;
1901
1902 if (of_get_property(np, "fsl,dte-mode", NULL))
1903 sport->dte_mode = 1;
1904
1905 sport->devdata = of_id->data;
1906
1907 return 0;
1908 }
1909 #else
1910 static inline int serial_imx_probe_dt(struct imx_port *sport,
1911 struct platform_device *pdev)
1912 {
1913 return 1;
1914 }
1915 #endif
1916
1917 static void serial_imx_probe_pdata(struct imx_port *sport,
1918 struct platform_device *pdev)
1919 {
1920 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1921
1922 sport->port.line = pdev->id;
1923 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1924
1925 if (!pdata)
1926 return;
1927
1928 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1929 sport->have_rtscts = 1;
1930
1931 if (pdata->flags & IMXUART_IRDA)
1932 sport->use_irda = 1;
1933 }
1934
1935 static int serial_imx_probe(struct platform_device *pdev)
1936 {
1937 struct imx_port *sport;
1938 struct imxuart_platform_data *pdata;
1939 void __iomem *base;
1940 int ret = 0;
1941 struct resource *res;
1942
1943 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1944 if (!sport)
1945 return -ENOMEM;
1946
1947 ret = serial_imx_probe_dt(sport, pdev);
1948 if (ret > 0)
1949 serial_imx_probe_pdata(sport, pdev);
1950 else if (ret < 0)
1951 return ret;
1952
1953 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1954 if (!res)
1955 return -ENODEV;
1956
1957 base = devm_ioremap(&pdev->dev, res->start, PAGE_SIZE);
1958 if (!base)
1959 return -ENOMEM;
1960
1961 sport->port.dev = &pdev->dev;
1962 sport->port.mapbase = res->start;
1963 sport->port.membase = base;
1964 sport->port.type = PORT_IMX,
1965 sport->port.iotype = UPIO_MEM;
1966 sport->port.irq = platform_get_irq(pdev, 0);
1967 sport->rxirq = platform_get_irq(pdev, 0);
1968 sport->txirq = platform_get_irq(pdev, 1);
1969 sport->rtsirq = platform_get_irq(pdev, 2);
1970 sport->port.fifosize = 32;
1971 sport->port.ops = &imx_pops;
1972 sport->port.flags = UPF_BOOT_AUTOCONF;
1973 init_timer(&sport->timer);
1974 sport->timer.function = imx_timeout;
1975 sport->timer.data = (unsigned long)sport;
1976
1977 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1978 if (IS_ERR(sport->clk_ipg)) {
1979 ret = PTR_ERR(sport->clk_ipg);
1980 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1981 return ret;
1982 }
1983
1984 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1985 if (IS_ERR(sport->clk_per)) {
1986 ret = PTR_ERR(sport->clk_per);
1987 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1988 return ret;
1989 }
1990
1991 sport->port.uartclk = clk_get_rate(sport->clk_per);
1992
1993 imx_ports[sport->port.line] = sport;
1994
1995 pdata = dev_get_platdata(&pdev->dev);
1996 if (pdata && pdata->init) {
1997 ret = pdata->init(pdev);
1998 if (ret)
1999 return ret;
2000 }
2001
2002 ret = uart_add_one_port(&imx_reg, &sport->port);
2003 if (ret)
2004 goto deinit;
2005 platform_set_drvdata(pdev, sport);
2006
2007 return 0;
2008 deinit:
2009 if (pdata && pdata->exit)
2010 pdata->exit(pdev);
2011 return ret;
2012 }
2013
2014 static int serial_imx_remove(struct platform_device *pdev)
2015 {
2016 struct imxuart_platform_data *pdata;
2017 struct imx_port *sport = platform_get_drvdata(pdev);
2018
2019 pdata = dev_get_platdata(&pdev->dev);
2020
2021 uart_remove_one_port(&imx_reg, &sport->port);
2022
2023 if (pdata && pdata->exit)
2024 pdata->exit(pdev);
2025
2026 return 0;
2027 }
2028
2029 static struct platform_driver serial_imx_driver = {
2030 .probe = serial_imx_probe,
2031 .remove = serial_imx_remove,
2032
2033 .suspend = serial_imx_suspend,
2034 .resume = serial_imx_resume,
2035 .id_table = imx_uart_devtype,
2036 .driver = {
2037 .name = "imx-uart",
2038 .owner = THIS_MODULE,
2039 .of_match_table = imx_uart_dt_ids,
2040 },
2041 };
2042
2043 static int __init imx_serial_init(void)
2044 {
2045 int ret;
2046
2047 pr_info("Serial: IMX driver\n");
2048
2049 ret = uart_register_driver(&imx_reg);
2050 if (ret)
2051 return ret;
2052
2053 ret = platform_driver_register(&serial_imx_driver);
2054 if (ret != 0)
2055 uart_unregister_driver(&imx_reg);
2056
2057 return ret;
2058 }
2059
2060 static void __exit imx_serial_exit(void)
2061 {
2062 platform_driver_unregister(&serial_imx_driver);
2063 uart_unregister_driver(&imx_reg);
2064 }
2065
2066 module_init(imx_serial_init);
2067 module_exit(imx_serial_exit);
2068
2069 MODULE_AUTHOR("Sascha Hauer");
2070 MODULE_DESCRIPTION("IMX generic serial port driver");
2071 MODULE_LICENSE("GPL");
2072 MODULE_ALIAS("platform:imx-uart");
Linux with added FPC-III support