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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / usb / host / ohci-hcd.c
blob3586460fb2a10afb38489401ab01a23bff2f262a
1 /*
2 * Open Host Controller Interface (OHCI) driver for USB.
3 *
4 * Maintainer: Alan Stern <stern@rowland.harvard.edu>
5 *
6 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
7 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
8 *
9 * [ Initialisation is based on Linus' ]
10 * [ uhci code and gregs ohci fragments ]
11 * [ (C) Copyright 1999 Linus Torvalds ]
12 * [ (C) Copyright 1999 Gregory P. Smith]
13 *
14 *
15 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
16 * interfaces (though some non-x86 Intel chips use it). It supports
17 * smarter hardware than UHCI. A download link for the spec available
18 * through the http://www.usb.org website.
19 *
20 * This file is licenced under the GPL.
21 */
22
23 #include <linux/module.h>
24 #include <linux/moduleparam.h>
25 #include <linux/pci.h>
26 #include <linux/kernel.h>
27 #include <linux/delay.h>
28 #include <linux/ioport.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/errno.h>
32 #include <linux/init.h>
33 #include <linux/timer.h>
34 #include <linux/list.h>
35 #include <linux/usb.h>
36 #include <linux/usb/otg.h>
37 #include <linux/usb/hcd.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/dmapool.h>
40 #include <linux/workqueue.h>
41 #include <linux/debugfs.h>
42
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/unaligned.h>
46 #include <asm/byteorder.h>
47
48
49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 /* For initializing controller (mask in an HCFS mode too) */
55 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
56 #define OHCI_INTR_INIT \
57 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
58 | OHCI_INTR_RD | OHCI_INTR_WDH)
59
60 #ifdef __hppa__
61 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
62 #define IR_DISABLE
63 #endif
64
65 #ifdef CONFIG_ARCH_OMAP
66 /* OMAP doesn't support IR (no SMM; not needed) */
67 #define IR_DISABLE
68 #endif
69
70 /*-------------------------------------------------------------------------*/
71
72 static const char hcd_name [] = "ohci_hcd";
73
74 #define STATECHANGE_DELAY msecs_to_jiffies(300)
75
76 #include "ohci.h"
77 #include "pci-quirks.h"
78
79 static void ohci_dump (struct ohci_hcd *ohci, int verbose);
80 static void ohci_stop (struct usb_hcd *hcd);
81
82 #include "ohci-hub.c"
83 #include "ohci-dbg.c"
84 #include "ohci-mem.c"
85 #include "ohci-q.c"
86
87
88 /*
89 * On architectures with edge-triggered interrupts we must never return
90 * IRQ_NONE.
91 */
92 #if defined(CONFIG_SA1111) /* ... or other edge-triggered systems */
93 #define IRQ_NOTMINE IRQ_HANDLED
94 #else
95 #define IRQ_NOTMINE IRQ_NONE
96 #endif
97
98
99 /* Some boards misreport power switching/overcurrent */
100 static bool distrust_firmware = 1;
101 module_param (distrust_firmware, bool, 0);
102 MODULE_PARM_DESC (distrust_firmware,
103 "true to distrust firmware power/overcurrent setup");
104
105 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
106 static bool no_handshake = 0;
107 module_param (no_handshake, bool, 0);
108 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
109
110 /*-------------------------------------------------------------------------*/
111
112 /*
113 * queue up an urb for anything except the root hub
114 */
115 static int ohci_urb_enqueue (
116 struct usb_hcd *hcd,
117 struct urb *urb,
118 gfp_t mem_flags
119 ) {
120 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
121 struct ed *ed;
122 urb_priv_t *urb_priv;
123 unsigned int pipe = urb->pipe;
124 int i, size = 0;
125 unsigned long flags;
126 int retval = 0;
127
128 /* every endpoint has a ed, locate and maybe (re)initialize it */
129 if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
130 return -ENOMEM;
131
132 /* for the private part of the URB we need the number of TDs (size) */
133 switch (ed->type) {
134 case PIPE_CONTROL:
135 /* td_submit_urb() doesn't yet handle these */
136 if (urb->transfer_buffer_length > 4096)
137 return -EMSGSIZE;
138
139 /* 1 TD for setup, 1 for ACK, plus ... */
140 size = 2;
141 /* FALLTHROUGH */
142 // case PIPE_INTERRUPT:
143 // case PIPE_BULK:
144 default:
145 /* one TD for every 4096 Bytes (can be up to 8K) */
146 size += urb->transfer_buffer_length / 4096;
147 /* ... and for any remaining bytes ... */
148 if ((urb->transfer_buffer_length % 4096) != 0)
149 size++;
150 /* ... and maybe a zero length packet to wrap it up */
151 if (size == 0)
152 size++;
153 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
154 && (urb->transfer_buffer_length
155 % usb_maxpacket (urb->dev, pipe,
156 usb_pipeout (pipe))) == 0)
157 size++;
158 break;
159 case PIPE_ISOCHRONOUS: /* number of packets from URB */
160 size = urb->number_of_packets;
161 break;
162 }
163
164 /* allocate the private part of the URB */
165 urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
166 mem_flags);
167 if (!urb_priv)
168 return -ENOMEM;
169 INIT_LIST_HEAD (&urb_priv->pending);
170 urb_priv->length = size;
171 urb_priv->ed = ed;
172
173 /* allocate the TDs (deferring hash chain updates) */
174 for (i = 0; i < size; i++) {
175 urb_priv->td [i] = td_alloc (ohci, mem_flags);
176 if (!urb_priv->td [i]) {
177 urb_priv->length = i;
178 urb_free_priv (ohci, urb_priv);
179 return -ENOMEM;
180 }
181 }
182
183 spin_lock_irqsave (&ohci->lock, flags);
184
185 /* don't submit to a dead HC */
186 if (!HCD_HW_ACCESSIBLE(hcd)) {
187 retval = -ENODEV;
188 goto fail;
189 }
190 if (ohci->rh_state != OHCI_RH_RUNNING) {
191 retval = -ENODEV;
192 goto fail;
193 }
194 retval = usb_hcd_link_urb_to_ep(hcd, urb);
195 if (retval)
196 goto fail;
197
198 /* schedule the ed if needed */
199 if (ed->state == ED_IDLE) {
200 retval = ed_schedule (ohci, ed);
201 if (retval < 0) {
202 usb_hcd_unlink_urb_from_ep(hcd, urb);
203 goto fail;
204 }
205 if (ed->type == PIPE_ISOCHRONOUS) {
206 u16 frame = ohci_frame_no(ohci);
207
208 /* delay a few frames before the first TD */
209 frame += max_t (u16, 8, ed->interval);
210 frame &= ~(ed->interval - 1);
211 frame |= ed->branch;
212 urb->start_frame = frame;
213 ed->last_iso = frame + ed->interval * (size - 1);
214 }
215 } else if (ed->type == PIPE_ISOCHRONOUS) {
216 u16 next = ohci_frame_no(ohci) + 1;
217 u16 frame = ed->last_iso + ed->interval;
218 u16 length = ed->interval * (size - 1);
219
220 /* Behind the scheduling threshold? */
221 if (unlikely(tick_before(frame, next))) {
222
223 /* URB_ISO_ASAP: Round up to the first available slot */
224 if (urb->transfer_flags & URB_ISO_ASAP) {
225 frame += (next - frame + ed->interval - 1) &
226 -ed->interval;
227
228 /*
229 * Not ASAP: Use the next slot in the stream,
230 * no matter what.
231 */
232 } else {
233 /*
234 * Some OHCI hardware doesn't handle late TDs
235 * correctly. After retiring them it proceeds
236 * to the next ED instead of the next TD.
237 * Therefore we have to omit the late TDs
238 * entirely.
239 */
240 urb_priv->td_cnt = DIV_ROUND_UP(
241 (u16) (next - frame),
242 ed->interval);
243 if (urb_priv->td_cnt >= urb_priv->length) {
244 ++urb_priv->td_cnt; /* Mark it */
245 ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
246 urb, frame, length,
247 next);
248 }
249 }
250 }
251 urb->start_frame = frame;
252 ed->last_iso = frame + length;
253 }
254
255 /* fill the TDs and link them to the ed; and
256 * enable that part of the schedule, if needed
257 * and update count of queued periodic urbs
258 */
259 urb->hcpriv = urb_priv;
260 td_submit_urb (ohci, urb);
261
262 fail:
263 if (retval)
264 urb_free_priv (ohci, urb_priv);
265 spin_unlock_irqrestore (&ohci->lock, flags);
266 return retval;
267 }
268
269 /*
270 * decouple the URB from the HC queues (TDs, urb_priv).
271 * reporting is always done
272 * asynchronously, and we might be dealing with an urb that's
273 * partially transferred, or an ED with other urbs being unlinked.
274 */
275 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
276 {
277 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
278 unsigned long flags;
279 int rc;
280
281 spin_lock_irqsave (&ohci->lock, flags);
282 rc = usb_hcd_check_unlink_urb(hcd, urb, status);
283 if (rc) {
284 ; /* Do nothing */
285 } else if (ohci->rh_state == OHCI_RH_RUNNING) {
286 urb_priv_t *urb_priv;
287
288 /* Unless an IRQ completed the unlink while it was being
289 * handed to us, flag it for unlink and giveback, and force
290 * some upcoming INTR_SF to call finish_unlinks()
291 */
292 urb_priv = urb->hcpriv;
293 if (urb_priv) {
294 if (urb_priv->ed->state == ED_OPER)
295 start_ed_unlink (ohci, urb_priv->ed);
296 }
297 } else {
298 /*
299 * with HC dead, we won't respect hc queue pointers
300 * any more ... just clean up every urb's memory.
301 */
302 if (urb->hcpriv)
303 finish_urb(ohci, urb, status);
304 }
305 spin_unlock_irqrestore (&ohci->lock, flags);
306 return rc;
307 }
308
309 /*-------------------------------------------------------------------------*/
310
311 /* frees config/altsetting state for endpoints,
312 * including ED memory, dummy TD, and bulk/intr data toggle
313 */
314
315 static void
316 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
317 {
318 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
319 unsigned long flags;
320 struct ed *ed = ep->hcpriv;
321 unsigned limit = 1000;
322
323 /* ASSERT: any requests/urbs are being unlinked */
324 /* ASSERT: nobody can be submitting urbs for this any more */
325
326 if (!ed)
327 return;
328
329 rescan:
330 spin_lock_irqsave (&ohci->lock, flags);
331
332 if (ohci->rh_state != OHCI_RH_RUNNING) {
333 sanitize:
334 ed->state = ED_IDLE;
335 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
336 ohci->eds_scheduled--;
337 finish_unlinks (ohci, 0);
338 }
339
340 switch (ed->state) {
341 case ED_UNLINK: /* wait for hw to finish? */
342 /* major IRQ delivery trouble loses INTR_SF too... */
343 if (limit-- == 0) {
344 ohci_warn(ohci, "ED unlink timeout\n");
345 if (quirk_zfmicro(ohci)) {
346 ohci_warn(ohci, "Attempting ZF TD recovery\n");
347 ohci->ed_to_check = ed;
348 ohci->zf_delay = 2;
349 }
350 goto sanitize;
351 }
352 spin_unlock_irqrestore (&ohci->lock, flags);
353 schedule_timeout_uninterruptible(1);
354 goto rescan;
355 case ED_IDLE: /* fully unlinked */
356 if (list_empty (&ed->td_list)) {
357 td_free (ohci, ed->dummy);
358 ed_free (ohci, ed);
359 break;
360 }
361 /* else FALL THROUGH */
362 default:
363 /* caller was supposed to have unlinked any requests;
364 * that's not our job. can't recover; must leak ed.
365 */
366 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
367 ed, ep->desc.bEndpointAddress, ed->state,
368 list_empty (&ed->td_list) ? "" : " (has tds)");
369 td_free (ohci, ed->dummy);
370 break;
371 }
372 ep->hcpriv = NULL;
373 spin_unlock_irqrestore (&ohci->lock, flags);
374 }
375
376 static int ohci_get_frame (struct usb_hcd *hcd)
377 {
378 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
379
380 return ohci_frame_no(ohci);
381 }
382
383 static void ohci_usb_reset (struct ohci_hcd *ohci)
384 {
385 ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
386 ohci->hc_control &= OHCI_CTRL_RWC;
387 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
388 ohci->rh_state = OHCI_RH_HALTED;
389 }
390
391 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
392 * other cases where the next software may expect clean state from the
393 * "firmware". this is bus-neutral, unlike shutdown() methods.
394 */
395 static void
396 ohci_shutdown (struct usb_hcd *hcd)
397 {
398 struct ohci_hcd *ohci;
399
400 ohci = hcd_to_ohci (hcd);
401 ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
402
403 /* Software reset, after which the controller goes into SUSPEND */
404 ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
405 ohci_readl(ohci, &ohci->regs->cmdstatus); /* flush the writes */
406 udelay(10);
407
408 ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
409 }
410
411 static int check_ed(struct ohci_hcd *ohci, struct ed *ed)
412 {
413 return (hc32_to_cpu(ohci, ed->hwINFO) & ED_IN) != 0
414 && (hc32_to_cpu(ohci, ed->hwHeadP) & TD_MASK)
415 == (hc32_to_cpu(ohci, ed->hwTailP) & TD_MASK)
416 && !list_empty(&ed->td_list);
417 }
418
419 /* ZF Micro watchdog timer callback. The ZF Micro chipset sometimes completes
420 * an interrupt TD but neglects to add it to the donelist. On systems with
421 * this chipset, we need to periodically check the state of the queues to look
422 * for such "lost" TDs.
423 */
424 static void unlink_watchdog_func(unsigned long _ohci)
425 {
426 unsigned long flags;
427 unsigned max;
428 unsigned seen_count = 0;
429 unsigned i;
430 struct ed **seen = NULL;
431 struct ohci_hcd *ohci = (struct ohci_hcd *) _ohci;
432
433 spin_lock_irqsave(&ohci->lock, flags);
434 max = ohci->eds_scheduled;
435 if (!max)
436 goto done;
437
438 if (ohci->ed_to_check)
439 goto out;
440
441 seen = kcalloc(max, sizeof *seen, GFP_ATOMIC);
442 if (!seen)
443 goto out;
444
445 for (i = 0; i < NUM_INTS; i++) {
446 struct ed *ed = ohci->periodic[i];
447
448 while (ed) {
449 unsigned temp;
450
451 /* scan this branch of the periodic schedule tree */
452 for (temp = 0; temp < seen_count; temp++) {
453 if (seen[temp] == ed) {
454 /* we've checked it and what's after */
455 ed = NULL;
456 break;
457 }
458 }
459 if (!ed)
460 break;
461 seen[seen_count++] = ed;
462 if (!check_ed(ohci, ed)) {
463 ed = ed->ed_next;
464 continue;
465 }
466
467 /* HC's TD list is empty, but HCD sees at least one
468 * TD that's not been sent through the donelist.
469 */
470 ohci->ed_to_check = ed;
471 ohci->zf_delay = 2;
472
473 /* The HC may wait until the next frame to report the
474 * TD as done through the donelist and INTR_WDH. (We
475 * just *assume* it's not a multi-TD interrupt URB;
476 * those could defer the IRQ more than one frame, using
477 * DI...) Check again after the next INTR_SF.
478 */
479 ohci_writel(ohci, OHCI_INTR_SF,
480 &ohci->regs->intrstatus);
481 ohci_writel(ohci, OHCI_INTR_SF,
482 &ohci->regs->intrenable);
483
484 /* flush those writes */
485 (void) ohci_readl(ohci, &ohci->regs->control);
486
487 goto out;
488 }
489 }
490 out:
491 kfree(seen);
492 if (ohci->eds_scheduled)
493 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
494 done:
495 spin_unlock_irqrestore(&ohci->lock, flags);
496 }
497
498 /*-------------------------------------------------------------------------*
499 * HC functions
500 *-------------------------------------------------------------------------*/
501
502 /* init memory, and kick BIOS/SMM off */
503
504 static int ohci_init (struct ohci_hcd *ohci)
505 {
506 int ret;
507 struct usb_hcd *hcd = ohci_to_hcd(ohci);
508
509 if (distrust_firmware)
510 ohci->flags |= OHCI_QUIRK_HUB_POWER;
511
512 ohci->rh_state = OHCI_RH_HALTED;
513 ohci->regs = hcd->regs;
514
515 /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
516 * was never needed for most non-PCI systems ... remove the code?
517 */
518
519 #ifndef IR_DISABLE
520 /* SMM owns the HC? not for long! */
521 if (!no_handshake && ohci_readl (ohci,
522 &ohci->regs->control) & OHCI_CTRL_IR) {
523 u32 temp;
524
525 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
526
527 /* this timeout is arbitrary. we make it long, so systems
528 * depending on usb keyboards may be usable even if the
529 * BIOS/SMM code seems pretty broken.
530 */
531 temp = 500; /* arbitrary: five seconds */
532
533 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
534 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
535 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
536 msleep (10);
537 if (--temp == 0) {
538 ohci_err (ohci, "USB HC takeover failed!"
539 " (BIOS/SMM bug)\n");
540 return -EBUSY;
541 }
542 }
543 ohci_usb_reset (ohci);
544 }
545 #endif
546
547 /* Disable HC interrupts */
548 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
549
550 /* flush the writes, and save key bits like RWC */
551 if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
552 ohci->hc_control |= OHCI_CTRL_RWC;
553
554 /* Read the number of ports unless overridden */
555 if (ohci->num_ports == 0)
556 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
557
558 if (ohci->hcca)
559 return 0;
560
561 ohci->hcca = dma_alloc_coherent (hcd->self.controller,
562 sizeof *ohci->hcca, &ohci->hcca_dma, 0);
563 if (!ohci->hcca)
564 return -ENOMEM;
565
566 if ((ret = ohci_mem_init (ohci)) < 0)
567 ohci_stop (hcd);
568 else {
569 create_debug_files (ohci);
570 }
571
572 return ret;
573 }
574
575 /*-------------------------------------------------------------------------*/
576
577 /* Start an OHCI controller, set the BUS operational
578 * resets USB and controller
579 * enable interrupts
580 */
581 static int ohci_run (struct ohci_hcd *ohci)
582 {
583 u32 mask, val;
584 int first = ohci->fminterval == 0;
585 struct usb_hcd *hcd = ohci_to_hcd(ohci);
586
587 ohci->rh_state = OHCI_RH_HALTED;
588
589 /* boot firmware should have set this up (5.1.1.3.1) */
590 if (first) {
591
592 val = ohci_readl (ohci, &ohci->regs->fminterval);
593 ohci->fminterval = val & 0x3fff;
594 if (ohci->fminterval != FI)
595 ohci_dbg (ohci, "fminterval delta %d\n",
596 ohci->fminterval - FI);
597 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
598 /* also: power/overcurrent flags in roothub.a */
599 }
600
601 /* Reset USB nearly "by the book". RemoteWakeupConnected has
602 * to be checked in case boot firmware (BIOS/SMM/...) has set up
603 * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
604 * If the bus glue detected wakeup capability then it should
605 * already be enabled; if so we'll just enable it again.
606 */
607 if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
608 device_set_wakeup_capable(hcd->self.controller, 1);
609
610 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
611 case OHCI_USB_OPER:
612 val = 0;
613 break;
614 case OHCI_USB_SUSPEND:
615 case OHCI_USB_RESUME:
616 ohci->hc_control &= OHCI_CTRL_RWC;
617 ohci->hc_control |= OHCI_USB_RESUME;
618 val = 10 /* msec wait */;
619 break;
620 // case OHCI_USB_RESET:
621 default:
622 ohci->hc_control &= OHCI_CTRL_RWC;
623 ohci->hc_control |= OHCI_USB_RESET;
624 val = 50 /* msec wait */;
625 break;
626 }
627 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
628 // flush the writes
629 (void) ohci_readl (ohci, &ohci->regs->control);
630 msleep(val);
631
632 memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
633
634 /* 2msec timelimit here means no irqs/preempt */
635 spin_lock_irq (&ohci->lock);
636
637 retry:
638 /* HC Reset requires max 10 us delay */
639 ohci_writel (ohci, OHCI_HCR, &ohci->regs->cmdstatus);
640 val = 30; /* ... allow extra time */
641 while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
642 if (--val == 0) {
643 spin_unlock_irq (&ohci->lock);
644 ohci_err (ohci, "USB HC reset timed out!\n");
645 return -1;
646 }
647 udelay (1);
648 }
649
650 /* now we're in the SUSPEND state ... must go OPERATIONAL
651 * within 2msec else HC enters RESUME
652 *
653 * ... but some hardware won't init fmInterval "by the book"
654 * (SiS, OPTi ...), so reset again instead. SiS doesn't need
655 * this if we write fmInterval after we're OPERATIONAL.
656 * Unclear about ALi, ServerWorks, and others ... this could
657 * easily be a longstanding bug in chip init on Linux.
658 */
659 if (ohci->flags & OHCI_QUIRK_INITRESET) {
660 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
661 // flush those writes
662 (void) ohci_readl (ohci, &ohci->regs->control);
663 }
664
665 /* Tell the controller where the control and bulk lists are
666 * The lists are empty now. */
667 ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
668 ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
669
670 /* a reset clears this */
671 ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
672
673 periodic_reinit (ohci);
674
675 /* some OHCI implementations are finicky about how they init.
676 * bogus values here mean not even enumeration could work.
677 */
678 if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
679 || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
680 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
681 ohci->flags |= OHCI_QUIRK_INITRESET;
682 ohci_dbg (ohci, "enabling initreset quirk\n");
683 goto retry;
684 }
685 spin_unlock_irq (&ohci->lock);
686 ohci_err (ohci, "init err (%08x %04x)\n",
687 ohci_readl (ohci, &ohci->regs->fminterval),
688 ohci_readl (ohci, &ohci->regs->periodicstart));
689 return -EOVERFLOW;
690 }
691
692 /* use rhsc irqs after khubd is fully initialized */
693 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
694 hcd->uses_new_polling = 1;
695
696 /* start controller operations */
697 ohci->hc_control &= OHCI_CTRL_RWC;
698 ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
699 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
700 ohci->rh_state = OHCI_RH_RUNNING;
701
702 /* wake on ConnectStatusChange, matching external hubs */
703 ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
704
705 /* Choose the interrupts we care about now, others later on demand */
706 mask = OHCI_INTR_INIT;
707 ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
708 ohci_writel (ohci, mask, &ohci->regs->intrenable);
709
710 /* handle root hub init quirks ... */
711 val = roothub_a (ohci);
712 val &= ~(RH_A_PSM | RH_A_OCPM);
713 if (ohci->flags & OHCI_QUIRK_SUPERIO) {
714 /* NSC 87560 and maybe others */
715 val |= RH_A_NOCP;
716 val &= ~(RH_A_POTPGT | RH_A_NPS);
717 ohci_writel (ohci, val, &ohci->regs->roothub.a);
718 } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
719 (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
720 /* hub power always on; required for AMD-756 and some
721 * Mac platforms. ganged overcurrent reporting, if any.
722 */
723 val |= RH_A_NPS;
724 ohci_writel (ohci, val, &ohci->regs->roothub.a);
725 }
726 ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
727 ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
728 &ohci->regs->roothub.b);
729 // flush those writes
730 (void) ohci_readl (ohci, &ohci->regs->control);
731
732 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
733 spin_unlock_irq (&ohci->lock);
734
735 // POTPGT delay is bits 24-31, in 2 ms units.
736 mdelay ((val >> 23) & 0x1fe);
737
738 if (quirk_zfmicro(ohci)) {
739 /* Create timer to watch for bad queue state on ZF Micro */
740 setup_timer(&ohci->unlink_watchdog, unlink_watchdog_func,
741 (unsigned long) ohci);
742
743 ohci->eds_scheduled = 0;
744 ohci->ed_to_check = NULL;
745 }
746
747 ohci_dump (ohci, 1);
748
749 return 0;
750 }
751
752 /* ohci_setup routine for generic controller initialization */
753
754 int ohci_setup(struct usb_hcd *hcd)
755 {
756 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
757
758 ohci_hcd_init(ohci);
759
760 return ohci_init(ohci);
761 }
762 EXPORT_SYMBOL_GPL(ohci_setup);
763
764 /* ohci_start routine for generic controller start of all OHCI bus glue */
765 static int ohci_start(struct usb_hcd *hcd)
766 {
767 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
768 int ret;
769
770 ret = ohci_run(ohci);
771 if (ret < 0) {
772 ohci_err(ohci, "can't start\n");
773 ohci_stop(hcd);
774 }
775 return ret;
776 }
777
778 /*-------------------------------------------------------------------------*/
779
780 /* an interrupt happens */
781
782 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
783 {
784 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
785 struct ohci_regs __iomem *regs = ohci->regs;
786 int ints;
787
788 /* Read interrupt status (and flush pending writes). We ignore the
789 * optimization of checking the LSB of hcca->done_head; it doesn't
790 * work on all systems (edge triggering for OHCI can be a factor).
791 */
792 ints = ohci_readl(ohci, &regs->intrstatus);
793
794 /* Check for an all 1's result which is a typical consequence
795 * of dead, unclocked, or unplugged (CardBus...) devices
796 */
797 if (ints == ~(u32)0) {
798 ohci->rh_state = OHCI_RH_HALTED;
799 ohci_dbg (ohci, "device removed!\n");
800 usb_hc_died(hcd);
801 return IRQ_HANDLED;
802 }
803
804 /* We only care about interrupts that are enabled */
805 ints &= ohci_readl(ohci, &regs->intrenable);
806
807 /* interrupt for some other device? */
808 if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
809 return IRQ_NOTMINE;
810
811 if (ints & OHCI_INTR_UE) {
812 // e.g. due to PCI Master/Target Abort
813 if (quirk_nec(ohci)) {
814 /* Workaround for a silicon bug in some NEC chips used
815 * in Apple's PowerBooks. Adapted from Darwin code.
816 */
817 ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
818
819 ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
820
821 schedule_work (&ohci->nec_work);
822 } else {
823 ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
824 ohci->rh_state = OHCI_RH_HALTED;
825 usb_hc_died(hcd);
826 }
827
828 ohci_dump (ohci, 1);
829 ohci_usb_reset (ohci);
830 }
831
832 if (ints & OHCI_INTR_RHSC) {
833 ohci_dbg(ohci, "rhsc\n");
834 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
835 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
836 &regs->intrstatus);
837
838 /* NOTE: Vendors didn't always make the same implementation
839 * choices for RHSC. Many followed the spec; RHSC triggers
840 * on an edge, like setting and maybe clearing a port status
841 * change bit. With others it's level-triggered, active
842 * until khubd clears all the port status change bits. We'll
843 * always disable it here and rely on polling until khubd
844 * re-enables it.
845 */
846 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
847 usb_hcd_poll_rh_status(hcd);
848 }
849
850 /* For connect and disconnect events, we expect the controller
851 * to turn on RHSC along with RD. But for remote wakeup events
852 * this might not happen.
853 */
854 else if (ints & OHCI_INTR_RD) {
855 ohci_dbg(ohci, "resume detect\n");
856 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
857 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
858 if (ohci->autostop) {
859 spin_lock (&ohci->lock);
860 ohci_rh_resume (ohci);
861 spin_unlock (&ohci->lock);
862 } else
863 usb_hcd_resume_root_hub(hcd);
864 }
865
866 if (ints & OHCI_INTR_WDH) {
867 spin_lock (&ohci->lock);
868 dl_done_list (ohci);
869 spin_unlock (&ohci->lock);
870 }
871
872 if (quirk_zfmicro(ohci) && (ints & OHCI_INTR_SF)) {
873 spin_lock(&ohci->lock);
874 if (ohci->ed_to_check) {
875 struct ed *ed = ohci->ed_to_check;
876
877 if (check_ed(ohci, ed)) {
878 /* HC thinks the TD list is empty; HCD knows
879 * at least one TD is outstanding
880 */
881 if (--ohci->zf_delay == 0) {
882 struct td *td = list_entry(
883 ed->td_list.next,
884 struct td, td_list);
885 ohci_warn(ohci,
886 "Reclaiming orphan TD %p\n",
887 td);
888 takeback_td(ohci, td);
889 ohci->ed_to_check = NULL;
890 }
891 } else
892 ohci->ed_to_check = NULL;
893 }
894 spin_unlock(&ohci->lock);
895 }
896
897 /* could track INTR_SO to reduce available PCI/... bandwidth */
898
899 /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
900 * when there's still unlinking to be done (next frame).
901 */
902 spin_lock (&ohci->lock);
903 if (ohci->ed_rm_list)
904 finish_unlinks (ohci, ohci_frame_no(ohci));
905 if ((ints & OHCI_INTR_SF) != 0
906 && !ohci->ed_rm_list
907 && !ohci->ed_to_check
908 && ohci->rh_state == OHCI_RH_RUNNING)
909 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
910 spin_unlock (&ohci->lock);
911
912 if (ohci->rh_state == OHCI_RH_RUNNING) {
913 ohci_writel (ohci, ints, &regs->intrstatus);
914 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
915 // flush those writes
916 (void) ohci_readl (ohci, &ohci->regs->control);
917 }
918
919 return IRQ_HANDLED;
920 }
921
922 /*-------------------------------------------------------------------------*/
923
924 static void ohci_stop (struct usb_hcd *hcd)
925 {
926 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
927
928 ohci_dump (ohci, 1);
929
930 if (quirk_nec(ohci))
931 flush_work(&ohci->nec_work);
932
933 ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
934 ohci_usb_reset(ohci);
935 free_irq(hcd->irq, hcd);
936 hcd->irq = 0;
937
938 if (quirk_zfmicro(ohci))
939 del_timer(&ohci->unlink_watchdog);
940 if (quirk_amdiso(ohci))
941 usb_amd_dev_put();
942
943 remove_debug_files (ohci);
944 ohci_mem_cleanup (ohci);
945 if (ohci->hcca) {
946 dma_free_coherent (hcd->self.controller,
947 sizeof *ohci->hcca,
948 ohci->hcca, ohci->hcca_dma);
949 ohci->hcca = NULL;
950 ohci->hcca_dma = 0;
951 }
952 }
953
954 /*-------------------------------------------------------------------------*/
955
956 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
957
958 /* must not be called from interrupt context */
959 int ohci_restart(struct ohci_hcd *ohci)
960 {
961 int temp;
962 int i;
963 struct urb_priv *priv;
964
965 ohci_init(ohci);
966 spin_lock_irq(&ohci->lock);
967 ohci->rh_state = OHCI_RH_HALTED;
968
969 /* Recycle any "live" eds/tds (and urbs). */
970 if (!list_empty (&ohci->pending))
971 ohci_dbg(ohci, "abort schedule...\n");
972 list_for_each_entry (priv, &ohci->pending, pending) {
973 struct urb *urb = priv->td[0]->urb;
974 struct ed *ed = priv->ed;
975
976 switch (ed->state) {
977 case ED_OPER:
978 ed->state = ED_UNLINK;
979 ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
980 ed_deschedule (ohci, ed);
981
982 ed->ed_next = ohci->ed_rm_list;
983 ed->ed_prev = NULL;
984 ohci->ed_rm_list = ed;
985 /* FALLTHROUGH */
986 case ED_UNLINK:
987 break;
988 default:
989 ohci_dbg(ohci, "bogus ed %p state %d\n",
990 ed, ed->state);
991 }
992
993 if (!urb->unlinked)
994 urb->unlinked = -ESHUTDOWN;
995 }
996 finish_unlinks (ohci, 0);
997 spin_unlock_irq(&ohci->lock);
998
999 /* paranoia, in case that didn't work: */
1000
1001 /* empty the interrupt branches */
1002 for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
1003 for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
1004
1005 /* no EDs to remove */
1006 ohci->ed_rm_list = NULL;
1007
1008 /* empty control and bulk lists */
1009 ohci->ed_controltail = NULL;
1010 ohci->ed_bulktail = NULL;
1011
1012 if ((temp = ohci_run (ohci)) < 0) {
1013 ohci_err (ohci, "can't restart, %d\n", temp);
1014 return temp;
1015 }
1016 ohci_dbg(ohci, "restart complete\n");
1017 return 0;
1018 }
1019 EXPORT_SYMBOL_GPL(ohci_restart);
1020
1021 #endif
1022
1023 #ifdef CONFIG_PM
1024
1025 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
1026 {
1027 struct ohci_hcd *ohci = hcd_to_ohci (hcd);
1028 unsigned long flags;
1029 int rc = 0;
1030
1031 /* Disable irq emission and mark HW unaccessible. Use
1032 * the spinlock to properly synchronize with possible pending
1033 * RH suspend or resume activity.
1034 */
1035 spin_lock_irqsave (&ohci->lock, flags);
1036 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
1037 (void)ohci_readl(ohci, &ohci->regs->intrdisable);
1038
1039 clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1040 spin_unlock_irqrestore (&ohci->lock, flags);
1041
1042 synchronize_irq(hcd->irq);
1043
1044 if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
1045 ohci_resume(hcd, false);
1046 rc = -EBUSY;
1047 }
1048 return rc;
1049 }
1050 EXPORT_SYMBOL_GPL(ohci_suspend);
1051
1052
1053 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
1054 {
1055 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
1056 int port;
1057 bool need_reinit = false;
1058
1059 set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
1060
1061 /* Make sure resume from hibernation re-enumerates everything */
1062 if (hibernated)
1063 ohci_usb_reset(ohci);
1064
1065 /* See if the controller is already running or has been reset */
1066 ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
1067 if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
1068 need_reinit = true;
1069 } else {
1070 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
1071 case OHCI_USB_OPER:
1072 case OHCI_USB_RESET:
1073 need_reinit = true;
1074 }
1075 }
1076
1077 /* If needed, reinitialize and suspend the root hub */
1078 if (need_reinit) {
1079 spin_lock_irq(&ohci->lock);
1080 ohci_rh_resume(ohci);
1081 ohci_rh_suspend(ohci, 0);
1082 spin_unlock_irq(&ohci->lock);
1083 }
1084
1085 /* Normally just turn on port power and enable interrupts */
1086 else {
1087 ohci_dbg(ohci, "powerup ports\n");
1088 for (port = 0; port < ohci->num_ports; port++)
1089 ohci_writel(ohci, RH_PS_PPS,
1090 &ohci->regs->roothub.portstatus[port]);
1091
1092 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
1093 ohci_readl(ohci, &ohci->regs->intrenable);
1094 msleep(20);
1095 }
1096
1097 usb_hcd_resume_root_hub(hcd);
1098
1099 return 0;
1100 }
1101 EXPORT_SYMBOL_GPL(ohci_resume);
1102
1103 #endif
1104
1105 /*-------------------------------------------------------------------------*/
1106
1107 /*
1108 * Generic structure: This gets copied for platform drivers so that
1109 * individual entries can be overridden as needed.
1110 */
1111
1112 static const struct hc_driver ohci_hc_driver = {
1113 .description = hcd_name,
1114 .product_desc = "OHCI Host Controller",
1115 .hcd_priv_size = sizeof(struct ohci_hcd),
1116
1117 /*
1118 * generic hardware linkage
1119 */
1120 .irq = ohci_irq,
1121 .flags = HCD_MEMORY | HCD_USB11,
1122
1123 /*
1124 * basic lifecycle operations
1125 */
1126 .reset = ohci_setup,
1127 .start = ohci_start,
1128 .stop = ohci_stop,
1129 .shutdown = ohci_shutdown,
1130
1131 /*
1132 * managing i/o requests and associated device resources
1133 */
1134 .urb_enqueue = ohci_urb_enqueue,
1135 .urb_dequeue = ohci_urb_dequeue,
1136 .endpoint_disable = ohci_endpoint_disable,
1137
1138 /*
1139 * scheduling support
1140 */
1141 .get_frame_number = ohci_get_frame,
1142
1143 /*
1144 * root hub support
1145 */
1146 .hub_status_data = ohci_hub_status_data,
1147 .hub_control = ohci_hub_control,
1148 #ifdef CONFIG_PM
1149 .bus_suspend = ohci_bus_suspend,
1150 .bus_resume = ohci_bus_resume,
1151 #endif
1152 .start_port_reset = ohci_start_port_reset,
1153 };
1154
1155 void ohci_init_driver(struct hc_driver *drv,
1156 const struct ohci_driver_overrides *over)
1157 {
1158 /* Copy the generic table to drv and then apply the overrides */
1159 *drv = ohci_hc_driver;
1160
1161 if (over) {
1162 drv->product_desc = over->product_desc;
1163 drv->hcd_priv_size += over->extra_priv_size;
1164 if (over->reset)
1165 drv->reset = over->reset;
1166 }
1167 }
1168 EXPORT_SYMBOL_GPL(ohci_init_driver);
1169
1170 /*-------------------------------------------------------------------------*/
1171
1172 MODULE_AUTHOR (DRIVER_AUTHOR);
1173 MODULE_DESCRIPTION(DRIVER_DESC);
1174 MODULE_LICENSE ("GPL");
1175
1176 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1177 #include "ohci-sa1111.c"
1178 #define SA1111_DRIVER ohci_hcd_sa1111_driver
1179 #endif
1180
1181 #ifdef CONFIG_ARCH_DAVINCI_DA8XX
1182 #include "ohci-da8xx.c"
1183 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1184 #endif
1185
1186 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1187 #include "ohci-ppc-of.c"
1188 #define OF_PLATFORM_DRIVER ohci_hcd_ppc_of_driver
1189 #endif
1190
1191 #ifdef CONFIG_PPC_PS3
1192 #include "ohci-ps3.c"
1193 #define PS3_SYSTEM_BUS_DRIVER ps3_ohci_driver
1194 #endif
1195
1196 #ifdef CONFIG_MFD_SM501
1197 #include "ohci-sm501.c"
1198 #define SM501_OHCI_DRIVER ohci_hcd_sm501_driver
1199 #endif
1200
1201 #ifdef CONFIG_MFD_TC6393XB
1202 #include "ohci-tmio.c"
1203 #define TMIO_OHCI_DRIVER ohci_hcd_tmio_driver
1204 #endif
1205
1206 #ifdef CONFIG_MACH_JZ4740
1207 #include "ohci-jz4740.c"
1208 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1209 #endif
1210
1211 #ifdef CONFIG_USB_OCTEON_OHCI
1212 #include "ohci-octeon.c"
1213 #define PLATFORM_DRIVER ohci_octeon_driver
1214 #endif
1215
1216 #ifdef CONFIG_TILE_USB
1217 #include "ohci-tilegx.c"
1218 #define PLATFORM_DRIVER ohci_hcd_tilegx_driver
1219 #endif
1220
1221 static int __init ohci_hcd_mod_init(void)
1222 {
1223 int retval = 0;
1224
1225 if (usb_disabled())
1226 return -ENODEV;
1227
1228 printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1229 pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1230 sizeof (struct ed), sizeof (struct td));
1231 set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1232
1233 ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1234 if (!ohci_debug_root) {
1235 retval = -ENOENT;
1236 goto error_debug;
1237 }
1238
1239 #ifdef PS3_SYSTEM_BUS_DRIVER
1240 retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1241 if (retval < 0)
1242 goto error_ps3;
1243 #endif
1244
1245 #ifdef PLATFORM_DRIVER
1246 retval = platform_driver_register(&PLATFORM_DRIVER);
1247 if (retval < 0)
1248 goto error_platform;
1249 #endif
1250
1251 #ifdef OF_PLATFORM_DRIVER
1252 retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1253 if (retval < 0)
1254 goto error_of_platform;
1255 #endif
1256
1257 #ifdef SA1111_DRIVER
1258 retval = sa1111_driver_register(&SA1111_DRIVER);
1259 if (retval < 0)
1260 goto error_sa1111;
1261 #endif
1262
1263 #ifdef SM501_OHCI_DRIVER
1264 retval = platform_driver_register(&SM501_OHCI_DRIVER);
1265 if (retval < 0)
1266 goto error_sm501;
1267 #endif
1268
1269 #ifdef TMIO_OHCI_DRIVER
1270 retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1271 if (retval < 0)
1272 goto error_tmio;
1273 #endif
1274
1275 #ifdef DAVINCI_PLATFORM_DRIVER
1276 retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1277 if (retval < 0)
1278 goto error_davinci;
1279 #endif
1280
1281 return retval;
1282
1283 /* Error path */
1284 #ifdef DAVINCI_PLATFORM_DRIVER
1285 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1286 error_davinci:
1287 #endif
1288 #ifdef TMIO_OHCI_DRIVER
1289 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1290 error_tmio:
1291 #endif
1292 #ifdef SM501_OHCI_DRIVER
1293 platform_driver_unregister(&SM501_OHCI_DRIVER);
1294 error_sm501:
1295 #endif
1296 #ifdef SA1111_DRIVER
1297 sa1111_driver_unregister(&SA1111_DRIVER);
1298 error_sa1111:
1299 #endif
1300 #ifdef OF_PLATFORM_DRIVER
1301 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1302 error_of_platform:
1303 #endif
1304 #ifdef PLATFORM_DRIVER
1305 platform_driver_unregister(&PLATFORM_DRIVER);
1306 error_platform:
1307 #endif
1308 #ifdef PS3_SYSTEM_BUS_DRIVER
1309 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1310 error_ps3:
1311 #endif
1312 debugfs_remove(ohci_debug_root);
1313 ohci_debug_root = NULL;
1314 error_debug:
1315
1316 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1317 return retval;
1318 }
1319 module_init(ohci_hcd_mod_init);
1320
1321 static void __exit ohci_hcd_mod_exit(void)
1322 {
1323 #ifdef DAVINCI_PLATFORM_DRIVER
1324 platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1325 #endif
1326 #ifdef TMIO_OHCI_DRIVER
1327 platform_driver_unregister(&TMIO_OHCI_DRIVER);
1328 #endif
1329 #ifdef SM501_OHCI_DRIVER
1330 platform_driver_unregister(&SM501_OHCI_DRIVER);
1331 #endif
1332 #ifdef SA1111_DRIVER
1333 sa1111_driver_unregister(&SA1111_DRIVER);
1334 #endif
1335 #ifdef OF_PLATFORM_DRIVER
1336 platform_driver_unregister(&OF_PLATFORM_DRIVER);
1337 #endif
1338 #ifdef PLATFORM_DRIVER
1339 platform_driver_unregister(&PLATFORM_DRIVER);
1340 #endif
1341 #ifdef PS3_SYSTEM_BUS_DRIVER
1342 ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1343 #endif
1344 debugfs_remove(ohci_debug_root);
1345 clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1346 }
1347 module_exit(ohci_hcd_mod_exit);
1348
Linux with added FPC-III support