drivers/usb/musb/am35x.c

   1 /*
   2  * Texas Instruments AM35x "glue layer"
   3  *
   4  * Copyright (c) 2010, by Texas Instruments
   5  *
   6  * Based on the DA8xx "glue layer" code.
   7  * Copyright (c) 2008-2009, MontaVista Software, Inc. <source@mvista.com>
   8  *
   9  * This file is part of the Inventra Controller Driver for Linux.
  10  *
  11  * The Inventra Controller Driver for Linux is free software; you
  12  * can redistribute it and/or modify it under the terms of the GNU
  13  * General Public License version 2 as published by the Free Software
  14  * Foundation.
  15  *
  16  * The Inventra Controller Driver for Linux is distributed in
  17  * the hope that it will be useful, but WITHOUT ANY WARRANTY;
  18  * without even the implied warranty of MERCHANTABILITY or
  19  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  20  * License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with The Inventra Controller Driver for Linux ; if not,
  24  * write to the Free Software Foundation, Inc., 59 Temple Place,
  25  * Suite 330, Boston, MA  02111-1307  USA
  26  *
  27  */
  28
  29 #include <linux/module.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/usb/usb_phy_gen_xceiv.h>
  36 #include <linux/platform_data/usb-omap.h>
  37
  38 #include "musb_core.h"
  39
  40 /*
  41  * AM35x specific definitions
  42  */
  43 /* USB 2.0 OTG module registers */
  44 #define USB_REVISION_REG        0x00
  45 #define USB_CTRL_REG            0x04
  46 #define USB_STAT_REG            0x08
  47 #define USB_EMULATION_REG       0x0c
  48 /* 0x10 Reserved */
  49 #define USB_AUTOREQ_REG         0x14
  50 #define USB_SRP_FIX_TIME_REG    0x18
  51 #define USB_TEARDOWN_REG        0x1c
  52 #define EP_INTR_SRC_REG         0x20
  53 #define EP_INTR_SRC_SET_REG     0x24
  54 #define EP_INTR_SRC_CLEAR_REG   0x28
  55 #define EP_INTR_MASK_REG        0x2c
  56 #define EP_INTR_MASK_SET_REG    0x30
  57 #define EP_INTR_MASK_CLEAR_REG  0x34
  58 #define EP_INTR_SRC_MASKED_REG  0x38
  59 #define CORE_INTR_SRC_REG       0x40
  60 #define CORE_INTR_SRC_SET_REG   0x44
  61 #define CORE_INTR_SRC_CLEAR_REG 0x48
  62 #define CORE_INTR_MASK_REG      0x4c
  63 #define CORE_INTR_MASK_SET_REG  0x50
  64 #define CORE_INTR_MASK_CLEAR_REG 0x54
  65 #define CORE_INTR_SRC_MASKED_REG 0x58
  66 /* 0x5c Reserved */
  67 #define USB_END_OF_INTR_REG     0x60
  68
  69 /* Control register bits */
  70 #define AM35X_SOFT_RESET_MASK   1
  71
  72 /* USB interrupt register bits */
  73 #define AM35X_INTR_USB_SHIFT    16
  74 #define AM35X_INTR_USB_MASK     (0x1ff << AM35X_INTR_USB_SHIFT)
  75 #define AM35X_INTR_DRVVBUS      0x100
  76 #define AM35X_INTR_RX_SHIFT     16
  77 #define AM35X_INTR_TX_SHIFT     0
  78 #define AM35X_TX_EP_MASK        0xffff          /* EP0 + 15 Tx EPs */
  79 #define AM35X_RX_EP_MASK        0xfffe          /* 15 Rx EPs */
  80 #define AM35X_TX_INTR_MASK      (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
  81 #define AM35X_RX_INTR_MASK      (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
  82
  83 #define USB_MENTOR_CORE_OFFSET  0x400
  84
  85 struct am35x_glue {
  86         struct device           *dev;
  87         struct platform_device  *musb;
  88         struct clk              *phy_clk;
  89         struct clk              *clk;
  90 };
  91
  92 /*
  93  * am35x_musb_enable - enable interrupts
  94  */
  95 static void am35x_musb_enable(struct musb *musb)
  96 {
  97         void __iomem *reg_base = musb->ctrl_base;
  98         u32 epmask;
  99
 100         /* Workaround: setup IRQs through both register sets. */
 101         epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
 102                ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
 103
 104         musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
 105         musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
 106
 107         /* Force the DRVVBUS IRQ so we can start polling for ID change. */
 108         musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
 109                         AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
 110 }
 111
 112 /*
 113  * am35x_musb_disable - disable HDRC and flush interrupts
 114  */
 115 static void am35x_musb_disable(struct musb *musb)
 116 {
 117         void __iomem *reg_base = musb->ctrl_base;
 118
 119         musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
 120         musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
 121                          AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
 122         musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
 123         musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 124 }
 125
 126 #define portstate(stmt)         stmt
 127
 128 static void am35x_musb_set_vbus(struct musb *musb, int is_on)
 129 {
 130         WARN_ON(is_on && is_peripheral_active(musb));
 131 }
 132
 133 #define POLL_SECONDS    2
 134
 135 static struct timer_list otg_workaround;
 136
 137 static void otg_timer(unsigned long _musb)
 138 {
 139         struct musb             *musb = (void *)_musb;
 140         void __iomem            *mregs = musb->mregs;
 141         u8                      devctl;
 142         unsigned long           flags;
 143
 144         /*
 145          * We poll because AM35x's won't expose several OTG-critical
 146          * status change events (from the transceiver) otherwise.
 147          */
 148         devctl = musb_readb(mregs, MUSB_DEVCTL);
 149         dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
 150                 usb_otg_state_string(musb->xceiv->state));
 151
 152         spin_lock_irqsave(&musb->lock, flags);
 153         switch (musb->xceiv->state) {
 154         case OTG_STATE_A_WAIT_BCON:
 155                 devctl &= ~MUSB_DEVCTL_SESSION;
 156                 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
 157
 158                 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
 159                 if (devctl & MUSB_DEVCTL_BDEVICE) {
 160                         musb->xceiv->state = OTG_STATE_B_IDLE;
 161                         MUSB_DEV_MODE(musb);
 162                 } else {
 163                         musb->xceiv->state = OTG_STATE_A_IDLE;
 164                         MUSB_HST_MODE(musb);
 165                 }
 166                 break;
 167         case OTG_STATE_A_WAIT_VFALL:
 168                 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 169                 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
 170                             MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
 171                 break;
 172         case OTG_STATE_B_IDLE:
 173                 devctl = musb_readb(mregs, MUSB_DEVCTL);
 174                 if (devctl & MUSB_DEVCTL_BDEVICE)
 175                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 176                 else
 177                         musb->xceiv->state = OTG_STATE_A_IDLE;
 178                 break;
 179         default:
 180                 break;
 181         }
 182         spin_unlock_irqrestore(&musb->lock, flags);
 183 }
 184
 185 static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
 186 {
 187         static unsigned long last_timer;
 188
 189         if (timeout == 0)
 190                 timeout = jiffies + msecs_to_jiffies(3);
 191
 192         /* Never idle if active, or when VBUS timeout is not set as host */
 193         if (musb->is_active || (musb->a_wait_bcon == 0 &&
 194                                 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
 195                 dev_dbg(musb->controller, "%s active, deleting timer\n",
 196                         usb_otg_state_string(musb->xceiv->state));
 197                 del_timer(&otg_workaround);
 198                 last_timer = jiffies;
 199                 return;
 200         }
 201
 202         if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
 203                 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
 204                 return;
 205         }
 206         last_timer = timeout;
 207
 208         dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
 209                 usb_otg_state_string(musb->xceiv->state),
 210                 jiffies_to_msecs(timeout - jiffies));
 211         mod_timer(&otg_workaround, timeout);
 212 }
 213
 214 static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
 215 {
 216         struct musb  *musb = hci;
 217         void __iomem *reg_base = musb->ctrl_base;
 218         struct device *dev = musb->controller;
 219         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 220         struct omap_musb_board_data *data = plat->board_data;
 221         struct usb_otg *otg = musb->xceiv->otg;
 222         unsigned long flags;
 223         irqreturn_t ret = IRQ_NONE;
 224         u32 epintr, usbintr;
 225
 226         spin_lock_irqsave(&musb->lock, flags);
 227
 228         /* Get endpoint interrupts */
 229         epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
 230
 231         if (epintr) {
 232                 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
 233
 234                 musb->int_rx =
 235                         (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
 236                 musb->int_tx =
 237                         (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
 238         }
 239
 240         /* Get usb core interrupts */
 241         usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
 242         if (!usbintr && !epintr)
 243                 goto eoi;
 244
 245         if (usbintr) {
 246                 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
 247
 248                 musb->int_usb =
 249                         (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
 250         }
 251         /*
 252          * DRVVBUS IRQs are the only proxy we have (a very poor one!) for
 253          * AM35x's missing ID change IRQ.  We need an ID change IRQ to
 254          * switch appropriately between halves of the OTG state machine.
 255          * Managing DEVCTL.SESSION per Mentor docs requires that we know its
 256          * value but DEVCTL.BDEVICE is invalid without DEVCTL.SESSION set.
 257          * Also, DRVVBUS pulses for SRP (but not at 5V) ...
 258          */
 259         if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
 260                 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
 261                 void __iomem *mregs = musb->mregs;
 262                 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
 263                 int err;
 264
 265                 err = musb->int_usb & MUSB_INTR_VBUSERROR;
 266                 if (err) {
 267                         /*
 268                          * The Mentor core doesn't debounce VBUS as needed
 269                          * to cope with device connect current spikes. This
 270                          * means it's not uncommon for bus-powered devices
 271                          * to get VBUS errors during enumeration.
 272                          *
 273                          * This is a workaround, but newer RTL from Mentor
 274                          * seems to allow a better one: "re"-starting sessions
 275                          * without waiting for VBUS to stop registering in
 276                          * devctl.
 277                          */
 278                         musb->int_usb &= ~MUSB_INTR_VBUSERROR;
 279                         musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
 280                         mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 281                         WARNING("VBUS error workaround (delay coming)\n");
 282                 } else if (drvvbus) {
 283                         MUSB_HST_MODE(musb);
 284                         otg->default_a = 1;
 285                         musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
 286                         portstate(musb->port1_status |= USB_PORT_STAT_POWER);
 287                         del_timer(&otg_workaround);
 288                 } else {
 289                         musb->is_active = 0;
 290                         MUSB_DEV_MODE(musb);
 291                         otg->default_a = 0;
 292                         musb->xceiv->state = OTG_STATE_B_IDLE;
 293                         portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
 294                 }
 295
 296                 /* NOTE: this must complete power-on within 100 ms. */
 297                 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
 298                                 drvvbus ? "on" : "off",
 299                                 usb_otg_state_string(musb->xceiv->state),
 300                                 err ? " ERROR" : "",
 301                                 devctl);
 302                 ret = IRQ_HANDLED;
 303         }
 304
 305         /* Drop spurious RX and TX if device is disconnected */
 306         if (musb->int_usb & MUSB_INTR_DISCONNECT) {
 307                 musb->int_tx = 0;
 308                 musb->int_rx = 0;
 309         }
 310
 311         if (musb->int_tx || musb->int_rx || musb->int_usb)
 312                 ret |= musb_interrupt(musb);
 313
 314 eoi:
 315         /* EOI needs to be written for the IRQ to be re-asserted. */
 316         if (ret == IRQ_HANDLED || epintr || usbintr) {
 317                 /* clear level interrupt */
 318                 if (data->clear_irq)
 319                         data->clear_irq();
 320                 /* write EOI */
 321                 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
 322         }
 323
 324         /* Poll for ID change */
 325         if (musb->xceiv->state == OTG_STATE_B_IDLE)
 326                 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
 327
 328         spin_unlock_irqrestore(&musb->lock, flags);
 329
 330         return ret;
 331 }
 332
 333 static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
 334 {
 335         struct device *dev = musb->controller;
 336         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 337         struct omap_musb_board_data *data = plat->board_data;
 338         int     retval = 0;
 339
 340         if (data->set_mode)
 341                 data->set_mode(musb_mode);
 342         else
 343                 retval = -EIO;
 344
 345         return retval;
 346 }
 347
 348 static int am35x_musb_init(struct musb *musb)
 349 {
 350         struct device *dev = musb->controller;
 351         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 352         struct omap_musb_board_data *data = plat->board_data;
 353         void __iomem *reg_base = musb->ctrl_base;
 354         u32 rev;
 355
 356         musb->mregs += USB_MENTOR_CORE_OFFSET;
 357
 358         /* Returns zero if e.g. not clocked */
 359         rev = musb_readl(reg_base, USB_REVISION_REG);
 360         if (!rev)
 361                 return -ENODEV;
 362
 363         usb_nop_xceiv_register();
 364         musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
 365         if (IS_ERR_OR_NULL(musb->xceiv))
 366                 return -EPROBE_DEFER;
 367
 368         setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
 369
 370         /* Reset the musb */
 371         if (data->reset)
 372                 data->reset();
 373
 374         /* Reset the controller */
 375         musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
 376
 377         /* Start the on-chip PHY and its PLL. */
 378         if (data->set_phy_power)
 379                 data->set_phy_power(1);
 380
 381         msleep(5);
 382
 383         musb->isr = am35x_musb_interrupt;
 384
 385         /* clear level interrupt */
 386         if (data->clear_irq)
 387                 data->clear_irq();
 388
 389         return 0;
 390 }
 391
 392 static int am35x_musb_exit(struct musb *musb)
 393 {
 394         struct device *dev = musb->controller;
 395         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 396         struct omap_musb_board_data *data = plat->board_data;
 397
 398         del_timer_sync(&otg_workaround);
 399
 400         /* Shutdown the on-chip PHY and its PLL. */
 401         if (data->set_phy_power)
 402                 data->set_phy_power(0);
 403
 404         usb_put_phy(musb->xceiv);
 405         usb_nop_xceiv_unregister();
 406
 407         return 0;
 408 }
 409
 410 /* AM35x supports only 32bit read operation */
 411 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
 412 {
 413         void __iomem *fifo = hw_ep->fifo;
 414         u32             val;
 415         int             i;
 416
 417         /* Read for 32bit-aligned destination address */
 418         if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
 419                 readsl(fifo, dst, len >> 2);
 420                 dst += len & ~0x03;
 421                 len &= 0x03;
 422         }
 423         /*
 424          * Now read the remaining 1 to 3 byte or complete length if
 425          * unaligned address.
 426          */
 427         if (len > 4) {
 428                 for (i = 0; i < (len >> 2); i++) {
 429                         *(u32 *) dst = musb_readl(fifo, 0);
 430                         dst += 4;
 431                 }
 432                 len &= 0x03;
 433         }
 434         if (len > 0) {
 435                 val = musb_readl(fifo, 0);
 436                 memcpy(dst, &val, len);
 437         }
 438 }
 439
 440 static const struct musb_platform_ops am35x_ops = {
 441         .init           = am35x_musb_init,
 442         .exit           = am35x_musb_exit,
 443
 444         .enable         = am35x_musb_enable,
 445         .disable        = am35x_musb_disable,
 446
 447         .set_mode       = am35x_musb_set_mode,
 448         .try_idle       = am35x_musb_try_idle,
 449
 450         .set_vbus       = am35x_musb_set_vbus,
 451 };
 452
 453 static const struct platform_device_info am35x_dev_info = {
 454         .name           = "musb-hdrc",
 455         .id             = PLATFORM_DEVID_AUTO,
 456         .dma_mask       = DMA_BIT_MASK(32),
 457 };
 458
 459 static int am35x_probe(struct platform_device *pdev)
 460 {
 461         struct musb_hdrc_platform_data  *pdata = dev_get_platdata(&pdev->dev);
 462         struct platform_device          *musb;
 463         struct am35x_glue               *glue;
 464         struct platform_device_info     pinfo;
 465         struct clk                      *phy_clk;
 466         struct clk                      *clk;
 467
 468         int                             ret = -ENOMEM;
 469
 470         glue = kzalloc(sizeof(*glue), GFP_KERNEL);
 471         if (!glue) {
 472                 dev_err(&pdev->dev, "failed to allocate glue context\n");
 473                 goto err0;
 474         }
 475
 476         phy_clk = clk_get(&pdev->dev, "fck");
 477         if (IS_ERR(phy_clk)) {
 478                 dev_err(&pdev->dev, "failed to get PHY clock\n");
 479                 ret = PTR_ERR(phy_clk);
 480                 goto err3;
 481         }
 482
 483         clk = clk_get(&pdev->dev, "ick");
 484         if (IS_ERR(clk)) {
 485                 dev_err(&pdev->dev, "failed to get clock\n");
 486                 ret = PTR_ERR(clk);
 487                 goto err4;
 488         }
 489
 490         ret = clk_enable(phy_clk);
 491         if (ret) {
 492                 dev_err(&pdev->dev, "failed to enable PHY clock\n");
 493                 goto err5;
 494         }
 495
 496         ret = clk_enable(clk);
 497         if (ret) {
 498                 dev_err(&pdev->dev, "failed to enable clock\n");
 499                 goto err6;
 500         }
 501
 502         glue->dev                       = &pdev->dev;
 503         glue->phy_clk                   = phy_clk;
 504         glue->clk                       = clk;
 505
 506         pdata->platform_ops             = &am35x_ops;
 507
 508         platform_set_drvdata(pdev, glue);
 509
 510         pinfo = am35x_dev_info;
 511         pinfo.parent = &pdev->dev;
 512         pinfo.res = pdev->resource;
 513         pinfo.num_res = pdev->num_resources;
 514         pinfo.data = pdata;
 515         pinfo.size_data = sizeof(*pdata);
 516
 517         glue->musb = musb = platform_device_register_full(&pinfo);
 518         if (IS_ERR(musb)) {
 519                 ret = PTR_ERR(musb);
 520                 dev_err(&pdev->dev, "failed to register musb device: %d\n", ret);
 521                 goto err7;
 522         }
 523
 524         return 0;
 525
 526 err7:
 527         clk_disable(clk);
 528
 529 err6:
 530         clk_disable(phy_clk);
 531
 532 err5:
 533         clk_put(clk);
 534
 535 err4:
 536         clk_put(phy_clk);
 537
 538 err3:
 539         kfree(glue);
 540
 541 err0:
 542         return ret;
 543 }
 544
 545 static int am35x_remove(struct platform_device *pdev)
 546 {
 547         struct am35x_glue       *glue = platform_get_drvdata(pdev);
 548
 549         platform_device_unregister(glue->musb);
 550         clk_disable(glue->clk);
 551         clk_disable(glue->phy_clk);
 552         clk_put(glue->clk);
 553         clk_put(glue->phy_clk);
 554         kfree(glue);
 555
 556         return 0;
 557 }
 558
 559 #ifdef CONFIG_PM
 560 static int am35x_suspend(struct device *dev)
 561 {
 562         struct am35x_glue       *glue = dev_get_drvdata(dev);
 563         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 564         struct omap_musb_board_data *data = plat->board_data;
 565
 566         /* Shutdown the on-chip PHY and its PLL. */
 567         if (data->set_phy_power)
 568                 data->set_phy_power(0);
 569
 570         clk_disable(glue->phy_clk);
 571         clk_disable(glue->clk);
 572
 573         return 0;
 574 }
 575
 576 static int am35x_resume(struct device *dev)
 577 {
 578         struct am35x_glue       *glue = dev_get_drvdata(dev);
 579         struct musb_hdrc_platform_data *plat = dev_get_platdata(dev);
 580         struct omap_musb_board_data *data = plat->board_data;
 581         int                     ret;
 582
 583         /* Start the on-chip PHY and its PLL. */
 584         if (data->set_phy_power)
 585                 data->set_phy_power(1);
 586
 587         ret = clk_enable(glue->phy_clk);
 588         if (ret) {
 589                 dev_err(dev, "failed to enable PHY clock\n");
 590                 return ret;
 591         }
 592
 593         ret = clk_enable(glue->clk);
 594         if (ret) {
 595                 dev_err(dev, "failed to enable clock\n");
 596                 return ret;
 597         }
 598
 599         return 0;
 600 }
 601 #endif
 602
 603 static SIMPLE_DEV_PM_OPS(am35x_pm_ops, am35x_suspend, am35x_resume);
 604
 605 static struct platform_driver am35x_driver = {
 606         .probe          = am35x_probe,
 607         .remove         = am35x_remove,
 608         .driver         = {
 609                 .name   = "musb-am35x",
 610                 .pm     = &am35x_pm_ops,
 611         },
 612 };
 613
 614 MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
 615 MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
 616 MODULE_LICENSE("GPL v2");
 617 module_platform_driver(am35x_driver);