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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / usb / musb / musb_host.c
blobed455724017b5767f6ad849961946d7ad7af3228
1 /*
2 * MUSB OTG driver host support
3 *
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
7 * Copyright (C) 2008-2009 MontaVista Software, Inc. <source@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
21 * 02110-1301 USA
22 *
23 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
24 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
25 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
26 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
29 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
30 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 *
34 */
35
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/delay.h>
39 #include <linux/sched.h>
40 #include <linux/slab.h>
41 #include <linux/errno.h>
42 #include <linux/list.h>
43 #include <linux/dma-mapping.h>
44
45 #include "musb_core.h"
46 #include "musb_host.h"
47
48 /* MUSB HOST status 22-mar-2006
49 *
50 * - There's still lots of partial code duplication for fault paths, so
51 * they aren't handled as consistently as they need to be.
52 *
53 * - PIO mostly behaved when last tested.
54 * + including ep0, with all usbtest cases 9, 10
55 * + usbtest 14 (ep0out) doesn't seem to run at all
56 * + double buffered OUT/TX endpoints saw stalls(!) with certain usbtest
57 * configurations, but otherwise double buffering passes basic tests.
58 * + for 2.6.N, for N > ~10, needs API changes for hcd framework.
59 *
60 * - DMA (CPPI) ... partially behaves, not currently recommended
61 * + about 1/15 the speed of typical EHCI implementations (PCI)
62 * + RX, all too often reqpkt seems to misbehave after tx
63 * + TX, no known issues (other than evident silicon issue)
64 *
65 * - DMA (Mentor/OMAP) ...has at least toggle update problems
66 *
67 * - [23-feb-2009] minimal traffic scheduling to avoid bulk RX packet
68 * starvation ... nothing yet for TX, interrupt, or bulk.
69 *
70 * - Not tested with HNP, but some SRP paths seem to behave.
71 *
72 * NOTE 24-August-2006:
73 *
74 * - Bulk traffic finally uses both sides of hardware ep1, freeing up an
75 * extra endpoint for periodic use enabling hub + keybd + mouse. That
76 * mostly works, except that with "usbnet" it's easy to trigger cases
77 * with "ping" where RX loses. (a) ping to davinci, even "ping -f",
78 * fine; but (b) ping _from_ davinci, even "ping -c 1", ICMP RX loses
79 * although ARP RX wins. (That test was done with a full speed link.)
80 */
81
82
83 /*
84 * NOTE on endpoint usage:
85 *
86 * CONTROL transfers all go through ep0. BULK ones go through dedicated IN
87 * and OUT endpoints ... hardware is dedicated for those "async" queue(s).
88 * (Yes, bulk _could_ use more of the endpoints than that, and would even
89 * benefit from it.)
90 *
91 * INTERUPPT and ISOCHRONOUS transfers are scheduled to the other endpoints.
92 * So far that scheduling is both dumb and optimistic: the endpoint will be
93 * "claimed" until its software queue is no longer refilled. No multiplexing
94 * of transfers between endpoints, or anything clever.
95 */
96
97 struct musb *hcd_to_musb(struct usb_hcd *hcd)
98 {
99 return *(struct musb **) hcd->hcd_priv;
100 }
101
102
103 static void musb_ep_program(struct musb *musb, u8 epnum,
104 struct urb *urb, int is_out,
105 u8 *buf, u32 offset, u32 len);
106
107 /*
108 * Clear TX fifo. Needed to avoid BABBLE errors.
109 */
110 static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
111 {
112 struct musb *musb = ep->musb;
113 void __iomem *epio = ep->regs;
114 u16 csr;
115 u16 lastcsr = 0;
116 int retries = 1000;
117
118 csr = musb_readw(epio, MUSB_TXCSR);
119 while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
120 if (csr != lastcsr)
121 dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
122 lastcsr = csr;
123 csr |= MUSB_TXCSR_FLUSHFIFO;
124 musb_writew(epio, MUSB_TXCSR, csr);
125 csr = musb_readw(epio, MUSB_TXCSR);
126 if (WARN(retries-- < 1,
127 "Could not flush host TX%d fifo: csr: %04x\n",
128 ep->epnum, csr))
129 return;
130 mdelay(1);
131 }
132 }
133
134 static void musb_h_ep0_flush_fifo(struct musb_hw_ep *ep)
135 {
136 void __iomem *epio = ep->regs;
137 u16 csr;
138 int retries = 5;
139
140 /* scrub any data left in the fifo */
141 do {
142 csr = musb_readw(epio, MUSB_TXCSR);
143 if (!(csr & (MUSB_CSR0_TXPKTRDY | MUSB_CSR0_RXPKTRDY)))
144 break;
145 musb_writew(epio, MUSB_TXCSR, MUSB_CSR0_FLUSHFIFO);
146 csr = musb_readw(epio, MUSB_TXCSR);
147 udelay(10);
148 } while (--retries);
149
150 WARN(!retries, "Could not flush host TX%d fifo: csr: %04x\n",
151 ep->epnum, csr);
152
153 /* and reset for the next transfer */
154 musb_writew(epio, MUSB_TXCSR, 0);
155 }
156
157 /*
158 * Start transmit. Caller is responsible for locking shared resources.
159 * musb must be locked.
160 */
161 static inline void musb_h_tx_start(struct musb_hw_ep *ep)
162 {
163 u16 txcsr;
164
165 /* NOTE: no locks here; caller should lock and select EP */
166 if (ep->epnum) {
167 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
168 txcsr |= MUSB_TXCSR_TXPKTRDY | MUSB_TXCSR_H_WZC_BITS;
169 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
170 } else {
171 txcsr = MUSB_CSR0_H_SETUPPKT | MUSB_CSR0_TXPKTRDY;
172 musb_writew(ep->regs, MUSB_CSR0, txcsr);
173 }
174
175 }
176
177 static inline void musb_h_tx_dma_start(struct musb_hw_ep *ep)
178 {
179 u16 txcsr;
180
181 /* NOTE: no locks here; caller should lock and select EP */
182 txcsr = musb_readw(ep->regs, MUSB_TXCSR);
183 txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
184 if (is_cppi_enabled())
185 txcsr |= MUSB_TXCSR_DMAMODE;
186 musb_writew(ep->regs, MUSB_TXCSR, txcsr);
187 }
188
189 static void musb_ep_set_qh(struct musb_hw_ep *ep, int is_in, struct musb_qh *qh)
190 {
191 if (is_in != 0 || ep->is_shared_fifo)
192 ep->in_qh = qh;
193 if (is_in == 0 || ep->is_shared_fifo)
194 ep->out_qh = qh;
195 }
196
197 static struct musb_qh *musb_ep_get_qh(struct musb_hw_ep *ep, int is_in)
198 {
199 return is_in ? ep->in_qh : ep->out_qh;
200 }
201
202 /*
203 * Start the URB at the front of an endpoint's queue
204 * end must be claimed from the caller.
205 *
206 * Context: controller locked, irqs blocked
207 */
208 static void
209 musb_start_urb(struct musb *musb, int is_in, struct musb_qh *qh)
210 {
211 u16 frame;
212 u32 len;
213 void __iomem *mbase = musb->mregs;
214 struct urb *urb = next_urb(qh);
215 void *buf = urb->transfer_buffer;
216 u32 offset = 0;
217 struct musb_hw_ep *hw_ep = qh->hw_ep;
218 unsigned pipe = urb->pipe;
219 u8 address = usb_pipedevice(pipe);
220 int epnum = hw_ep->epnum;
221
222 /* initialize software qh state */
223 qh->offset = 0;
224 qh->segsize = 0;
225
226 /* gather right source of data */
227 switch (qh->type) {
228 case USB_ENDPOINT_XFER_CONTROL:
229 /* control transfers always start with SETUP */
230 is_in = 0;
231 musb->ep0_stage = MUSB_EP0_START;
232 buf = urb->setup_packet;
233 len = 8;
234 break;
235 case USB_ENDPOINT_XFER_ISOC:
236 qh->iso_idx = 0;
237 qh->frame = 0;
238 offset = urb->iso_frame_desc[0].offset;
239 len = urb->iso_frame_desc[0].length;
240 break;
241 default: /* bulk, interrupt */
242 /* actual_length may be nonzero on retry paths */
243 buf = urb->transfer_buffer + urb->actual_length;
244 len = urb->transfer_buffer_length - urb->actual_length;
245 }
246
247 dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
248 qh, urb, address, qh->epnum,
249 is_in ? "in" : "out",
250 ({char *s; switch (qh->type) {
251 case USB_ENDPOINT_XFER_CONTROL: s = ""; break;
252 case USB_ENDPOINT_XFER_BULK: s = "-bulk"; break;
253 case USB_ENDPOINT_XFER_ISOC: s = "-iso"; break;
254 default: s = "-intr"; break;
255 } s; }),
256 epnum, buf + offset, len);
257
258 /* Configure endpoint */
259 musb_ep_set_qh(hw_ep, is_in, qh);
260 musb_ep_program(musb, epnum, urb, !is_in, buf, offset, len);
261
262 /* transmit may have more work: start it when it is time */
263 if (is_in)
264 return;
265
266 /* determine if the time is right for a periodic transfer */
267 switch (qh->type) {
268 case USB_ENDPOINT_XFER_ISOC:
269 case USB_ENDPOINT_XFER_INT:
270 dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
271 frame = musb_readw(mbase, MUSB_FRAME);
272 /* FIXME this doesn't implement that scheduling policy ...
273 * or handle framecounter wrapping
274 */
275 if (1) { /* Always assume URB_ISO_ASAP */
276 /* REVISIT the SOF irq handler shouldn't duplicate
277 * this code; and we don't init urb->start_frame...
278 */
279 qh->frame = 0;
280 goto start;
281 } else {
282 qh->frame = urb->start_frame;
283 /* enable SOF interrupt so we can count down */
284 dev_dbg(musb->controller, "SOF for %d\n", epnum);
285 #if 1 /* ifndef CONFIG_ARCH_DAVINCI */
286 musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
287 #endif
288 }
289 break;
290 default:
291 start:
292 dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
293 hw_ep->tx_channel ? "dma" : "pio");
294
295 if (!hw_ep->tx_channel)
296 musb_h_tx_start(hw_ep);
297 else if (is_cppi_enabled() || tusb_dma_omap())
298 musb_h_tx_dma_start(hw_ep);
299 }
300 }
301
302 /* Context: caller owns controller lock, IRQs are blocked */
303 static void musb_giveback(struct musb *musb, struct urb *urb, int status)
304 __releases(musb->lock)
305 __acquires(musb->lock)
306 {
307 dev_dbg(musb->controller,
308 "complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
309 urb, urb->complete, status,
310 usb_pipedevice(urb->pipe),
311 usb_pipeendpoint(urb->pipe),
312 usb_pipein(urb->pipe) ? "in" : "out",
313 urb->actual_length, urb->transfer_buffer_length
314 );
315
316 usb_hcd_unlink_urb_from_ep(musb->hcd, urb);
317 spin_unlock(&musb->lock);
318 usb_hcd_giveback_urb(musb->hcd, urb, status);
319 spin_lock(&musb->lock);
320 }
321
322 /* For bulk/interrupt endpoints only */
323 static inline void musb_save_toggle(struct musb_qh *qh, int is_in,
324 struct urb *urb)
325 {
326 void __iomem *epio = qh->hw_ep->regs;
327 u16 csr;
328
329 /*
330 * FIXME: the current Mentor DMA code seems to have
331 * problems getting toggle correct.
332 */
333
334 if (is_in)
335 csr = musb_readw(epio, MUSB_RXCSR) & MUSB_RXCSR_H_DATATOGGLE;
336 else
337 csr = musb_readw(epio, MUSB_TXCSR) & MUSB_TXCSR_H_DATATOGGLE;
338
339 usb_settoggle(urb->dev, qh->epnum, !is_in, csr ? 1 : 0);
340 }
341
342 /*
343 * Advance this hardware endpoint's queue, completing the specified URB and
344 * advancing to either the next URB queued to that qh, or else invalidating
345 * that qh and advancing to the next qh scheduled after the current one.
346 *
347 * Context: caller owns controller lock, IRQs are blocked
348 */
349 static void musb_advance_schedule(struct musb *musb, struct urb *urb,
350 struct musb_hw_ep *hw_ep, int is_in)
351 {
352 struct musb_qh *qh = musb_ep_get_qh(hw_ep, is_in);
353 struct musb_hw_ep *ep = qh->hw_ep;
354 int ready = qh->is_ready;
355 int status;
356
357 status = (urb->status == -EINPROGRESS) ? 0 : urb->status;
358
359 /* save toggle eagerly, for paranoia */
360 switch (qh->type) {
361 case USB_ENDPOINT_XFER_BULK:
362 case USB_ENDPOINT_XFER_INT:
363 musb_save_toggle(qh, is_in, urb);
364 break;
365 case USB_ENDPOINT_XFER_ISOC:
366 if (status == 0 && urb->error_count)
367 status = -EXDEV;
368 break;
369 }
370
371 qh->is_ready = 0;
372 musb_giveback(musb, urb, status);
373 qh->is_ready = ready;
374
375 /* reclaim resources (and bandwidth) ASAP; deschedule it, and
376 * invalidate qh as soon as list_empty(&hep->urb_list)
377 */
378 if (list_empty(&qh->hep->urb_list)) {
379 struct list_head *head;
380 struct dma_controller *dma = musb->dma_controller;
381
382 if (is_in) {
383 ep->rx_reinit = 1;
384 if (ep->rx_channel) {
385 dma->channel_release(ep->rx_channel);
386 ep->rx_channel = NULL;
387 }
388 } else {
389 ep->tx_reinit = 1;
390 if (ep->tx_channel) {
391 dma->channel_release(ep->tx_channel);
392 ep->tx_channel = NULL;
393 }
394 }
395
396 /* Clobber old pointers to this qh */
397 musb_ep_set_qh(ep, is_in, NULL);
398 qh->hep->hcpriv = NULL;
399
400 switch (qh->type) {
401
402 case USB_ENDPOINT_XFER_CONTROL:
403 case USB_ENDPOINT_XFER_BULK:
404 /* fifo policy for these lists, except that NAKing
405 * should rotate a qh to the end (for fairness).
406 */
407 if (qh->mux == 1) {
408 head = qh->ring.prev;
409 list_del(&qh->ring);
410 kfree(qh);
411 qh = first_qh(head);
412 break;
413 }
414
415 case USB_ENDPOINT_XFER_ISOC:
416 case USB_ENDPOINT_XFER_INT:
417 /* this is where periodic bandwidth should be
418 * de-allocated if it's tracked and allocated;
419 * and where we'd update the schedule tree...
420 */
421 kfree(qh);
422 qh = NULL;
423 break;
424 }
425 }
426
427 if (qh != NULL && qh->is_ready) {
428 dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
429 hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
430 musb_start_urb(musb, is_in, qh);
431 }
432 }
433
434 static u16 musb_h_flush_rxfifo(struct musb_hw_ep *hw_ep, u16 csr)
435 {
436 /* we don't want fifo to fill itself again;
437 * ignore dma (various models),
438 * leave toggle alone (may not have been saved yet)
439 */
440 csr |= MUSB_RXCSR_FLUSHFIFO | MUSB_RXCSR_RXPKTRDY;
441 csr &= ~(MUSB_RXCSR_H_REQPKT
442 | MUSB_RXCSR_H_AUTOREQ
443 | MUSB_RXCSR_AUTOCLEAR);
444
445 /* write 2x to allow double buffering */
446 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
447 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
448
449 /* flush writebuffer */
450 return musb_readw(hw_ep->regs, MUSB_RXCSR);
451 }
452
453 /*
454 * PIO RX for a packet (or part of it).
455 */
456 static bool
457 musb_host_packet_rx(struct musb *musb, struct urb *urb, u8 epnum, u8 iso_err)
458 {
459 u16 rx_count;
460 u8 *buf;
461 u16 csr;
462 bool done = false;
463 u32 length;
464 int do_flush = 0;
465 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
466 void __iomem *epio = hw_ep->regs;
467 struct musb_qh *qh = hw_ep->in_qh;
468 int pipe = urb->pipe;
469 void *buffer = urb->transfer_buffer;
470
471 /* musb_ep_select(mbase, epnum); */
472 rx_count = musb_readw(epio, MUSB_RXCOUNT);
473 dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
474 urb->transfer_buffer, qh->offset,
475 urb->transfer_buffer_length);
476
477 /* unload FIFO */
478 if (usb_pipeisoc(pipe)) {
479 int status = 0;
480 struct usb_iso_packet_descriptor *d;
481
482 if (iso_err) {
483 status = -EILSEQ;
484 urb->error_count++;
485 }
486
487 d = urb->iso_frame_desc + qh->iso_idx;
488 buf = buffer + d->offset;
489 length = d->length;
490 if (rx_count > length) {
491 if (status == 0) {
492 status = -EOVERFLOW;
493 urb->error_count++;
494 }
495 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
496 do_flush = 1;
497 } else
498 length = rx_count;
499 urb->actual_length += length;
500 d->actual_length = length;
501
502 d->status = status;
503
504 /* see if we are done */
505 done = (++qh->iso_idx >= urb->number_of_packets);
506 } else {
507 /* non-isoch */
508 buf = buffer + qh->offset;
509 length = urb->transfer_buffer_length - qh->offset;
510 if (rx_count > length) {
511 if (urb->status == -EINPROGRESS)
512 urb->status = -EOVERFLOW;
513 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
514 do_flush = 1;
515 } else
516 length = rx_count;
517 urb->actual_length += length;
518 qh->offset += length;
519
520 /* see if we are done */
521 done = (urb->actual_length == urb->transfer_buffer_length)
522 || (rx_count < qh->maxpacket)
523 || (urb->status != -EINPROGRESS);
524 if (done
525 && (urb->status == -EINPROGRESS)
526 && (urb->transfer_flags & URB_SHORT_NOT_OK)
527 && (urb->actual_length
528 < urb->transfer_buffer_length))
529 urb->status = -EREMOTEIO;
530 }
531
532 musb_read_fifo(hw_ep, length, buf);
533
534 csr = musb_readw(epio, MUSB_RXCSR);
535 csr |= MUSB_RXCSR_H_WZC_BITS;
536 if (unlikely(do_flush))
537 musb_h_flush_rxfifo(hw_ep, csr);
538 else {
539 /* REVISIT this assumes AUTOCLEAR is never set */
540 csr &= ~(MUSB_RXCSR_RXPKTRDY | MUSB_RXCSR_H_REQPKT);
541 if (!done)
542 csr |= MUSB_RXCSR_H_REQPKT;
543 musb_writew(epio, MUSB_RXCSR, csr);
544 }
545
546 return done;
547 }
548
549 /* we don't always need to reinit a given side of an endpoint...
550 * when we do, use tx/rx reinit routine and then construct a new CSR
551 * to address data toggle, NYET, and DMA or PIO.
552 *
553 * it's possible that driver bugs (especially for DMA) or aborting a
554 * transfer might have left the endpoint busier than it should be.
555 * the busy/not-empty tests are basically paranoia.
556 */
557 static void
558 musb_rx_reinit(struct musb *musb, struct musb_qh *qh, struct musb_hw_ep *ep)
559 {
560 u16 csr;
561
562 /* NOTE: we know the "rx" fifo reinit never triggers for ep0.
563 * That always uses tx_reinit since ep0 repurposes TX register
564 * offsets; the initial SETUP packet is also a kind of OUT.
565 */
566
567 /* if programmed for Tx, put it in RX mode */
568 if (ep->is_shared_fifo) {
569 csr = musb_readw(ep->regs, MUSB_TXCSR);
570 if (csr & MUSB_TXCSR_MODE) {
571 musb_h_tx_flush_fifo(ep);
572 csr = musb_readw(ep->regs, MUSB_TXCSR);
573 musb_writew(ep->regs, MUSB_TXCSR,
574 csr | MUSB_TXCSR_FRCDATATOG);
575 }
576
577 /*
578 * Clear the MODE bit (and everything else) to enable Rx.
579 * NOTE: we mustn't clear the DMAMODE bit before DMAENAB.
580 */
581 if (csr & MUSB_TXCSR_DMAMODE)
582 musb_writew(ep->regs, MUSB_TXCSR, MUSB_TXCSR_DMAMODE);
583 musb_writew(ep->regs, MUSB_TXCSR, 0);
584
585 /* scrub all previous state, clearing toggle */
586 } else {
587 csr = musb_readw(ep->regs, MUSB_RXCSR);
588 if (csr & MUSB_RXCSR_RXPKTRDY)
589 WARNING("rx%d, packet/%d ready?\n", ep->epnum,
590 musb_readw(ep->regs, MUSB_RXCOUNT));
591
592 musb_h_flush_rxfifo(ep, MUSB_RXCSR_CLRDATATOG);
593 }
594
595 /* target addr and (for multipoint) hub addr/port */
596 if (musb->is_multipoint) {
597 musb_write_rxfunaddr(ep->target_regs, qh->addr_reg);
598 musb_write_rxhubaddr(ep->target_regs, qh->h_addr_reg);
599 musb_write_rxhubport(ep->target_regs, qh->h_port_reg);
600
601 } else
602 musb_writeb(musb->mregs, MUSB_FADDR, qh->addr_reg);
603
604 /* protocol/endpoint, interval/NAKlimit, i/o size */
605 musb_writeb(ep->regs, MUSB_RXTYPE, qh->type_reg);
606 musb_writeb(ep->regs, MUSB_RXINTERVAL, qh->intv_reg);
607 /* NOTE: bulk combining rewrites high bits of maxpacket */
608 /* Set RXMAXP with the FIFO size of the endpoint
609 * to disable double buffer mode.
610 */
611 if (musb->double_buffer_not_ok)
612 musb_writew(ep->regs, MUSB_RXMAXP, ep->max_packet_sz_rx);
613 else
614 musb_writew(ep->regs, MUSB_RXMAXP,
615 qh->maxpacket | ((qh->hb_mult - 1) << 11));
616
617 ep->rx_reinit = 0;
618 }
619
620 static bool musb_tx_dma_program(struct dma_controller *dma,
621 struct musb_hw_ep *hw_ep, struct musb_qh *qh,
622 struct urb *urb, u32 offset, u32 length)
623 {
624 struct dma_channel *channel = hw_ep->tx_channel;
625 void __iomem *epio = hw_ep->regs;
626 u16 pkt_size = qh->maxpacket;
627 u16 csr;
628 u8 mode;
629
630 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
631 if (length > channel->max_len)
632 length = channel->max_len;
633
634 csr = musb_readw(epio, MUSB_TXCSR);
635 if (length > pkt_size) {
636 mode = 1;
637 csr |= MUSB_TXCSR_DMAMODE | MUSB_TXCSR_DMAENAB;
638 /* autoset shouldn't be set in high bandwidth */
639 /*
640 * Enable Autoset according to table
641 * below
642 * bulk_split hb_mult Autoset_Enable
643 * 0 1 Yes(Normal)
644 * 0 >1 No(High BW ISO)
645 * 1 1 Yes(HS bulk)
646 * 1 >1 Yes(FS bulk)
647 */
648 if (qh->hb_mult == 1 || (qh->hb_mult > 1 &&
649 can_bulk_split(hw_ep->musb, qh->type)))
650 csr |= MUSB_TXCSR_AUTOSET;
651 } else {
652 mode = 0;
653 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAMODE);
654 csr |= MUSB_TXCSR_DMAENAB; /* against programmer's guide */
655 }
656 channel->desired_mode = mode;
657 musb_writew(epio, MUSB_TXCSR, csr);
658 #else
659 if (!is_cppi_enabled() && !tusb_dma_omap())
660 return false;
661
662 channel->actual_len = 0;
663
664 /*
665 * TX uses "RNDIS" mode automatically but needs help
666 * to identify the zero-length-final-packet case.
667 */
668 mode = (urb->transfer_flags & URB_ZERO_PACKET) ? 1 : 0;
669 #endif
670
671 qh->segsize = length;
672
673 /*
674 * Ensure the data reaches to main memory before starting
675 * DMA transfer
676 */
677 wmb();
678
679 if (!dma->channel_program(channel, pkt_size, mode,
680 urb->transfer_dma + offset, length)) {
681 dma->channel_release(channel);
682 hw_ep->tx_channel = NULL;
683
684 csr = musb_readw(epio, MUSB_TXCSR);
685 csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
686 musb_writew(epio, MUSB_TXCSR, csr | MUSB_TXCSR_H_WZC_BITS);
687 return false;
688 }
689 return true;
690 }
691
692 /*
693 * Program an HDRC endpoint as per the given URB
694 * Context: irqs blocked, controller lock held
695 */
696 static void musb_ep_program(struct musb *musb, u8 epnum,
697 struct urb *urb, int is_out,
698 u8 *buf, u32 offset, u32 len)
699 {
700 struct dma_controller *dma_controller;
701 struct dma_channel *dma_channel;
702 u8 dma_ok;
703 void __iomem *mbase = musb->mregs;
704 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
705 void __iomem *epio = hw_ep->regs;
706 struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
707 u16 packet_sz = qh->maxpacket;
708 u8 use_dma = 1;
709 u16 csr;
710
711 dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
712 "h_addr%02x h_port%02x bytes %d\n",
713 is_out ? "-->" : "<--",
714 epnum, urb, urb->dev->speed,
715 qh->addr_reg, qh->epnum, is_out ? "out" : "in",
716 qh->h_addr_reg, qh->h_port_reg,
717 len);
718
719 musb_ep_select(mbase, epnum);
720
721 if (is_out && !len) {
722 use_dma = 0;
723 csr = musb_readw(epio, MUSB_TXCSR);
724 csr &= ~MUSB_TXCSR_DMAENAB;
725 musb_writew(epio, MUSB_TXCSR, csr);
726 hw_ep->tx_channel = NULL;
727 }
728
729 /* candidate for DMA? */
730 dma_controller = musb->dma_controller;
731 if (use_dma && is_dma_capable() && epnum && dma_controller) {
732 dma_channel = is_out ? hw_ep->tx_channel : hw_ep->rx_channel;
733 if (!dma_channel) {
734 dma_channel = dma_controller->channel_alloc(
735 dma_controller, hw_ep, is_out);
736 if (is_out)
737 hw_ep->tx_channel = dma_channel;
738 else
739 hw_ep->rx_channel = dma_channel;
740 }
741 } else
742 dma_channel = NULL;
743
744 /* make sure we clear DMAEnab, autoSet bits from previous run */
745
746 /* OUT/transmit/EP0 or IN/receive? */
747 if (is_out) {
748 u16 csr;
749 u16 int_txe;
750 u16 load_count;
751
752 csr = musb_readw(epio, MUSB_TXCSR);
753
754 /* disable interrupt in case we flush */
755 int_txe = musb->intrtxe;
756 musb_writew(mbase, MUSB_INTRTXE, int_txe & ~(1 << epnum));
757
758 /* general endpoint setup */
759 if (epnum) {
760 /* flush all old state, set default */
761 /*
762 * We could be flushing valid
763 * packets in double buffering
764 * case
765 */
766 if (!hw_ep->tx_double_buffered)
767 musb_h_tx_flush_fifo(hw_ep);
768
769 /*
770 * We must not clear the DMAMODE bit before or in
771 * the same cycle with the DMAENAB bit, so we clear
772 * the latter first...
773 */
774 csr &= ~(MUSB_TXCSR_H_NAKTIMEOUT
775 | MUSB_TXCSR_AUTOSET
776 | MUSB_TXCSR_DMAENAB
777 | MUSB_TXCSR_FRCDATATOG
778 | MUSB_TXCSR_H_RXSTALL
779 | MUSB_TXCSR_H_ERROR
780 | MUSB_TXCSR_TXPKTRDY
781 );
782 csr |= MUSB_TXCSR_MODE;
783
784 if (!hw_ep->tx_double_buffered) {
785 if (usb_gettoggle(urb->dev, qh->epnum, 1))
786 csr |= MUSB_TXCSR_H_WR_DATATOGGLE
787 | MUSB_TXCSR_H_DATATOGGLE;
788 else
789 csr |= MUSB_TXCSR_CLRDATATOG;
790 }
791
792 musb_writew(epio, MUSB_TXCSR, csr);
793 /* REVISIT may need to clear FLUSHFIFO ... */
794 csr &= ~MUSB_TXCSR_DMAMODE;
795 musb_writew(epio, MUSB_TXCSR, csr);
796 csr = musb_readw(epio, MUSB_TXCSR);
797 } else {
798 /* endpoint 0: just flush */
799 musb_h_ep0_flush_fifo(hw_ep);
800 }
801
802 /* target addr and (for multipoint) hub addr/port */
803 if (musb->is_multipoint) {
804 musb_write_txfunaddr(mbase, epnum, qh->addr_reg);
805 musb_write_txhubaddr(mbase, epnum, qh->h_addr_reg);
806 musb_write_txhubport(mbase, epnum, qh->h_port_reg);
807 /* FIXME if !epnum, do the same for RX ... */
808 } else
809 musb_writeb(mbase, MUSB_FADDR, qh->addr_reg);
810
811 /* protocol/endpoint/interval/NAKlimit */
812 if (epnum) {
813 musb_writeb(epio, MUSB_TXTYPE, qh->type_reg);
814 if (musb->double_buffer_not_ok) {
815 musb_writew(epio, MUSB_TXMAXP,
816 hw_ep->max_packet_sz_tx);
817 } else if (can_bulk_split(musb, qh->type)) {
818 qh->hb_mult = hw_ep->max_packet_sz_tx
819 / packet_sz;
820 musb_writew(epio, MUSB_TXMAXP, packet_sz
821 | ((qh->hb_mult) - 1) << 11);
822 } else {
823 musb_writew(epio, MUSB_TXMAXP,
824 qh->maxpacket |
825 ((qh->hb_mult - 1) << 11));
826 }
827 musb_writeb(epio, MUSB_TXINTERVAL, qh->intv_reg);
828 } else {
829 musb_writeb(epio, MUSB_NAKLIMIT0, qh->intv_reg);
830 if (musb->is_multipoint)
831 musb_writeb(epio, MUSB_TYPE0,
832 qh->type_reg);
833 }
834
835 if (can_bulk_split(musb, qh->type))
836 load_count = min((u32) hw_ep->max_packet_sz_tx,
837 len);
838 else
839 load_count = min((u32) packet_sz, len);
840
841 if (dma_channel && musb_tx_dma_program(dma_controller,
842 hw_ep, qh, urb, offset, len))
843 load_count = 0;
844
845 if (load_count) {
846 /* PIO to load FIFO */
847 qh->segsize = load_count;
848 if (!buf) {
849 sg_miter_start(&qh->sg_miter, urb->sg, 1,
850 SG_MITER_ATOMIC
851 | SG_MITER_FROM_SG);
852 if (!sg_miter_next(&qh->sg_miter)) {
853 dev_err(musb->controller,
854 "error: sg"
855 "list empty\n");
856 sg_miter_stop(&qh->sg_miter);
857 goto finish;
858 }
859 buf = qh->sg_miter.addr + urb->sg->offset +
860 urb->actual_length;
861 load_count = min_t(u32, load_count,
862 qh->sg_miter.length);
863 musb_write_fifo(hw_ep, load_count, buf);
864 qh->sg_miter.consumed = load_count;
865 sg_miter_stop(&qh->sg_miter);
866 } else
867 musb_write_fifo(hw_ep, load_count, buf);
868 }
869 finish:
870 /* re-enable interrupt */
871 musb_writew(mbase, MUSB_INTRTXE, int_txe);
872
873 /* IN/receive */
874 } else {
875 u16 csr;
876
877 if (hw_ep->rx_reinit) {
878 musb_rx_reinit(musb, qh, hw_ep);
879
880 /* init new state: toggle and NYET, maybe DMA later */
881 if (usb_gettoggle(urb->dev, qh->epnum, 0))
882 csr = MUSB_RXCSR_H_WR_DATATOGGLE
883 | MUSB_RXCSR_H_DATATOGGLE;
884 else
885 csr = 0;
886 if (qh->type == USB_ENDPOINT_XFER_INT)
887 csr |= MUSB_RXCSR_DISNYET;
888
889 } else {
890 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
891
892 if (csr & (MUSB_RXCSR_RXPKTRDY
893 | MUSB_RXCSR_DMAENAB
894 | MUSB_RXCSR_H_REQPKT))
895 ERR("broken !rx_reinit, ep%d csr %04x\n",
896 hw_ep->epnum, csr);
897
898 /* scrub any stale state, leaving toggle alone */
899 csr &= MUSB_RXCSR_DISNYET;
900 }
901
902 /* kick things off */
903
904 if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
905 /* Candidate for DMA */
906 dma_channel->actual_len = 0L;
907 qh->segsize = len;
908
909 /* AUTOREQ is in a DMA register */
910 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
911 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
912
913 /*
914 * Unless caller treats short RX transfers as
915 * errors, we dare not queue multiple transfers.
916 */
917 dma_ok = dma_controller->channel_program(dma_channel,
918 packet_sz, !(urb->transfer_flags &
919 URB_SHORT_NOT_OK),
920 urb->transfer_dma + offset,
921 qh->segsize);
922 if (!dma_ok) {
923 dma_controller->channel_release(dma_channel);
924 hw_ep->rx_channel = dma_channel = NULL;
925 } else
926 csr |= MUSB_RXCSR_DMAENAB;
927 }
928
929 csr |= MUSB_RXCSR_H_REQPKT;
930 dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
931 musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
932 csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
933 }
934 }
935
936 /* Schedule next QH from musb->in_bulk/out_bulk and move the current qh to
937 * the end; avoids starvation for other endpoints.
938 */
939 static void musb_bulk_nak_timeout(struct musb *musb, struct musb_hw_ep *ep,
940 int is_in)
941 {
942 struct dma_channel *dma;
943 struct urb *urb;
944 void __iomem *mbase = musb->mregs;
945 void __iomem *epio = ep->regs;
946 struct musb_qh *cur_qh, *next_qh;
947 u16 rx_csr, tx_csr;
948
949 musb_ep_select(mbase, ep->epnum);
950 if (is_in) {
951 dma = is_dma_capable() ? ep->rx_channel : NULL;
952
953 /* clear nak timeout bit */
954 rx_csr = musb_readw(epio, MUSB_RXCSR);
955 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
956 rx_csr &= ~MUSB_RXCSR_DATAERROR;
957 musb_writew(epio, MUSB_RXCSR, rx_csr);
958
959 cur_qh = first_qh(&musb->in_bulk);
960 } else {
961 dma = is_dma_capable() ? ep->tx_channel : NULL;
962
963 /* clear nak timeout bit */
964 tx_csr = musb_readw(epio, MUSB_TXCSR);
965 tx_csr |= MUSB_TXCSR_H_WZC_BITS;
966 tx_csr &= ~MUSB_TXCSR_H_NAKTIMEOUT;
967 musb_writew(epio, MUSB_TXCSR, tx_csr);
968
969 cur_qh = first_qh(&musb->out_bulk);
970 }
971 if (cur_qh) {
972 urb = next_urb(cur_qh);
973 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
974 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
975 musb->dma_controller->channel_abort(dma);
976 urb->actual_length += dma->actual_len;
977 dma->actual_len = 0L;
978 }
979 musb_save_toggle(cur_qh, is_in, urb);
980
981 if (is_in) {
982 /* move cur_qh to end of queue */
983 list_move_tail(&cur_qh->ring, &musb->in_bulk);
984
985 /* get the next qh from musb->in_bulk */
986 next_qh = first_qh(&musb->in_bulk);
987
988 /* set rx_reinit and schedule the next qh */
989 ep->rx_reinit = 1;
990 } else {
991 /* move cur_qh to end of queue */
992 list_move_tail(&cur_qh->ring, &musb->out_bulk);
993
994 /* get the next qh from musb->out_bulk */
995 next_qh = first_qh(&musb->out_bulk);
996
997 /* set tx_reinit and schedule the next qh */
998 ep->tx_reinit = 1;
999 }
1000 musb_start_urb(musb, is_in, next_qh);
1001 }
1002 }
1003
1004 /*
1005 * Service the default endpoint (ep0) as host.
1006 * Return true until it's time to start the status stage.
1007 */
1008 static bool musb_h_ep0_continue(struct musb *musb, u16 len, struct urb *urb)
1009 {
1010 bool more = false;
1011 u8 *fifo_dest = NULL;
1012 u16 fifo_count = 0;
1013 struct musb_hw_ep *hw_ep = musb->control_ep;
1014 struct musb_qh *qh = hw_ep->in_qh;
1015 struct usb_ctrlrequest *request;
1016
1017 switch (musb->ep0_stage) {
1018 case MUSB_EP0_IN:
1019 fifo_dest = urb->transfer_buffer + urb->actual_length;
1020 fifo_count = min_t(size_t, len, urb->transfer_buffer_length -
1021 urb->actual_length);
1022 if (fifo_count < len)
1023 urb->status = -EOVERFLOW;
1024
1025 musb_read_fifo(hw_ep, fifo_count, fifo_dest);
1026
1027 urb->actual_length += fifo_count;
1028 if (len < qh->maxpacket) {
1029 /* always terminate on short read; it's
1030 * rarely reported as an error.
1031 */
1032 } else if (urb->actual_length <
1033 urb->transfer_buffer_length)
1034 more = true;
1035 break;
1036 case MUSB_EP0_START:
1037 request = (struct usb_ctrlrequest *) urb->setup_packet;
1038
1039 if (!request->wLength) {
1040 dev_dbg(musb->controller, "start no-DATA\n");
1041 break;
1042 } else if (request->bRequestType & USB_DIR_IN) {
1043 dev_dbg(musb->controller, "start IN-DATA\n");
1044 musb->ep0_stage = MUSB_EP0_IN;
1045 more = true;
1046 break;
1047 } else {
1048 dev_dbg(musb->controller, "start OUT-DATA\n");
1049 musb->ep0_stage = MUSB_EP0_OUT;
1050 more = true;
1051 }
1052 /* FALLTHROUGH */
1053 case MUSB_EP0_OUT:
1054 fifo_count = min_t(size_t, qh->maxpacket,
1055 urb->transfer_buffer_length -
1056 urb->actual_length);
1057 if (fifo_count) {
1058 fifo_dest = (u8 *) (urb->transfer_buffer
1059 + urb->actual_length);
1060 dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
1061 fifo_count,
1062 (fifo_count == 1) ? "" : "s",
1063 fifo_dest);
1064 musb_write_fifo(hw_ep, fifo_count, fifo_dest);
1065
1066 urb->actual_length += fifo_count;
1067 more = true;
1068 }
1069 break;
1070 default:
1071 ERR("bogus ep0 stage %d\n", musb->ep0_stage);
1072 break;
1073 }
1074
1075 return more;
1076 }
1077
1078 /*
1079 * Handle default endpoint interrupt as host. Only called in IRQ time
1080 * from musb_interrupt().
1081 *
1082 * called with controller irqlocked
1083 */
1084 irqreturn_t musb_h_ep0_irq(struct musb *musb)
1085 {
1086 struct urb *urb;
1087 u16 csr, len;
1088 int status = 0;
1089 void __iomem *mbase = musb->mregs;
1090 struct musb_hw_ep *hw_ep = musb->control_ep;
1091 void __iomem *epio = hw_ep->regs;
1092 struct musb_qh *qh = hw_ep->in_qh;
1093 bool complete = false;
1094 irqreturn_t retval = IRQ_NONE;
1095
1096 /* ep0 only has one queue, "in" */
1097 urb = next_urb(qh);
1098
1099 musb_ep_select(mbase, 0);
1100 csr = musb_readw(epio, MUSB_CSR0);
1101 len = (csr & MUSB_CSR0_RXPKTRDY)
1102 ? musb_readb(epio, MUSB_COUNT0)
1103 : 0;
1104
1105 dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
1106 csr, qh, len, urb, musb->ep0_stage);
1107
1108 /* if we just did status stage, we are done */
1109 if (MUSB_EP0_STATUS == musb->ep0_stage) {
1110 retval = IRQ_HANDLED;
1111 complete = true;
1112 }
1113
1114 /* prepare status */
1115 if (csr & MUSB_CSR0_H_RXSTALL) {
1116 dev_dbg(musb->controller, "STALLING ENDPOINT\n");
1117 status = -EPIPE;
1118
1119 } else if (csr & MUSB_CSR0_H_ERROR) {
1120 dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
1121 status = -EPROTO;
1122
1123 } else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
1124 dev_dbg(musb->controller, "control NAK timeout\n");
1125
1126 /* NOTE: this code path would be a good place to PAUSE a
1127 * control transfer, if another one is queued, so that
1128 * ep0 is more likely to stay busy. That's already done
1129 * for bulk RX transfers.
1130 *
1131 * if (qh->ring.next != &musb->control), then
1132 * we have a candidate... NAKing is *NOT* an error
1133 */
1134 musb_writew(epio, MUSB_CSR0, 0);
1135 retval = IRQ_HANDLED;
1136 }
1137
1138 if (status) {
1139 dev_dbg(musb->controller, "aborting\n");
1140 retval = IRQ_HANDLED;
1141 if (urb)
1142 urb->status = status;
1143 complete = true;
1144
1145 /* use the proper sequence to abort the transfer */
1146 if (csr & MUSB_CSR0_H_REQPKT) {
1147 csr &= ~MUSB_CSR0_H_REQPKT;
1148 musb_writew(epio, MUSB_CSR0, csr);
1149 csr &= ~MUSB_CSR0_H_NAKTIMEOUT;
1150 musb_writew(epio, MUSB_CSR0, csr);
1151 } else {
1152 musb_h_ep0_flush_fifo(hw_ep);
1153 }
1154
1155 musb_writeb(epio, MUSB_NAKLIMIT0, 0);
1156
1157 /* clear it */
1158 musb_writew(epio, MUSB_CSR0, 0);
1159 }
1160
1161 if (unlikely(!urb)) {
1162 /* stop endpoint since we have no place for its data, this
1163 * SHOULD NEVER HAPPEN! */
1164 ERR("no URB for end 0\n");
1165
1166 musb_h_ep0_flush_fifo(hw_ep);
1167 goto done;
1168 }
1169
1170 if (!complete) {
1171 /* call common logic and prepare response */
1172 if (musb_h_ep0_continue(musb, len, urb)) {
1173 /* more packets required */
1174 csr = (MUSB_EP0_IN == musb->ep0_stage)
1175 ? MUSB_CSR0_H_REQPKT : MUSB_CSR0_TXPKTRDY;
1176 } else {
1177 /* data transfer complete; perform status phase */
1178 if (usb_pipeout(urb->pipe)
1179 || !urb->transfer_buffer_length)
1180 csr = MUSB_CSR0_H_STATUSPKT
1181 | MUSB_CSR0_H_REQPKT;
1182 else
1183 csr = MUSB_CSR0_H_STATUSPKT
1184 | MUSB_CSR0_TXPKTRDY;
1185
1186 /* flag status stage */
1187 musb->ep0_stage = MUSB_EP0_STATUS;
1188
1189 dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
1190
1191 }
1192 musb_writew(epio, MUSB_CSR0, csr);
1193 retval = IRQ_HANDLED;
1194 } else
1195 musb->ep0_stage = MUSB_EP0_IDLE;
1196
1197 /* call completion handler if done */
1198 if (complete)
1199 musb_advance_schedule(musb, urb, hw_ep, 1);
1200 done:
1201 return retval;
1202 }
1203
1204
1205 #ifdef CONFIG_USB_INVENTRA_DMA
1206
1207 /* Host side TX (OUT) using Mentor DMA works as follows:
1208 submit_urb ->
1209 - if queue was empty, Program Endpoint
1210 - ... which starts DMA to fifo in mode 1 or 0
1211
1212 DMA Isr (transfer complete) -> TxAvail()
1213 - Stop DMA (~DmaEnab) (<--- Alert ... currently happens
1214 only in musb_cleanup_urb)
1215 - TxPktRdy has to be set in mode 0 or for
1216 short packets in mode 1.
1217 */
1218
1219 #endif
1220
1221 /* Service a Tx-Available or dma completion irq for the endpoint */
1222 void musb_host_tx(struct musb *musb, u8 epnum)
1223 {
1224 int pipe;
1225 bool done = false;
1226 u16 tx_csr;
1227 size_t length = 0;
1228 size_t offset = 0;
1229 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1230 void __iomem *epio = hw_ep->regs;
1231 struct musb_qh *qh = hw_ep->out_qh;
1232 struct urb *urb = next_urb(qh);
1233 u32 status = 0;
1234 void __iomem *mbase = musb->mregs;
1235 struct dma_channel *dma;
1236 bool transfer_pending = false;
1237
1238 musb_ep_select(mbase, epnum);
1239 tx_csr = musb_readw(epio, MUSB_TXCSR);
1240
1241 /* with CPPI, DMA sometimes triggers "extra" irqs */
1242 if (!urb) {
1243 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1244 return;
1245 }
1246
1247 pipe = urb->pipe;
1248 dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
1249 dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
1250 dma ? ", dma" : "");
1251
1252 /* check for errors */
1253 if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
1254 /* dma was disabled, fifo flushed */
1255 dev_dbg(musb->controller, "TX end %d stall\n", epnum);
1256
1257 /* stall; record URB status */
1258 status = -EPIPE;
1259
1260 } else if (tx_csr & MUSB_TXCSR_H_ERROR) {
1261 /* (NON-ISO) dma was disabled, fifo flushed */
1262 dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
1263
1264 status = -ETIMEDOUT;
1265
1266 } else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
1267 if (USB_ENDPOINT_XFER_BULK == qh->type && qh->mux == 1
1268 && !list_is_singular(&musb->out_bulk)) {
1269 dev_dbg(musb->controller,
1270 "NAK timeout on TX%d ep\n", epnum);
1271 musb_bulk_nak_timeout(musb, hw_ep, 0);
1272 } else {
1273 dev_dbg(musb->controller,
1274 "TX end=%d device not responding\n", epnum);
1275 /* NOTE: this code path would be a good place to PAUSE a
1276 * transfer, if there's some other (nonperiodic) tx urb
1277 * that could use this fifo. (dma complicates it...)
1278 * That's already done for bulk RX transfers.
1279 *
1280 * if (bulk && qh->ring.next != &musb->out_bulk), then
1281 * we have a candidate... NAKing is *NOT* an error
1282 */
1283 musb_ep_select(mbase, epnum);
1284 musb_writew(epio, MUSB_TXCSR,
1285 MUSB_TXCSR_H_WZC_BITS
1286 | MUSB_TXCSR_TXPKTRDY);
1287 }
1288 return;
1289 }
1290
1291 done:
1292 if (status) {
1293 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1294 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1295 (void) musb->dma_controller->channel_abort(dma);
1296 }
1297
1298 /* do the proper sequence to abort the transfer in the
1299 * usb core; the dma engine should already be stopped.
1300 */
1301 musb_h_tx_flush_fifo(hw_ep);
1302 tx_csr &= ~(MUSB_TXCSR_AUTOSET
1303 | MUSB_TXCSR_DMAENAB
1304 | MUSB_TXCSR_H_ERROR
1305 | MUSB_TXCSR_H_RXSTALL
1306 | MUSB_TXCSR_H_NAKTIMEOUT
1307 );
1308
1309 musb_ep_select(mbase, epnum);
1310 musb_writew(epio, MUSB_TXCSR, tx_csr);
1311 /* REVISIT may need to clear FLUSHFIFO ... */
1312 musb_writew(epio, MUSB_TXCSR, tx_csr);
1313 musb_writeb(epio, MUSB_TXINTERVAL, 0);
1314
1315 done = true;
1316 }
1317
1318 /* second cppi case */
1319 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1320 dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
1321 return;
1322 }
1323
1324 if (is_dma_capable() && dma && !status) {
1325 /*
1326 * DMA has completed. But if we're using DMA mode 1 (multi
1327 * packet DMA), we need a terminal TXPKTRDY interrupt before
1328 * we can consider this transfer completed, lest we trash
1329 * its last packet when writing the next URB's data. So we
1330 * switch back to mode 0 to get that interrupt; we'll come
1331 * back here once it happens.
1332 */
1333 if (tx_csr & MUSB_TXCSR_DMAMODE) {
1334 /*
1335 * We shouldn't clear DMAMODE with DMAENAB set; so
1336 * clear them in a safe order. That should be OK
1337 * once TXPKTRDY has been set (and I've never seen
1338 * it being 0 at this moment -- DMA interrupt latency
1339 * is significant) but if it hasn't been then we have
1340 * no choice but to stop being polite and ignore the
1341 * programmer's guide... :-)
1342 *
1343 * Note that we must write TXCSR with TXPKTRDY cleared
1344 * in order not to re-trigger the packet send (this bit
1345 * can't be cleared by CPU), and there's another caveat:
1346 * TXPKTRDY may be set shortly and then cleared in the
1347 * double-buffered FIFO mode, so we do an extra TXCSR
1348 * read for debouncing...
1349 */
1350 tx_csr &= musb_readw(epio, MUSB_TXCSR);
1351 if (tx_csr & MUSB_TXCSR_TXPKTRDY) {
1352 tx_csr &= ~(MUSB_TXCSR_DMAENAB |
1353 MUSB_TXCSR_TXPKTRDY);
1354 musb_writew(epio, MUSB_TXCSR,
1355 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1356 }
1357 tx_csr &= ~(MUSB_TXCSR_DMAMODE |
1358 MUSB_TXCSR_TXPKTRDY);
1359 musb_writew(epio, MUSB_TXCSR,
1360 tx_csr | MUSB_TXCSR_H_WZC_BITS);
1361
1362 /*
1363 * There is no guarantee that we'll get an interrupt
1364 * after clearing DMAMODE as we might have done this
1365 * too late (after TXPKTRDY was cleared by controller).
1366 * Re-read TXCSR as we have spoiled its previous value.
1367 */
1368 tx_csr = musb_readw(epio, MUSB_TXCSR);
1369 }
1370
1371 /*
1372 * We may get here from a DMA completion or TXPKTRDY interrupt.
1373 * In any case, we must check the FIFO status here and bail out
1374 * only if the FIFO still has data -- that should prevent the
1375 * "missed" TXPKTRDY interrupts and deal with double-buffered
1376 * FIFO mode too...
1377 */
1378 if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
1379 dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
1380 "CSR %04x\n", tx_csr);
1381 return;
1382 }
1383 }
1384
1385 if (!status || dma || usb_pipeisoc(pipe)) {
1386 if (dma)
1387 length = dma->actual_len;
1388 else
1389 length = qh->segsize;
1390 qh->offset += length;
1391
1392 if (usb_pipeisoc(pipe)) {
1393 struct usb_iso_packet_descriptor *d;
1394
1395 d = urb->iso_frame_desc + qh->iso_idx;
1396 d->actual_length = length;
1397 d->status = status;
1398 if (++qh->iso_idx >= urb->number_of_packets) {
1399 done = true;
1400 } else {
1401 d++;
1402 offset = d->offset;
1403 length = d->length;
1404 }
1405 } else if (dma && urb->transfer_buffer_length == qh->offset) {
1406 done = true;
1407 } else {
1408 /* see if we need to send more data, or ZLP */
1409 if (qh->segsize < qh->maxpacket)
1410 done = true;
1411 else if (qh->offset == urb->transfer_buffer_length
1412 && !(urb->transfer_flags
1413 & URB_ZERO_PACKET))
1414 done = true;
1415 if (!done) {
1416 offset = qh->offset;
1417 length = urb->transfer_buffer_length - offset;
1418 transfer_pending = true;
1419 }
1420 }
1421 }
1422
1423 /* urb->status != -EINPROGRESS means request has been faulted,
1424 * so we must abort this transfer after cleanup
1425 */
1426 if (urb->status != -EINPROGRESS) {
1427 done = true;
1428 if (status == 0)
1429 status = urb->status;
1430 }
1431
1432 if (done) {
1433 /* set status */
1434 urb->status = status;
1435 urb->actual_length = qh->offset;
1436 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_OUT);
1437 return;
1438 } else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
1439 if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
1440 offset, length)) {
1441 if (is_cppi_enabled() || tusb_dma_omap())
1442 musb_h_tx_dma_start(hw_ep);
1443 return;
1444 }
1445 } else if (tx_csr & MUSB_TXCSR_DMAENAB) {
1446 dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
1447 return;
1448 }
1449
1450 /*
1451 * PIO: start next packet in this URB.
1452 *
1453 * REVISIT: some docs say that when hw_ep->tx_double_buffered,
1454 * (and presumably, FIFO is not half-full) we should write *two*
1455 * packets before updating TXCSR; other docs disagree...
1456 */
1457 if (length > qh->maxpacket)
1458 length = qh->maxpacket;
1459 /* Unmap the buffer so that CPU can use it */
1460 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1461
1462 /*
1463 * We need to map sg if the transfer_buffer is
1464 * NULL.
1465 */
1466 if (!urb->transfer_buffer)
1467 qh->use_sg = true;
1468
1469 if (qh->use_sg) {
1470 /* sg_miter_start is already done in musb_ep_program */
1471 if (!sg_miter_next(&qh->sg_miter)) {
1472 dev_err(musb->controller, "error: sg list empty\n");
1473 sg_miter_stop(&qh->sg_miter);
1474 status = -EINVAL;
1475 goto done;
1476 }
1477 urb->transfer_buffer = qh->sg_miter.addr;
1478 length = min_t(u32, length, qh->sg_miter.length);
1479 musb_write_fifo(hw_ep, length, urb->transfer_buffer);
1480 qh->sg_miter.consumed = length;
1481 sg_miter_stop(&qh->sg_miter);
1482 } else {
1483 musb_write_fifo(hw_ep, length, urb->transfer_buffer + offset);
1484 }
1485
1486 qh->segsize = length;
1487
1488 if (qh->use_sg) {
1489 if (offset + length >= urb->transfer_buffer_length)
1490 qh->use_sg = false;
1491 }
1492
1493 musb_ep_select(mbase, epnum);
1494 musb_writew(epio, MUSB_TXCSR,
1495 MUSB_TXCSR_H_WZC_BITS | MUSB_TXCSR_TXPKTRDY);
1496 }
1497
1498
1499 #ifdef CONFIG_USB_INVENTRA_DMA
1500
1501 /* Host side RX (IN) using Mentor DMA works as follows:
1502 submit_urb ->
1503 - if queue was empty, ProgramEndpoint
1504 - first IN token is sent out (by setting ReqPkt)
1505 LinuxIsr -> RxReady()
1506 /\ => first packet is received
1507 | - Set in mode 0 (DmaEnab, ~ReqPkt)
1508 | -> DMA Isr (transfer complete) -> RxReady()
1509 | - Ack receive (~RxPktRdy), turn off DMA (~DmaEnab)
1510 | - if urb not complete, send next IN token (ReqPkt)
1511 | | else complete urb.
1512 | |
1513 ---------------------------
1514 *
1515 * Nuances of mode 1:
1516 * For short packets, no ack (+RxPktRdy) is sent automatically
1517 * (even if AutoClear is ON)
1518 * For full packets, ack (~RxPktRdy) and next IN token (+ReqPkt) is sent
1519 * automatically => major problem, as collecting the next packet becomes
1520 * difficult. Hence mode 1 is not used.
1521 *
1522 * REVISIT
1523 * All we care about at this driver level is that
1524 * (a) all URBs terminate with REQPKT cleared and fifo(s) empty;
1525 * (b) termination conditions are: short RX, or buffer full;
1526 * (c) fault modes include
1527 * - iff URB_SHORT_NOT_OK, short RX status is -EREMOTEIO.
1528 * (and that endpoint's dma queue stops immediately)
1529 * - overflow (full, PLUS more bytes in the terminal packet)
1530 *
1531 * So for example, usb-storage sets URB_SHORT_NOT_OK, and would
1532 * thus be a great candidate for using mode 1 ... for all but the
1533 * last packet of one URB's transfer.
1534 */
1535
1536 #endif
1537
1538 /*
1539 * Service an RX interrupt for the given IN endpoint; docs cover bulk, iso,
1540 * and high-bandwidth IN transfer cases.
1541 */
1542 void musb_host_rx(struct musb *musb, u8 epnum)
1543 {
1544 struct urb *urb;
1545 struct musb_hw_ep *hw_ep = musb->endpoints + epnum;
1546 void __iomem *epio = hw_ep->regs;
1547 struct musb_qh *qh = hw_ep->in_qh;
1548 size_t xfer_len;
1549 void __iomem *mbase = musb->mregs;
1550 int pipe;
1551 u16 rx_csr, val;
1552 bool iso_err = false;
1553 bool done = false;
1554 u32 status;
1555 struct dma_channel *dma;
1556 unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
1557
1558 musb_ep_select(mbase, epnum);
1559
1560 urb = next_urb(qh);
1561 dma = is_dma_capable() ? hw_ep->rx_channel : NULL;
1562 status = 0;
1563 xfer_len = 0;
1564
1565 rx_csr = musb_readw(epio, MUSB_RXCSR);
1566 val = rx_csr;
1567
1568 if (unlikely(!urb)) {
1569 /* REVISIT -- THIS SHOULD NEVER HAPPEN ... but, at least
1570 * usbtest #11 (unlinks) triggers it regularly, sometimes
1571 * with fifo full. (Only with DMA??)
1572 */
1573 dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
1574 musb_readw(epio, MUSB_RXCOUNT));
1575 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1576 return;
1577 }
1578
1579 pipe = urb->pipe;
1580
1581 dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
1582 epnum, rx_csr, urb->actual_length,
1583 dma ? dma->actual_len : 0);
1584
1585 /* check for errors, concurrent stall & unlink is not really
1586 * handled yet! */
1587 if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
1588 dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
1589
1590 /* stall; record URB status */
1591 status = -EPIPE;
1592
1593 } else if (rx_csr & MUSB_RXCSR_H_ERROR) {
1594 dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
1595
1596 status = -EPROTO;
1597 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1598
1599 } else if (rx_csr & MUSB_RXCSR_DATAERROR) {
1600
1601 if (USB_ENDPOINT_XFER_ISOC != qh->type) {
1602 dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
1603
1604 /* NOTE: NAKing is *NOT* an error, so we want to
1605 * continue. Except ... if there's a request for
1606 * another QH, use that instead of starving it.
1607 *
1608 * Devices like Ethernet and serial adapters keep
1609 * reads posted at all times, which will starve
1610 * other devices without this logic.
1611 */
1612 if (usb_pipebulk(urb->pipe)
1613 && qh->mux == 1
1614 && !list_is_singular(&musb->in_bulk)) {
1615 musb_bulk_nak_timeout(musb, hw_ep, 1);
1616 return;
1617 }
1618 musb_ep_select(mbase, epnum);
1619 rx_csr |= MUSB_RXCSR_H_WZC_BITS;
1620 rx_csr &= ~MUSB_RXCSR_DATAERROR;
1621 musb_writew(epio, MUSB_RXCSR, rx_csr);
1622
1623 goto finish;
1624 } else {
1625 dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
1626 /* packet error reported later */
1627 iso_err = true;
1628 }
1629 } else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
1630 dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
1631 epnum);
1632 status = -EPROTO;
1633 }
1634
1635 /* faults abort the transfer */
1636 if (status) {
1637 /* clean up dma and collect transfer count */
1638 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1639 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1640 (void) musb->dma_controller->channel_abort(dma);
1641 xfer_len = dma->actual_len;
1642 }
1643 musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
1644 musb_writeb(epio, MUSB_RXINTERVAL, 0);
1645 done = true;
1646 goto finish;
1647 }
1648
1649 if (unlikely(dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY)) {
1650 /* SHOULD NEVER HAPPEN ... but at least DaVinci has done it */
1651 ERR("RX%d dma busy, csr %04x\n", epnum, rx_csr);
1652 goto finish;
1653 }
1654
1655 /* thorough shutdown for now ... given more precise fault handling
1656 * and better queueing support, we might keep a DMA pipeline going
1657 * while processing this irq for earlier completions.
1658 */
1659
1660 /* FIXME this is _way_ too much in-line logic for Mentor DMA */
1661
1662 #if !defined(CONFIG_USB_INVENTRA_DMA) && !defined(CONFIG_USB_UX500_DMA)
1663 if (rx_csr & MUSB_RXCSR_H_REQPKT) {
1664 /* REVISIT this happened for a while on some short reads...
1665 * the cleanup still needs investigation... looks bad...
1666 * and also duplicates dma cleanup code above ... plus,
1667 * shouldn't this be the "half full" double buffer case?
1668 */
1669 if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
1670 dma->status = MUSB_DMA_STATUS_CORE_ABORT;
1671 (void) musb->dma_controller->channel_abort(dma);
1672 xfer_len = dma->actual_len;
1673 done = true;
1674 }
1675
1676 dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
1677 xfer_len, dma ? ", dma" : "");
1678 rx_csr &= ~MUSB_RXCSR_H_REQPKT;
1679
1680 musb_ep_select(mbase, epnum);
1681 musb_writew(epio, MUSB_RXCSR,
1682 MUSB_RXCSR_H_WZC_BITS | rx_csr);
1683 }
1684 #endif
1685 if (dma && (rx_csr & MUSB_RXCSR_DMAENAB)) {
1686 xfer_len = dma->actual_len;
1687
1688 val &= ~(MUSB_RXCSR_DMAENAB
1689 | MUSB_RXCSR_H_AUTOREQ
1690 | MUSB_RXCSR_AUTOCLEAR
1691 | MUSB_RXCSR_RXPKTRDY);
1692 musb_writew(hw_ep->regs, MUSB_RXCSR, val);
1693
1694 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
1695 if (usb_pipeisoc(pipe)) {
1696 struct usb_iso_packet_descriptor *d;
1697
1698 d = urb->iso_frame_desc + qh->iso_idx;
1699 d->actual_length = xfer_len;
1700
1701 /* even if there was an error, we did the dma
1702 * for iso_frame_desc->length
1703 */
1704 if (d->status != -EILSEQ && d->status != -EOVERFLOW)
1705 d->status = 0;
1706
1707 if (++qh->iso_idx >= urb->number_of_packets)
1708 done = true;
1709 else
1710 done = false;
1711
1712 } else {
1713 /* done if urb buffer is full or short packet is recd */
1714 done = (urb->actual_length + xfer_len >=
1715 urb->transfer_buffer_length
1716 || dma->actual_len < qh->maxpacket);
1717 }
1718
1719 /* send IN token for next packet, without AUTOREQ */
1720 if (!done) {
1721 val |= MUSB_RXCSR_H_REQPKT;
1722 musb_writew(epio, MUSB_RXCSR,
1723 MUSB_RXCSR_H_WZC_BITS | val);
1724 }
1725
1726 dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
1727 done ? "off" : "reset",
1728 musb_readw(epio, MUSB_RXCSR),
1729 musb_readw(epio, MUSB_RXCOUNT));
1730 #else
1731 done = true;
1732 #endif
1733 } else if (urb->status == -EINPROGRESS) {
1734 /* if no errors, be sure a packet is ready for unloading */
1735 if (unlikely(!(rx_csr & MUSB_RXCSR_RXPKTRDY))) {
1736 status = -EPROTO;
1737 ERR("Rx interrupt with no errors or packet!\n");
1738
1739 /* FIXME this is another "SHOULD NEVER HAPPEN" */
1740
1741 /* SCRUB (RX) */
1742 /* do the proper sequence to abort the transfer */
1743 musb_ep_select(mbase, epnum);
1744 val &= ~MUSB_RXCSR_H_REQPKT;
1745 musb_writew(epio, MUSB_RXCSR, val);
1746 goto finish;
1747 }
1748
1749 /* we are expecting IN packets */
1750 #if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
1751 if (dma) {
1752 struct dma_controller *c;
1753 u16 rx_count;
1754 int ret, length;
1755 dma_addr_t buf;
1756
1757 rx_count = musb_readw(epio, MUSB_RXCOUNT);
1758
1759 dev_dbg(musb->controller, "RX%d count %d, buffer 0x%llx len %d/%d\n",
1760 epnum, rx_count,
1761 (unsigned long long) urb->transfer_dma
1762 + urb->actual_length,
1763 qh->offset,
1764 urb->transfer_buffer_length);
1765
1766 c = musb->dma_controller;
1767
1768 if (usb_pipeisoc(pipe)) {
1769 int d_status = 0;
1770 struct usb_iso_packet_descriptor *d;
1771
1772 d = urb->iso_frame_desc + qh->iso_idx;
1773
1774 if (iso_err) {
1775 d_status = -EILSEQ;
1776 urb->error_count++;
1777 }
1778 if (rx_count > d->length) {
1779 if (d_status == 0) {
1780 d_status = -EOVERFLOW;
1781 urb->error_count++;
1782 }
1783 dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
1784 rx_count, d->length);
1785
1786 length = d->length;
1787 } else
1788 length = rx_count;
1789 d->status = d_status;
1790 buf = urb->transfer_dma + d->offset;
1791 } else {
1792 length = rx_count;
1793 buf = urb->transfer_dma +
1794 urb->actual_length;
1795 }
1796
1797 dma->desired_mode = 0;
1798 #ifdef USE_MODE1
1799 /* because of the issue below, mode 1 will
1800 * only rarely behave with correct semantics.
1801 */
1802 if ((urb->transfer_flags &
1803 URB_SHORT_NOT_OK)
1804 && (urb->transfer_buffer_length -
1805 urb->actual_length)
1806 > qh->maxpacket)
1807 dma->desired_mode = 1;
1808 if (rx_count < hw_ep->max_packet_sz_rx) {
1809 length = rx_count;
1810 dma->desired_mode = 0;
1811 } else {
1812 length = urb->transfer_buffer_length;
1813 }
1814 #endif
1815
1816 /* Disadvantage of using mode 1:
1817 * It's basically usable only for mass storage class; essentially all
1818 * other protocols also terminate transfers on short packets.
1819 *
1820 * Details:
1821 * An extra IN token is sent at the end of the transfer (due to AUTOREQ)
1822 * If you try to use mode 1 for (transfer_buffer_length - 512), and try
1823 * to use the extra IN token to grab the last packet using mode 0, then
1824 * the problem is that you cannot be sure when the device will send the
1825 * last packet and RxPktRdy set. Sometimes the packet is recd too soon
1826 * such that it gets lost when RxCSR is re-set at the end of the mode 1
1827 * transfer, while sometimes it is recd just a little late so that if you
1828 * try to configure for mode 0 soon after the mode 1 transfer is
1829 * completed, you will find rxcount 0. Okay, so you might think why not
1830 * wait for an interrupt when the pkt is recd. Well, you won't get any!
1831 */
1832
1833 val = musb_readw(epio, MUSB_RXCSR);
1834 val &= ~MUSB_RXCSR_H_REQPKT;
1835
1836 if (dma->desired_mode == 0)
1837 val &= ~MUSB_RXCSR_H_AUTOREQ;
1838 else
1839 val |= MUSB_RXCSR_H_AUTOREQ;
1840 val |= MUSB_RXCSR_DMAENAB;
1841
1842 /* autoclear shouldn't be set in high bandwidth */
1843 if (qh->hb_mult == 1)
1844 val |= MUSB_RXCSR_AUTOCLEAR;
1845
1846 musb_writew(epio, MUSB_RXCSR,
1847 MUSB_RXCSR_H_WZC_BITS | val);
1848
1849 /* REVISIT if when actual_length != 0,
1850 * transfer_buffer_length needs to be
1851 * adjusted first...
1852 */
1853 ret = c->channel_program(
1854 dma, qh->maxpacket,
1855 dma->desired_mode, buf, length);
1856
1857 if (!ret) {
1858 c->channel_release(dma);
1859 hw_ep->rx_channel = NULL;
1860 dma = NULL;
1861 val = musb_readw(epio, MUSB_RXCSR);
1862 val &= ~(MUSB_RXCSR_DMAENAB
1863 | MUSB_RXCSR_H_AUTOREQ
1864 | MUSB_RXCSR_AUTOCLEAR);
1865 musb_writew(epio, MUSB_RXCSR, val);
1866 }
1867 }
1868 #endif /* Mentor DMA */
1869
1870 if (!dma) {
1871 unsigned int received_len;
1872
1873 /* Unmap the buffer so that CPU can use it */
1874 usb_hcd_unmap_urb_for_dma(musb->hcd, urb);
1875
1876 /*
1877 * We need to map sg if the transfer_buffer is
1878 * NULL.
1879 */
1880 if (!urb->transfer_buffer) {
1881 qh->use_sg = true;
1882 sg_miter_start(&qh->sg_miter, urb->sg, 1,
1883 sg_flags);
1884 }
1885
1886 if (qh->use_sg) {
1887 if (!sg_miter_next(&qh->sg_miter)) {
1888 dev_err(musb->controller, "error: sg list empty\n");
1889 sg_miter_stop(&qh->sg_miter);
1890 status = -EINVAL;
1891 done = true;
1892 goto finish;
1893 }
1894 urb->transfer_buffer = qh->sg_miter.addr;
1895 received_len = urb->actual_length;
1896 qh->offset = 0x0;
1897 done = musb_host_packet_rx(musb, urb, epnum,
1898 iso_err);
1899 /* Calculate the number of bytes received */
1900 received_len = urb->actual_length -
1901 received_len;
1902 qh->sg_miter.consumed = received_len;
1903 sg_miter_stop(&qh->sg_miter);
1904 } else {
1905 done = musb_host_packet_rx(musb, urb,
1906 epnum, iso_err);
1907 }
1908 dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
1909 }
1910 }
1911
1912 finish:
1913 urb->actual_length += xfer_len;
1914 qh->offset += xfer_len;
1915 if (done) {
1916 if (qh->use_sg)
1917 qh->use_sg = false;
1918
1919 if (urb->status == -EINPROGRESS)
1920 urb->status = status;
1921 musb_advance_schedule(musb, urb, hw_ep, USB_DIR_IN);
1922 }
1923 }
1924
1925 /* schedule nodes correspond to peripheral endpoints, like an OHCI QH.
1926 * the software schedule associates multiple such nodes with a given
1927 * host side hardware endpoint + direction; scheduling may activate
1928 * that hardware endpoint.
1929 */
1930 static int musb_schedule(
1931 struct musb *musb,
1932 struct musb_qh *qh,
1933 int is_in)
1934 {
1935 int idle;
1936 int best_diff;
1937 int best_end, epnum;
1938 struct musb_hw_ep *hw_ep = NULL;
1939 struct list_head *head = NULL;
1940 u8 toggle;
1941 u8 txtype;
1942 struct urb *urb = next_urb(qh);
1943
1944 /* use fixed hardware for control and bulk */
1945 if (qh->type == USB_ENDPOINT_XFER_CONTROL) {
1946 head = &musb->control;
1947 hw_ep = musb->control_ep;
1948 goto success;
1949 }
1950
1951 /* else, periodic transfers get muxed to other endpoints */
1952
1953 /*
1954 * We know this qh hasn't been scheduled, so all we need to do
1955 * is choose which hardware endpoint to put it on ...
1956 *
1957 * REVISIT what we really want here is a regular schedule tree
1958 * like e.g. OHCI uses.
1959 */
1960 best_diff = 4096;
1961 best_end = -1;
1962
1963 for (epnum = 1, hw_ep = musb->endpoints + 1;
1964 epnum < musb->nr_endpoints;
1965 epnum++, hw_ep++) {
1966 int diff;
1967
1968 if (musb_ep_get_qh(hw_ep, is_in) != NULL)
1969 continue;
1970
1971 if (hw_ep == musb->bulk_ep)
1972 continue;
1973
1974 if (is_in)
1975 diff = hw_ep->max_packet_sz_rx;
1976 else
1977 diff = hw_ep->max_packet_sz_tx;
1978 diff -= (qh->maxpacket * qh->hb_mult);
1979
1980 if (diff >= 0 && best_diff > diff) {
1981
1982 /*
1983 * Mentor controller has a bug in that if we schedule
1984 * a BULK Tx transfer on an endpoint that had earlier
1985 * handled ISOC then the BULK transfer has to start on
1986 * a zero toggle. If the BULK transfer starts on a 1
1987 * toggle then this transfer will fail as the mentor
1988 * controller starts the Bulk transfer on a 0 toggle
1989 * irrespective of the programming of the toggle bits
1990 * in the TXCSR register. Check for this condition
1991 * while allocating the EP for a Tx Bulk transfer. If
1992 * so skip this EP.
1993 */
1994 hw_ep = musb->endpoints + epnum;
1995 toggle = usb_gettoggle(urb->dev, qh->epnum, !is_in);
1996 txtype = (musb_readb(hw_ep->regs, MUSB_TXTYPE)
1997 >> 4) & 0x3;
1998 if (!is_in && (qh->type == USB_ENDPOINT_XFER_BULK) &&
1999 toggle && (txtype == USB_ENDPOINT_XFER_ISOC))
2000 continue;
2001
2002 best_diff = diff;
2003 best_end = epnum;
2004 }
2005 }
2006 /* use bulk reserved ep1 if no other ep is free */
2007 if (best_end < 0 && qh->type == USB_ENDPOINT_XFER_BULK) {
2008 hw_ep = musb->bulk_ep;
2009 if (is_in)
2010 head = &musb->in_bulk;
2011 else
2012 head = &musb->out_bulk;
2013
2014 /* Enable bulk RX/TX NAK timeout scheme when bulk requests are
2015 * multiplexed. This scheme does not work in high speed to full
2016 * speed scenario as NAK interrupts are not coming from a
2017 * full speed device connected to a high speed device.
2018 * NAK timeout interval is 8 (128 uframe or 16ms) for HS and
2019 * 4 (8 frame or 8ms) for FS device.
2020 */
2021 if (qh->dev)
2022 qh->intv_reg =
2023 (USB_SPEED_HIGH == qh->dev->speed) ? 8 : 4;
2024 goto success;
2025 } else if (best_end < 0) {
2026 return -ENOSPC;
2027 }
2028
2029 idle = 1;
2030 qh->mux = 0;
2031 hw_ep = musb->endpoints + best_end;
2032 dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
2033 success:
2034 if (head) {
2035 idle = list_empty(head);
2036 list_add_tail(&qh->ring, head);
2037 qh->mux = 1;
2038 }
2039 qh->hw_ep = hw_ep;
2040 qh->hep->hcpriv = qh;
2041 if (idle)
2042 musb_start_urb(musb, is_in, qh);
2043 return 0;
2044 }
2045
2046 static int musb_urb_enqueue(
2047 struct usb_hcd *hcd,
2048 struct urb *urb,
2049 gfp_t mem_flags)
2050 {
2051 unsigned long flags;
2052 struct musb *musb = hcd_to_musb(hcd);
2053 struct usb_host_endpoint *hep = urb->ep;
2054 struct musb_qh *qh;
2055 struct usb_endpoint_descriptor *epd = &hep->desc;
2056 int ret;
2057 unsigned type_reg;
2058 unsigned interval;
2059
2060 /* host role must be active */
2061 if (!is_host_active(musb) || !musb->is_active)
2062 return -ENODEV;
2063
2064 spin_lock_irqsave(&musb->lock, flags);
2065 ret = usb_hcd_link_urb_to_ep(hcd, urb);
2066 qh = ret ? NULL : hep->hcpriv;
2067 if (qh)
2068 urb->hcpriv = qh;
2069 spin_unlock_irqrestore(&musb->lock, flags);
2070
2071 /* DMA mapping was already done, if needed, and this urb is on
2072 * hep->urb_list now ... so we're done, unless hep wasn't yet
2073 * scheduled onto a live qh.
2074 *
2075 * REVISIT best to keep hep->hcpriv valid until the endpoint gets
2076 * disabled, testing for empty qh->ring and avoiding qh setup costs
2077 * except for the first urb queued after a config change.
2078 */
2079 if (qh || ret)
2080 return ret;
2081
2082 /* Allocate and initialize qh, minimizing the work done each time
2083 * hw_ep gets reprogrammed, or with irqs blocked. Then schedule it.
2084 *
2085 * REVISIT consider a dedicated qh kmem_cache, so it's harder
2086 * for bugs in other kernel code to break this driver...
2087 */
2088 qh = kzalloc(sizeof *qh, mem_flags);
2089 if (!qh) {
2090 spin_lock_irqsave(&musb->lock, flags);
2091 usb_hcd_unlink_urb_from_ep(hcd, urb);
2092 spin_unlock_irqrestore(&musb->lock, flags);
2093 return -ENOMEM;
2094 }
2095
2096 qh->hep = hep;
2097 qh->dev = urb->dev;
2098 INIT_LIST_HEAD(&qh->ring);
2099 qh->is_ready = 1;
2100
2101 qh->maxpacket = usb_endpoint_maxp(epd);
2102 qh->type = usb_endpoint_type(epd);
2103
2104 /* Bits 11 & 12 of wMaxPacketSize encode high bandwidth multiplier.
2105 * Some musb cores don't support high bandwidth ISO transfers; and
2106 * we don't (yet!) support high bandwidth interrupt transfers.
2107 */
2108 qh->hb_mult = 1 + ((qh->maxpacket >> 11) & 0x03);
2109 if (qh->hb_mult > 1) {
2110 int ok = (qh->type == USB_ENDPOINT_XFER_ISOC);
2111
2112 if (ok)
2113 ok = (usb_pipein(urb->pipe) && musb->hb_iso_rx)
2114 || (usb_pipeout(urb->pipe) && musb->hb_iso_tx);
2115 if (!ok) {
2116 ret = -EMSGSIZE;
2117 goto done;
2118 }
2119 qh->maxpacket &= 0x7ff;
2120 }
2121
2122 qh->epnum = usb_endpoint_num(epd);
2123
2124 /* NOTE: urb->dev->devnum is wrong during SET_ADDRESS */
2125 qh->addr_reg = (u8) usb_pipedevice(urb->pipe);
2126
2127 /* precompute rxtype/txtype/type0 register */
2128 type_reg = (qh->type << 4) | qh->epnum;
2129 switch (urb->dev->speed) {
2130 case USB_SPEED_LOW:
2131 type_reg |= 0xc0;
2132 break;
2133 case USB_SPEED_FULL:
2134 type_reg |= 0x80;
2135 break;
2136 default:
2137 type_reg |= 0x40;
2138 }
2139 qh->type_reg = type_reg;
2140
2141 /* Precompute RXINTERVAL/TXINTERVAL register */
2142 switch (qh->type) {
2143 case USB_ENDPOINT_XFER_INT:
2144 /*
2145 * Full/low speeds use the linear encoding,
2146 * high speed uses the logarithmic encoding.
2147 */
2148 if (urb->dev->speed <= USB_SPEED_FULL) {
2149 interval = max_t(u8, epd->bInterval, 1);
2150 break;
2151 }
2152 /* FALLTHROUGH */
2153 case USB_ENDPOINT_XFER_ISOC:
2154 /* ISO always uses logarithmic encoding */
2155 interval = min_t(u8, epd->bInterval, 16);
2156 break;
2157 default:
2158 /* REVISIT we actually want to use NAK limits, hinting to the
2159 * transfer scheduling logic to try some other qh, e.g. try
2160 * for 2 msec first:
2161 *
2162 * interval = (USB_SPEED_HIGH == urb->dev->speed) ? 16 : 2;
2163 *
2164 * The downside of disabling this is that transfer scheduling
2165 * gets VERY unfair for nonperiodic transfers; a misbehaving
2166 * peripheral could make that hurt. That's perfectly normal
2167 * for reads from network or serial adapters ... so we have
2168 * partial NAKlimit support for bulk RX.
2169 *
2170 * The upside of disabling it is simpler transfer scheduling.
2171 */
2172 interval = 0;
2173 }
2174 qh->intv_reg = interval;
2175
2176 /* precompute addressing for external hub/tt ports */
2177 if (musb->is_multipoint) {
2178 struct usb_device *parent = urb->dev->parent;
2179
2180 if (parent != hcd->self.root_hub) {
2181 qh->h_addr_reg = (u8) parent->devnum;
2182
2183 /* set up tt info if needed */
2184 if (urb->dev->tt) {
2185 qh->h_port_reg = (u8) urb->dev->ttport;
2186 if (urb->dev->tt->hub)
2187 qh->h_addr_reg =
2188 (u8) urb->dev->tt->hub->devnum;
2189 if (urb->dev->tt->multi)
2190 qh->h_addr_reg |= 0x80;
2191 }
2192 }
2193 }
2194
2195 /* invariant: hep->hcpriv is null OR the qh that's already scheduled.
2196 * until we get real dma queues (with an entry for each urb/buffer),
2197 * we only have work to do in the former case.
2198 */
2199 spin_lock_irqsave(&musb->lock, flags);
2200 if (hep->hcpriv || !next_urb(qh)) {
2201 /* some concurrent activity submitted another urb to hep...
2202 * odd, rare, error prone, but legal.
2203 */
2204 kfree(qh);
2205 qh = NULL;
2206 ret = 0;
2207 } else
2208 ret = musb_schedule(musb, qh,
2209 epd->bEndpointAddress & USB_ENDPOINT_DIR_MASK);
2210
2211 if (ret == 0) {
2212 urb->hcpriv = qh;
2213 /* FIXME set urb->start_frame for iso/intr, it's tested in
2214 * musb_start_urb(), but otherwise only konicawc cares ...
2215 */
2216 }
2217 spin_unlock_irqrestore(&musb->lock, flags);
2218
2219 done:
2220 if (ret != 0) {
2221 spin_lock_irqsave(&musb->lock, flags);
2222 usb_hcd_unlink_urb_from_ep(hcd, urb);
2223 spin_unlock_irqrestore(&musb->lock, flags);
2224 kfree(qh);
2225 }
2226 return ret;
2227 }
2228
2229
2230 /*
2231 * abort a transfer that's at the head of a hardware queue.
2232 * called with controller locked, irqs blocked
2233 * that hardware queue advances to the next transfer, unless prevented
2234 */
2235 static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
2236 {
2237 struct musb_hw_ep *ep = qh->hw_ep;
2238 struct musb *musb = ep->musb;
2239 void __iomem *epio = ep->regs;
2240 unsigned hw_end = ep->epnum;
2241 void __iomem *regs = ep->musb->mregs;
2242 int is_in = usb_pipein(urb->pipe);
2243 int status = 0;
2244 u16 csr;
2245
2246 musb_ep_select(regs, hw_end);
2247
2248 if (is_dma_capable()) {
2249 struct dma_channel *dma;
2250
2251 dma = is_in ? ep->rx_channel : ep->tx_channel;
2252 if (dma) {
2253 status = ep->musb->dma_controller->channel_abort(dma);
2254 dev_dbg(musb->controller,
2255 "abort %cX%d DMA for urb %p --> %d\n",
2256 is_in ? 'R' : 'T', ep->epnum,
2257 urb, status);
2258 urb->actual_length += dma->actual_len;
2259 }
2260 }
2261
2262 /* turn off DMA requests, discard state, stop polling ... */
2263 if (ep->epnum && is_in) {
2264 /* giveback saves bulk toggle */
2265 csr = musb_h_flush_rxfifo(ep, 0);
2266
2267 /* REVISIT we still get an irq; should likely clear the
2268 * endpoint's irq status here to avoid bogus irqs.
2269 * clearing that status is platform-specific...
2270 */
2271 } else if (ep->epnum) {
2272 musb_h_tx_flush_fifo(ep);
2273 csr = musb_readw(epio, MUSB_TXCSR);
2274 csr &= ~(MUSB_TXCSR_AUTOSET
2275 | MUSB_TXCSR_DMAENAB
2276 | MUSB_TXCSR_H_RXSTALL
2277 | MUSB_TXCSR_H_NAKTIMEOUT
2278 | MUSB_TXCSR_H_ERROR
2279 | MUSB_TXCSR_TXPKTRDY);
2280 musb_writew(epio, MUSB_TXCSR, csr);
2281 /* REVISIT may need to clear FLUSHFIFO ... */
2282 musb_writew(epio, MUSB_TXCSR, csr);
2283 /* flush cpu writebuffer */
2284 csr = musb_readw(epio, MUSB_TXCSR);
2285 } else {
2286 musb_h_ep0_flush_fifo(ep);
2287 }
2288 if (status == 0)
2289 musb_advance_schedule(ep->musb, urb, ep, is_in);
2290 return status;
2291 }
2292
2293 static int musb_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
2294 {
2295 struct musb *musb = hcd_to_musb(hcd);
2296 struct musb_qh *qh;
2297 unsigned long flags;
2298 int is_in = usb_pipein(urb->pipe);
2299 int ret;
2300
2301 dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
2302 usb_pipedevice(urb->pipe),
2303 usb_pipeendpoint(urb->pipe),
2304 is_in ? "in" : "out");
2305
2306 spin_lock_irqsave(&musb->lock, flags);
2307 ret = usb_hcd_check_unlink_urb(hcd, urb, status);
2308 if (ret)
2309 goto done;
2310
2311 qh = urb->hcpriv;
2312 if (!qh)
2313 goto done;
2314
2315 /*
2316 * Any URB not actively programmed into endpoint hardware can be
2317 * immediately given back; that's any URB not at the head of an
2318 * endpoint queue, unless someday we get real DMA queues. And even
2319 * if it's at the head, it might not be known to the hardware...
2320 *
2321 * Otherwise abort current transfer, pending DMA, etc.; urb->status
2322 * has already been updated. This is a synchronous abort; it'd be
2323 * OK to hold off until after some IRQ, though.
2324 *
2325 * NOTE: qh is invalid unless !list_empty(&hep->urb_list)
2326 */
2327 if (!qh->is_ready
2328 || urb->urb_list.prev != &qh->hep->urb_list
2329 || musb_ep_get_qh(qh->hw_ep, is_in) != qh) {
2330 int ready = qh->is_ready;
2331
2332 qh->is_ready = 0;
2333 musb_giveback(musb, urb, 0);
2334 qh->is_ready = ready;
2335
2336 /* If nothing else (usually musb_giveback) is using it
2337 * and its URB list has emptied, recycle this qh.
2338 */
2339 if (ready && list_empty(&qh->hep->urb_list)) {
2340 qh->hep->hcpriv = NULL;
2341 list_del(&qh->ring);
2342 kfree(qh);
2343 }
2344 } else
2345 ret = musb_cleanup_urb(urb, qh);
2346 done:
2347 spin_unlock_irqrestore(&musb->lock, flags);
2348 return ret;
2349 }
2350
2351 /* disable an endpoint */
2352 static void
2353 musb_h_disable(struct usb_hcd *hcd, struct usb_host_endpoint *hep)
2354 {
2355 u8 is_in = hep->desc.bEndpointAddress & USB_DIR_IN;
2356 unsigned long flags;
2357 struct musb *musb = hcd_to_musb(hcd);
2358 struct musb_qh *qh;
2359 struct urb *urb;
2360
2361 spin_lock_irqsave(&musb->lock, flags);
2362
2363 qh = hep->hcpriv;
2364 if (qh == NULL)
2365 goto exit;
2366
2367 /* NOTE: qh is invalid unless !list_empty(&hep->urb_list) */
2368
2369 /* Kick the first URB off the hardware, if needed */
2370 qh->is_ready = 0;
2371 if (musb_ep_get_qh(qh->hw_ep, is_in) == qh) {
2372 urb = next_urb(qh);
2373
2374 /* make software (then hardware) stop ASAP */
2375 if (!urb->unlinked)
2376 urb->status = -ESHUTDOWN;
2377
2378 /* cleanup */
2379 musb_cleanup_urb(urb, qh);
2380
2381 /* Then nuke all the others ... and advance the
2382 * queue on hw_ep (e.g. bulk ring) when we're done.
2383 */
2384 while (!list_empty(&hep->urb_list)) {
2385 urb = next_urb(qh);
2386 urb->status = -ESHUTDOWN;
2387 musb_advance_schedule(musb, urb, qh->hw_ep, is_in);
2388 }
2389 } else {
2390 /* Just empty the queue; the hardware is busy with
2391 * other transfers, and since !qh->is_ready nothing
2392 * will activate any of these as it advances.
2393 */
2394 while (!list_empty(&hep->urb_list))
2395 musb_giveback(musb, next_urb(qh), -ESHUTDOWN);
2396
2397 hep->hcpriv = NULL;
2398 list_del(&qh->ring);
2399 kfree(qh);
2400 }
2401 exit:
2402 spin_unlock_irqrestore(&musb->lock, flags);
2403 }
2404
2405 static int musb_h_get_frame_number(struct usb_hcd *hcd)
2406 {
2407 struct musb *musb = hcd_to_musb(hcd);
2408
2409 return musb_readw(musb->mregs, MUSB_FRAME);
2410 }
2411
2412 static int musb_h_start(struct usb_hcd *hcd)
2413 {
2414 struct musb *musb = hcd_to_musb(hcd);
2415
2416 /* NOTE: musb_start() is called when the hub driver turns
2417 * on port power, or when (OTG) peripheral starts.
2418 */
2419 hcd->state = HC_STATE_RUNNING;
2420 musb->port1_status = 0;
2421 return 0;
2422 }
2423
2424 static void musb_h_stop(struct usb_hcd *hcd)
2425 {
2426 musb_stop(hcd_to_musb(hcd));
2427 hcd->state = HC_STATE_HALT;
2428 }
2429
2430 static int musb_bus_suspend(struct usb_hcd *hcd)
2431 {
2432 struct musb *musb = hcd_to_musb(hcd);
2433 u8 devctl;
2434
2435 musb_port_suspend(musb, true);
2436
2437 if (!is_host_active(musb))
2438 return 0;
2439
2440 switch (musb->xceiv->state) {
2441 case OTG_STATE_A_SUSPEND:
2442 return 0;
2443 case OTG_STATE_A_WAIT_VRISE:
2444 /* ID could be grounded even if there's no device
2445 * on the other end of the cable. NOTE that the
2446 * A_WAIT_VRISE timers are messy with MUSB...
2447 */
2448 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2449 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
2450 musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
2451 break;
2452 default:
2453 break;
2454 }
2455
2456 if (musb->is_active) {
2457 WARNING("trying to suspend as %s while active\n",
2458 usb_otg_state_string(musb->xceiv->state));
2459 return -EBUSY;
2460 } else
2461 return 0;
2462 }
2463
2464 static int musb_bus_resume(struct usb_hcd *hcd)
2465 {
2466 struct musb *musb = hcd_to_musb(hcd);
2467
2468 if (musb->config &&
2469 musb->config->host_port_deassert_reset_at_resume)
2470 musb_port_reset(musb, false);
2471
2472 return 0;
2473 }
2474
2475 #ifndef CONFIG_MUSB_PIO_ONLY
2476
2477 #define MUSB_USB_DMA_ALIGN 4
2478
2479 struct musb_temp_buffer {
2480 void *kmalloc_ptr;
2481 void *old_xfer_buffer;
2482 u8 data[0];
2483 };
2484
2485 static void musb_free_temp_buffer(struct urb *urb)
2486 {
2487 enum dma_data_direction dir;
2488 struct musb_temp_buffer *temp;
2489
2490 if (!(urb->transfer_flags & URB_ALIGNED_TEMP_BUFFER))
2491 return;
2492
2493 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2494
2495 temp = container_of(urb->transfer_buffer, struct musb_temp_buffer,
2496 data);
2497
2498 if (dir == DMA_FROM_DEVICE) {
2499 memcpy(temp->old_xfer_buffer, temp->data,
2500 urb->transfer_buffer_length);
2501 }
2502 urb->transfer_buffer = temp->old_xfer_buffer;
2503 kfree(temp->kmalloc_ptr);
2504
2505 urb->transfer_flags &= ~URB_ALIGNED_TEMP_BUFFER;
2506 }
2507
2508 static int musb_alloc_temp_buffer(struct urb *urb, gfp_t mem_flags)
2509 {
2510 enum dma_data_direction dir;
2511 struct musb_temp_buffer *temp;
2512 void *kmalloc_ptr;
2513 size_t kmalloc_size;
2514
2515 if (urb->num_sgs || urb->sg ||
2516 urb->transfer_buffer_length == 0 ||
2517 !((uintptr_t)urb->transfer_buffer & (MUSB_USB_DMA_ALIGN - 1)))
2518 return 0;
2519
2520 dir = usb_urb_dir_in(urb) ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
2521
2522 /* Allocate a buffer with enough padding for alignment */
2523 kmalloc_size = urb->transfer_buffer_length +
2524 sizeof(struct musb_temp_buffer) + MUSB_USB_DMA_ALIGN - 1;
2525
2526 kmalloc_ptr = kmalloc(kmalloc_size, mem_flags);
2527 if (!kmalloc_ptr)
2528 return -ENOMEM;
2529
2530 /* Position our struct temp_buffer such that data is aligned */
2531 temp = PTR_ALIGN(kmalloc_ptr, MUSB_USB_DMA_ALIGN);
2532
2533
2534 temp->kmalloc_ptr = kmalloc_ptr;
2535 temp->old_xfer_buffer = urb->transfer_buffer;
2536 if (dir == DMA_TO_DEVICE)
2537 memcpy(temp->data, urb->transfer_buffer,
2538 urb->transfer_buffer_length);
2539 urb->transfer_buffer = temp->data;
2540
2541 urb->transfer_flags |= URB_ALIGNED_TEMP_BUFFER;
2542
2543 return 0;
2544 }
2545
2546 static int musb_map_urb_for_dma(struct usb_hcd *hcd, struct urb *urb,
2547 gfp_t mem_flags)
2548 {
2549 struct musb *musb = hcd_to_musb(hcd);
2550 int ret;
2551
2552 /*
2553 * The DMA engine in RTL1.8 and above cannot handle
2554 * DMA addresses that are not aligned to a 4 byte boundary.
2555 * For such engine implemented (un)map_urb_for_dma hooks.
2556 * Do not use these hooks for RTL<1.8
2557 */
2558 if (musb->hwvers < MUSB_HWVERS_1800)
2559 return usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2560
2561 ret = musb_alloc_temp_buffer(urb, mem_flags);
2562 if (ret)
2563 return ret;
2564
2565 ret = usb_hcd_map_urb_for_dma(hcd, urb, mem_flags);
2566 if (ret)
2567 musb_free_temp_buffer(urb);
2568
2569 return ret;
2570 }
2571
2572 static void musb_unmap_urb_for_dma(struct usb_hcd *hcd, struct urb *urb)
2573 {
2574 struct musb *musb = hcd_to_musb(hcd);
2575
2576 usb_hcd_unmap_urb_for_dma(hcd, urb);
2577
2578 /* Do not use this hook for RTL<1.8 (see description above) */
2579 if (musb->hwvers < MUSB_HWVERS_1800)
2580 return;
2581
2582 musb_free_temp_buffer(urb);
2583 }
2584 #endif /* !CONFIG_MUSB_PIO_ONLY */
2585
2586 static const struct hc_driver musb_hc_driver = {
2587 .description = "musb-hcd",
2588 .product_desc = "MUSB HDRC host driver",
2589 .hcd_priv_size = sizeof(struct musb *),
2590 .flags = HCD_USB2 | HCD_MEMORY,
2591
2592 /* not using irq handler or reset hooks from usbcore, since
2593 * those must be shared with peripheral code for OTG configs
2594 */
2595
2596 .start = musb_h_start,
2597 .stop = musb_h_stop,
2598
2599 .get_frame_number = musb_h_get_frame_number,
2600
2601 .urb_enqueue = musb_urb_enqueue,
2602 .urb_dequeue = musb_urb_dequeue,
2603 .endpoint_disable = musb_h_disable,
2604
2605 #ifndef CONFIG_MUSB_PIO_ONLY
2606 .map_urb_for_dma = musb_map_urb_for_dma,
2607 .unmap_urb_for_dma = musb_unmap_urb_for_dma,
2608 #endif
2609
2610 .hub_status_data = musb_hub_status_data,
2611 .hub_control = musb_hub_control,
2612 .bus_suspend = musb_bus_suspend,
2613 .bus_resume = musb_bus_resume,
2614 /* .start_port_reset = NULL, */
2615 /* .hub_irq_enable = NULL, */
2616 };
2617
2618 int musb_host_alloc(struct musb *musb)
2619 {
2620 struct device *dev = musb->controller;
2621
2622 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2623 musb->hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2624 if (!musb->hcd)
2625 return -EINVAL;
2626
2627 *musb->hcd->hcd_priv = (unsigned long) musb;
2628 musb->hcd->self.uses_pio_for_control = 1;
2629 musb->hcd->uses_new_polling = 1;
2630 musb->hcd->has_tt = 1;
2631
2632 return 0;
2633 }
2634
2635 void musb_host_cleanup(struct musb *musb)
2636 {
2637 if (musb->port_mode == MUSB_PORT_MODE_GADGET)
2638 return;
2639 usb_remove_hcd(musb->hcd);
2640 musb->hcd = NULL;
2641 }
2642
2643 void musb_host_free(struct musb *musb)
2644 {
2645 usb_put_hcd(musb->hcd);
2646 }
2647
2648 int musb_host_setup(struct musb *musb, int power_budget)
2649 {
2650 int ret;
2651 struct usb_hcd *hcd = musb->hcd;
2652
2653 MUSB_HST_MODE(musb);
2654 musb->xceiv->otg->default_a = 1;
2655 musb->xceiv->state = OTG_STATE_A_IDLE;
2656
2657 otg_set_host(musb->xceiv->otg, &hcd->self);
2658 hcd->self.otg_port = 1;
2659 musb->xceiv->otg->host = &hcd->self;
2660 hcd->power_budget = 2 * (power_budget ? : 250);
2661
2662 ret = usb_add_hcd(hcd, 0, 0);
2663 if (ret < 0)
2664 return ret;
2665
2666 device_wakeup_enable(hcd->self.controller);
2667 return 0;
2668 }
2669
2670 void musb_host_resume_root_hub(struct musb *musb)
2671 {
2672 usb_hcd_resume_root_hub(musb->hcd);
2673 }
2674
2675 void musb_host_poke_root_hub(struct musb *musb)
2676 {
2677 MUSB_HST_MODE(musb);
2678 if (musb->hcd->status_urb)
2679 usb_hcd_poll_rh_status(musb->hcd);
2680 else
2681 usb_hcd_resume_root_hub(musb->hcd);
2682 }
Linux with added FPC-III support