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PM / sleep: Asynchronous threads for suspend_noirq
[linux/fpc-iii.git] / drivers / video / da8xx-fb.c
bloba1d74dd119884b26a0b8ceaa91650846402f5878
1 /*
2 * Copyright (C) 2008-2009 MontaVista Software Inc.
3 * Copyright (C) 2008-2009 Texas Instruments Inc
4 *
5 * Based on the LCD driver for TI Avalanche processors written by
6 * Ajay Singh and Shalom Hai.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option)any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/fb.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/uaccess.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/interrupt.h>
31 #include <linux/wait.h>
32 #include <linux/clk.h>
33 #include <linux/cpufreq.h>
34 #include <linux/console.h>
35 #include <linux/spinlock.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <linux/lcm.h>
39 #include <video/da8xx-fb.h>
40 #include <asm/div64.h>
41
42 #define DRIVER_NAME "da8xx_lcdc"
43
44 #define LCD_VERSION_1 1
45 #define LCD_VERSION_2 2
46
47 /* LCD Status Register */
48 #define LCD_END_OF_FRAME1 BIT(9)
49 #define LCD_END_OF_FRAME0 BIT(8)
50 #define LCD_PL_LOAD_DONE BIT(6)
51 #define LCD_FIFO_UNDERFLOW BIT(5)
52 #define LCD_SYNC_LOST BIT(2)
53 #define LCD_FRAME_DONE BIT(0)
54
55 /* LCD DMA Control Register */
56 #define LCD_DMA_BURST_SIZE(x) ((x) << 4)
57 #define LCD_DMA_BURST_1 0x0
58 #define LCD_DMA_BURST_2 0x1
59 #define LCD_DMA_BURST_4 0x2
60 #define LCD_DMA_BURST_8 0x3
61 #define LCD_DMA_BURST_16 0x4
62 #define LCD_V1_END_OF_FRAME_INT_ENA BIT(2)
63 #define LCD_V2_END_OF_FRAME0_INT_ENA BIT(8)
64 #define LCD_V2_END_OF_FRAME1_INT_ENA BIT(9)
65 #define LCD_DUAL_FRAME_BUFFER_ENABLE BIT(0)
66
67 /* LCD Control Register */
68 #define LCD_CLK_DIVISOR(x) ((x) << 8)
69 #define LCD_RASTER_MODE 0x01
70
71 /* LCD Raster Control Register */
72 #define LCD_PALETTE_LOAD_MODE(x) ((x) << 20)
73 #define PALETTE_AND_DATA 0x00
74 #define PALETTE_ONLY 0x01
75 #define DATA_ONLY 0x02
76
77 #define LCD_MONO_8BIT_MODE BIT(9)
78 #define LCD_RASTER_ORDER BIT(8)
79 #define LCD_TFT_MODE BIT(7)
80 #define LCD_V1_UNDERFLOW_INT_ENA BIT(6)
81 #define LCD_V2_UNDERFLOW_INT_ENA BIT(5)
82 #define LCD_V1_PL_INT_ENA BIT(4)
83 #define LCD_V2_PL_INT_ENA BIT(6)
84 #define LCD_MONOCHROME_MODE BIT(1)
85 #define LCD_RASTER_ENABLE BIT(0)
86 #define LCD_TFT_ALT_ENABLE BIT(23)
87 #define LCD_STN_565_ENABLE BIT(24)
88 #define LCD_V2_DMA_CLK_EN BIT(2)
89 #define LCD_V2_LIDD_CLK_EN BIT(1)
90 #define LCD_V2_CORE_CLK_EN BIT(0)
91 #define LCD_V2_LPP_B10 26
92 #define LCD_V2_TFT_24BPP_MODE BIT(25)
93 #define LCD_V2_TFT_24BPP_UNPACK BIT(26)
94
95 /* LCD Raster Timing 2 Register */
96 #define LCD_AC_BIAS_TRANSITIONS_PER_INT(x) ((x) << 16)
97 #define LCD_AC_BIAS_FREQUENCY(x) ((x) << 8)
98 #define LCD_SYNC_CTRL BIT(25)
99 #define LCD_SYNC_EDGE BIT(24)
100 #define LCD_INVERT_PIXEL_CLOCK BIT(22)
101 #define LCD_INVERT_LINE_CLOCK BIT(21)
102 #define LCD_INVERT_FRAME_CLOCK BIT(20)
103
104 /* LCD Block */
105 #define LCD_PID_REG 0x0
106 #define LCD_CTRL_REG 0x4
107 #define LCD_STAT_REG 0x8
108 #define LCD_RASTER_CTRL_REG 0x28
109 #define LCD_RASTER_TIMING_0_REG 0x2C
110 #define LCD_RASTER_TIMING_1_REG 0x30
111 #define LCD_RASTER_TIMING_2_REG 0x34
112 #define LCD_DMA_CTRL_REG 0x40
113 #define LCD_DMA_FRM_BUF_BASE_ADDR_0_REG 0x44
114 #define LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG 0x48
115 #define LCD_DMA_FRM_BUF_BASE_ADDR_1_REG 0x4C
116 #define LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG 0x50
117
118 /* Interrupt Registers available only in Version 2 */
119 #define LCD_RAW_STAT_REG 0x58
120 #define LCD_MASKED_STAT_REG 0x5c
121 #define LCD_INT_ENABLE_SET_REG 0x60
122 #define LCD_INT_ENABLE_CLR_REG 0x64
123 #define LCD_END_OF_INT_IND_REG 0x68
124
125 /* Clock registers available only on Version 2 */
126 #define LCD_CLK_ENABLE_REG 0x6c
127 #define LCD_CLK_RESET_REG 0x70
128 #define LCD_CLK_MAIN_RESET BIT(3)
129
130 #define LCD_NUM_BUFFERS 2
131
132 #define PALETTE_SIZE 256
133
134 #define CLK_MIN_DIV 2
135 #define CLK_MAX_DIV 255
136
137 static void __iomem *da8xx_fb_reg_base;
138 static unsigned int lcd_revision;
139 static irq_handler_t lcdc_irq_handler;
140 static wait_queue_head_t frame_done_wq;
141 static int frame_done_flag;
142
143 static unsigned int lcdc_read(unsigned int addr)
144 {
145 return (unsigned int)__raw_readl(da8xx_fb_reg_base + (addr));
146 }
147
148 static void lcdc_write(unsigned int val, unsigned int addr)
149 {
150 __raw_writel(val, da8xx_fb_reg_base + (addr));
151 }
152
153 struct da8xx_fb_par {
154 struct device *dev;
155 resource_size_t p_palette_base;
156 unsigned char *v_palette_base;
157 dma_addr_t vram_phys;
158 unsigned long vram_size;
159 void *vram_virt;
160 unsigned int dma_start;
161 unsigned int dma_end;
162 struct clk *lcdc_clk;
163 int irq;
164 unsigned int palette_sz;
165 int blank;
166 wait_queue_head_t vsync_wait;
167 int vsync_flag;
168 int vsync_timeout;
169 spinlock_t lock_for_chan_update;
170
171 /*
172 * LCDC has 2 ping pong DMA channels, channel 0
173 * and channel 1.
174 */
175 unsigned int which_dma_channel_done;
176 #ifdef CONFIG_CPU_FREQ
177 struct notifier_block freq_transition;
178 #endif
179 unsigned int lcdc_clk_rate;
180 void (*panel_power_ctrl)(int);
181 u32 pseudo_palette[16];
182 struct fb_videomode mode;
183 struct lcd_ctrl_config cfg;
184 };
185
186 static struct fb_var_screeninfo da8xx_fb_var;
187
188 static struct fb_fix_screeninfo da8xx_fb_fix = {
189 .id = "DA8xx FB Drv",
190 .type = FB_TYPE_PACKED_PIXELS,
191 .type_aux = 0,
192 .visual = FB_VISUAL_PSEUDOCOLOR,
193 .xpanstep = 0,
194 .ypanstep = 1,
195 .ywrapstep = 0,
196 .accel = FB_ACCEL_NONE
197 };
198
199 static struct fb_videomode known_lcd_panels[] = {
200 /* Sharp LCD035Q3DG01 */
201 [0] = {
202 .name = "Sharp_LCD035Q3DG01",
203 .xres = 320,
204 .yres = 240,
205 .pixclock = KHZ2PICOS(4607),
206 .left_margin = 6,
207 .right_margin = 8,
208 .upper_margin = 2,
209 .lower_margin = 2,
210 .hsync_len = 0,
211 .vsync_len = 0,
212 .sync = FB_SYNC_CLK_INVERT |
213 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
214 },
215 /* Sharp LK043T1DG01 */
216 [1] = {
217 .name = "Sharp_LK043T1DG01",
218 .xres = 480,
219 .yres = 272,
220 .pixclock = KHZ2PICOS(7833),
221 .left_margin = 2,
222 .right_margin = 2,
223 .upper_margin = 2,
224 .lower_margin = 2,
225 .hsync_len = 41,
226 .vsync_len = 10,
227 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
228 .flag = 0,
229 },
230 [2] = {
231 /* Hitachi SP10Q010 */
232 .name = "SP10Q010",
233 .xres = 320,
234 .yres = 240,
235 .pixclock = KHZ2PICOS(7833),
236 .left_margin = 10,
237 .right_margin = 10,
238 .upper_margin = 10,
239 .lower_margin = 10,
240 .hsync_len = 10,
241 .vsync_len = 10,
242 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
243 .flag = 0,
244 },
245 };
246
247 static bool da8xx_fb_is_raster_enabled(void)
248 {
249 return !!(lcdc_read(LCD_RASTER_CTRL_REG) & LCD_RASTER_ENABLE);
250 }
251
252 /* Enable the Raster Engine of the LCD Controller */
253 static void lcd_enable_raster(void)
254 {
255 u32 reg;
256
257 /* Put LCDC in reset for several cycles */
258 if (lcd_revision == LCD_VERSION_2)
259 /* Write 1 to reset LCDC */
260 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
261 mdelay(1);
262
263 /* Bring LCDC out of reset */
264 if (lcd_revision == LCD_VERSION_2)
265 lcdc_write(0, LCD_CLK_RESET_REG);
266 mdelay(1);
267
268 /* Above reset sequence doesnot reset register context */
269 reg = lcdc_read(LCD_RASTER_CTRL_REG);
270 if (!(reg & LCD_RASTER_ENABLE))
271 lcdc_write(reg | LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
272 }
273
274 /* Disable the Raster Engine of the LCD Controller */
275 static void lcd_disable_raster(enum da8xx_frame_complete wait_for_frame_done)
276 {
277 u32 reg;
278 int ret;
279
280 reg = lcdc_read(LCD_RASTER_CTRL_REG);
281 if (reg & LCD_RASTER_ENABLE)
282 lcdc_write(reg & ~LCD_RASTER_ENABLE, LCD_RASTER_CTRL_REG);
283 else
284 /* return if already disabled */
285 return;
286
287 if ((wait_for_frame_done == DA8XX_FRAME_WAIT) &&
288 (lcd_revision == LCD_VERSION_2)) {
289 frame_done_flag = 0;
290 ret = wait_event_interruptible_timeout(frame_done_wq,
291 frame_done_flag != 0,
292 msecs_to_jiffies(50));
293 if (ret == 0)
294 pr_err("LCD Controller timed out\n");
295 }
296 }
297
298 static void lcd_blit(int load_mode, struct da8xx_fb_par *par)
299 {
300 u32 start;
301 u32 end;
302 u32 reg_ras;
303 u32 reg_dma;
304 u32 reg_int;
305
306 /* init reg to clear PLM (loading mode) fields */
307 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
308 reg_ras &= ~(3 << 20);
309
310 reg_dma = lcdc_read(LCD_DMA_CTRL_REG);
311
312 if (load_mode == LOAD_DATA) {
313 start = par->dma_start;
314 end = par->dma_end;
315
316 reg_ras |= LCD_PALETTE_LOAD_MODE(DATA_ONLY);
317 if (lcd_revision == LCD_VERSION_1) {
318 reg_dma |= LCD_V1_END_OF_FRAME_INT_ENA;
319 } else {
320 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
321 LCD_V2_END_OF_FRAME0_INT_ENA |
322 LCD_V2_END_OF_FRAME1_INT_ENA |
323 LCD_FRAME_DONE | LCD_SYNC_LOST;
324 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
325 }
326 reg_dma |= LCD_DUAL_FRAME_BUFFER_ENABLE;
327
328 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
329 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
330 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
331 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
332 } else if (load_mode == LOAD_PALETTE) {
333 start = par->p_palette_base;
334 end = start + par->palette_sz - 1;
335
336 reg_ras |= LCD_PALETTE_LOAD_MODE(PALETTE_ONLY);
337
338 if (lcd_revision == LCD_VERSION_1) {
339 reg_ras |= LCD_V1_PL_INT_ENA;
340 } else {
341 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
342 LCD_V2_PL_INT_ENA;
343 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
344 }
345
346 lcdc_write(start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
347 lcdc_write(end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
348 }
349
350 lcdc_write(reg_dma, LCD_DMA_CTRL_REG);
351 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
352
353 /*
354 * The Raster enable bit must be set after all other control fields are
355 * set.
356 */
357 lcd_enable_raster();
358 }
359
360 /* Configure the Burst Size and fifo threhold of DMA */
361 static int lcd_cfg_dma(int burst_size, int fifo_th)
362 {
363 u32 reg;
364
365 reg = lcdc_read(LCD_DMA_CTRL_REG) & 0x00000001;
366 switch (burst_size) {
367 case 1:
368 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_1);
369 break;
370 case 2:
371 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_2);
372 break;
373 case 4:
374 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_4);
375 break;
376 case 8:
377 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_8);
378 break;
379 case 16:
380 default:
381 reg |= LCD_DMA_BURST_SIZE(LCD_DMA_BURST_16);
382 break;
383 }
384
385 reg |= (fifo_th << 8);
386
387 lcdc_write(reg, LCD_DMA_CTRL_REG);
388
389 return 0;
390 }
391
392 static void lcd_cfg_ac_bias(int period, int transitions_per_int)
393 {
394 u32 reg;
395
396 /* Set the AC Bias Period and Number of Transisitons per Interrupt */
397 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & 0xFFF00000;
398 reg |= LCD_AC_BIAS_FREQUENCY(period) |
399 LCD_AC_BIAS_TRANSITIONS_PER_INT(transitions_per_int);
400 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
401 }
402
403 static void lcd_cfg_horizontal_sync(int back_porch, int pulse_width,
404 int front_porch)
405 {
406 u32 reg;
407
408 reg = lcdc_read(LCD_RASTER_TIMING_0_REG) & 0xf;
409 reg |= (((back_porch-1) & 0xff) << 24)
410 | (((front_porch-1) & 0xff) << 16)
411 | (((pulse_width-1) & 0x3f) << 10);
412 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
413
414 /*
415 * LCDC Version 2 adds some extra bits that increase the allowable
416 * size of the horizontal timing registers.
417 * remember that the registers use 0 to represent 1 so all values
418 * that get set into register need to be decremented by 1
419 */
420 if (lcd_revision == LCD_VERSION_2) {
421 /* Mask off the bits we want to change */
422 reg = lcdc_read(LCD_RASTER_TIMING_2_REG) & ~0x780000ff;
423 reg |= ((front_porch-1) & 0x300) >> 8;
424 reg |= ((back_porch-1) & 0x300) >> 4;
425 reg |= ((pulse_width-1) & 0x3c0) << 21;
426 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
427 }
428 }
429
430 static void lcd_cfg_vertical_sync(int back_porch, int pulse_width,
431 int front_porch)
432 {
433 u32 reg;
434
435 reg = lcdc_read(LCD_RASTER_TIMING_1_REG) & 0x3ff;
436 reg |= ((back_porch & 0xff) << 24)
437 | ((front_porch & 0xff) << 16)
438 | (((pulse_width-1) & 0x3f) << 10);
439 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
440 }
441
442 static int lcd_cfg_display(const struct lcd_ctrl_config *cfg,
443 struct fb_videomode *panel)
444 {
445 u32 reg;
446 u32 reg_int;
447
448 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(LCD_TFT_MODE |
449 LCD_MONO_8BIT_MODE |
450 LCD_MONOCHROME_MODE);
451
452 switch (cfg->panel_shade) {
453 case MONOCHROME:
454 reg |= LCD_MONOCHROME_MODE;
455 if (cfg->mono_8bit_mode)
456 reg |= LCD_MONO_8BIT_MODE;
457 break;
458 case COLOR_ACTIVE:
459 reg |= LCD_TFT_MODE;
460 if (cfg->tft_alt_mode)
461 reg |= LCD_TFT_ALT_ENABLE;
462 break;
463
464 case COLOR_PASSIVE:
465 /* AC bias applicable only for Pasive panels */
466 lcd_cfg_ac_bias(cfg->ac_bias, cfg->ac_bias_intrpt);
467 if (cfg->bpp == 12 && cfg->stn_565_mode)
468 reg |= LCD_STN_565_ENABLE;
469 break;
470
471 default:
472 return -EINVAL;
473 }
474
475 /* enable additional interrupts here */
476 if (lcd_revision == LCD_VERSION_1) {
477 reg |= LCD_V1_UNDERFLOW_INT_ENA;
478 } else {
479 reg_int = lcdc_read(LCD_INT_ENABLE_SET_REG) |
480 LCD_V2_UNDERFLOW_INT_ENA;
481 lcdc_write(reg_int, LCD_INT_ENABLE_SET_REG);
482 }
483
484 lcdc_write(reg, LCD_RASTER_CTRL_REG);
485
486 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
487
488 reg |= LCD_SYNC_CTRL;
489
490 if (cfg->sync_edge)
491 reg |= LCD_SYNC_EDGE;
492 else
493 reg &= ~LCD_SYNC_EDGE;
494
495 if ((panel->sync & FB_SYNC_HOR_HIGH_ACT) == 0)
496 reg |= LCD_INVERT_LINE_CLOCK;
497 else
498 reg &= ~LCD_INVERT_LINE_CLOCK;
499
500 if ((panel->sync & FB_SYNC_VERT_HIGH_ACT) == 0)
501 reg |= LCD_INVERT_FRAME_CLOCK;
502 else
503 reg &= ~LCD_INVERT_FRAME_CLOCK;
504
505 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
506
507 return 0;
508 }
509
510 static int lcd_cfg_frame_buffer(struct da8xx_fb_par *par, u32 width, u32 height,
511 u32 bpp, u32 raster_order)
512 {
513 u32 reg;
514
515 if (bpp > 16 && lcd_revision == LCD_VERSION_1)
516 return -EINVAL;
517
518 /* Set the Panel Width */
519 /* Pixels per line = (PPL + 1)*16 */
520 if (lcd_revision == LCD_VERSION_1) {
521 /*
522 * 0x3F in bits 4..9 gives max horizontal resolution = 1024
523 * pixels.
524 */
525 width &= 0x3f0;
526 } else {
527 /*
528 * 0x7F in bits 4..10 gives max horizontal resolution = 2048
529 * pixels.
530 */
531 width &= 0x7f0;
532 }
533
534 reg = lcdc_read(LCD_RASTER_TIMING_0_REG);
535 reg &= 0xfffffc00;
536 if (lcd_revision == LCD_VERSION_1) {
537 reg |= ((width >> 4) - 1) << 4;
538 } else {
539 width = (width >> 4) - 1;
540 reg |= ((width & 0x3f) << 4) | ((width & 0x40) >> 3);
541 }
542 lcdc_write(reg, LCD_RASTER_TIMING_0_REG);
543
544 /* Set the Panel Height */
545 /* Set bits 9:0 of Lines Per Pixel */
546 reg = lcdc_read(LCD_RASTER_TIMING_1_REG);
547 reg = ((height - 1) & 0x3ff) | (reg & 0xfffffc00);
548 lcdc_write(reg, LCD_RASTER_TIMING_1_REG);
549
550 /* Set bit 10 of Lines Per Pixel */
551 if (lcd_revision == LCD_VERSION_2) {
552 reg = lcdc_read(LCD_RASTER_TIMING_2_REG);
553 reg |= ((height - 1) & 0x400) << 16;
554 lcdc_write(reg, LCD_RASTER_TIMING_2_REG);
555 }
556
557 /* Set the Raster Order of the Frame Buffer */
558 reg = lcdc_read(LCD_RASTER_CTRL_REG) & ~(1 << 8);
559 if (raster_order)
560 reg |= LCD_RASTER_ORDER;
561
562 par->palette_sz = 16 * 2;
563
564 switch (bpp) {
565 case 1:
566 case 2:
567 case 4:
568 case 16:
569 break;
570 case 24:
571 reg |= LCD_V2_TFT_24BPP_MODE;
572 break;
573 case 32:
574 reg |= LCD_V2_TFT_24BPP_MODE;
575 reg |= LCD_V2_TFT_24BPP_UNPACK;
576 break;
577 case 8:
578 par->palette_sz = 256 * 2;
579 break;
580
581 default:
582 return -EINVAL;
583 }
584
585 lcdc_write(reg, LCD_RASTER_CTRL_REG);
586
587 return 0;
588 }
589
590 #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF - (val)) >> 16)
591 static int fb_setcolreg(unsigned regno, unsigned red, unsigned green,
592 unsigned blue, unsigned transp,
593 struct fb_info *info)
594 {
595 struct da8xx_fb_par *par = info->par;
596 unsigned short *palette = (unsigned short *) par->v_palette_base;
597 u_short pal;
598 int update_hw = 0;
599
600 if (regno > 255)
601 return 1;
602
603 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
604 return 1;
605
606 if (info->var.bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
607 return -EINVAL;
608
609 switch (info->fix.visual) {
610 case FB_VISUAL_TRUECOLOR:
611 red = CNVT_TOHW(red, info->var.red.length);
612 green = CNVT_TOHW(green, info->var.green.length);
613 blue = CNVT_TOHW(blue, info->var.blue.length);
614 break;
615 case FB_VISUAL_PSEUDOCOLOR:
616 switch (info->var.bits_per_pixel) {
617 case 4:
618 if (regno > 15)
619 return -EINVAL;
620
621 if (info->var.grayscale) {
622 pal = regno;
623 } else {
624 red >>= 4;
625 green >>= 8;
626 blue >>= 12;
627
628 pal = red & 0x0f00;
629 pal |= green & 0x00f0;
630 pal |= blue & 0x000f;
631 }
632 if (regno == 0)
633 pal |= 0x2000;
634 palette[regno] = pal;
635 break;
636
637 case 8:
638 red >>= 4;
639 green >>= 8;
640 blue >>= 12;
641
642 pal = (red & 0x0f00);
643 pal |= (green & 0x00f0);
644 pal |= (blue & 0x000f);
645
646 if (palette[regno] != pal) {
647 update_hw = 1;
648 palette[regno] = pal;
649 }
650 break;
651 }
652 break;
653 }
654
655 /* Truecolor has hardware independent palette */
656 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
657 u32 v;
658
659 if (regno > 15)
660 return -EINVAL;
661
662 v = (red << info->var.red.offset) |
663 (green << info->var.green.offset) |
664 (blue << info->var.blue.offset);
665
666 switch (info->var.bits_per_pixel) {
667 case 16:
668 ((u16 *) (info->pseudo_palette))[regno] = v;
669 break;
670 case 24:
671 case 32:
672 ((u32 *) (info->pseudo_palette))[regno] = v;
673 break;
674 }
675 if (palette[0] != 0x4000) {
676 update_hw = 1;
677 palette[0] = 0x4000;
678 }
679 }
680
681 /* Update the palette in the h/w as needed. */
682 if (update_hw)
683 lcd_blit(LOAD_PALETTE, par);
684
685 return 0;
686 }
687 #undef CNVT_TOHW
688
689 static void da8xx_fb_lcd_reset(void)
690 {
691 /* DMA has to be disabled */
692 lcdc_write(0, LCD_DMA_CTRL_REG);
693 lcdc_write(0, LCD_RASTER_CTRL_REG);
694
695 if (lcd_revision == LCD_VERSION_2) {
696 lcdc_write(0, LCD_INT_ENABLE_SET_REG);
697 /* Write 1 to reset */
698 lcdc_write(LCD_CLK_MAIN_RESET, LCD_CLK_RESET_REG);
699 lcdc_write(0, LCD_CLK_RESET_REG);
700 }
701 }
702
703 static int da8xx_fb_config_clk_divider(struct da8xx_fb_par *par,
704 unsigned lcdc_clk_div,
705 unsigned lcdc_clk_rate)
706 {
707 int ret;
708
709 if (par->lcdc_clk_rate != lcdc_clk_rate) {
710 ret = clk_set_rate(par->lcdc_clk, lcdc_clk_rate);
711 if (IS_ERR_VALUE(ret)) {
712 dev_err(par->dev,
713 "unable to set clock rate at %u\n",
714 lcdc_clk_rate);
715 return ret;
716 }
717 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
718 }
719
720 /* Configure the LCD clock divisor. */
721 lcdc_write(LCD_CLK_DIVISOR(lcdc_clk_div) |
722 (LCD_RASTER_MODE & 0x1), LCD_CTRL_REG);
723
724 if (lcd_revision == LCD_VERSION_2)
725 lcdc_write(LCD_V2_DMA_CLK_EN | LCD_V2_LIDD_CLK_EN |
726 LCD_V2_CORE_CLK_EN, LCD_CLK_ENABLE_REG);
727
728 return 0;
729 }
730
731 static unsigned int da8xx_fb_calc_clk_divider(struct da8xx_fb_par *par,
732 unsigned pixclock,
733 unsigned *lcdc_clk_rate)
734 {
735 unsigned lcdc_clk_div;
736
737 pixclock = PICOS2KHZ(pixclock) * 1000;
738
739 *lcdc_clk_rate = par->lcdc_clk_rate;
740
741 if (pixclock < (*lcdc_clk_rate / CLK_MAX_DIV)) {
742 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
743 pixclock * CLK_MAX_DIV);
744 lcdc_clk_div = CLK_MAX_DIV;
745 } else if (pixclock > (*lcdc_clk_rate / CLK_MIN_DIV)) {
746 *lcdc_clk_rate = clk_round_rate(par->lcdc_clk,
747 pixclock * CLK_MIN_DIV);
748 lcdc_clk_div = CLK_MIN_DIV;
749 } else {
750 lcdc_clk_div = *lcdc_clk_rate / pixclock;
751 }
752
753 return lcdc_clk_div;
754 }
755
756 static int da8xx_fb_calc_config_clk_divider(struct da8xx_fb_par *par,
757 struct fb_videomode *mode)
758 {
759 unsigned lcdc_clk_rate;
760 unsigned lcdc_clk_div = da8xx_fb_calc_clk_divider(par, mode->pixclock,
761 &lcdc_clk_rate);
762
763 return da8xx_fb_config_clk_divider(par, lcdc_clk_div, lcdc_clk_rate);
764 }
765
766 static unsigned da8xx_fb_round_clk(struct da8xx_fb_par *par,
767 unsigned pixclock)
768 {
769 unsigned lcdc_clk_div, lcdc_clk_rate;
770
771 lcdc_clk_div = da8xx_fb_calc_clk_divider(par, pixclock, &lcdc_clk_rate);
772 return KHZ2PICOS(lcdc_clk_rate / (1000 * lcdc_clk_div));
773 }
774
775 static int lcd_init(struct da8xx_fb_par *par, const struct lcd_ctrl_config *cfg,
776 struct fb_videomode *panel)
777 {
778 u32 bpp;
779 int ret = 0;
780
781 ret = da8xx_fb_calc_config_clk_divider(par, panel);
782 if (IS_ERR_VALUE(ret)) {
783 dev_err(par->dev, "unable to configure clock\n");
784 return ret;
785 }
786
787 if (panel->sync & FB_SYNC_CLK_INVERT)
788 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) |
789 LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
790 else
791 lcdc_write((lcdc_read(LCD_RASTER_TIMING_2_REG) &
792 ~LCD_INVERT_PIXEL_CLOCK), LCD_RASTER_TIMING_2_REG);
793
794 /* Configure the DMA burst size and fifo threshold. */
795 ret = lcd_cfg_dma(cfg->dma_burst_sz, cfg->fifo_th);
796 if (ret < 0)
797 return ret;
798
799 /* Configure the vertical and horizontal sync properties. */
800 lcd_cfg_vertical_sync(panel->upper_margin, panel->vsync_len,
801 panel->lower_margin);
802 lcd_cfg_horizontal_sync(panel->left_margin, panel->hsync_len,
803 panel->right_margin);
804
805 /* Configure for disply */
806 ret = lcd_cfg_display(cfg, panel);
807 if (ret < 0)
808 return ret;
809
810 bpp = cfg->bpp;
811
812 if (bpp == 12)
813 bpp = 16;
814 ret = lcd_cfg_frame_buffer(par, (unsigned int)panel->xres,
815 (unsigned int)panel->yres, bpp,
816 cfg->raster_order);
817 if (ret < 0)
818 return ret;
819
820 /* Configure FDD */
821 lcdc_write((lcdc_read(LCD_RASTER_CTRL_REG) & 0xfff00fff) |
822 (cfg->fdd << 12), LCD_RASTER_CTRL_REG);
823
824 return 0;
825 }
826
827 /* IRQ handler for version 2 of LCDC */
828 static irqreturn_t lcdc_irq_handler_rev02(int irq, void *arg)
829 {
830 struct da8xx_fb_par *par = arg;
831 u32 stat = lcdc_read(LCD_MASKED_STAT_REG);
832
833 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
834 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
835 lcdc_write(stat, LCD_MASKED_STAT_REG);
836 lcd_enable_raster();
837 } else if (stat & LCD_PL_LOAD_DONE) {
838 /*
839 * Must disable raster before changing state of any control bit.
840 * And also must be disabled before clearing the PL loading
841 * interrupt via the following write to the status register. If
842 * this is done after then one gets multiple PL done interrupts.
843 */
844 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
845
846 lcdc_write(stat, LCD_MASKED_STAT_REG);
847
848 /* Disable PL completion interrupt */
849 lcdc_write(LCD_V2_PL_INT_ENA, LCD_INT_ENABLE_CLR_REG);
850
851 /* Setup and start data loading mode */
852 lcd_blit(LOAD_DATA, par);
853 } else {
854 lcdc_write(stat, LCD_MASKED_STAT_REG);
855
856 if (stat & LCD_END_OF_FRAME0) {
857 par->which_dma_channel_done = 0;
858 lcdc_write(par->dma_start,
859 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
860 lcdc_write(par->dma_end,
861 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
862 par->vsync_flag = 1;
863 wake_up_interruptible(&par->vsync_wait);
864 }
865
866 if (stat & LCD_END_OF_FRAME1) {
867 par->which_dma_channel_done = 1;
868 lcdc_write(par->dma_start,
869 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
870 lcdc_write(par->dma_end,
871 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
872 par->vsync_flag = 1;
873 wake_up_interruptible(&par->vsync_wait);
874 }
875
876 /* Set only when controller is disabled and at the end of
877 * active frame
878 */
879 if (stat & BIT(0)) {
880 frame_done_flag = 1;
881 wake_up_interruptible(&frame_done_wq);
882 }
883 }
884
885 lcdc_write(0, LCD_END_OF_INT_IND_REG);
886 return IRQ_HANDLED;
887 }
888
889 /* IRQ handler for version 1 LCDC */
890 static irqreturn_t lcdc_irq_handler_rev01(int irq, void *arg)
891 {
892 struct da8xx_fb_par *par = arg;
893 u32 stat = lcdc_read(LCD_STAT_REG);
894 u32 reg_ras;
895
896 if ((stat & LCD_SYNC_LOST) && (stat & LCD_FIFO_UNDERFLOW)) {
897 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
898 lcdc_write(stat, LCD_STAT_REG);
899 lcd_enable_raster();
900 } else if (stat & LCD_PL_LOAD_DONE) {
901 /*
902 * Must disable raster before changing state of any control bit.
903 * And also must be disabled before clearing the PL loading
904 * interrupt via the following write to the status register. If
905 * this is done after then one gets multiple PL done interrupts.
906 */
907 lcd_disable_raster(DA8XX_FRAME_NOWAIT);
908
909 lcdc_write(stat, LCD_STAT_REG);
910
911 /* Disable PL completion inerrupt */
912 reg_ras = lcdc_read(LCD_RASTER_CTRL_REG);
913 reg_ras &= ~LCD_V1_PL_INT_ENA;
914 lcdc_write(reg_ras, LCD_RASTER_CTRL_REG);
915
916 /* Setup and start data loading mode */
917 lcd_blit(LOAD_DATA, par);
918 } else {
919 lcdc_write(stat, LCD_STAT_REG);
920
921 if (stat & LCD_END_OF_FRAME0) {
922 par->which_dma_channel_done = 0;
923 lcdc_write(par->dma_start,
924 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
925 lcdc_write(par->dma_end,
926 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
927 par->vsync_flag = 1;
928 wake_up_interruptible(&par->vsync_wait);
929 }
930
931 if (stat & LCD_END_OF_FRAME1) {
932 par->which_dma_channel_done = 1;
933 lcdc_write(par->dma_start,
934 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
935 lcdc_write(par->dma_end,
936 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
937 par->vsync_flag = 1;
938 wake_up_interruptible(&par->vsync_wait);
939 }
940 }
941
942 return IRQ_HANDLED;
943 }
944
945 static int fb_check_var(struct fb_var_screeninfo *var,
946 struct fb_info *info)
947 {
948 int err = 0;
949 struct da8xx_fb_par *par = info->par;
950 int bpp = var->bits_per_pixel >> 3;
951 unsigned long line_size = var->xres_virtual * bpp;
952
953 if (var->bits_per_pixel > 16 && lcd_revision == LCD_VERSION_1)
954 return -EINVAL;
955
956 switch (var->bits_per_pixel) {
957 case 1:
958 case 8:
959 var->red.offset = 0;
960 var->red.length = 8;
961 var->green.offset = 0;
962 var->green.length = 8;
963 var->blue.offset = 0;
964 var->blue.length = 8;
965 var->transp.offset = 0;
966 var->transp.length = 0;
967 var->nonstd = 0;
968 break;
969 case 4:
970 var->red.offset = 0;
971 var->red.length = 4;
972 var->green.offset = 0;
973 var->green.length = 4;
974 var->blue.offset = 0;
975 var->blue.length = 4;
976 var->transp.offset = 0;
977 var->transp.length = 0;
978 var->nonstd = FB_NONSTD_REV_PIX_IN_B;
979 break;
980 case 16: /* RGB 565 */
981 var->red.offset = 11;
982 var->red.length = 5;
983 var->green.offset = 5;
984 var->green.length = 6;
985 var->blue.offset = 0;
986 var->blue.length = 5;
987 var->transp.offset = 0;
988 var->transp.length = 0;
989 var->nonstd = 0;
990 break;
991 case 24:
992 var->red.offset = 16;
993 var->red.length = 8;
994 var->green.offset = 8;
995 var->green.length = 8;
996 var->blue.offset = 0;
997 var->blue.length = 8;
998 var->nonstd = 0;
999 break;
1000 case 32:
1001 var->transp.offset = 24;
1002 var->transp.length = 8;
1003 var->red.offset = 16;
1004 var->red.length = 8;
1005 var->green.offset = 8;
1006 var->green.length = 8;
1007 var->blue.offset = 0;
1008 var->blue.length = 8;
1009 var->nonstd = 0;
1010 break;
1011 default:
1012 err = -EINVAL;
1013 }
1014
1015 var->red.msb_right = 0;
1016 var->green.msb_right = 0;
1017 var->blue.msb_right = 0;
1018 var->transp.msb_right = 0;
1019
1020 if (line_size * var->yres_virtual > par->vram_size)
1021 var->yres_virtual = par->vram_size / line_size;
1022
1023 if (var->yres > var->yres_virtual)
1024 var->yres = var->yres_virtual;
1025
1026 if (var->xres > var->xres_virtual)
1027 var->xres = var->xres_virtual;
1028
1029 if (var->xres + var->xoffset > var->xres_virtual)
1030 var->xoffset = var->xres_virtual - var->xres;
1031 if (var->yres + var->yoffset > var->yres_virtual)
1032 var->yoffset = var->yres_virtual - var->yres;
1033
1034 var->pixclock = da8xx_fb_round_clk(par, var->pixclock);
1035
1036 return err;
1037 }
1038
1039 #ifdef CONFIG_CPU_FREQ
1040 static int lcd_da8xx_cpufreq_transition(struct notifier_block *nb,
1041 unsigned long val, void *data)
1042 {
1043 struct da8xx_fb_par *par;
1044
1045 par = container_of(nb, struct da8xx_fb_par, freq_transition);
1046 if (val == CPUFREQ_POSTCHANGE) {
1047 if (par->lcdc_clk_rate != clk_get_rate(par->lcdc_clk)) {
1048 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1049 lcd_disable_raster(DA8XX_FRAME_WAIT);
1050 da8xx_fb_calc_config_clk_divider(par, &par->mode);
1051 if (par->blank == FB_BLANK_UNBLANK)
1052 lcd_enable_raster();
1053 }
1054 }
1055
1056 return 0;
1057 }
1058
1059 static int lcd_da8xx_cpufreq_register(struct da8xx_fb_par *par)
1060 {
1061 par->freq_transition.notifier_call = lcd_da8xx_cpufreq_transition;
1062
1063 return cpufreq_register_notifier(&par->freq_transition,
1064 CPUFREQ_TRANSITION_NOTIFIER);
1065 }
1066
1067 static void lcd_da8xx_cpufreq_deregister(struct da8xx_fb_par *par)
1068 {
1069 cpufreq_unregister_notifier(&par->freq_transition,
1070 CPUFREQ_TRANSITION_NOTIFIER);
1071 }
1072 #endif
1073
1074 static int fb_remove(struct platform_device *dev)
1075 {
1076 struct fb_info *info = dev_get_drvdata(&dev->dev);
1077
1078 if (info) {
1079 struct da8xx_fb_par *par = info->par;
1080
1081 #ifdef CONFIG_CPU_FREQ
1082 lcd_da8xx_cpufreq_deregister(par);
1083 #endif
1084 if (par->panel_power_ctrl)
1085 par->panel_power_ctrl(0);
1086
1087 lcd_disable_raster(DA8XX_FRAME_WAIT);
1088 lcdc_write(0, LCD_RASTER_CTRL_REG);
1089
1090 /* disable DMA */
1091 lcdc_write(0, LCD_DMA_CTRL_REG);
1092
1093 unregister_framebuffer(info);
1094 fb_dealloc_cmap(&info->cmap);
1095 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1096 par->p_palette_base);
1097 dma_free_coherent(NULL, par->vram_size, par->vram_virt,
1098 par->vram_phys);
1099 pm_runtime_put_sync(&dev->dev);
1100 pm_runtime_disable(&dev->dev);
1101 framebuffer_release(info);
1102
1103 }
1104 return 0;
1105 }
1106
1107 /*
1108 * Function to wait for vertical sync which for this LCD peripheral
1109 * translates into waiting for the current raster frame to complete.
1110 */
1111 static int fb_wait_for_vsync(struct fb_info *info)
1112 {
1113 struct da8xx_fb_par *par = info->par;
1114 int ret;
1115
1116 /*
1117 * Set flag to 0 and wait for isr to set to 1. It would seem there is a
1118 * race condition here where the ISR could have occurred just before or
1119 * just after this set. But since we are just coarsely waiting for
1120 * a frame to complete then that's OK. i.e. if the frame completed
1121 * just before this code executed then we have to wait another full
1122 * frame time but there is no way to avoid such a situation. On the
1123 * other hand if the frame completed just after then we don't need
1124 * to wait long at all. Either way we are guaranteed to return to the
1125 * user immediately after a frame completion which is all that is
1126 * required.
1127 */
1128 par->vsync_flag = 0;
1129 ret = wait_event_interruptible_timeout(par->vsync_wait,
1130 par->vsync_flag != 0,
1131 par->vsync_timeout);
1132 if (ret < 0)
1133 return ret;
1134 if (ret == 0)
1135 return -ETIMEDOUT;
1136
1137 return 0;
1138 }
1139
1140 static int fb_ioctl(struct fb_info *info, unsigned int cmd,
1141 unsigned long arg)
1142 {
1143 struct lcd_sync_arg sync_arg;
1144
1145 switch (cmd) {
1146 case FBIOGET_CONTRAST:
1147 case FBIOPUT_CONTRAST:
1148 case FBIGET_BRIGHTNESS:
1149 case FBIPUT_BRIGHTNESS:
1150 case FBIGET_COLOR:
1151 case FBIPUT_COLOR:
1152 return -ENOTTY;
1153 case FBIPUT_HSYNC:
1154 if (copy_from_user(&sync_arg, (char *)arg,
1155 sizeof(struct lcd_sync_arg)))
1156 return -EFAULT;
1157 lcd_cfg_horizontal_sync(sync_arg.back_porch,
1158 sync_arg.pulse_width,
1159 sync_arg.front_porch);
1160 break;
1161 case FBIPUT_VSYNC:
1162 if (copy_from_user(&sync_arg, (char *)arg,
1163 sizeof(struct lcd_sync_arg)))
1164 return -EFAULT;
1165 lcd_cfg_vertical_sync(sync_arg.back_porch,
1166 sync_arg.pulse_width,
1167 sync_arg.front_porch);
1168 break;
1169 case FBIO_WAITFORVSYNC:
1170 return fb_wait_for_vsync(info);
1171 default:
1172 return -EINVAL;
1173 }
1174 return 0;
1175 }
1176
1177 static int cfb_blank(int blank, struct fb_info *info)
1178 {
1179 struct da8xx_fb_par *par = info->par;
1180 int ret = 0;
1181
1182 if (par->blank == blank)
1183 return 0;
1184
1185 par->blank = blank;
1186 switch (blank) {
1187 case FB_BLANK_UNBLANK:
1188 lcd_enable_raster();
1189
1190 if (par->panel_power_ctrl)
1191 par->panel_power_ctrl(1);
1192 break;
1193 case FB_BLANK_NORMAL:
1194 case FB_BLANK_VSYNC_SUSPEND:
1195 case FB_BLANK_HSYNC_SUSPEND:
1196 case FB_BLANK_POWERDOWN:
1197 if (par->panel_power_ctrl)
1198 par->panel_power_ctrl(0);
1199
1200 lcd_disable_raster(DA8XX_FRAME_WAIT);
1201 break;
1202 default:
1203 ret = -EINVAL;
1204 }
1205
1206 return ret;
1207 }
1208
1209 /*
1210 * Set new x,y offsets in the virtual display for the visible area and switch
1211 * to the new mode.
1212 */
1213 static int da8xx_pan_display(struct fb_var_screeninfo *var,
1214 struct fb_info *fbi)
1215 {
1216 int ret = 0;
1217 struct fb_var_screeninfo new_var;
1218 struct da8xx_fb_par *par = fbi->par;
1219 struct fb_fix_screeninfo *fix = &fbi->fix;
1220 unsigned int end;
1221 unsigned int start;
1222 unsigned long irq_flags;
1223
1224 if (var->xoffset != fbi->var.xoffset ||
1225 var->yoffset != fbi->var.yoffset) {
1226 memcpy(&new_var, &fbi->var, sizeof(new_var));
1227 new_var.xoffset = var->xoffset;
1228 new_var.yoffset = var->yoffset;
1229 if (fb_check_var(&new_var, fbi))
1230 ret = -EINVAL;
1231 else {
1232 memcpy(&fbi->var, &new_var, sizeof(new_var));
1233
1234 start = fix->smem_start +
1235 new_var.yoffset * fix->line_length +
1236 new_var.xoffset * fbi->var.bits_per_pixel / 8;
1237 end = start + fbi->var.yres * fix->line_length - 1;
1238 par->dma_start = start;
1239 par->dma_end = end;
1240 spin_lock_irqsave(&par->lock_for_chan_update,
1241 irq_flags);
1242 if (par->which_dma_channel_done == 0) {
1243 lcdc_write(par->dma_start,
1244 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1245 lcdc_write(par->dma_end,
1246 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1247 } else if (par->which_dma_channel_done == 1) {
1248 lcdc_write(par->dma_start,
1249 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1250 lcdc_write(par->dma_end,
1251 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1252 }
1253 spin_unlock_irqrestore(&par->lock_for_chan_update,
1254 irq_flags);
1255 }
1256 }
1257
1258 return ret;
1259 }
1260
1261 static int da8xxfb_set_par(struct fb_info *info)
1262 {
1263 struct da8xx_fb_par *par = info->par;
1264 int ret;
1265 bool raster = da8xx_fb_is_raster_enabled();
1266
1267 if (raster)
1268 lcd_disable_raster(DA8XX_FRAME_WAIT);
1269
1270 fb_var_to_videomode(&par->mode, &info->var);
1271
1272 par->cfg.bpp = info->var.bits_per_pixel;
1273
1274 info->fix.visual = (par->cfg.bpp <= 8) ?
1275 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1276 info->fix.line_length = (par->mode.xres * par->cfg.bpp) / 8;
1277
1278 ret = lcd_init(par, &par->cfg, &par->mode);
1279 if (ret < 0) {
1280 dev_err(par->dev, "lcd init failed\n");
1281 return ret;
1282 }
1283
1284 par->dma_start = info->fix.smem_start +
1285 info->var.yoffset * info->fix.line_length +
1286 info->var.xoffset * info->var.bits_per_pixel / 8;
1287 par->dma_end = par->dma_start +
1288 info->var.yres * info->fix.line_length - 1;
1289
1290 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1291 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1292 lcdc_write(par->dma_start, LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1293 lcdc_write(par->dma_end, LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1294
1295 if (raster)
1296 lcd_enable_raster();
1297
1298 return 0;
1299 }
1300
1301 static struct fb_ops da8xx_fb_ops = {
1302 .owner = THIS_MODULE,
1303 .fb_check_var = fb_check_var,
1304 .fb_set_par = da8xxfb_set_par,
1305 .fb_setcolreg = fb_setcolreg,
1306 .fb_pan_display = da8xx_pan_display,
1307 .fb_ioctl = fb_ioctl,
1308 .fb_fillrect = cfb_fillrect,
1309 .fb_copyarea = cfb_copyarea,
1310 .fb_imageblit = cfb_imageblit,
1311 .fb_blank = cfb_blank,
1312 };
1313
1314 static struct fb_videomode *da8xx_fb_get_videomode(struct platform_device *dev)
1315 {
1316 struct da8xx_lcdc_platform_data *fb_pdata = dev_get_platdata(&dev->dev);
1317 struct fb_videomode *lcdc_info;
1318 int i;
1319
1320 for (i = 0, lcdc_info = known_lcd_panels;
1321 i < ARRAY_SIZE(known_lcd_panels); i++, lcdc_info++) {
1322 if (strcmp(fb_pdata->type, lcdc_info->name) == 0)
1323 break;
1324 }
1325
1326 if (i == ARRAY_SIZE(known_lcd_panels)) {
1327 dev_err(&dev->dev, "no panel found\n");
1328 return NULL;
1329 }
1330 dev_info(&dev->dev, "found %s panel\n", lcdc_info->name);
1331
1332 return lcdc_info;
1333 }
1334
1335 static int fb_probe(struct platform_device *device)
1336 {
1337 struct da8xx_lcdc_platform_data *fb_pdata =
1338 dev_get_platdata(&device->dev);
1339 static struct resource *lcdc_regs;
1340 struct lcd_ctrl_config *lcd_cfg;
1341 struct fb_videomode *lcdc_info;
1342 struct fb_info *da8xx_fb_info;
1343 struct da8xx_fb_par *par;
1344 struct clk *tmp_lcdc_clk;
1345 int ret;
1346 unsigned long ulcm;
1347
1348 if (fb_pdata == NULL) {
1349 dev_err(&device->dev, "Can not get platform data\n");
1350 return -ENOENT;
1351 }
1352
1353 lcdc_info = da8xx_fb_get_videomode(device);
1354 if (lcdc_info == NULL)
1355 return -ENODEV;
1356
1357 lcdc_regs = platform_get_resource(device, IORESOURCE_MEM, 0);
1358 da8xx_fb_reg_base = devm_ioremap_resource(&device->dev, lcdc_regs);
1359 if (IS_ERR(da8xx_fb_reg_base))
1360 return PTR_ERR(da8xx_fb_reg_base);
1361
1362 tmp_lcdc_clk = devm_clk_get(&device->dev, "fck");
1363 if (IS_ERR(tmp_lcdc_clk)) {
1364 dev_err(&device->dev, "Can not get device clock\n");
1365 return PTR_ERR(tmp_lcdc_clk);
1366 }
1367
1368 pm_runtime_enable(&device->dev);
1369 pm_runtime_get_sync(&device->dev);
1370
1371 /* Determine LCD IP Version */
1372 switch (lcdc_read(LCD_PID_REG)) {
1373 case 0x4C100102:
1374 lcd_revision = LCD_VERSION_1;
1375 break;
1376 case 0x4F200800:
1377 case 0x4F201000:
1378 lcd_revision = LCD_VERSION_2;
1379 break;
1380 default:
1381 dev_warn(&device->dev, "Unknown PID Reg value 0x%x, "
1382 "defaulting to LCD revision 1\n",
1383 lcdc_read(LCD_PID_REG));
1384 lcd_revision = LCD_VERSION_1;
1385 break;
1386 }
1387
1388 lcd_cfg = (struct lcd_ctrl_config *)fb_pdata->controller_data;
1389
1390 if (!lcd_cfg) {
1391 ret = -EINVAL;
1392 goto err_pm_runtime_disable;
1393 }
1394
1395 da8xx_fb_info = framebuffer_alloc(sizeof(struct da8xx_fb_par),
1396 &device->dev);
1397 if (!da8xx_fb_info) {
1398 dev_dbg(&device->dev, "Memory allocation failed for fb_info\n");
1399 ret = -ENOMEM;
1400 goto err_pm_runtime_disable;
1401 }
1402
1403 par = da8xx_fb_info->par;
1404 par->dev = &device->dev;
1405 par->lcdc_clk = tmp_lcdc_clk;
1406 par->lcdc_clk_rate = clk_get_rate(par->lcdc_clk);
1407 if (fb_pdata->panel_power_ctrl) {
1408 par->panel_power_ctrl = fb_pdata->panel_power_ctrl;
1409 par->panel_power_ctrl(1);
1410 }
1411
1412 fb_videomode_to_var(&da8xx_fb_var, lcdc_info);
1413 par->cfg = *lcd_cfg;
1414
1415 da8xx_fb_lcd_reset();
1416
1417 /* allocate frame buffer */
1418 par->vram_size = lcdc_info->xres * lcdc_info->yres * lcd_cfg->bpp;
1419 ulcm = lcm((lcdc_info->xres * lcd_cfg->bpp)/8, PAGE_SIZE);
1420 par->vram_size = roundup(par->vram_size/8, ulcm);
1421 par->vram_size = par->vram_size * LCD_NUM_BUFFERS;
1422
1423 par->vram_virt = dma_alloc_coherent(NULL,
1424 par->vram_size,
1425 (resource_size_t *) &par->vram_phys,
1426 GFP_KERNEL | GFP_DMA);
1427 if (!par->vram_virt) {
1428 dev_err(&device->dev,
1429 "GLCD: kmalloc for frame buffer failed\n");
1430 ret = -EINVAL;
1431 goto err_release_fb;
1432 }
1433
1434 da8xx_fb_info->screen_base = (char __iomem *) par->vram_virt;
1435 da8xx_fb_fix.smem_start = par->vram_phys;
1436 da8xx_fb_fix.smem_len = par->vram_size;
1437 da8xx_fb_fix.line_length = (lcdc_info->xres * lcd_cfg->bpp) / 8;
1438
1439 par->dma_start = par->vram_phys;
1440 par->dma_end = par->dma_start + lcdc_info->yres *
1441 da8xx_fb_fix.line_length - 1;
1442
1443 /* allocate palette buffer */
1444 par->v_palette_base = dma_alloc_coherent(NULL,
1445 PALETTE_SIZE,
1446 (resource_size_t *)
1447 &par->p_palette_base,
1448 GFP_KERNEL | GFP_DMA);
1449 if (!par->v_palette_base) {
1450 dev_err(&device->dev,
1451 "GLCD: kmalloc for palette buffer failed\n");
1452 ret = -EINVAL;
1453 goto err_release_fb_mem;
1454 }
1455 memset(par->v_palette_base, 0, PALETTE_SIZE);
1456
1457 par->irq = platform_get_irq(device, 0);
1458 if (par->irq < 0) {
1459 ret = -ENOENT;
1460 goto err_release_pl_mem;
1461 }
1462
1463 da8xx_fb_var.grayscale =
1464 lcd_cfg->panel_shade == MONOCHROME ? 1 : 0;
1465 da8xx_fb_var.bits_per_pixel = lcd_cfg->bpp;
1466
1467 /* Initialize fbinfo */
1468 da8xx_fb_info->flags = FBINFO_FLAG_DEFAULT;
1469 da8xx_fb_info->fix = da8xx_fb_fix;
1470 da8xx_fb_info->var = da8xx_fb_var;
1471 da8xx_fb_info->fbops = &da8xx_fb_ops;
1472 da8xx_fb_info->pseudo_palette = par->pseudo_palette;
1473 da8xx_fb_info->fix.visual = (da8xx_fb_info->var.bits_per_pixel <= 8) ?
1474 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1475
1476 ret = fb_alloc_cmap(&da8xx_fb_info->cmap, PALETTE_SIZE, 0);
1477 if (ret)
1478 goto err_release_pl_mem;
1479 da8xx_fb_info->cmap.len = par->palette_sz;
1480
1481 /* initialize var_screeninfo */
1482 da8xx_fb_var.activate = FB_ACTIVATE_FORCE;
1483 fb_set_var(da8xx_fb_info, &da8xx_fb_var);
1484
1485 dev_set_drvdata(&device->dev, da8xx_fb_info);
1486
1487 /* initialize the vsync wait queue */
1488 init_waitqueue_head(&par->vsync_wait);
1489 par->vsync_timeout = HZ / 5;
1490 par->which_dma_channel_done = -1;
1491 spin_lock_init(&par->lock_for_chan_update);
1492
1493 /* Register the Frame Buffer */
1494 if (register_framebuffer(da8xx_fb_info) < 0) {
1495 dev_err(&device->dev,
1496 "GLCD: Frame Buffer Registration Failed!\n");
1497 ret = -EINVAL;
1498 goto err_dealloc_cmap;
1499 }
1500
1501 #ifdef CONFIG_CPU_FREQ
1502 ret = lcd_da8xx_cpufreq_register(par);
1503 if (ret) {
1504 dev_err(&device->dev, "failed to register cpufreq\n");
1505 goto err_cpu_freq;
1506 }
1507 #endif
1508
1509 if (lcd_revision == LCD_VERSION_1)
1510 lcdc_irq_handler = lcdc_irq_handler_rev01;
1511 else {
1512 init_waitqueue_head(&frame_done_wq);
1513 lcdc_irq_handler = lcdc_irq_handler_rev02;
1514 }
1515
1516 ret = devm_request_irq(&device->dev, par->irq, lcdc_irq_handler, 0,
1517 DRIVER_NAME, par);
1518 if (ret)
1519 goto irq_freq;
1520 return 0;
1521
1522 irq_freq:
1523 #ifdef CONFIG_CPU_FREQ
1524 lcd_da8xx_cpufreq_deregister(par);
1525 err_cpu_freq:
1526 #endif
1527 unregister_framebuffer(da8xx_fb_info);
1528
1529 err_dealloc_cmap:
1530 fb_dealloc_cmap(&da8xx_fb_info->cmap);
1531
1532 err_release_pl_mem:
1533 dma_free_coherent(NULL, PALETTE_SIZE, par->v_palette_base,
1534 par->p_palette_base);
1535
1536 err_release_fb_mem:
1537 dma_free_coherent(NULL, par->vram_size, par->vram_virt, par->vram_phys);
1538
1539 err_release_fb:
1540 framebuffer_release(da8xx_fb_info);
1541
1542 err_pm_runtime_disable:
1543 pm_runtime_put_sync(&device->dev);
1544 pm_runtime_disable(&device->dev);
1545
1546 return ret;
1547 }
1548
1549 #ifdef CONFIG_PM
1550 static struct lcdc_context {
1551 u32 clk_enable;
1552 u32 ctrl;
1553 u32 dma_ctrl;
1554 u32 raster_timing_0;
1555 u32 raster_timing_1;
1556 u32 raster_timing_2;
1557 u32 int_enable_set;
1558 u32 dma_frm_buf_base_addr_0;
1559 u32 dma_frm_buf_ceiling_addr_0;
1560 u32 dma_frm_buf_base_addr_1;
1561 u32 dma_frm_buf_ceiling_addr_1;
1562 u32 raster_ctrl;
1563 } reg_context;
1564
1565 static void lcd_context_save(void)
1566 {
1567 if (lcd_revision == LCD_VERSION_2) {
1568 reg_context.clk_enable = lcdc_read(LCD_CLK_ENABLE_REG);
1569 reg_context.int_enable_set = lcdc_read(LCD_INT_ENABLE_SET_REG);
1570 }
1571
1572 reg_context.ctrl = lcdc_read(LCD_CTRL_REG);
1573 reg_context.dma_ctrl = lcdc_read(LCD_DMA_CTRL_REG);
1574 reg_context.raster_timing_0 = lcdc_read(LCD_RASTER_TIMING_0_REG);
1575 reg_context.raster_timing_1 = lcdc_read(LCD_RASTER_TIMING_1_REG);
1576 reg_context.raster_timing_2 = lcdc_read(LCD_RASTER_TIMING_2_REG);
1577 reg_context.dma_frm_buf_base_addr_0 =
1578 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1579 reg_context.dma_frm_buf_ceiling_addr_0 =
1580 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1581 reg_context.dma_frm_buf_base_addr_1 =
1582 lcdc_read(LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1583 reg_context.dma_frm_buf_ceiling_addr_1 =
1584 lcdc_read(LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1585 reg_context.raster_ctrl = lcdc_read(LCD_RASTER_CTRL_REG);
1586 return;
1587 }
1588
1589 static void lcd_context_restore(void)
1590 {
1591 if (lcd_revision == LCD_VERSION_2) {
1592 lcdc_write(reg_context.clk_enable, LCD_CLK_ENABLE_REG);
1593 lcdc_write(reg_context.int_enable_set, LCD_INT_ENABLE_SET_REG);
1594 }
1595
1596 lcdc_write(reg_context.ctrl, LCD_CTRL_REG);
1597 lcdc_write(reg_context.dma_ctrl, LCD_DMA_CTRL_REG);
1598 lcdc_write(reg_context.raster_timing_0, LCD_RASTER_TIMING_0_REG);
1599 lcdc_write(reg_context.raster_timing_1, LCD_RASTER_TIMING_1_REG);
1600 lcdc_write(reg_context.raster_timing_2, LCD_RASTER_TIMING_2_REG);
1601 lcdc_write(reg_context.dma_frm_buf_base_addr_0,
1602 LCD_DMA_FRM_BUF_BASE_ADDR_0_REG);
1603 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_0,
1604 LCD_DMA_FRM_BUF_CEILING_ADDR_0_REG);
1605 lcdc_write(reg_context.dma_frm_buf_base_addr_1,
1606 LCD_DMA_FRM_BUF_BASE_ADDR_1_REG);
1607 lcdc_write(reg_context.dma_frm_buf_ceiling_addr_1,
1608 LCD_DMA_FRM_BUF_CEILING_ADDR_1_REG);
1609 lcdc_write(reg_context.raster_ctrl, LCD_RASTER_CTRL_REG);
1610 return;
1611 }
1612
1613 static int fb_suspend(struct platform_device *dev, pm_message_t state)
1614 {
1615 struct fb_info *info = platform_get_drvdata(dev);
1616 struct da8xx_fb_par *par = info->par;
1617
1618 console_lock();
1619 if (par->panel_power_ctrl)
1620 par->panel_power_ctrl(0);
1621
1622 fb_set_suspend(info, 1);
1623 lcd_disable_raster(DA8XX_FRAME_WAIT);
1624 lcd_context_save();
1625 pm_runtime_put_sync(&dev->dev);
1626 console_unlock();
1627
1628 return 0;
1629 }
1630 static int fb_resume(struct platform_device *dev)
1631 {
1632 struct fb_info *info = platform_get_drvdata(dev);
1633 struct da8xx_fb_par *par = info->par;
1634
1635 console_lock();
1636 pm_runtime_get_sync(&dev->dev);
1637 lcd_context_restore();
1638 if (par->blank == FB_BLANK_UNBLANK) {
1639 lcd_enable_raster();
1640
1641 if (par->panel_power_ctrl)
1642 par->panel_power_ctrl(1);
1643 }
1644
1645 fb_set_suspend(info, 0);
1646 console_unlock();
1647
1648 return 0;
1649 }
1650 #else
1651 #define fb_suspend NULL
1652 #define fb_resume NULL
1653 #endif
1654
1655 static struct platform_driver da8xx_fb_driver = {
1656 .probe = fb_probe,
1657 .remove = fb_remove,
1658 .suspend = fb_suspend,
1659 .resume = fb_resume,
1660 .driver = {
1661 .name = DRIVER_NAME,
1662 .owner = THIS_MODULE,
1663 },
1664 };
1665 module_platform_driver(da8xx_fb_driver);
1666
1667 MODULE_DESCRIPTION("Framebuffer driver for TI da8xx/omap-l1xx");
1668 MODULE_AUTHOR("Texas Instruments");
1669 MODULE_LICENSE("GPL");
Linux with added FPC-III support