?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
net: dsa: mt7530: set CPU port to fallback mode
[linux/fpc-iii.git] / sound / pci / hda / patch_ca0132.c
blobc9f3c002bd553483227a1c8ced327f1bad30abdf
1 /*
2 * HD audio interface patch for Creative CA0132 chip
3 *
4 * Copyright (c) 2011, Creative Technology Ltd.
5 *
6 * Based on patch_ca0110.c
7 * Copyright (c) 2008 Takashi Iwai <tiwai@suse.de>
8 *
9 * This driver is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This driver is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 */
23
24 #include <linux/init.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/mutex.h>
28 #include <linux/module.h>
29 #include <linux/firmware.h>
30 #include <linux/kernel.h>
31 #include <linux/types.h>
32 #include <linux/io.h>
33 #include <linux/pci.h>
34 #include <asm/io.h>
35 #include <sound/core.h>
36 #include "hda_codec.h"
37 #include "hda_local.h"
38 #include "hda_auto_parser.h"
39 #include "hda_jack.h"
40
41 #include "ca0132_regs.h"
42
43 /* Enable this to see controls for tuning purpose. */
44 /*#define ENABLE_TUNING_CONTROLS*/
45
46 #ifdef ENABLE_TUNING_CONTROLS
47 #include <sound/tlv.h>
48 #endif
49
50 #define FLOAT_ZERO 0x00000000
51 #define FLOAT_ONE 0x3f800000
52 #define FLOAT_TWO 0x40000000
53 #define FLOAT_THREE 0x40400000
54 #define FLOAT_EIGHT 0x41000000
55 #define FLOAT_MINUS_5 0xc0a00000
56
57 #define UNSOL_TAG_DSP 0x16
58
59 #define DSP_DMA_WRITE_BUFLEN_INIT (1UL<<18)
60 #define DSP_DMA_WRITE_BUFLEN_OVLY (1UL<<15)
61
62 #define DMA_TRANSFER_FRAME_SIZE_NWORDS 8
63 #define DMA_TRANSFER_MAX_FRAME_SIZE_NWORDS 32
64 #define DMA_OVERLAY_FRAME_SIZE_NWORDS 2
65
66 #define MASTERCONTROL 0x80
67 #define MASTERCONTROL_ALLOC_DMA_CHAN 10
68 #define MASTERCONTROL_QUERY_SPEAKER_EQ_ADDRESS 60
69
70 #define WIDGET_CHIP_CTRL 0x15
71 #define WIDGET_DSP_CTRL 0x16
72
73 #define MEM_CONNID_MICIN1 3
74 #define MEM_CONNID_MICIN2 5
75 #define MEM_CONNID_MICOUT1 12
76 #define MEM_CONNID_MICOUT2 14
77 #define MEM_CONNID_WUH 10
78 #define MEM_CONNID_DSP 16
79 #define MEM_CONNID_DMIC 100
80
81 #define SCP_SET 0
82 #define SCP_GET 1
83
84 #define EFX_FILE "ctefx.bin"
85 #define SBZ_EFX_FILE "ctefx-sbz.bin"
86 #define R3DI_EFX_FILE "ctefx-r3di.bin"
87
88 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
89 MODULE_FIRMWARE(EFX_FILE);
90 MODULE_FIRMWARE(SBZ_EFX_FILE);
91 MODULE_FIRMWARE(R3DI_EFX_FILE);
92 #endif
93
94 static const char *const dirstr[2] = { "Playback", "Capture" };
95
96 #define NUM_OF_OUTPUTS 3
97 enum {
98 SPEAKER_OUT,
99 HEADPHONE_OUT,
100 SURROUND_OUT
101 };
102
103 enum {
104 DIGITAL_MIC,
105 LINE_MIC_IN
106 };
107
108 /* Strings for Input Source Enum Control */
109 static const char *const in_src_str[3] = {"Rear Mic", "Line", "Front Mic" };
110 #define IN_SRC_NUM_OF_INPUTS 3
111 enum {
112 REAR_MIC,
113 REAR_LINE_IN,
114 FRONT_MIC,
115 };
116
117 enum {
118 #define VNODE_START_NID 0x80
119 VNID_SPK = VNODE_START_NID, /* Speaker vnid */
120 VNID_MIC,
121 VNID_HP_SEL,
122 VNID_AMIC1_SEL,
123 VNID_HP_ASEL,
124 VNID_AMIC1_ASEL,
125 VNODE_END_NID,
126 #define VNODES_COUNT (VNODE_END_NID - VNODE_START_NID)
127
128 #define EFFECT_START_NID 0x90
129 #define OUT_EFFECT_START_NID EFFECT_START_NID
130 SURROUND = OUT_EFFECT_START_NID,
131 CRYSTALIZER,
132 DIALOG_PLUS,
133 SMART_VOLUME,
134 X_BASS,
135 EQUALIZER,
136 OUT_EFFECT_END_NID,
137 #define OUT_EFFECTS_COUNT (OUT_EFFECT_END_NID - OUT_EFFECT_START_NID)
138
139 #define IN_EFFECT_START_NID OUT_EFFECT_END_NID
140 ECHO_CANCELLATION = IN_EFFECT_START_NID,
141 VOICE_FOCUS,
142 MIC_SVM,
143 NOISE_REDUCTION,
144 IN_EFFECT_END_NID,
145 #define IN_EFFECTS_COUNT (IN_EFFECT_END_NID - IN_EFFECT_START_NID)
146
147 VOICEFX = IN_EFFECT_END_NID,
148 PLAY_ENHANCEMENT,
149 CRYSTAL_VOICE,
150 EFFECT_END_NID,
151 OUTPUT_SOURCE_ENUM,
152 INPUT_SOURCE_ENUM,
153 XBASS_XOVER,
154 EQ_PRESET_ENUM,
155 SMART_VOLUME_ENUM,
156 MIC_BOOST_ENUM
157 #define EFFECTS_COUNT (EFFECT_END_NID - EFFECT_START_NID)
158 };
159
160 /* Effects values size*/
161 #define EFFECT_VALS_MAX_COUNT 12
162
163 /*
164 * Default values for the effect slider controls, they are in order of their
165 * effect NID's. Surround, Crystalizer, Dialog Plus, Smart Volume, and then
166 * X-bass.
167 */
168 static const unsigned int effect_slider_defaults[] = {67, 65, 50, 74, 50};
169 /* Amount of effect level sliders for ca0132_alt controls. */
170 #define EFFECT_LEVEL_SLIDERS 5
171
172 /* Latency introduced by DSP blocks in milliseconds. */
173 #define DSP_CAPTURE_INIT_LATENCY 0
174 #define DSP_CRYSTAL_VOICE_LATENCY 124
175 #define DSP_PLAYBACK_INIT_LATENCY 13
176 #define DSP_PLAY_ENHANCEMENT_LATENCY 30
177 #define DSP_SPEAKER_OUT_LATENCY 7
178
179 struct ct_effect {
180 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
181 hda_nid_t nid;
182 int mid; /*effect module ID*/
183 int reqs[EFFECT_VALS_MAX_COUNT]; /*effect module request*/
184 int direct; /* 0:output; 1:input*/
185 int params; /* number of default non-on/off params */
186 /*effect default values, 1st is on/off. */
187 unsigned int def_vals[EFFECT_VALS_MAX_COUNT];
188 };
189
190 #define EFX_DIR_OUT 0
191 #define EFX_DIR_IN 1
192
193 static const struct ct_effect ca0132_effects[EFFECTS_COUNT] = {
194 { .name = "Surround",
195 .nid = SURROUND,
196 .mid = 0x96,
197 .reqs = {0, 1},
198 .direct = EFX_DIR_OUT,
199 .params = 1,
200 .def_vals = {0x3F800000, 0x3F2B851F}
201 },
202 { .name = "Crystalizer",
203 .nid = CRYSTALIZER,
204 .mid = 0x96,
205 .reqs = {7, 8},
206 .direct = EFX_DIR_OUT,
207 .params = 1,
208 .def_vals = {0x3F800000, 0x3F266666}
209 },
210 { .name = "Dialog Plus",
211 .nid = DIALOG_PLUS,
212 .mid = 0x96,
213 .reqs = {2, 3},
214 .direct = EFX_DIR_OUT,
215 .params = 1,
216 .def_vals = {0x00000000, 0x3F000000}
217 },
218 { .name = "Smart Volume",
219 .nid = SMART_VOLUME,
220 .mid = 0x96,
221 .reqs = {4, 5, 6},
222 .direct = EFX_DIR_OUT,
223 .params = 2,
224 .def_vals = {0x3F800000, 0x3F3D70A4, 0x00000000}
225 },
226 { .name = "X-Bass",
227 .nid = X_BASS,
228 .mid = 0x96,
229 .reqs = {24, 23, 25},
230 .direct = EFX_DIR_OUT,
231 .params = 2,
232 .def_vals = {0x3F800000, 0x42A00000, 0x3F000000}
233 },
234 { .name = "Equalizer",
235 .nid = EQUALIZER,
236 .mid = 0x96,
237 .reqs = {9, 10, 11, 12, 13, 14,
238 15, 16, 17, 18, 19, 20},
239 .direct = EFX_DIR_OUT,
240 .params = 11,
241 .def_vals = {0x00000000, 0x00000000, 0x00000000, 0x00000000,
242 0x00000000, 0x00000000, 0x00000000, 0x00000000,
243 0x00000000, 0x00000000, 0x00000000, 0x00000000}
244 },
245 { .name = "Echo Cancellation",
246 .nid = ECHO_CANCELLATION,
247 .mid = 0x95,
248 .reqs = {0, 1, 2, 3},
249 .direct = EFX_DIR_IN,
250 .params = 3,
251 .def_vals = {0x00000000, 0x3F3A9692, 0x00000000, 0x00000000}
252 },
253 { .name = "Voice Focus",
254 .nid = VOICE_FOCUS,
255 .mid = 0x95,
256 .reqs = {6, 7, 8, 9},
257 .direct = EFX_DIR_IN,
258 .params = 3,
259 .def_vals = {0x3F800000, 0x3D7DF3B6, 0x41F00000, 0x41F00000}
260 },
261 { .name = "Mic SVM",
262 .nid = MIC_SVM,
263 .mid = 0x95,
264 .reqs = {44, 45},
265 .direct = EFX_DIR_IN,
266 .params = 1,
267 .def_vals = {0x00000000, 0x3F3D70A4}
268 },
269 { .name = "Noise Reduction",
270 .nid = NOISE_REDUCTION,
271 .mid = 0x95,
272 .reqs = {4, 5},
273 .direct = EFX_DIR_IN,
274 .params = 1,
275 .def_vals = {0x3F800000, 0x3F000000}
276 },
277 { .name = "VoiceFX",
278 .nid = VOICEFX,
279 .mid = 0x95,
280 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18},
281 .direct = EFX_DIR_IN,
282 .params = 8,
283 .def_vals = {0x00000000, 0x43C80000, 0x44AF0000, 0x44FA0000,
284 0x3F800000, 0x3F800000, 0x3F800000, 0x00000000,
285 0x00000000}
286 }
287 };
288
289 /* Tuning controls */
290 #ifdef ENABLE_TUNING_CONTROLS
291
292 enum {
293 #define TUNING_CTL_START_NID 0xC0
294 WEDGE_ANGLE = TUNING_CTL_START_NID,
295 SVM_LEVEL,
296 EQUALIZER_BAND_0,
297 EQUALIZER_BAND_1,
298 EQUALIZER_BAND_2,
299 EQUALIZER_BAND_3,
300 EQUALIZER_BAND_4,
301 EQUALIZER_BAND_5,
302 EQUALIZER_BAND_6,
303 EQUALIZER_BAND_7,
304 EQUALIZER_BAND_8,
305 EQUALIZER_BAND_9,
306 TUNING_CTL_END_NID
307 #define TUNING_CTLS_COUNT (TUNING_CTL_END_NID - TUNING_CTL_START_NID)
308 };
309
310 struct ct_tuning_ctl {
311 char name[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
312 hda_nid_t parent_nid;
313 hda_nid_t nid;
314 int mid; /*effect module ID*/
315 int req; /*effect module request*/
316 int direct; /* 0:output; 1:input*/
317 unsigned int def_val;/*effect default values*/
318 };
319
320 static const struct ct_tuning_ctl ca0132_tuning_ctls[] = {
321 { .name = "Wedge Angle",
322 .parent_nid = VOICE_FOCUS,
323 .nid = WEDGE_ANGLE,
324 .mid = 0x95,
325 .req = 8,
326 .direct = EFX_DIR_IN,
327 .def_val = 0x41F00000
328 },
329 { .name = "SVM Level",
330 .parent_nid = MIC_SVM,
331 .nid = SVM_LEVEL,
332 .mid = 0x95,
333 .req = 45,
334 .direct = EFX_DIR_IN,
335 .def_val = 0x3F3D70A4
336 },
337 { .name = "EQ Band0",
338 .parent_nid = EQUALIZER,
339 .nid = EQUALIZER_BAND_0,
340 .mid = 0x96,
341 .req = 11,
342 .direct = EFX_DIR_OUT,
343 .def_val = 0x00000000
344 },
345 { .name = "EQ Band1",
346 .parent_nid = EQUALIZER,
347 .nid = EQUALIZER_BAND_1,
348 .mid = 0x96,
349 .req = 12,
350 .direct = EFX_DIR_OUT,
351 .def_val = 0x00000000
352 },
353 { .name = "EQ Band2",
354 .parent_nid = EQUALIZER,
355 .nid = EQUALIZER_BAND_2,
356 .mid = 0x96,
357 .req = 13,
358 .direct = EFX_DIR_OUT,
359 .def_val = 0x00000000
360 },
361 { .name = "EQ Band3",
362 .parent_nid = EQUALIZER,
363 .nid = EQUALIZER_BAND_3,
364 .mid = 0x96,
365 .req = 14,
366 .direct = EFX_DIR_OUT,
367 .def_val = 0x00000000
368 },
369 { .name = "EQ Band4",
370 .parent_nid = EQUALIZER,
371 .nid = EQUALIZER_BAND_4,
372 .mid = 0x96,
373 .req = 15,
374 .direct = EFX_DIR_OUT,
375 .def_val = 0x00000000
376 },
377 { .name = "EQ Band5",
378 .parent_nid = EQUALIZER,
379 .nid = EQUALIZER_BAND_5,
380 .mid = 0x96,
381 .req = 16,
382 .direct = EFX_DIR_OUT,
383 .def_val = 0x00000000
384 },
385 { .name = "EQ Band6",
386 .parent_nid = EQUALIZER,
387 .nid = EQUALIZER_BAND_6,
388 .mid = 0x96,
389 .req = 17,
390 .direct = EFX_DIR_OUT,
391 .def_val = 0x00000000
392 },
393 { .name = "EQ Band7",
394 .parent_nid = EQUALIZER,
395 .nid = EQUALIZER_BAND_7,
396 .mid = 0x96,
397 .req = 18,
398 .direct = EFX_DIR_OUT,
399 .def_val = 0x00000000
400 },
401 { .name = "EQ Band8",
402 .parent_nid = EQUALIZER,
403 .nid = EQUALIZER_BAND_8,
404 .mid = 0x96,
405 .req = 19,
406 .direct = EFX_DIR_OUT,
407 .def_val = 0x00000000
408 },
409 { .name = "EQ Band9",
410 .parent_nid = EQUALIZER,
411 .nid = EQUALIZER_BAND_9,
412 .mid = 0x96,
413 .req = 20,
414 .direct = EFX_DIR_OUT,
415 .def_val = 0x00000000
416 }
417 };
418 #endif
419
420 /* Voice FX Presets */
421 #define VOICEFX_MAX_PARAM_COUNT 9
422
423 struct ct_voicefx {
424 char *name;
425 hda_nid_t nid;
426 int mid;
427 int reqs[VOICEFX_MAX_PARAM_COUNT]; /*effect module request*/
428 };
429
430 struct ct_voicefx_preset {
431 char *name; /*preset name*/
432 unsigned int vals[VOICEFX_MAX_PARAM_COUNT];
433 };
434
435 static const struct ct_voicefx ca0132_voicefx = {
436 .name = "VoiceFX Capture Switch",
437 .nid = VOICEFX,
438 .mid = 0x95,
439 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18}
440 };
441
442 static const struct ct_voicefx_preset ca0132_voicefx_presets[] = {
443 { .name = "Neutral",
444 .vals = { 0x00000000, 0x43C80000, 0x44AF0000,
445 0x44FA0000, 0x3F800000, 0x3F800000,
446 0x3F800000, 0x00000000, 0x00000000 }
447 },
448 { .name = "Female2Male",
449 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
450 0x44FA0000, 0x3F19999A, 0x3F866666,
451 0x3F800000, 0x00000000, 0x00000000 }
452 },
453 { .name = "Male2Female",
454 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
455 0x450AC000, 0x4017AE14, 0x3F6B851F,
456 0x3F800000, 0x00000000, 0x00000000 }
457 },
458 { .name = "ScrappyKid",
459 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
460 0x44FA0000, 0x40400000, 0x3F28F5C3,
461 0x3F800000, 0x00000000, 0x00000000 }
462 },
463 { .name = "Elderly",
464 .vals = { 0x3F800000, 0x44324000, 0x44BB8000,
465 0x44E10000, 0x3FB33333, 0x3FB9999A,
466 0x3F800000, 0x3E3A2E43, 0x00000000 }
467 },
468 { .name = "Orc",
469 .vals = { 0x3F800000, 0x43EA0000, 0x44A52000,
470 0x45098000, 0x3F266666, 0x3FC00000,
471 0x3F800000, 0x00000000, 0x00000000 }
472 },
473 { .name = "Elf",
474 .vals = { 0x3F800000, 0x43C70000, 0x44AE6000,
475 0x45193000, 0x3F8E147B, 0x3F75C28F,
476 0x3F800000, 0x00000000, 0x00000000 }
477 },
478 { .name = "Dwarf",
479 .vals = { 0x3F800000, 0x43930000, 0x44BEE000,
480 0x45007000, 0x3F451EB8, 0x3F7851EC,
481 0x3F800000, 0x00000000, 0x00000000 }
482 },
483 { .name = "AlienBrute",
484 .vals = { 0x3F800000, 0x43BFC5AC, 0x44B28FDF,
485 0x451F6000, 0x3F266666, 0x3FA7D945,
486 0x3F800000, 0x3CF5C28F, 0x00000000 }
487 },
488 { .name = "Robot",
489 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
490 0x44FA0000, 0x3FB2718B, 0x3F800000,
491 0xBC07010E, 0x00000000, 0x00000000 }
492 },
493 { .name = "Marine",
494 .vals = { 0x3F800000, 0x43C20000, 0x44906000,
495 0x44E70000, 0x3F4CCCCD, 0x3F8A3D71,
496 0x3F0A3D71, 0x00000000, 0x00000000 }
497 },
498 { .name = "Emo",
499 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
500 0x44FA0000, 0x3F800000, 0x3F800000,
501 0x3E4CCCCD, 0x00000000, 0x00000000 }
502 },
503 { .name = "DeepVoice",
504 .vals = { 0x3F800000, 0x43A9C5AC, 0x44AA4FDF,
505 0x44FFC000, 0x3EDBB56F, 0x3F99C4CA,
506 0x3F800000, 0x00000000, 0x00000000 }
507 },
508 { .name = "Munchkin",
509 .vals = { 0x3F800000, 0x43C80000, 0x44AF0000,
510 0x44FA0000, 0x3F800000, 0x3F1A043C,
511 0x3F800000, 0x00000000, 0x00000000 }
512 }
513 };
514
515 /* ca0132 EQ presets, taken from Windows Sound Blaster Z Driver */
516
517 #define EQ_PRESET_MAX_PARAM_COUNT 11
518
519 struct ct_eq {
520 char *name;
521 hda_nid_t nid;
522 int mid;
523 int reqs[EQ_PRESET_MAX_PARAM_COUNT]; /*effect module request*/
524 };
525
526 struct ct_eq_preset {
527 char *name; /*preset name*/
528 unsigned int vals[EQ_PRESET_MAX_PARAM_COUNT];
529 };
530
531 static const struct ct_eq ca0132_alt_eq_enum = {
532 .name = "FX: Equalizer Preset Switch",
533 .nid = EQ_PRESET_ENUM,
534 .mid = 0x96,
535 .reqs = {10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20}
536 };
537
538
539 static const struct ct_eq_preset ca0132_alt_eq_presets[] = {
540 { .name = "Flat",
541 .vals = { 0x00000000, 0x00000000, 0x00000000,
542 0x00000000, 0x00000000, 0x00000000,
543 0x00000000, 0x00000000, 0x00000000,
544 0x00000000, 0x00000000 }
545 },
546 { .name = "Acoustic",
547 .vals = { 0x00000000, 0x00000000, 0x3F8CCCCD,
548 0x40000000, 0x00000000, 0x00000000,
549 0x00000000, 0x00000000, 0x40000000,
550 0x40000000, 0x40000000 }
551 },
552 { .name = "Classical",
553 .vals = { 0x00000000, 0x00000000, 0x40C00000,
554 0x40C00000, 0x40466666, 0x00000000,
555 0x00000000, 0x00000000, 0x00000000,
556 0x40466666, 0x40466666 }
557 },
558 { .name = "Country",
559 .vals = { 0x00000000, 0xBF99999A, 0x00000000,
560 0x3FA66666, 0x3FA66666, 0x3F8CCCCD,
561 0x00000000, 0x00000000, 0x40000000,
562 0x40466666, 0x40800000 }
563 },
564 { .name = "Dance",
565 .vals = { 0x00000000, 0xBF99999A, 0x40000000,
566 0x40466666, 0x40866666, 0xBF99999A,
567 0xBF99999A, 0x00000000, 0x00000000,
568 0x40800000, 0x40800000 }
569 },
570 { .name = "Jazz",
571 .vals = { 0x00000000, 0x00000000, 0x00000000,
572 0x3F8CCCCD, 0x40800000, 0x40800000,
573 0x40800000, 0x00000000, 0x3F8CCCCD,
574 0x40466666, 0x40466666 }
575 },
576 { .name = "New Age",
577 .vals = { 0x00000000, 0x00000000, 0x40000000,
578 0x40000000, 0x00000000, 0x00000000,
579 0x00000000, 0x3F8CCCCD, 0x40000000,
580 0x40000000, 0x40000000 }
581 },
582 { .name = "Pop",
583 .vals = { 0x00000000, 0xBFCCCCCD, 0x00000000,
584 0x40000000, 0x40000000, 0x00000000,
585 0xBF99999A, 0xBF99999A, 0x00000000,
586 0x40466666, 0x40C00000 }
587 },
588 { .name = "Rock",
589 .vals = { 0x00000000, 0xBF99999A, 0xBF99999A,
590 0x3F8CCCCD, 0x40000000, 0xBF99999A,
591 0xBF99999A, 0x00000000, 0x00000000,
592 0x40800000, 0x40800000 }
593 },
594 { .name = "Vocal",
595 .vals = { 0x00000000, 0xC0000000, 0xBF99999A,
596 0xBF99999A, 0x00000000, 0x40466666,
597 0x40800000, 0x40466666, 0x00000000,
598 0x00000000, 0x3F8CCCCD }
599 }
600 };
601
602 /* DSP command sequences for ca0132_alt_select_out */
603 #define ALT_OUT_SET_MAX_COMMANDS 9 /* Max number of commands in sequence */
604 struct ca0132_alt_out_set {
605 char *name; /*preset name*/
606 unsigned char commands;
607 unsigned int mids[ALT_OUT_SET_MAX_COMMANDS];
608 unsigned int reqs[ALT_OUT_SET_MAX_COMMANDS];
609 unsigned int vals[ALT_OUT_SET_MAX_COMMANDS];
610 };
611
612 static const struct ca0132_alt_out_set alt_out_presets[] = {
613 { .name = "Line Out",
614 .commands = 7,
615 .mids = { 0x96, 0x96, 0x96, 0x8F,
616 0x96, 0x96, 0x96 },
617 .reqs = { 0x19, 0x17, 0x18, 0x01,
618 0x1F, 0x15, 0x3A },
619 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
620 0x00000000, 0x00000000, 0x00000000,
621 0x00000000 }
622 },
623 { .name = "Headphone",
624 .commands = 7,
625 .mids = { 0x96, 0x96, 0x96, 0x8F,
626 0x96, 0x96, 0x96 },
627 .reqs = { 0x19, 0x17, 0x18, 0x01,
628 0x1F, 0x15, 0x3A },
629 .vals = { 0x3F000000, 0x42A00000, 0x00000000,
630 0x00000000, 0x00000000, 0x00000000,
631 0x00000000 }
632 },
633 { .name = "Surround",
634 .commands = 8,
635 .mids = { 0x96, 0x8F, 0x96, 0x96,
636 0x96, 0x96, 0x96, 0x96 },
637 .reqs = { 0x18, 0x01, 0x1F, 0x15,
638 0x3A, 0x1A, 0x1B, 0x1C },
639 .vals = { 0x00000000, 0x00000000, 0x00000000,
640 0x00000000, 0x00000000, 0x00000000,
641 0x00000000, 0x00000000 }
642 }
643 };
644
645 /*
646 * DSP volume setting structs. Req 1 is left volume, req 2 is right volume,
647 * and I don't know what the third req is, but it's always zero. I assume it's
648 * some sort of update or set command to tell the DSP there's new volume info.
649 */
650 #define DSP_VOL_OUT 0
651 #define DSP_VOL_IN 1
652
653 struct ct_dsp_volume_ctl {
654 hda_nid_t vnid;
655 int mid; /* module ID*/
656 unsigned int reqs[3]; /* scp req ID */
657 };
658
659 static const struct ct_dsp_volume_ctl ca0132_alt_vol_ctls[] = {
660 { .vnid = VNID_SPK,
661 .mid = 0x32,
662 .reqs = {3, 4, 2}
663 },
664 { .vnid = VNID_MIC,
665 .mid = 0x37,
666 .reqs = {2, 3, 1}
667 }
668 };
669
670 enum hda_cmd_vendor_io {
671 /* for DspIO node */
672 VENDOR_DSPIO_SCP_WRITE_DATA_LOW = 0x000,
673 VENDOR_DSPIO_SCP_WRITE_DATA_HIGH = 0x100,
674
675 VENDOR_DSPIO_STATUS = 0xF01,
676 VENDOR_DSPIO_SCP_POST_READ_DATA = 0x702,
677 VENDOR_DSPIO_SCP_READ_DATA = 0xF02,
678 VENDOR_DSPIO_DSP_INIT = 0x703,
679 VENDOR_DSPIO_SCP_POST_COUNT_QUERY = 0x704,
680 VENDOR_DSPIO_SCP_READ_COUNT = 0xF04,
681
682 /* for ChipIO node */
683 VENDOR_CHIPIO_ADDRESS_LOW = 0x000,
684 VENDOR_CHIPIO_ADDRESS_HIGH = 0x100,
685 VENDOR_CHIPIO_STREAM_FORMAT = 0x200,
686 VENDOR_CHIPIO_DATA_LOW = 0x300,
687 VENDOR_CHIPIO_DATA_HIGH = 0x400,
688
689 VENDOR_CHIPIO_GET_PARAMETER = 0xF00,
690 VENDOR_CHIPIO_STATUS = 0xF01,
691 VENDOR_CHIPIO_HIC_POST_READ = 0x702,
692 VENDOR_CHIPIO_HIC_READ_DATA = 0xF03,
693
694 VENDOR_CHIPIO_8051_DATA_WRITE = 0x707,
695 VENDOR_CHIPIO_8051_DATA_READ = 0xF07,
696
697 VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE = 0x70A,
698 VENDOR_CHIPIO_CT_EXTENSIONS_GET = 0xF0A,
699
700 VENDOR_CHIPIO_PLL_PMU_WRITE = 0x70C,
701 VENDOR_CHIPIO_PLL_PMU_READ = 0xF0C,
702 VENDOR_CHIPIO_8051_ADDRESS_LOW = 0x70D,
703 VENDOR_CHIPIO_8051_ADDRESS_HIGH = 0x70E,
704 VENDOR_CHIPIO_FLAG_SET = 0x70F,
705 VENDOR_CHIPIO_FLAGS_GET = 0xF0F,
706 VENDOR_CHIPIO_PARAM_SET = 0x710,
707 VENDOR_CHIPIO_PARAM_GET = 0xF10,
708
709 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET = 0x711,
710 VENDOR_CHIPIO_PORT_ALLOC_SET = 0x712,
711 VENDOR_CHIPIO_PORT_ALLOC_GET = 0xF12,
712 VENDOR_CHIPIO_PORT_FREE_SET = 0x713,
713
714 VENDOR_CHIPIO_PARAM_EX_ID_GET = 0xF17,
715 VENDOR_CHIPIO_PARAM_EX_ID_SET = 0x717,
716 VENDOR_CHIPIO_PARAM_EX_VALUE_GET = 0xF18,
717 VENDOR_CHIPIO_PARAM_EX_VALUE_SET = 0x718,
718
719 VENDOR_CHIPIO_DMIC_CTL_SET = 0x788,
720 VENDOR_CHIPIO_DMIC_CTL_GET = 0xF88,
721 VENDOR_CHIPIO_DMIC_PIN_SET = 0x789,
722 VENDOR_CHIPIO_DMIC_PIN_GET = 0xF89,
723 VENDOR_CHIPIO_DMIC_MCLK_SET = 0x78A,
724 VENDOR_CHIPIO_DMIC_MCLK_GET = 0xF8A,
725
726 VENDOR_CHIPIO_EAPD_SEL_SET = 0x78D
727 };
728
729 /*
730 * Control flag IDs
731 */
732 enum control_flag_id {
733 /* Connection manager stream setup is bypassed/enabled */
734 CONTROL_FLAG_C_MGR = 0,
735 /* DSP DMA is bypassed/enabled */
736 CONTROL_FLAG_DMA = 1,
737 /* 8051 'idle' mode is disabled/enabled */
738 CONTROL_FLAG_IDLE_ENABLE = 2,
739 /* Tracker for the SPDIF-in path is bypassed/enabled */
740 CONTROL_FLAG_TRACKER = 3,
741 /* DigitalOut to Spdif2Out connection is disabled/enabled */
742 CONTROL_FLAG_SPDIF2OUT = 4,
743 /* Digital Microphone is disabled/enabled */
744 CONTROL_FLAG_DMIC = 5,
745 /* ADC_B rate is 48 kHz/96 kHz */
746 CONTROL_FLAG_ADC_B_96KHZ = 6,
747 /* ADC_C rate is 48 kHz/96 kHz */
748 CONTROL_FLAG_ADC_C_96KHZ = 7,
749 /* DAC rate is 48 kHz/96 kHz (affects all DACs) */
750 CONTROL_FLAG_DAC_96KHZ = 8,
751 /* DSP rate is 48 kHz/96 kHz */
752 CONTROL_FLAG_DSP_96KHZ = 9,
753 /* SRC clock is 98 MHz/196 MHz (196 MHz forces rate to 96 KHz) */
754 CONTROL_FLAG_SRC_CLOCK_196MHZ = 10,
755 /* SRC rate is 48 kHz/96 kHz (48 kHz disabled when clock is 196 MHz) */
756 CONTROL_FLAG_SRC_RATE_96KHZ = 11,
757 /* Decode Loop (DSP->SRC->DSP) is disabled/enabled */
758 CONTROL_FLAG_DECODE_LOOP = 12,
759 /* De-emphasis filter on DAC-1 disabled/enabled */
760 CONTROL_FLAG_DAC1_DEEMPHASIS = 13,
761 /* De-emphasis filter on DAC-2 disabled/enabled */
762 CONTROL_FLAG_DAC2_DEEMPHASIS = 14,
763 /* De-emphasis filter on DAC-3 disabled/enabled */
764 CONTROL_FLAG_DAC3_DEEMPHASIS = 15,
765 /* High-pass filter on ADC_B disabled/enabled */
766 CONTROL_FLAG_ADC_B_HIGH_PASS = 16,
767 /* High-pass filter on ADC_C disabled/enabled */
768 CONTROL_FLAG_ADC_C_HIGH_PASS = 17,
769 /* Common mode on Port_A disabled/enabled */
770 CONTROL_FLAG_PORT_A_COMMON_MODE = 18,
771 /* Common mode on Port_D disabled/enabled */
772 CONTROL_FLAG_PORT_D_COMMON_MODE = 19,
773 /* Impedance for ramp generator on Port_A 16 Ohm/10K Ohm */
774 CONTROL_FLAG_PORT_A_10KOHM_LOAD = 20,
775 /* Impedance for ramp generator on Port_D, 16 Ohm/10K Ohm */
776 CONTROL_FLAG_PORT_D_10KOHM_LOAD = 21,
777 /* ASI rate is 48kHz/96kHz */
778 CONTROL_FLAG_ASI_96KHZ = 22,
779 /* DAC power settings able to control attached ports no/yes */
780 CONTROL_FLAG_DACS_CONTROL_PORTS = 23,
781 /* Clock Stop OK reporting is disabled/enabled */
782 CONTROL_FLAG_CONTROL_STOP_OK_ENABLE = 24,
783 /* Number of control flags */
784 CONTROL_FLAGS_MAX = (CONTROL_FLAG_CONTROL_STOP_OK_ENABLE+1)
785 };
786
787 /*
788 * Control parameter IDs
789 */
790 enum control_param_id {
791 /* 0: None, 1: Mic1In*/
792 CONTROL_PARAM_VIP_SOURCE = 1,
793 /* 0: force HDA, 1: allow DSP if HDA Spdif1Out stream is idle */
794 CONTROL_PARAM_SPDIF1_SOURCE = 2,
795 /* Port A output stage gain setting to use when 16 Ohm output
796 * impedance is selected*/
797 CONTROL_PARAM_PORTA_160OHM_GAIN = 8,
798 /* Port D output stage gain setting to use when 16 Ohm output
799 * impedance is selected*/
800 CONTROL_PARAM_PORTD_160OHM_GAIN = 10,
801
802 /* Stream Control */
803
804 /* Select stream with the given ID */
805 CONTROL_PARAM_STREAM_ID = 24,
806 /* Source connection point for the selected stream */
807 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT = 25,
808 /* Destination connection point for the selected stream */
809 CONTROL_PARAM_STREAM_DEST_CONN_POINT = 26,
810 /* Number of audio channels in the selected stream */
811 CONTROL_PARAM_STREAMS_CHANNELS = 27,
812 /*Enable control for the selected stream */
813 CONTROL_PARAM_STREAM_CONTROL = 28,
814
815 /* Connection Point Control */
816
817 /* Select connection point with the given ID */
818 CONTROL_PARAM_CONN_POINT_ID = 29,
819 /* Connection point sample rate */
820 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE = 30,
821
822 /* Node Control */
823
824 /* Select HDA node with the given ID */
825 CONTROL_PARAM_NODE_ID = 31
826 };
827
828 /*
829 * Dsp Io Status codes
830 */
831 enum hda_vendor_status_dspio {
832 /* Success */
833 VENDOR_STATUS_DSPIO_OK = 0x00,
834 /* Busy, unable to accept new command, the host must retry */
835 VENDOR_STATUS_DSPIO_BUSY = 0x01,
836 /* SCP command queue is full */
837 VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL = 0x02,
838 /* SCP response queue is empty */
839 VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY = 0x03
840 };
841
842 /*
843 * Chip Io Status codes
844 */
845 enum hda_vendor_status_chipio {
846 /* Success */
847 VENDOR_STATUS_CHIPIO_OK = 0x00,
848 /* Busy, unable to accept new command, the host must retry */
849 VENDOR_STATUS_CHIPIO_BUSY = 0x01
850 };
851
852 /*
853 * CA0132 sample rate
854 */
855 enum ca0132_sample_rate {
856 SR_6_000 = 0x00,
857 SR_8_000 = 0x01,
858 SR_9_600 = 0x02,
859 SR_11_025 = 0x03,
860 SR_16_000 = 0x04,
861 SR_22_050 = 0x05,
862 SR_24_000 = 0x06,
863 SR_32_000 = 0x07,
864 SR_44_100 = 0x08,
865 SR_48_000 = 0x09,
866 SR_88_200 = 0x0A,
867 SR_96_000 = 0x0B,
868 SR_144_000 = 0x0C,
869 SR_176_400 = 0x0D,
870 SR_192_000 = 0x0E,
871 SR_384_000 = 0x0F,
872
873 SR_COUNT = 0x10,
874
875 SR_RATE_UNKNOWN = 0x1F
876 };
877
878 enum dsp_download_state {
879 DSP_DOWNLOAD_FAILED = -1,
880 DSP_DOWNLOAD_INIT = 0,
881 DSP_DOWNLOADING = 1,
882 DSP_DOWNLOADED = 2
883 };
884
885 /* retrieve parameters from hda format */
886 #define get_hdafmt_chs(fmt) (fmt & 0xf)
887 #define get_hdafmt_bits(fmt) ((fmt >> 4) & 0x7)
888 #define get_hdafmt_rate(fmt) ((fmt >> 8) & 0x7f)
889 #define get_hdafmt_type(fmt) ((fmt >> 15) & 0x1)
890
891 /*
892 * CA0132 specific
893 */
894
895 struct ca0132_spec {
896 const struct snd_kcontrol_new *mixers[5];
897 unsigned int num_mixers;
898 const struct hda_verb *base_init_verbs;
899 const struct hda_verb *base_exit_verbs;
900 const struct hda_verb *chip_init_verbs;
901 const struct hda_verb *desktop_init_verbs;
902 struct hda_verb *spec_init_verbs;
903 struct auto_pin_cfg autocfg;
904
905 /* Nodes configurations */
906 struct hda_multi_out multiout;
907 hda_nid_t out_pins[AUTO_CFG_MAX_OUTS];
908 hda_nid_t dacs[AUTO_CFG_MAX_OUTS];
909 unsigned int num_outputs;
910 hda_nid_t input_pins[AUTO_PIN_LAST];
911 hda_nid_t adcs[AUTO_PIN_LAST];
912 hda_nid_t dig_out;
913 hda_nid_t dig_in;
914 unsigned int num_inputs;
915 hda_nid_t shared_mic_nid;
916 hda_nid_t shared_out_nid;
917 hda_nid_t unsol_tag_hp;
918 hda_nid_t unsol_tag_front_hp; /* for desktop ca0132 codecs */
919 hda_nid_t unsol_tag_amic1;
920
921 /* chip access */
922 struct mutex chipio_mutex; /* chip access mutex */
923 u32 curr_chip_addx;
924
925 /* DSP download related */
926 enum dsp_download_state dsp_state;
927 unsigned int dsp_stream_id;
928 unsigned int wait_scp;
929 unsigned int wait_scp_header;
930 unsigned int wait_num_data;
931 unsigned int scp_resp_header;
932 unsigned int scp_resp_data[4];
933 unsigned int scp_resp_count;
934 bool alt_firmware_present;
935 bool startup_check_entered;
936 bool dsp_reload;
937
938 /* mixer and effects related */
939 unsigned char dmic_ctl;
940 int cur_out_type;
941 int cur_mic_type;
942 long vnode_lvol[VNODES_COUNT];
943 long vnode_rvol[VNODES_COUNT];
944 long vnode_lswitch[VNODES_COUNT];
945 long vnode_rswitch[VNODES_COUNT];
946 long effects_switch[EFFECTS_COUNT];
947 long voicefx_val;
948 long cur_mic_boost;
949 /* ca0132_alt control related values */
950 unsigned char in_enum_val;
951 unsigned char out_enum_val;
952 unsigned char mic_boost_enum_val;
953 unsigned char smart_volume_setting;
954 long fx_ctl_val[EFFECT_LEVEL_SLIDERS];
955 long xbass_xover_freq;
956 long eq_preset_val;
957 unsigned int tlv[4];
958 struct hda_vmaster_mute_hook vmaster_mute;
959
960
961 struct hda_codec *codec;
962 struct delayed_work unsol_hp_work;
963 int quirk;
964
965 #ifdef ENABLE_TUNING_CONTROLS
966 long cur_ctl_vals[TUNING_CTLS_COUNT];
967 #endif
968 /*
969 * The Recon3D, Sound Blaster Z, Sound Blaster ZxR, and Sound Blaster
970 * AE-5 all use PCI region 2 to toggle GPIO and other currently unknown
971 * things.
972 */
973 bool use_pci_mmio;
974 void __iomem *mem_base;
975
976 /*
977 * Whether or not to use the alt functions like alt_select_out,
978 * alt_select_in, etc. Only used on desktop codecs for now, because of
979 * surround sound support.
980 */
981 bool use_alt_functions;
982
983 /*
984 * Whether or not to use alt controls: volume effect sliders, EQ
985 * presets, smart volume presets, and new control names with FX prefix.
986 * Renames PlayEnhancement and CrystalVoice too.
987 */
988 bool use_alt_controls;
989 };
990
991 /*
992 * CA0132 quirks table
993 */
994 enum {
995 QUIRK_NONE,
996 QUIRK_ALIENWARE,
997 QUIRK_ALIENWARE_M17XR4,
998 QUIRK_SBZ,
999 QUIRK_R3DI,
1000 QUIRK_R3D,
1001 };
1002
1003 static const struct hda_pintbl alienware_pincfgs[] = {
1004 { 0x0b, 0x90170110 }, /* Builtin Speaker */
1005 { 0x0c, 0x411111f0 }, /* N/A */
1006 { 0x0d, 0x411111f0 }, /* N/A */
1007 { 0x0e, 0x411111f0 }, /* N/A */
1008 { 0x0f, 0x0321101f }, /* HP */
1009 { 0x10, 0x411111f0 }, /* Headset? disabled for now */
1010 { 0x11, 0x03a11021 }, /* Mic */
1011 { 0x12, 0xd5a30140 }, /* Builtin Mic */
1012 { 0x13, 0x411111f0 }, /* N/A */
1013 { 0x18, 0x411111f0 }, /* N/A */
1014 {}
1015 };
1016
1017 /* Sound Blaster Z pin configs taken from Windows Driver */
1018 static const struct hda_pintbl sbz_pincfgs[] = {
1019 { 0x0b, 0x01017010 }, /* Port G -- Lineout FRONT L/R */
1020 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1021 { 0x0d, 0x014510f0 }, /* Digital Out */
1022 { 0x0e, 0x01c510f0 }, /* SPDIF In */
1023 { 0x0f, 0x0221701f }, /* Port A -- BackPanel HP */
1024 { 0x10, 0x01017012 }, /* Port D -- Center/LFE or FP Hp */
1025 { 0x11, 0x01017014 }, /* Port B -- LineMicIn2 / Rear L/R */
1026 { 0x12, 0x01a170f0 }, /* Port C -- LineIn1 */
1027 { 0x13, 0x908700f0 }, /* What U Hear In*/
1028 { 0x18, 0x50d000f0 }, /* N/A */
1029 {}
1030 };
1031
1032 /* Recon3D pin configs taken from Windows Driver */
1033 static const struct hda_pintbl r3d_pincfgs[] = {
1034 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1035 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1036 { 0x0d, 0x014510f0 }, /* Digital Out */
1037 { 0x0e, 0x01c520f0 }, /* SPDIF In */
1038 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1039 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1040 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1041 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1042 { 0x13, 0x908700f0 }, /* What U Hear In*/
1043 { 0x18, 0x50d000f0 }, /* N/A */
1044 {}
1045 };
1046
1047 /* Recon3D integrated pin configs taken from Windows Driver */
1048 static const struct hda_pintbl r3di_pincfgs[] = {
1049 { 0x0b, 0x01014110 }, /* Port G -- Lineout FRONT L/R */
1050 { 0x0c, 0x014510f0 }, /* SPDIF Out 1 */
1051 { 0x0d, 0x014510f0 }, /* Digital Out */
1052 { 0x0e, 0x41c520f0 }, /* SPDIF In */
1053 { 0x0f, 0x0221401f }, /* Port A -- BackPanel HP */
1054 { 0x10, 0x01016011 }, /* Port D -- Center/LFE or FP Hp */
1055 { 0x11, 0x01011014 }, /* Port B -- LineMicIn2 / Rear L/R */
1056 { 0x12, 0x02a090f0 }, /* Port C -- LineIn1 */
1057 { 0x13, 0x908700f0 }, /* What U Hear In*/
1058 { 0x18, 0x500000f0 }, /* N/A */
1059 {}
1060 };
1061
1062 static const struct snd_pci_quirk ca0132_quirks[] = {
1063 SND_PCI_QUIRK(0x1028, 0x057b, "Alienware M17x R4", QUIRK_ALIENWARE_M17XR4),
1064 SND_PCI_QUIRK(0x1028, 0x0685, "Alienware 15 2015", QUIRK_ALIENWARE),
1065 SND_PCI_QUIRK(0x1028, 0x0688, "Alienware 17 2015", QUIRK_ALIENWARE),
1066 SND_PCI_QUIRK(0x1028, 0x0708, "Alienware 15 R2 2016", QUIRK_ALIENWARE),
1067 SND_PCI_QUIRK(0x1102, 0x0010, "Sound Blaster Z", QUIRK_SBZ),
1068 SND_PCI_QUIRK(0x1102, 0x0023, "Sound Blaster Z", QUIRK_SBZ),
1069 SND_PCI_QUIRK(0x1458, 0xA016, "Recon3Di", QUIRK_R3DI),
1070 SND_PCI_QUIRK(0x1458, 0xA026, "Gigabyte G1.Sniper Z97", QUIRK_R3DI),
1071 SND_PCI_QUIRK(0x1458, 0xA036, "Gigabyte GA-Z170X-Gaming 7", QUIRK_R3DI),
1072 SND_PCI_QUIRK(0x3842, 0x1038, "EVGA X99 Classified", QUIRK_R3DI),
1073 SND_PCI_QUIRK(0x1102, 0x0013, "Recon3D", QUIRK_R3D),
1074 {}
1075 };
1076
1077 /*
1078 * CA0132 codec access
1079 */
1080 static unsigned int codec_send_command(struct hda_codec *codec, hda_nid_t nid,
1081 unsigned int verb, unsigned int parm, unsigned int *res)
1082 {
1083 unsigned int response;
1084 response = snd_hda_codec_read(codec, nid, 0, verb, parm);
1085 *res = response;
1086
1087 return ((response == -1) ? -1 : 0);
1088 }
1089
1090 static int codec_set_converter_format(struct hda_codec *codec, hda_nid_t nid,
1091 unsigned short converter_format, unsigned int *res)
1092 {
1093 return codec_send_command(codec, nid, VENDOR_CHIPIO_STREAM_FORMAT,
1094 converter_format & 0xffff, res);
1095 }
1096
1097 static int codec_set_converter_stream_channel(struct hda_codec *codec,
1098 hda_nid_t nid, unsigned char stream,
1099 unsigned char channel, unsigned int *res)
1100 {
1101 unsigned char converter_stream_channel = 0;
1102
1103 converter_stream_channel = (stream << 4) | (channel & 0x0f);
1104 return codec_send_command(codec, nid, AC_VERB_SET_CHANNEL_STREAMID,
1105 converter_stream_channel, res);
1106 }
1107
1108 /* Chip access helper function */
1109 static int chipio_send(struct hda_codec *codec,
1110 unsigned int reg,
1111 unsigned int data)
1112 {
1113 unsigned int res;
1114 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1115
1116 /* send bits of data specified by reg */
1117 do {
1118 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1119 reg, data);
1120 if (res == VENDOR_STATUS_CHIPIO_OK)
1121 return 0;
1122 msleep(20);
1123 } while (time_before(jiffies, timeout));
1124
1125 return -EIO;
1126 }
1127
1128 /*
1129 * Write chip address through the vendor widget -- NOT protected by the Mutex!
1130 */
1131 static int chipio_write_address(struct hda_codec *codec,
1132 unsigned int chip_addx)
1133 {
1134 struct ca0132_spec *spec = codec->spec;
1135 int res;
1136
1137 if (spec->curr_chip_addx == chip_addx)
1138 return 0;
1139
1140 /* send low 16 bits of the address */
1141 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_LOW,
1142 chip_addx & 0xffff);
1143
1144 if (res != -EIO) {
1145 /* send high 16 bits of the address */
1146 res = chipio_send(codec, VENDOR_CHIPIO_ADDRESS_HIGH,
1147 chip_addx >> 16);
1148 }
1149
1150 spec->curr_chip_addx = (res < 0) ? ~0U : chip_addx;
1151
1152 return res;
1153 }
1154
1155 /*
1156 * Write data through the vendor widget -- NOT protected by the Mutex!
1157 */
1158 static int chipio_write_data(struct hda_codec *codec, unsigned int data)
1159 {
1160 struct ca0132_spec *spec = codec->spec;
1161 int res;
1162
1163 /* send low 16 bits of the data */
1164 res = chipio_send(codec, VENDOR_CHIPIO_DATA_LOW, data & 0xffff);
1165
1166 if (res != -EIO) {
1167 /* send high 16 bits of the data */
1168 res = chipio_send(codec, VENDOR_CHIPIO_DATA_HIGH,
1169 data >> 16);
1170 }
1171
1172 /*If no error encountered, automatically increment the address
1173 as per chip behaviour*/
1174 spec->curr_chip_addx = (res != -EIO) ?
1175 (spec->curr_chip_addx + 4) : ~0U;
1176 return res;
1177 }
1178
1179 /*
1180 * Write multiple data through the vendor widget -- NOT protected by the Mutex!
1181 */
1182 static int chipio_write_data_multiple(struct hda_codec *codec,
1183 const u32 *data,
1184 unsigned int count)
1185 {
1186 int status = 0;
1187
1188 if (data == NULL) {
1189 codec_dbg(codec, "chipio_write_data null ptr\n");
1190 return -EINVAL;
1191 }
1192
1193 while ((count-- != 0) && (status == 0))
1194 status = chipio_write_data(codec, *data++);
1195
1196 return status;
1197 }
1198
1199
1200 /*
1201 * Read data through the vendor widget -- NOT protected by the Mutex!
1202 */
1203 static int chipio_read_data(struct hda_codec *codec, unsigned int *data)
1204 {
1205 struct ca0132_spec *spec = codec->spec;
1206 int res;
1207
1208 /* post read */
1209 res = chipio_send(codec, VENDOR_CHIPIO_HIC_POST_READ, 0);
1210
1211 if (res != -EIO) {
1212 /* read status */
1213 res = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
1214 }
1215
1216 if (res != -EIO) {
1217 /* read data */
1218 *data = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
1219 VENDOR_CHIPIO_HIC_READ_DATA,
1220 0);
1221 }
1222
1223 /*If no error encountered, automatically increment the address
1224 as per chip behaviour*/
1225 spec->curr_chip_addx = (res != -EIO) ?
1226 (spec->curr_chip_addx + 4) : ~0U;
1227 return res;
1228 }
1229
1230 /*
1231 * Write given value to the given address through the chip I/O widget.
1232 * protected by the Mutex
1233 */
1234 static int chipio_write(struct hda_codec *codec,
1235 unsigned int chip_addx, const unsigned int data)
1236 {
1237 struct ca0132_spec *spec = codec->spec;
1238 int err;
1239
1240 mutex_lock(&spec->chipio_mutex);
1241
1242 /* write the address, and if successful proceed to write data */
1243 err = chipio_write_address(codec, chip_addx);
1244 if (err < 0)
1245 goto exit;
1246
1247 err = chipio_write_data(codec, data);
1248 if (err < 0)
1249 goto exit;
1250
1251 exit:
1252 mutex_unlock(&spec->chipio_mutex);
1253 return err;
1254 }
1255
1256 /*
1257 * Write given value to the given address through the chip I/O widget.
1258 * not protected by the Mutex
1259 */
1260 static int chipio_write_no_mutex(struct hda_codec *codec,
1261 unsigned int chip_addx, const unsigned int data)
1262 {
1263 int err;
1264
1265
1266 /* write the address, and if successful proceed to write data */
1267 err = chipio_write_address(codec, chip_addx);
1268 if (err < 0)
1269 goto exit;
1270
1271 err = chipio_write_data(codec, data);
1272 if (err < 0)
1273 goto exit;
1274
1275 exit:
1276 return err;
1277 }
1278
1279 /*
1280 * Write multiple values to the given address through the chip I/O widget.
1281 * protected by the Mutex
1282 */
1283 static int chipio_write_multiple(struct hda_codec *codec,
1284 u32 chip_addx,
1285 const u32 *data,
1286 unsigned int count)
1287 {
1288 struct ca0132_spec *spec = codec->spec;
1289 int status;
1290
1291 mutex_lock(&spec->chipio_mutex);
1292 status = chipio_write_address(codec, chip_addx);
1293 if (status < 0)
1294 goto error;
1295
1296 status = chipio_write_data_multiple(codec, data, count);
1297 error:
1298 mutex_unlock(&spec->chipio_mutex);
1299
1300 return status;
1301 }
1302
1303 /*
1304 * Read the given address through the chip I/O widget
1305 * protected by the Mutex
1306 */
1307 static int chipio_read(struct hda_codec *codec,
1308 unsigned int chip_addx, unsigned int *data)
1309 {
1310 struct ca0132_spec *spec = codec->spec;
1311 int err;
1312
1313 mutex_lock(&spec->chipio_mutex);
1314
1315 /* write the address, and if successful proceed to write data */
1316 err = chipio_write_address(codec, chip_addx);
1317 if (err < 0)
1318 goto exit;
1319
1320 err = chipio_read_data(codec, data);
1321 if (err < 0)
1322 goto exit;
1323
1324 exit:
1325 mutex_unlock(&spec->chipio_mutex);
1326 return err;
1327 }
1328
1329 /*
1330 * Set chip control flags through the chip I/O widget.
1331 */
1332 static void chipio_set_control_flag(struct hda_codec *codec,
1333 enum control_flag_id flag_id,
1334 bool flag_state)
1335 {
1336 unsigned int val;
1337 unsigned int flag_bit;
1338
1339 flag_bit = (flag_state ? 1 : 0);
1340 val = (flag_bit << 7) | (flag_id);
1341 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1342 VENDOR_CHIPIO_FLAG_SET, val);
1343 }
1344
1345 /*
1346 * Set chip parameters through the chip I/O widget.
1347 */
1348 static void chipio_set_control_param(struct hda_codec *codec,
1349 enum control_param_id param_id, int param_val)
1350 {
1351 struct ca0132_spec *spec = codec->spec;
1352 int val;
1353
1354 if ((param_id < 32) && (param_val < 8)) {
1355 val = (param_val << 5) | (param_id);
1356 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1357 VENDOR_CHIPIO_PARAM_SET, val);
1358 } else {
1359 mutex_lock(&spec->chipio_mutex);
1360 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1361 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1362 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1363 param_id);
1364 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1365 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1366 param_val);
1367 }
1368 mutex_unlock(&spec->chipio_mutex);
1369 }
1370 }
1371
1372 /*
1373 * Set chip parameters through the chip I/O widget. NO MUTEX.
1374 */
1375 static void chipio_set_control_param_no_mutex(struct hda_codec *codec,
1376 enum control_param_id param_id, int param_val)
1377 {
1378 int val;
1379
1380 if ((param_id < 32) && (param_val < 8)) {
1381 val = (param_val << 5) | (param_id);
1382 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1383 VENDOR_CHIPIO_PARAM_SET, val);
1384 } else {
1385 if (chipio_send(codec, VENDOR_CHIPIO_STATUS, 0) == 0) {
1386 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1387 VENDOR_CHIPIO_PARAM_EX_ID_SET,
1388 param_id);
1389 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1390 VENDOR_CHIPIO_PARAM_EX_VALUE_SET,
1391 param_val);
1392 }
1393 }
1394 }
1395 /*
1396 * Connect stream to a source point, and then connect
1397 * that source point to a destination point.
1398 */
1399 static void chipio_set_stream_source_dest(struct hda_codec *codec,
1400 int streamid, int source_point, int dest_point)
1401 {
1402 chipio_set_control_param_no_mutex(codec,
1403 CONTROL_PARAM_STREAM_ID, streamid);
1404 chipio_set_control_param_no_mutex(codec,
1405 CONTROL_PARAM_STREAM_SOURCE_CONN_POINT, source_point);
1406 chipio_set_control_param_no_mutex(codec,
1407 CONTROL_PARAM_STREAM_DEST_CONN_POINT, dest_point);
1408 }
1409
1410 /*
1411 * Set number of channels in the selected stream.
1412 */
1413 static void chipio_set_stream_channels(struct hda_codec *codec,
1414 int streamid, unsigned int channels)
1415 {
1416 chipio_set_control_param_no_mutex(codec,
1417 CONTROL_PARAM_STREAM_ID, streamid);
1418 chipio_set_control_param_no_mutex(codec,
1419 CONTROL_PARAM_STREAMS_CHANNELS, channels);
1420 }
1421
1422 /*
1423 * Enable/Disable audio stream.
1424 */
1425 static void chipio_set_stream_control(struct hda_codec *codec,
1426 int streamid, int enable)
1427 {
1428 chipio_set_control_param_no_mutex(codec,
1429 CONTROL_PARAM_STREAM_ID, streamid);
1430 chipio_set_control_param_no_mutex(codec,
1431 CONTROL_PARAM_STREAM_CONTROL, enable);
1432 }
1433
1434
1435 /*
1436 * Set sampling rate of the connection point. NO MUTEX.
1437 */
1438 static void chipio_set_conn_rate_no_mutex(struct hda_codec *codec,
1439 int connid, enum ca0132_sample_rate rate)
1440 {
1441 chipio_set_control_param_no_mutex(codec,
1442 CONTROL_PARAM_CONN_POINT_ID, connid);
1443 chipio_set_control_param_no_mutex(codec,
1444 CONTROL_PARAM_CONN_POINT_SAMPLE_RATE, rate);
1445 }
1446
1447 /*
1448 * Set sampling rate of the connection point.
1449 */
1450 static void chipio_set_conn_rate(struct hda_codec *codec,
1451 int connid, enum ca0132_sample_rate rate)
1452 {
1453 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_ID, connid);
1454 chipio_set_control_param(codec, CONTROL_PARAM_CONN_POINT_SAMPLE_RATE,
1455 rate);
1456 }
1457
1458 /*
1459 * Enable clocks.
1460 */
1461 static void chipio_enable_clocks(struct hda_codec *codec)
1462 {
1463 struct ca0132_spec *spec = codec->spec;
1464
1465 mutex_lock(&spec->chipio_mutex);
1466 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1467 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0);
1468 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1469 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1470 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1471 VENDOR_CHIPIO_8051_ADDRESS_LOW, 5);
1472 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1473 VENDOR_CHIPIO_PLL_PMU_WRITE, 0x0b);
1474 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1475 VENDOR_CHIPIO_8051_ADDRESS_LOW, 6);
1476 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
1477 VENDOR_CHIPIO_PLL_PMU_WRITE, 0xff);
1478 mutex_unlock(&spec->chipio_mutex);
1479 }
1480
1481 /*
1482 * CA0132 DSP IO stuffs
1483 */
1484 static int dspio_send(struct hda_codec *codec, unsigned int reg,
1485 unsigned int data)
1486 {
1487 int res;
1488 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1489
1490 /* send bits of data specified by reg to dsp */
1491 do {
1492 res = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0, reg, data);
1493 if ((res >= 0) && (res != VENDOR_STATUS_DSPIO_BUSY))
1494 return res;
1495 msleep(20);
1496 } while (time_before(jiffies, timeout));
1497
1498 return -EIO;
1499 }
1500
1501 /*
1502 * Wait for DSP to be ready for commands
1503 */
1504 static void dspio_write_wait(struct hda_codec *codec)
1505 {
1506 int status;
1507 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1508
1509 do {
1510 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1511 VENDOR_DSPIO_STATUS, 0);
1512 if ((status == VENDOR_STATUS_DSPIO_OK) ||
1513 (status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY))
1514 break;
1515 msleep(1);
1516 } while (time_before(jiffies, timeout));
1517 }
1518
1519 /*
1520 * Write SCP data to DSP
1521 */
1522 static int dspio_write(struct hda_codec *codec, unsigned int scp_data)
1523 {
1524 struct ca0132_spec *spec = codec->spec;
1525 int status;
1526
1527 dspio_write_wait(codec);
1528
1529 mutex_lock(&spec->chipio_mutex);
1530 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_LOW,
1531 scp_data & 0xffff);
1532 if (status < 0)
1533 goto error;
1534
1535 status = dspio_send(codec, VENDOR_DSPIO_SCP_WRITE_DATA_HIGH,
1536 scp_data >> 16);
1537 if (status < 0)
1538 goto error;
1539
1540 /* OK, now check if the write itself has executed*/
1541 status = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1542 VENDOR_DSPIO_STATUS, 0);
1543 error:
1544 mutex_unlock(&spec->chipio_mutex);
1545
1546 return (status == VENDOR_STATUS_DSPIO_SCP_COMMAND_QUEUE_FULL) ?
1547 -EIO : 0;
1548 }
1549
1550 /*
1551 * Write multiple SCP data to DSP
1552 */
1553 static int dspio_write_multiple(struct hda_codec *codec,
1554 unsigned int *buffer, unsigned int size)
1555 {
1556 int status = 0;
1557 unsigned int count;
1558
1559 if (buffer == NULL)
1560 return -EINVAL;
1561
1562 count = 0;
1563 while (count < size) {
1564 status = dspio_write(codec, *buffer++);
1565 if (status != 0)
1566 break;
1567 count++;
1568 }
1569
1570 return status;
1571 }
1572
1573 static int dspio_read(struct hda_codec *codec, unsigned int *data)
1574 {
1575 int status;
1576
1577 status = dspio_send(codec, VENDOR_DSPIO_SCP_POST_READ_DATA, 0);
1578 if (status == -EIO)
1579 return status;
1580
1581 status = dspio_send(codec, VENDOR_DSPIO_STATUS, 0);
1582 if (status == -EIO ||
1583 status == VENDOR_STATUS_DSPIO_SCP_RESPONSE_QUEUE_EMPTY)
1584 return -EIO;
1585
1586 *data = snd_hda_codec_read(codec, WIDGET_DSP_CTRL, 0,
1587 VENDOR_DSPIO_SCP_READ_DATA, 0);
1588
1589 return 0;
1590 }
1591
1592 static int dspio_read_multiple(struct hda_codec *codec, unsigned int *buffer,
1593 unsigned int *buf_size, unsigned int size_count)
1594 {
1595 int status = 0;
1596 unsigned int size = *buf_size;
1597 unsigned int count;
1598 unsigned int skip_count;
1599 unsigned int dummy;
1600
1601 if (buffer == NULL)
1602 return -1;
1603
1604 count = 0;
1605 while (count < size && count < size_count) {
1606 status = dspio_read(codec, buffer++);
1607 if (status != 0)
1608 break;
1609 count++;
1610 }
1611
1612 skip_count = count;
1613 if (status == 0) {
1614 while (skip_count < size) {
1615 status = dspio_read(codec, &dummy);
1616 if (status != 0)
1617 break;
1618 skip_count++;
1619 }
1620 }
1621 *buf_size = count;
1622
1623 return status;
1624 }
1625
1626 /*
1627 * Construct the SCP header using corresponding fields
1628 */
1629 static inline unsigned int
1630 make_scp_header(unsigned int target_id, unsigned int source_id,
1631 unsigned int get_flag, unsigned int req,
1632 unsigned int device_flag, unsigned int resp_flag,
1633 unsigned int error_flag, unsigned int data_size)
1634 {
1635 unsigned int header = 0;
1636
1637 header = (data_size & 0x1f) << 27;
1638 header |= (error_flag & 0x01) << 26;
1639 header |= (resp_flag & 0x01) << 25;
1640 header |= (device_flag & 0x01) << 24;
1641 header |= (req & 0x7f) << 17;
1642 header |= (get_flag & 0x01) << 16;
1643 header |= (source_id & 0xff) << 8;
1644 header |= target_id & 0xff;
1645
1646 return header;
1647 }
1648
1649 /*
1650 * Extract corresponding fields from SCP header
1651 */
1652 static inline void
1653 extract_scp_header(unsigned int header,
1654 unsigned int *target_id, unsigned int *source_id,
1655 unsigned int *get_flag, unsigned int *req,
1656 unsigned int *device_flag, unsigned int *resp_flag,
1657 unsigned int *error_flag, unsigned int *data_size)
1658 {
1659 if (data_size)
1660 *data_size = (header >> 27) & 0x1f;
1661 if (error_flag)
1662 *error_flag = (header >> 26) & 0x01;
1663 if (resp_flag)
1664 *resp_flag = (header >> 25) & 0x01;
1665 if (device_flag)
1666 *device_flag = (header >> 24) & 0x01;
1667 if (req)
1668 *req = (header >> 17) & 0x7f;
1669 if (get_flag)
1670 *get_flag = (header >> 16) & 0x01;
1671 if (source_id)
1672 *source_id = (header >> 8) & 0xff;
1673 if (target_id)
1674 *target_id = header & 0xff;
1675 }
1676
1677 #define SCP_MAX_DATA_WORDS (16)
1678
1679 /* Structure to contain any SCP message */
1680 struct scp_msg {
1681 unsigned int hdr;
1682 unsigned int data[SCP_MAX_DATA_WORDS];
1683 };
1684
1685 static void dspio_clear_response_queue(struct hda_codec *codec)
1686 {
1687 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1688 unsigned int dummy = 0;
1689 int status;
1690
1691 /* clear all from the response queue */
1692 do {
1693 status = dspio_read(codec, &dummy);
1694 } while (status == 0 && time_before(jiffies, timeout));
1695 }
1696
1697 static int dspio_get_response_data(struct hda_codec *codec)
1698 {
1699 struct ca0132_spec *spec = codec->spec;
1700 unsigned int data = 0;
1701 unsigned int count;
1702
1703 if (dspio_read(codec, &data) < 0)
1704 return -EIO;
1705
1706 if ((data & 0x00ffffff) == spec->wait_scp_header) {
1707 spec->scp_resp_header = data;
1708 spec->scp_resp_count = data >> 27;
1709 count = spec->wait_num_data;
1710 dspio_read_multiple(codec, spec->scp_resp_data,
1711 &spec->scp_resp_count, count);
1712 return 0;
1713 }
1714
1715 return -EIO;
1716 }
1717
1718 /*
1719 * Send SCP message to DSP
1720 */
1721 static int dspio_send_scp_message(struct hda_codec *codec,
1722 unsigned char *send_buf,
1723 unsigned int send_buf_size,
1724 unsigned char *return_buf,
1725 unsigned int return_buf_size,
1726 unsigned int *bytes_returned)
1727 {
1728 struct ca0132_spec *spec = codec->spec;
1729 int status = -1;
1730 unsigned int scp_send_size = 0;
1731 unsigned int total_size;
1732 bool waiting_for_resp = false;
1733 unsigned int header;
1734 struct scp_msg *ret_msg;
1735 unsigned int resp_src_id, resp_target_id;
1736 unsigned int data_size, src_id, target_id, get_flag, device_flag;
1737
1738 if (bytes_returned)
1739 *bytes_returned = 0;
1740
1741 /* get scp header from buffer */
1742 header = *((unsigned int *)send_buf);
1743 extract_scp_header(header, &target_id, &src_id, &get_flag, NULL,
1744 &device_flag, NULL, NULL, &data_size);
1745 scp_send_size = data_size + 1;
1746 total_size = (scp_send_size * 4);
1747
1748 if (send_buf_size < total_size)
1749 return -EINVAL;
1750
1751 if (get_flag || device_flag) {
1752 if (!return_buf || return_buf_size < 4 || !bytes_returned)
1753 return -EINVAL;
1754
1755 spec->wait_scp_header = *((unsigned int *)send_buf);
1756
1757 /* swap source id with target id */
1758 resp_target_id = src_id;
1759 resp_src_id = target_id;
1760 spec->wait_scp_header &= 0xffff0000;
1761 spec->wait_scp_header |= (resp_src_id << 8) | (resp_target_id);
1762 spec->wait_num_data = return_buf_size/sizeof(unsigned int) - 1;
1763 spec->wait_scp = 1;
1764 waiting_for_resp = true;
1765 }
1766
1767 status = dspio_write_multiple(codec, (unsigned int *)send_buf,
1768 scp_send_size);
1769 if (status < 0) {
1770 spec->wait_scp = 0;
1771 return status;
1772 }
1773
1774 if (waiting_for_resp) {
1775 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
1776 memset(return_buf, 0, return_buf_size);
1777 do {
1778 msleep(20);
1779 } while (spec->wait_scp && time_before(jiffies, timeout));
1780 waiting_for_resp = false;
1781 if (!spec->wait_scp) {
1782 ret_msg = (struct scp_msg *)return_buf;
1783 memcpy(&ret_msg->hdr, &spec->scp_resp_header, 4);
1784 memcpy(&ret_msg->data, spec->scp_resp_data,
1785 spec->wait_num_data);
1786 *bytes_returned = (spec->scp_resp_count + 1) * 4;
1787 status = 0;
1788 } else {
1789 status = -EIO;
1790 }
1791 spec->wait_scp = 0;
1792 }
1793
1794 return status;
1795 }
1796
1797 /**
1798 * Prepare and send the SCP message to DSP
1799 * @codec: the HDA codec
1800 * @mod_id: ID of the DSP module to send the command
1801 * @req: ID of request to send to the DSP module
1802 * @dir: SET or GET
1803 * @data: pointer to the data to send with the request, request specific
1804 * @len: length of the data, in bytes
1805 * @reply: point to the buffer to hold data returned for a reply
1806 * @reply_len: length of the reply buffer returned from GET
1807 *
1808 * Returns zero or a negative error code.
1809 */
1810 static int dspio_scp(struct hda_codec *codec,
1811 int mod_id, int src_id, int req, int dir, const void *data,
1812 unsigned int len, void *reply, unsigned int *reply_len)
1813 {
1814 int status = 0;
1815 struct scp_msg scp_send, scp_reply;
1816 unsigned int ret_bytes, send_size, ret_size;
1817 unsigned int send_get_flag, reply_resp_flag, reply_error_flag;
1818 unsigned int reply_data_size;
1819
1820 memset(&scp_send, 0, sizeof(scp_send));
1821 memset(&scp_reply, 0, sizeof(scp_reply));
1822
1823 if ((len != 0 && data == NULL) || (len > SCP_MAX_DATA_WORDS))
1824 return -EINVAL;
1825
1826 if (dir == SCP_GET && reply == NULL) {
1827 codec_dbg(codec, "dspio_scp get but has no buffer\n");
1828 return -EINVAL;
1829 }
1830
1831 if (reply != NULL && (reply_len == NULL || (*reply_len == 0))) {
1832 codec_dbg(codec, "dspio_scp bad resp buf len parms\n");
1833 return -EINVAL;
1834 }
1835
1836 scp_send.hdr = make_scp_header(mod_id, src_id, (dir == SCP_GET), req,
1837 0, 0, 0, len/sizeof(unsigned int));
1838 if (data != NULL && len > 0) {
1839 len = min((unsigned int)(sizeof(scp_send.data)), len);
1840 memcpy(scp_send.data, data, len);
1841 }
1842
1843 ret_bytes = 0;
1844 send_size = sizeof(unsigned int) + len;
1845 status = dspio_send_scp_message(codec, (unsigned char *)&scp_send,
1846 send_size, (unsigned char *)&scp_reply,
1847 sizeof(scp_reply), &ret_bytes);
1848
1849 if (status < 0) {
1850 codec_dbg(codec, "dspio_scp: send scp msg failed\n");
1851 return status;
1852 }
1853
1854 /* extract send and reply headers members */
1855 extract_scp_header(scp_send.hdr, NULL, NULL, &send_get_flag,
1856 NULL, NULL, NULL, NULL, NULL);
1857 extract_scp_header(scp_reply.hdr, NULL, NULL, NULL, NULL, NULL,
1858 &reply_resp_flag, &reply_error_flag,
1859 &reply_data_size);
1860
1861 if (!send_get_flag)
1862 return 0;
1863
1864 if (reply_resp_flag && !reply_error_flag) {
1865 ret_size = (ret_bytes - sizeof(scp_reply.hdr))
1866 / sizeof(unsigned int);
1867
1868 if (*reply_len < ret_size*sizeof(unsigned int)) {
1869 codec_dbg(codec, "reply too long for buf\n");
1870 return -EINVAL;
1871 } else if (ret_size != reply_data_size) {
1872 codec_dbg(codec, "RetLen and HdrLen .NE.\n");
1873 return -EINVAL;
1874 } else if (!reply) {
1875 codec_dbg(codec, "NULL reply\n");
1876 return -EINVAL;
1877 } else {
1878 *reply_len = ret_size*sizeof(unsigned int);
1879 memcpy(reply, scp_reply.data, *reply_len);
1880 }
1881 } else {
1882 codec_dbg(codec, "reply ill-formed or errflag set\n");
1883 return -EIO;
1884 }
1885
1886 return status;
1887 }
1888
1889 /*
1890 * Set DSP parameters
1891 */
1892 static int dspio_set_param(struct hda_codec *codec, int mod_id,
1893 int src_id, int req, const void *data, unsigned int len)
1894 {
1895 return dspio_scp(codec, mod_id, src_id, req, SCP_SET, data, len, NULL,
1896 NULL);
1897 }
1898
1899 static int dspio_set_uint_param(struct hda_codec *codec, int mod_id,
1900 int req, const unsigned int data)
1901 {
1902 return dspio_set_param(codec, mod_id, 0x20, req, &data,
1903 sizeof(unsigned int));
1904 }
1905
1906 static int dspio_set_uint_param_no_source(struct hda_codec *codec, int mod_id,
1907 int req, const unsigned int data)
1908 {
1909 return dspio_set_param(codec, mod_id, 0x00, req, &data,
1910 sizeof(unsigned int));
1911 }
1912
1913 /*
1914 * Allocate a DSP DMA channel via an SCP message
1915 */
1916 static int dspio_alloc_dma_chan(struct hda_codec *codec, unsigned int *dma_chan)
1917 {
1918 int status = 0;
1919 unsigned int size = sizeof(dma_chan);
1920
1921 codec_dbg(codec, " dspio_alloc_dma_chan() -- begin\n");
1922 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1923 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_GET, NULL, 0,
1924 dma_chan, &size);
1925
1926 if (status < 0) {
1927 codec_dbg(codec, "dspio_alloc_dma_chan: SCP Failed\n");
1928 return status;
1929 }
1930
1931 if ((*dma_chan + 1) == 0) {
1932 codec_dbg(codec, "no free dma channels to allocate\n");
1933 return -EBUSY;
1934 }
1935
1936 codec_dbg(codec, "dspio_alloc_dma_chan: chan=%d\n", *dma_chan);
1937 codec_dbg(codec, " dspio_alloc_dma_chan() -- complete\n");
1938
1939 return status;
1940 }
1941
1942 /*
1943 * Free a DSP DMA via an SCP message
1944 */
1945 static int dspio_free_dma_chan(struct hda_codec *codec, unsigned int dma_chan)
1946 {
1947 int status = 0;
1948 unsigned int dummy = 0;
1949
1950 codec_dbg(codec, " dspio_free_dma_chan() -- begin\n");
1951 codec_dbg(codec, "dspio_free_dma_chan: chan=%d\n", dma_chan);
1952
1953 status = dspio_scp(codec, MASTERCONTROL, 0x20,
1954 MASTERCONTROL_ALLOC_DMA_CHAN, SCP_SET, &dma_chan,
1955 sizeof(dma_chan), NULL, &dummy);
1956
1957 if (status < 0) {
1958 codec_dbg(codec, "dspio_free_dma_chan: SCP Failed\n");
1959 return status;
1960 }
1961
1962 codec_dbg(codec, " dspio_free_dma_chan() -- complete\n");
1963
1964 return status;
1965 }
1966
1967 /*
1968 * (Re)start the DSP
1969 */
1970 static int dsp_set_run_state(struct hda_codec *codec)
1971 {
1972 unsigned int dbg_ctrl_reg;
1973 unsigned int halt_state;
1974 int err;
1975
1976 err = chipio_read(codec, DSP_DBGCNTL_INST_OFFSET, &dbg_ctrl_reg);
1977 if (err < 0)
1978 return err;
1979
1980 halt_state = (dbg_ctrl_reg & DSP_DBGCNTL_STATE_MASK) >>
1981 DSP_DBGCNTL_STATE_LOBIT;
1982
1983 if (halt_state != 0) {
1984 dbg_ctrl_reg &= ~((halt_state << DSP_DBGCNTL_SS_LOBIT) &
1985 DSP_DBGCNTL_SS_MASK);
1986 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1987 dbg_ctrl_reg);
1988 if (err < 0)
1989 return err;
1990
1991 dbg_ctrl_reg |= (halt_state << DSP_DBGCNTL_EXEC_LOBIT) &
1992 DSP_DBGCNTL_EXEC_MASK;
1993 err = chipio_write(codec, DSP_DBGCNTL_INST_OFFSET,
1994 dbg_ctrl_reg);
1995 if (err < 0)
1996 return err;
1997 }
1998
1999 return 0;
2000 }
2001
2002 /*
2003 * Reset the DSP
2004 */
2005 static int dsp_reset(struct hda_codec *codec)
2006 {
2007 unsigned int res;
2008 int retry = 20;
2009
2010 codec_dbg(codec, "dsp_reset\n");
2011 do {
2012 res = dspio_send(codec, VENDOR_DSPIO_DSP_INIT, 0);
2013 retry--;
2014 } while (res == -EIO && retry);
2015
2016 if (!retry) {
2017 codec_dbg(codec, "dsp_reset timeout\n");
2018 return -EIO;
2019 }
2020
2021 return 0;
2022 }
2023
2024 /*
2025 * Convert chip address to DSP address
2026 */
2027 static unsigned int dsp_chip_to_dsp_addx(unsigned int chip_addx,
2028 bool *code, bool *yram)
2029 {
2030 *code = *yram = false;
2031
2032 if (UC_RANGE(chip_addx, 1)) {
2033 *code = true;
2034 return UC_OFF(chip_addx);
2035 } else if (X_RANGE_ALL(chip_addx, 1)) {
2036 return X_OFF(chip_addx);
2037 } else if (Y_RANGE_ALL(chip_addx, 1)) {
2038 *yram = true;
2039 return Y_OFF(chip_addx);
2040 }
2041
2042 return INVALID_CHIP_ADDRESS;
2043 }
2044
2045 /*
2046 * Check if the DSP DMA is active
2047 */
2048 static bool dsp_is_dma_active(struct hda_codec *codec, unsigned int dma_chan)
2049 {
2050 unsigned int dma_chnlstart_reg;
2051
2052 chipio_read(codec, DSPDMAC_CHNLSTART_INST_OFFSET, &dma_chnlstart_reg);
2053
2054 return ((dma_chnlstart_reg & (1 <<
2055 (DSPDMAC_CHNLSTART_EN_LOBIT + dma_chan))) != 0);
2056 }
2057
2058 static int dsp_dma_setup_common(struct hda_codec *codec,
2059 unsigned int chip_addx,
2060 unsigned int dma_chan,
2061 unsigned int port_map_mask,
2062 bool ovly)
2063 {
2064 int status = 0;
2065 unsigned int chnl_prop;
2066 unsigned int dsp_addx;
2067 unsigned int active;
2068 bool code, yram;
2069
2070 codec_dbg(codec, "-- dsp_dma_setup_common() -- Begin ---------\n");
2071
2072 if (dma_chan >= DSPDMAC_DMA_CFG_CHANNEL_COUNT) {
2073 codec_dbg(codec, "dma chan num invalid\n");
2074 return -EINVAL;
2075 }
2076
2077 if (dsp_is_dma_active(codec, dma_chan)) {
2078 codec_dbg(codec, "dma already active\n");
2079 return -EBUSY;
2080 }
2081
2082 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2083
2084 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2085 codec_dbg(codec, "invalid chip addr\n");
2086 return -ENXIO;
2087 }
2088
2089 chnl_prop = DSPDMAC_CHNLPROP_AC_MASK;
2090 active = 0;
2091
2092 codec_dbg(codec, " dsp_dma_setup_common() start reg pgm\n");
2093
2094 if (ovly) {
2095 status = chipio_read(codec, DSPDMAC_CHNLPROP_INST_OFFSET,
2096 &chnl_prop);
2097
2098 if (status < 0) {
2099 codec_dbg(codec, "read CHNLPROP Reg fail\n");
2100 return status;
2101 }
2102 codec_dbg(codec, "dsp_dma_setup_common() Read CHNLPROP\n");
2103 }
2104
2105 if (!code)
2106 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2107 else
2108 chnl_prop |= (1 << (DSPDMAC_CHNLPROP_MSPCE_LOBIT + dma_chan));
2109
2110 chnl_prop &= ~(1 << (DSPDMAC_CHNLPROP_DCON_LOBIT + dma_chan));
2111
2112 status = chipio_write(codec, DSPDMAC_CHNLPROP_INST_OFFSET, chnl_prop);
2113 if (status < 0) {
2114 codec_dbg(codec, "write CHNLPROP Reg fail\n");
2115 return status;
2116 }
2117 codec_dbg(codec, " dsp_dma_setup_common() Write CHNLPROP\n");
2118
2119 if (ovly) {
2120 status = chipio_read(codec, DSPDMAC_ACTIVE_INST_OFFSET,
2121 &active);
2122
2123 if (status < 0) {
2124 codec_dbg(codec, "read ACTIVE Reg fail\n");
2125 return status;
2126 }
2127 codec_dbg(codec, "dsp_dma_setup_common() Read ACTIVE\n");
2128 }
2129
2130 active &= (~(1 << (DSPDMAC_ACTIVE_AAR_LOBIT + dma_chan))) &
2131 DSPDMAC_ACTIVE_AAR_MASK;
2132
2133 status = chipio_write(codec, DSPDMAC_ACTIVE_INST_OFFSET, active);
2134 if (status < 0) {
2135 codec_dbg(codec, "write ACTIVE Reg fail\n");
2136 return status;
2137 }
2138
2139 codec_dbg(codec, " dsp_dma_setup_common() Write ACTIVE\n");
2140
2141 status = chipio_write(codec, DSPDMAC_AUDCHSEL_INST_OFFSET(dma_chan),
2142 port_map_mask);
2143 if (status < 0) {
2144 codec_dbg(codec, "write AUDCHSEL Reg fail\n");
2145 return status;
2146 }
2147 codec_dbg(codec, " dsp_dma_setup_common() Write AUDCHSEL\n");
2148
2149 status = chipio_write(codec, DSPDMAC_IRQCNT_INST_OFFSET(dma_chan),
2150 DSPDMAC_IRQCNT_BICNT_MASK | DSPDMAC_IRQCNT_CICNT_MASK);
2151 if (status < 0) {
2152 codec_dbg(codec, "write IRQCNT Reg fail\n");
2153 return status;
2154 }
2155 codec_dbg(codec, " dsp_dma_setup_common() Write IRQCNT\n");
2156
2157 codec_dbg(codec,
2158 "ChipA=0x%x,DspA=0x%x,dmaCh=%u, "
2159 "CHSEL=0x%x,CHPROP=0x%x,Active=0x%x\n",
2160 chip_addx, dsp_addx, dma_chan,
2161 port_map_mask, chnl_prop, active);
2162
2163 codec_dbg(codec, "-- dsp_dma_setup_common() -- Complete ------\n");
2164
2165 return 0;
2166 }
2167
2168 /*
2169 * Setup the DSP DMA per-transfer-specific registers
2170 */
2171 static int dsp_dma_setup(struct hda_codec *codec,
2172 unsigned int chip_addx,
2173 unsigned int count,
2174 unsigned int dma_chan)
2175 {
2176 int status = 0;
2177 bool code, yram;
2178 unsigned int dsp_addx;
2179 unsigned int addr_field;
2180 unsigned int incr_field;
2181 unsigned int base_cnt;
2182 unsigned int cur_cnt;
2183 unsigned int dma_cfg = 0;
2184 unsigned int adr_ofs = 0;
2185 unsigned int xfr_cnt = 0;
2186 const unsigned int max_dma_count = 1 << (DSPDMAC_XFRCNT_BCNT_HIBIT -
2187 DSPDMAC_XFRCNT_BCNT_LOBIT + 1);
2188
2189 codec_dbg(codec, "-- dsp_dma_setup() -- Begin ---------\n");
2190
2191 if (count > max_dma_count) {
2192 codec_dbg(codec, "count too big\n");
2193 return -EINVAL;
2194 }
2195
2196 dsp_addx = dsp_chip_to_dsp_addx(chip_addx, &code, &yram);
2197 if (dsp_addx == INVALID_CHIP_ADDRESS) {
2198 codec_dbg(codec, "invalid chip addr\n");
2199 return -ENXIO;
2200 }
2201
2202 codec_dbg(codec, " dsp_dma_setup() start reg pgm\n");
2203
2204 addr_field = dsp_addx << DSPDMAC_DMACFG_DBADR_LOBIT;
2205 incr_field = 0;
2206
2207 if (!code) {
2208 addr_field <<= 1;
2209 if (yram)
2210 addr_field |= (1 << DSPDMAC_DMACFG_DBADR_LOBIT);
2211
2212 incr_field = (1 << DSPDMAC_DMACFG_AINCR_LOBIT);
2213 }
2214
2215 dma_cfg = addr_field + incr_field;
2216 status = chipio_write(codec, DSPDMAC_DMACFG_INST_OFFSET(dma_chan),
2217 dma_cfg);
2218 if (status < 0) {
2219 codec_dbg(codec, "write DMACFG Reg fail\n");
2220 return status;
2221 }
2222 codec_dbg(codec, " dsp_dma_setup() Write DMACFG\n");
2223
2224 adr_ofs = (count - 1) << (DSPDMAC_DSPADROFS_BOFS_LOBIT +
2225 (code ? 0 : 1));
2226
2227 status = chipio_write(codec, DSPDMAC_DSPADROFS_INST_OFFSET(dma_chan),
2228 adr_ofs);
2229 if (status < 0) {
2230 codec_dbg(codec, "write DSPADROFS Reg fail\n");
2231 return status;
2232 }
2233 codec_dbg(codec, " dsp_dma_setup() Write DSPADROFS\n");
2234
2235 base_cnt = (count - 1) << DSPDMAC_XFRCNT_BCNT_LOBIT;
2236
2237 cur_cnt = (count - 1) << DSPDMAC_XFRCNT_CCNT_LOBIT;
2238
2239 xfr_cnt = base_cnt | cur_cnt;
2240
2241 status = chipio_write(codec,
2242 DSPDMAC_XFRCNT_INST_OFFSET(dma_chan), xfr_cnt);
2243 if (status < 0) {
2244 codec_dbg(codec, "write XFRCNT Reg fail\n");
2245 return status;
2246 }
2247 codec_dbg(codec, " dsp_dma_setup() Write XFRCNT\n");
2248
2249 codec_dbg(codec,
2250 "ChipA=0x%x, cnt=0x%x, DMACFG=0x%x, "
2251 "ADROFS=0x%x, XFRCNT=0x%x\n",
2252 chip_addx, count, dma_cfg, adr_ofs, xfr_cnt);
2253
2254 codec_dbg(codec, "-- dsp_dma_setup() -- Complete ---------\n");
2255
2256 return 0;
2257 }
2258
2259 /*
2260 * Start the DSP DMA
2261 */
2262 static int dsp_dma_start(struct hda_codec *codec,
2263 unsigned int dma_chan, bool ovly)
2264 {
2265 unsigned int reg = 0;
2266 int status = 0;
2267
2268 codec_dbg(codec, "-- dsp_dma_start() -- Begin ---------\n");
2269
2270 if (ovly) {
2271 status = chipio_read(codec,
2272 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2273
2274 if (status < 0) {
2275 codec_dbg(codec, "read CHNLSTART reg fail\n");
2276 return status;
2277 }
2278 codec_dbg(codec, "-- dsp_dma_start() Read CHNLSTART\n");
2279
2280 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2281 DSPDMAC_CHNLSTART_DIS_MASK);
2282 }
2283
2284 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2285 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_EN_LOBIT)));
2286 if (status < 0) {
2287 codec_dbg(codec, "write CHNLSTART reg fail\n");
2288 return status;
2289 }
2290 codec_dbg(codec, "-- dsp_dma_start() -- Complete ---------\n");
2291
2292 return status;
2293 }
2294
2295 /*
2296 * Stop the DSP DMA
2297 */
2298 static int dsp_dma_stop(struct hda_codec *codec,
2299 unsigned int dma_chan, bool ovly)
2300 {
2301 unsigned int reg = 0;
2302 int status = 0;
2303
2304 codec_dbg(codec, "-- dsp_dma_stop() -- Begin ---------\n");
2305
2306 if (ovly) {
2307 status = chipio_read(codec,
2308 DSPDMAC_CHNLSTART_INST_OFFSET, &reg);
2309
2310 if (status < 0) {
2311 codec_dbg(codec, "read CHNLSTART reg fail\n");
2312 return status;
2313 }
2314 codec_dbg(codec, "-- dsp_dma_stop() Read CHNLSTART\n");
2315 reg &= ~(DSPDMAC_CHNLSTART_EN_MASK |
2316 DSPDMAC_CHNLSTART_DIS_MASK);
2317 }
2318
2319 status = chipio_write(codec, DSPDMAC_CHNLSTART_INST_OFFSET,
2320 reg | (1 << (dma_chan + DSPDMAC_CHNLSTART_DIS_LOBIT)));
2321 if (status < 0) {
2322 codec_dbg(codec, "write CHNLSTART reg fail\n");
2323 return status;
2324 }
2325 codec_dbg(codec, "-- dsp_dma_stop() -- Complete ---------\n");
2326
2327 return status;
2328 }
2329
2330 /**
2331 * Allocate router ports
2332 *
2333 * @codec: the HDA codec
2334 * @num_chans: number of channels in the stream
2335 * @ports_per_channel: number of ports per channel
2336 * @start_device: start device
2337 * @port_map: pointer to the port list to hold the allocated ports
2338 *
2339 * Returns zero or a negative error code.
2340 */
2341 static int dsp_allocate_router_ports(struct hda_codec *codec,
2342 unsigned int num_chans,
2343 unsigned int ports_per_channel,
2344 unsigned int start_device,
2345 unsigned int *port_map)
2346 {
2347 int status = 0;
2348 int res;
2349 u8 val;
2350
2351 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2352 if (status < 0)
2353 return status;
2354
2355 val = start_device << 6;
2356 val |= (ports_per_channel - 1) << 4;
2357 val |= num_chans - 1;
2358
2359 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2360 VENDOR_CHIPIO_PORT_ALLOC_CONFIG_SET,
2361 val);
2362
2363 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2364 VENDOR_CHIPIO_PORT_ALLOC_SET,
2365 MEM_CONNID_DSP);
2366
2367 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2368 if (status < 0)
2369 return status;
2370
2371 res = snd_hda_codec_read(codec, WIDGET_CHIP_CTRL, 0,
2372 VENDOR_CHIPIO_PORT_ALLOC_GET, 0);
2373
2374 *port_map = res;
2375
2376 return (res < 0) ? res : 0;
2377 }
2378
2379 /*
2380 * Free router ports
2381 */
2382 static int dsp_free_router_ports(struct hda_codec *codec)
2383 {
2384 int status = 0;
2385
2386 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2387 if (status < 0)
2388 return status;
2389
2390 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
2391 VENDOR_CHIPIO_PORT_FREE_SET,
2392 MEM_CONNID_DSP);
2393
2394 status = chipio_send(codec, VENDOR_CHIPIO_STATUS, 0);
2395
2396 return status;
2397 }
2398
2399 /*
2400 * Allocate DSP ports for the download stream
2401 */
2402 static int dsp_allocate_ports(struct hda_codec *codec,
2403 unsigned int num_chans,
2404 unsigned int rate_multi, unsigned int *port_map)
2405 {
2406 int status;
2407
2408 codec_dbg(codec, " dsp_allocate_ports() -- begin\n");
2409
2410 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2411 codec_dbg(codec, "bad rate multiple\n");
2412 return -EINVAL;
2413 }
2414
2415 status = dsp_allocate_router_ports(codec, num_chans,
2416 rate_multi, 0, port_map);
2417
2418 codec_dbg(codec, " dsp_allocate_ports() -- complete\n");
2419
2420 return status;
2421 }
2422
2423 static int dsp_allocate_ports_format(struct hda_codec *codec,
2424 const unsigned short fmt,
2425 unsigned int *port_map)
2426 {
2427 int status;
2428 unsigned int num_chans;
2429
2430 unsigned int sample_rate_div = ((get_hdafmt_rate(fmt) >> 0) & 3) + 1;
2431 unsigned int sample_rate_mul = ((get_hdafmt_rate(fmt) >> 3) & 3) + 1;
2432 unsigned int rate_multi = sample_rate_mul / sample_rate_div;
2433
2434 if ((rate_multi != 1) && (rate_multi != 2) && (rate_multi != 4)) {
2435 codec_dbg(codec, "bad rate multiple\n");
2436 return -EINVAL;
2437 }
2438
2439 num_chans = get_hdafmt_chs(fmt) + 1;
2440
2441 status = dsp_allocate_ports(codec, num_chans, rate_multi, port_map);
2442
2443 return status;
2444 }
2445
2446 /*
2447 * free DSP ports
2448 */
2449 static int dsp_free_ports(struct hda_codec *codec)
2450 {
2451 int status;
2452
2453 codec_dbg(codec, " dsp_free_ports() -- begin\n");
2454
2455 status = dsp_free_router_ports(codec);
2456 if (status < 0) {
2457 codec_dbg(codec, "free router ports fail\n");
2458 return status;
2459 }
2460 codec_dbg(codec, " dsp_free_ports() -- complete\n");
2461
2462 return status;
2463 }
2464
2465 /*
2466 * HDA DMA engine stuffs for DSP code download
2467 */
2468 struct dma_engine {
2469 struct hda_codec *codec;
2470 unsigned short m_converter_format;
2471 struct snd_dma_buffer *dmab;
2472 unsigned int buf_size;
2473 };
2474
2475
2476 enum dma_state {
2477 DMA_STATE_STOP = 0,
2478 DMA_STATE_RUN = 1
2479 };
2480
2481 static int dma_convert_to_hda_format(struct hda_codec *codec,
2482 unsigned int sample_rate,
2483 unsigned short channels,
2484 unsigned short *hda_format)
2485 {
2486 unsigned int format_val;
2487
2488 format_val = snd_hdac_calc_stream_format(sample_rate,
2489 channels, SNDRV_PCM_FORMAT_S32_LE, 32, 0);
2490
2491 if (hda_format)
2492 *hda_format = (unsigned short)format_val;
2493
2494 return 0;
2495 }
2496
2497 /*
2498 * Reset DMA for DSP download
2499 */
2500 static int dma_reset(struct dma_engine *dma)
2501 {
2502 struct hda_codec *codec = dma->codec;
2503 struct ca0132_spec *spec = codec->spec;
2504 int status;
2505
2506 if (dma->dmab->area)
2507 snd_hda_codec_load_dsp_cleanup(codec, dma->dmab);
2508
2509 status = snd_hda_codec_load_dsp_prepare(codec,
2510 dma->m_converter_format,
2511 dma->buf_size,
2512 dma->dmab);
2513 if (status < 0)
2514 return status;
2515 spec->dsp_stream_id = status;
2516 return 0;
2517 }
2518
2519 static int dma_set_state(struct dma_engine *dma, enum dma_state state)
2520 {
2521 bool cmd;
2522
2523 switch (state) {
2524 case DMA_STATE_STOP:
2525 cmd = false;
2526 break;
2527 case DMA_STATE_RUN:
2528 cmd = true;
2529 break;
2530 default:
2531 return 0;
2532 }
2533
2534 snd_hda_codec_load_dsp_trigger(dma->codec, cmd);
2535 return 0;
2536 }
2537
2538 static unsigned int dma_get_buffer_size(struct dma_engine *dma)
2539 {
2540 return dma->dmab->bytes;
2541 }
2542
2543 static unsigned char *dma_get_buffer_addr(struct dma_engine *dma)
2544 {
2545 return dma->dmab->area;
2546 }
2547
2548 static int dma_xfer(struct dma_engine *dma,
2549 const unsigned int *data,
2550 unsigned int count)
2551 {
2552 memcpy(dma->dmab->area, data, count);
2553 return 0;
2554 }
2555
2556 static void dma_get_converter_format(
2557 struct dma_engine *dma,
2558 unsigned short *format)
2559 {
2560 if (format)
2561 *format = dma->m_converter_format;
2562 }
2563
2564 static unsigned int dma_get_stream_id(struct dma_engine *dma)
2565 {
2566 struct ca0132_spec *spec = dma->codec->spec;
2567
2568 return spec->dsp_stream_id;
2569 }
2570
2571 struct dsp_image_seg {
2572 u32 magic;
2573 u32 chip_addr;
2574 u32 count;
2575 u32 data[0];
2576 };
2577
2578 static const u32 g_magic_value = 0x4c46584d;
2579 static const u32 g_chip_addr_magic_value = 0xFFFFFF01;
2580
2581 static bool is_valid(const struct dsp_image_seg *p)
2582 {
2583 return p->magic == g_magic_value;
2584 }
2585
2586 static bool is_hci_prog_list_seg(const struct dsp_image_seg *p)
2587 {
2588 return g_chip_addr_magic_value == p->chip_addr;
2589 }
2590
2591 static bool is_last(const struct dsp_image_seg *p)
2592 {
2593 return p->count == 0;
2594 }
2595
2596 static size_t dsp_sizeof(const struct dsp_image_seg *p)
2597 {
2598 return sizeof(*p) + p->count*sizeof(u32);
2599 }
2600
2601 static const struct dsp_image_seg *get_next_seg_ptr(
2602 const struct dsp_image_seg *p)
2603 {
2604 return (struct dsp_image_seg *)((unsigned char *)(p) + dsp_sizeof(p));
2605 }
2606
2607 /*
2608 * CA0132 chip DSP transfer stuffs. For DSP download.
2609 */
2610 #define INVALID_DMA_CHANNEL (~0U)
2611
2612 /*
2613 * Program a list of address/data pairs via the ChipIO widget.
2614 * The segment data is in the format of successive pairs of words.
2615 * These are repeated as indicated by the segment's count field.
2616 */
2617 static int dspxfr_hci_write(struct hda_codec *codec,
2618 const struct dsp_image_seg *fls)
2619 {
2620 int status;
2621 const u32 *data;
2622 unsigned int count;
2623
2624 if (fls == NULL || fls->chip_addr != g_chip_addr_magic_value) {
2625 codec_dbg(codec, "hci_write invalid params\n");
2626 return -EINVAL;
2627 }
2628
2629 count = fls->count;
2630 data = (u32 *)(fls->data);
2631 while (count >= 2) {
2632 status = chipio_write(codec, data[0], data[1]);
2633 if (status < 0) {
2634 codec_dbg(codec, "hci_write chipio failed\n");
2635 return status;
2636 }
2637 count -= 2;
2638 data += 2;
2639 }
2640 return 0;
2641 }
2642
2643 /**
2644 * Write a block of data into DSP code or data RAM using pre-allocated
2645 * DMA engine.
2646 *
2647 * @codec: the HDA codec
2648 * @fls: pointer to a fast load image
2649 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2650 * no relocation
2651 * @dma_engine: pointer to DMA engine to be used for DSP download
2652 * @dma_chan: The number of DMA channels used for DSP download
2653 * @port_map_mask: port mapping
2654 * @ovly: TRUE if overlay format is required
2655 *
2656 * Returns zero or a negative error code.
2657 */
2658 static int dspxfr_one_seg(struct hda_codec *codec,
2659 const struct dsp_image_seg *fls,
2660 unsigned int reloc,
2661 struct dma_engine *dma_engine,
2662 unsigned int dma_chan,
2663 unsigned int port_map_mask,
2664 bool ovly)
2665 {
2666 int status = 0;
2667 bool comm_dma_setup_done = false;
2668 const unsigned int *data;
2669 unsigned int chip_addx;
2670 unsigned int words_to_write;
2671 unsigned int buffer_size_words;
2672 unsigned char *buffer_addx;
2673 unsigned short hda_format;
2674 unsigned int sample_rate_div;
2675 unsigned int sample_rate_mul;
2676 unsigned int num_chans;
2677 unsigned int hda_frame_size_words;
2678 unsigned int remainder_words;
2679 const u32 *data_remainder;
2680 u32 chip_addx_remainder;
2681 unsigned int run_size_words;
2682 const struct dsp_image_seg *hci_write = NULL;
2683 unsigned long timeout;
2684 bool dma_active;
2685
2686 if (fls == NULL)
2687 return -EINVAL;
2688 if (is_hci_prog_list_seg(fls)) {
2689 hci_write = fls;
2690 fls = get_next_seg_ptr(fls);
2691 }
2692
2693 if (hci_write && (!fls || is_last(fls))) {
2694 codec_dbg(codec, "hci_write\n");
2695 return dspxfr_hci_write(codec, hci_write);
2696 }
2697
2698 if (fls == NULL || dma_engine == NULL || port_map_mask == 0) {
2699 codec_dbg(codec, "Invalid Params\n");
2700 return -EINVAL;
2701 }
2702
2703 data = fls->data;
2704 chip_addx = fls->chip_addr,
2705 words_to_write = fls->count;
2706
2707 if (!words_to_write)
2708 return hci_write ? dspxfr_hci_write(codec, hci_write) : 0;
2709 if (reloc)
2710 chip_addx = (chip_addx & (0xFFFF0000 << 2)) + (reloc << 2);
2711
2712 if (!UC_RANGE(chip_addx, words_to_write) &&
2713 !X_RANGE_ALL(chip_addx, words_to_write) &&
2714 !Y_RANGE_ALL(chip_addx, words_to_write)) {
2715 codec_dbg(codec, "Invalid chip_addx Params\n");
2716 return -EINVAL;
2717 }
2718
2719 buffer_size_words = (unsigned int)dma_get_buffer_size(dma_engine) /
2720 sizeof(u32);
2721
2722 buffer_addx = dma_get_buffer_addr(dma_engine);
2723
2724 if (buffer_addx == NULL) {
2725 codec_dbg(codec, "dma_engine buffer NULL\n");
2726 return -EINVAL;
2727 }
2728
2729 dma_get_converter_format(dma_engine, &hda_format);
2730 sample_rate_div = ((get_hdafmt_rate(hda_format) >> 0) & 3) + 1;
2731 sample_rate_mul = ((get_hdafmt_rate(hda_format) >> 3) & 3) + 1;
2732 num_chans = get_hdafmt_chs(hda_format) + 1;
2733
2734 hda_frame_size_words = ((sample_rate_div == 0) ? 0 :
2735 (num_chans * sample_rate_mul / sample_rate_div));
2736
2737 if (hda_frame_size_words == 0) {
2738 codec_dbg(codec, "frmsz zero\n");
2739 return -EINVAL;
2740 }
2741
2742 buffer_size_words = min(buffer_size_words,
2743 (unsigned int)(UC_RANGE(chip_addx, 1) ?
2744 65536 : 32768));
2745 buffer_size_words -= buffer_size_words % hda_frame_size_words;
2746 codec_dbg(codec,
2747 "chpadr=0x%08x frmsz=%u nchan=%u "
2748 "rate_mul=%u div=%u bufsz=%u\n",
2749 chip_addx, hda_frame_size_words, num_chans,
2750 sample_rate_mul, sample_rate_div, buffer_size_words);
2751
2752 if (buffer_size_words < hda_frame_size_words) {
2753 codec_dbg(codec, "dspxfr_one_seg:failed\n");
2754 return -EINVAL;
2755 }
2756
2757 remainder_words = words_to_write % hda_frame_size_words;
2758 data_remainder = data;
2759 chip_addx_remainder = chip_addx;
2760
2761 data += remainder_words;
2762 chip_addx += remainder_words*sizeof(u32);
2763 words_to_write -= remainder_words;
2764
2765 while (words_to_write != 0) {
2766 run_size_words = min(buffer_size_words, words_to_write);
2767 codec_dbg(codec, "dspxfr (seg loop)cnt=%u rs=%u remainder=%u\n",
2768 words_to_write, run_size_words, remainder_words);
2769 dma_xfer(dma_engine, data, run_size_words*sizeof(u32));
2770 if (!comm_dma_setup_done) {
2771 status = dsp_dma_stop(codec, dma_chan, ovly);
2772 if (status < 0)
2773 return status;
2774 status = dsp_dma_setup_common(codec, chip_addx,
2775 dma_chan, port_map_mask, ovly);
2776 if (status < 0)
2777 return status;
2778 comm_dma_setup_done = true;
2779 }
2780
2781 status = dsp_dma_setup(codec, chip_addx,
2782 run_size_words, dma_chan);
2783 if (status < 0)
2784 return status;
2785 status = dsp_dma_start(codec, dma_chan, ovly);
2786 if (status < 0)
2787 return status;
2788 if (!dsp_is_dma_active(codec, dma_chan)) {
2789 codec_dbg(codec, "dspxfr:DMA did not start\n");
2790 return -EIO;
2791 }
2792 status = dma_set_state(dma_engine, DMA_STATE_RUN);
2793 if (status < 0)
2794 return status;
2795 if (remainder_words != 0) {
2796 status = chipio_write_multiple(codec,
2797 chip_addx_remainder,
2798 data_remainder,
2799 remainder_words);
2800 if (status < 0)
2801 return status;
2802 remainder_words = 0;
2803 }
2804 if (hci_write) {
2805 status = dspxfr_hci_write(codec, hci_write);
2806 if (status < 0)
2807 return status;
2808 hci_write = NULL;
2809 }
2810
2811 timeout = jiffies + msecs_to_jiffies(2000);
2812 do {
2813 dma_active = dsp_is_dma_active(codec, dma_chan);
2814 if (!dma_active)
2815 break;
2816 msleep(20);
2817 } while (time_before(jiffies, timeout));
2818 if (dma_active)
2819 break;
2820
2821 codec_dbg(codec, "+++++ DMA complete\n");
2822 dma_set_state(dma_engine, DMA_STATE_STOP);
2823 status = dma_reset(dma_engine);
2824
2825 if (status < 0)
2826 return status;
2827
2828 data += run_size_words;
2829 chip_addx += run_size_words*sizeof(u32);
2830 words_to_write -= run_size_words;
2831 }
2832
2833 if (remainder_words != 0) {
2834 status = chipio_write_multiple(codec, chip_addx_remainder,
2835 data_remainder, remainder_words);
2836 }
2837
2838 return status;
2839 }
2840
2841 /**
2842 * Write the entire DSP image of a DSP code/data overlay to DSP memories
2843 *
2844 * @codec: the HDA codec
2845 * @fls_data: pointer to a fast load image
2846 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2847 * no relocation
2848 * @sample_rate: sampling rate of the stream used for DSP download
2849 * @channels: channels of the stream used for DSP download
2850 * @ovly: TRUE if overlay format is required
2851 *
2852 * Returns zero or a negative error code.
2853 */
2854 static int dspxfr_image(struct hda_codec *codec,
2855 const struct dsp_image_seg *fls_data,
2856 unsigned int reloc,
2857 unsigned int sample_rate,
2858 unsigned short channels,
2859 bool ovly)
2860 {
2861 struct ca0132_spec *spec = codec->spec;
2862 int status;
2863 unsigned short hda_format = 0;
2864 unsigned int response;
2865 unsigned char stream_id = 0;
2866 struct dma_engine *dma_engine;
2867 unsigned int dma_chan;
2868 unsigned int port_map_mask;
2869
2870 if (fls_data == NULL)
2871 return -EINVAL;
2872
2873 dma_engine = kzalloc(sizeof(*dma_engine), GFP_KERNEL);
2874 if (!dma_engine)
2875 return -ENOMEM;
2876
2877 dma_engine->dmab = kzalloc(sizeof(*dma_engine->dmab), GFP_KERNEL);
2878 if (!dma_engine->dmab) {
2879 kfree(dma_engine);
2880 return -ENOMEM;
2881 }
2882
2883 dma_engine->codec = codec;
2884 dma_convert_to_hda_format(codec, sample_rate, channels, &hda_format);
2885 dma_engine->m_converter_format = hda_format;
2886 dma_engine->buf_size = (ovly ? DSP_DMA_WRITE_BUFLEN_OVLY :
2887 DSP_DMA_WRITE_BUFLEN_INIT) * 2;
2888
2889 dma_chan = ovly ? INVALID_DMA_CHANNEL : 0;
2890
2891 status = codec_set_converter_format(codec, WIDGET_CHIP_CTRL,
2892 hda_format, &response);
2893
2894 if (status < 0) {
2895 codec_dbg(codec, "set converter format fail\n");
2896 goto exit;
2897 }
2898
2899 status = snd_hda_codec_load_dsp_prepare(codec,
2900 dma_engine->m_converter_format,
2901 dma_engine->buf_size,
2902 dma_engine->dmab);
2903 if (status < 0)
2904 goto exit;
2905 spec->dsp_stream_id = status;
2906
2907 if (ovly) {
2908 status = dspio_alloc_dma_chan(codec, &dma_chan);
2909 if (status < 0) {
2910 codec_dbg(codec, "alloc dmachan fail\n");
2911 dma_chan = INVALID_DMA_CHANNEL;
2912 goto exit;
2913 }
2914 }
2915
2916 port_map_mask = 0;
2917 status = dsp_allocate_ports_format(codec, hda_format,
2918 &port_map_mask);
2919 if (status < 0) {
2920 codec_dbg(codec, "alloc ports fail\n");
2921 goto exit;
2922 }
2923
2924 stream_id = dma_get_stream_id(dma_engine);
2925 status = codec_set_converter_stream_channel(codec,
2926 WIDGET_CHIP_CTRL, stream_id, 0, &response);
2927 if (status < 0) {
2928 codec_dbg(codec, "set stream chan fail\n");
2929 goto exit;
2930 }
2931
2932 while ((fls_data != NULL) && !is_last(fls_data)) {
2933 if (!is_valid(fls_data)) {
2934 codec_dbg(codec, "FLS check fail\n");
2935 status = -EINVAL;
2936 goto exit;
2937 }
2938 status = dspxfr_one_seg(codec, fls_data, reloc,
2939 dma_engine, dma_chan,
2940 port_map_mask, ovly);
2941 if (status < 0)
2942 break;
2943
2944 if (is_hci_prog_list_seg(fls_data))
2945 fls_data = get_next_seg_ptr(fls_data);
2946
2947 if ((fls_data != NULL) && !is_last(fls_data))
2948 fls_data = get_next_seg_ptr(fls_data);
2949 }
2950
2951 if (port_map_mask != 0)
2952 status = dsp_free_ports(codec);
2953
2954 if (status < 0)
2955 goto exit;
2956
2957 status = codec_set_converter_stream_channel(codec,
2958 WIDGET_CHIP_CTRL, 0, 0, &response);
2959
2960 exit:
2961 if (ovly && (dma_chan != INVALID_DMA_CHANNEL))
2962 dspio_free_dma_chan(codec, dma_chan);
2963
2964 if (dma_engine->dmab->area)
2965 snd_hda_codec_load_dsp_cleanup(codec, dma_engine->dmab);
2966 kfree(dma_engine->dmab);
2967 kfree(dma_engine);
2968
2969 return status;
2970 }
2971
2972 /*
2973 * CA0132 DSP download stuffs.
2974 */
2975 static void dspload_post_setup(struct hda_codec *codec)
2976 {
2977 struct ca0132_spec *spec = codec->spec;
2978 codec_dbg(codec, "---- dspload_post_setup ------\n");
2979 if (!spec->use_alt_functions) {
2980 /*set DSP speaker to 2.0 configuration*/
2981 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x18), 0x08080080);
2982 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x19), 0x3f800000);
2983
2984 /*update write pointer*/
2985 chipio_write(codec, XRAM_XRAM_INST_OFFSET(0x29), 0x00000002);
2986 }
2987 }
2988
2989 /**
2990 * dspload_image - Download DSP from a DSP Image Fast Load structure.
2991 *
2992 * @codec: the HDA codec
2993 * @fls: pointer to a fast load image
2994 * @ovly: TRUE if overlay format is required
2995 * @reloc: Relocation address for loading single-segment overlays, or 0 for
2996 * no relocation
2997 * @autostart: TRUE if DSP starts after loading; ignored if ovly is TRUE
2998 * @router_chans: number of audio router channels to be allocated (0 means use
2999 * internal defaults; max is 32)
3000 *
3001 * Download DSP from a DSP Image Fast Load structure. This structure is a
3002 * linear, non-constant sized element array of structures, each of which
3003 * contain the count of the data to be loaded, the data itself, and the
3004 * corresponding starting chip address of the starting data location.
3005 * Returns zero or a negative error code.
3006 */
3007 static int dspload_image(struct hda_codec *codec,
3008 const struct dsp_image_seg *fls,
3009 bool ovly,
3010 unsigned int reloc,
3011 bool autostart,
3012 int router_chans)
3013 {
3014 int status = 0;
3015 unsigned int sample_rate;
3016 unsigned short channels;
3017
3018 codec_dbg(codec, "---- dspload_image begin ------\n");
3019 if (router_chans == 0) {
3020 if (!ovly)
3021 router_chans = DMA_TRANSFER_FRAME_SIZE_NWORDS;
3022 else
3023 router_chans = DMA_OVERLAY_FRAME_SIZE_NWORDS;
3024 }
3025
3026 sample_rate = 48000;
3027 channels = (unsigned short)router_chans;
3028
3029 while (channels > 16) {
3030 sample_rate *= 2;
3031 channels /= 2;
3032 }
3033
3034 do {
3035 codec_dbg(codec, "Ready to program DMA\n");
3036 if (!ovly)
3037 status = dsp_reset(codec);
3038
3039 if (status < 0)
3040 break;
3041
3042 codec_dbg(codec, "dsp_reset() complete\n");
3043 status = dspxfr_image(codec, fls, reloc, sample_rate, channels,
3044 ovly);
3045
3046 if (status < 0)
3047 break;
3048
3049 codec_dbg(codec, "dspxfr_image() complete\n");
3050 if (autostart && !ovly) {
3051 dspload_post_setup(codec);
3052 status = dsp_set_run_state(codec);
3053 }
3054
3055 codec_dbg(codec, "LOAD FINISHED\n");
3056 } while (0);
3057
3058 return status;
3059 }
3060
3061 #ifdef CONFIG_SND_HDA_CODEC_CA0132_DSP
3062 static bool dspload_is_loaded(struct hda_codec *codec)
3063 {
3064 unsigned int data = 0;
3065 int status = 0;
3066
3067 status = chipio_read(codec, 0x40004, &data);
3068 if ((status < 0) || (data != 1))
3069 return false;
3070
3071 return true;
3072 }
3073 #else
3074 #define dspload_is_loaded(codec) false
3075 #endif
3076
3077 static bool dspload_wait_loaded(struct hda_codec *codec)
3078 {
3079 unsigned long timeout = jiffies + msecs_to_jiffies(2000);
3080
3081 do {
3082 if (dspload_is_loaded(codec)) {
3083 codec_info(codec, "ca0132 DSP downloaded and running\n");
3084 return true;
3085 }
3086 msleep(20);
3087 } while (time_before(jiffies, timeout));
3088
3089 codec_err(codec, "ca0132 failed to download DSP\n");
3090 return false;
3091 }
3092
3093 /*
3094 * Setup GPIO for the other variants of Core3D.
3095 */
3096
3097 /*
3098 * For cards with PCI-E region2 (Sound Blaster Z/ZxR, Recon3D, and AE-5)
3099 * the mmio address 0x320 is used to set GPIO pins. The format for the data
3100 * The first eight bits are just the number of the pin. So far, I've only seen
3101 * this number go to 7.
3102 */
3103 static void ca0132_mmio_gpio_set(struct hda_codec *codec, unsigned int gpio_pin,
3104 bool enable)
3105 {
3106 struct ca0132_spec *spec = codec->spec;
3107 unsigned short gpio_data;
3108
3109 gpio_data = gpio_pin & 0xF;
3110 gpio_data |= ((enable << 8) & 0x100);
3111
3112 writew(gpio_data, spec->mem_base + 0x320);
3113 }
3114
3115 /*
3116 * Sets up the GPIO pins so that they are discoverable. If this isn't done,
3117 * the card shows as having no GPIO pins.
3118 */
3119 static void ca0132_gpio_init(struct hda_codec *codec)
3120 {
3121 struct ca0132_spec *spec = codec->spec;
3122
3123 switch (spec->quirk) {
3124 case QUIRK_SBZ:
3125 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3126 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x53);
3127 snd_hda_codec_write(codec, 0x01, 0, 0x790, 0x23);
3128 break;
3129 case QUIRK_R3DI:
3130 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
3131 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5B);
3132 break;
3133 }
3134
3135 }
3136
3137 /* Sets the GPIO for audio output. */
3138 static void ca0132_gpio_setup(struct hda_codec *codec)
3139 {
3140 struct ca0132_spec *spec = codec->spec;
3141
3142 switch (spec->quirk) {
3143 case QUIRK_SBZ:
3144 snd_hda_codec_write(codec, 0x01, 0,
3145 AC_VERB_SET_GPIO_DIRECTION, 0x07);
3146 snd_hda_codec_write(codec, 0x01, 0,
3147 AC_VERB_SET_GPIO_MASK, 0x07);
3148 snd_hda_codec_write(codec, 0x01, 0,
3149 AC_VERB_SET_GPIO_DATA, 0x04);
3150 snd_hda_codec_write(codec, 0x01, 0,
3151 AC_VERB_SET_GPIO_DATA, 0x06);
3152 break;
3153 case QUIRK_R3DI:
3154 snd_hda_codec_write(codec, 0x01, 0,
3155 AC_VERB_SET_GPIO_DIRECTION, 0x1E);
3156 snd_hda_codec_write(codec, 0x01, 0,
3157 AC_VERB_SET_GPIO_MASK, 0x1F);
3158 snd_hda_codec_write(codec, 0x01, 0,
3159 AC_VERB_SET_GPIO_DATA, 0x0C);
3160 break;
3161 }
3162 }
3163
3164 /*
3165 * GPIO control functions for the Recon3D integrated.
3166 */
3167
3168 enum r3di_gpio_bit {
3169 /* Bit 1 - Switch between front/rear mic. 0 = rear, 1 = front */
3170 R3DI_MIC_SELECT_BIT = 1,
3171 /* Bit 2 - Switch between headphone/line out. 0 = Headphone, 1 = Line */
3172 R3DI_OUT_SELECT_BIT = 2,
3173 /*
3174 * I dunno what this actually does, but it stays on until the dsp
3175 * is downloaded.
3176 */
3177 R3DI_GPIO_DSP_DOWNLOADING = 3,
3178 /*
3179 * Same as above, no clue what it does, but it comes on after the dsp
3180 * is downloaded.
3181 */
3182 R3DI_GPIO_DSP_DOWNLOADED = 4
3183 };
3184
3185 enum r3di_mic_select {
3186 /* Set GPIO bit 1 to 0 for rear mic */
3187 R3DI_REAR_MIC = 0,
3188 /* Set GPIO bit 1 to 1 for front microphone*/
3189 R3DI_FRONT_MIC = 1
3190 };
3191
3192 enum r3di_out_select {
3193 /* Set GPIO bit 2 to 0 for headphone */
3194 R3DI_HEADPHONE_OUT = 0,
3195 /* Set GPIO bit 2 to 1 for speaker */
3196 R3DI_LINE_OUT = 1
3197 };
3198 enum r3di_dsp_status {
3199 /* Set GPIO bit 3 to 1 until DSP is downloaded */
3200 R3DI_DSP_DOWNLOADING = 0,
3201 /* Set GPIO bit 4 to 1 once DSP is downloaded */
3202 R3DI_DSP_DOWNLOADED = 1
3203 };
3204
3205
3206 static void r3di_gpio_mic_set(struct hda_codec *codec,
3207 enum r3di_mic_select cur_mic)
3208 {
3209 unsigned int cur_gpio;
3210
3211 /* Get the current GPIO Data setup */
3212 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3213
3214 switch (cur_mic) {
3215 case R3DI_REAR_MIC:
3216 cur_gpio &= ~(1 << R3DI_MIC_SELECT_BIT);
3217 break;
3218 case R3DI_FRONT_MIC:
3219 cur_gpio |= (1 << R3DI_MIC_SELECT_BIT);
3220 break;
3221 }
3222 snd_hda_codec_write(codec, codec->core.afg, 0,
3223 AC_VERB_SET_GPIO_DATA, cur_gpio);
3224 }
3225
3226 static void r3di_gpio_out_set(struct hda_codec *codec,
3227 enum r3di_out_select cur_out)
3228 {
3229 unsigned int cur_gpio;
3230
3231 /* Get the current GPIO Data setup */
3232 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3233
3234 switch (cur_out) {
3235 case R3DI_HEADPHONE_OUT:
3236 cur_gpio &= ~(1 << R3DI_OUT_SELECT_BIT);
3237 break;
3238 case R3DI_LINE_OUT:
3239 cur_gpio |= (1 << R3DI_OUT_SELECT_BIT);
3240 break;
3241 }
3242 snd_hda_codec_write(codec, codec->core.afg, 0,
3243 AC_VERB_SET_GPIO_DATA, cur_gpio);
3244 }
3245
3246 static void r3di_gpio_dsp_status_set(struct hda_codec *codec,
3247 enum r3di_dsp_status dsp_status)
3248 {
3249 unsigned int cur_gpio;
3250
3251 /* Get the current GPIO Data setup */
3252 cur_gpio = snd_hda_codec_read(codec, 0x01, 0, AC_VERB_GET_GPIO_DATA, 0);
3253
3254 switch (dsp_status) {
3255 case R3DI_DSP_DOWNLOADING:
3256 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADING);
3257 snd_hda_codec_write(codec, codec->core.afg, 0,
3258 AC_VERB_SET_GPIO_DATA, cur_gpio);
3259 break;
3260 case R3DI_DSP_DOWNLOADED:
3261 /* Set DOWNLOADING bit to 0. */
3262 cur_gpio &= ~(1 << R3DI_GPIO_DSP_DOWNLOADING);
3263
3264 snd_hda_codec_write(codec, codec->core.afg, 0,
3265 AC_VERB_SET_GPIO_DATA, cur_gpio);
3266
3267 cur_gpio |= (1 << R3DI_GPIO_DSP_DOWNLOADED);
3268 break;
3269 }
3270
3271 snd_hda_codec_write(codec, codec->core.afg, 0,
3272 AC_VERB_SET_GPIO_DATA, cur_gpio);
3273 }
3274
3275 /*
3276 * PCM callbacks
3277 */
3278 static int ca0132_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3279 struct hda_codec *codec,
3280 unsigned int stream_tag,
3281 unsigned int format,
3282 struct snd_pcm_substream *substream)
3283 {
3284 struct ca0132_spec *spec = codec->spec;
3285
3286 snd_hda_codec_setup_stream(codec, spec->dacs[0], stream_tag, 0, format);
3287
3288 return 0;
3289 }
3290
3291 static int ca0132_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3292 struct hda_codec *codec,
3293 struct snd_pcm_substream *substream)
3294 {
3295 struct ca0132_spec *spec = codec->spec;
3296
3297 if (spec->dsp_state == DSP_DOWNLOADING)
3298 return 0;
3299
3300 /*If Playback effects are on, allow stream some time to flush
3301 *effects tail*/
3302 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
3303 msleep(50);
3304
3305 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
3306
3307 return 0;
3308 }
3309
3310 static unsigned int ca0132_playback_pcm_delay(struct hda_pcm_stream *info,
3311 struct hda_codec *codec,
3312 struct snd_pcm_substream *substream)
3313 {
3314 struct ca0132_spec *spec = codec->spec;
3315 unsigned int latency = DSP_PLAYBACK_INIT_LATENCY;
3316 struct snd_pcm_runtime *runtime = substream->runtime;
3317
3318 if (spec->dsp_state != DSP_DOWNLOADED)
3319 return 0;
3320
3321 /* Add latency if playback enhancement and either effect is enabled. */
3322 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]) {
3323 if ((spec->effects_switch[SURROUND - EFFECT_START_NID]) ||
3324 (spec->effects_switch[DIALOG_PLUS - EFFECT_START_NID]))
3325 latency += DSP_PLAY_ENHANCEMENT_LATENCY;
3326 }
3327
3328 /* Applying Speaker EQ adds latency as well. */
3329 if (spec->cur_out_type == SPEAKER_OUT)
3330 latency += DSP_SPEAKER_OUT_LATENCY;
3331
3332 return (latency * runtime->rate) / 1000;
3333 }
3334
3335 /*
3336 * Digital out
3337 */
3338 static int ca0132_dig_playback_pcm_open(struct hda_pcm_stream *hinfo,
3339 struct hda_codec *codec,
3340 struct snd_pcm_substream *substream)
3341 {
3342 struct ca0132_spec *spec = codec->spec;
3343 return snd_hda_multi_out_dig_open(codec, &spec->multiout);
3344 }
3345
3346 static int ca0132_dig_playback_pcm_prepare(struct hda_pcm_stream *hinfo,
3347 struct hda_codec *codec,
3348 unsigned int stream_tag,
3349 unsigned int format,
3350 struct snd_pcm_substream *substream)
3351 {
3352 struct ca0132_spec *spec = codec->spec;
3353 return snd_hda_multi_out_dig_prepare(codec, &spec->multiout,
3354 stream_tag, format, substream);
3355 }
3356
3357 static int ca0132_dig_playback_pcm_cleanup(struct hda_pcm_stream *hinfo,
3358 struct hda_codec *codec,
3359 struct snd_pcm_substream *substream)
3360 {
3361 struct ca0132_spec *spec = codec->spec;
3362 return snd_hda_multi_out_dig_cleanup(codec, &spec->multiout);
3363 }
3364
3365 static int ca0132_dig_playback_pcm_close(struct hda_pcm_stream *hinfo,
3366 struct hda_codec *codec,
3367 struct snd_pcm_substream *substream)
3368 {
3369 struct ca0132_spec *spec = codec->spec;
3370 return snd_hda_multi_out_dig_close(codec, &spec->multiout);
3371 }
3372
3373 /*
3374 * Analog capture
3375 */
3376 static int ca0132_capture_pcm_prepare(struct hda_pcm_stream *hinfo,
3377 struct hda_codec *codec,
3378 unsigned int stream_tag,
3379 unsigned int format,
3380 struct snd_pcm_substream *substream)
3381 {
3382 snd_hda_codec_setup_stream(codec, hinfo->nid,
3383 stream_tag, 0, format);
3384
3385 return 0;
3386 }
3387
3388 static int ca0132_capture_pcm_cleanup(struct hda_pcm_stream *hinfo,
3389 struct hda_codec *codec,
3390 struct snd_pcm_substream *substream)
3391 {
3392 struct ca0132_spec *spec = codec->spec;
3393
3394 if (spec->dsp_state == DSP_DOWNLOADING)
3395 return 0;
3396
3397 snd_hda_codec_cleanup_stream(codec, hinfo->nid);
3398 return 0;
3399 }
3400
3401 static unsigned int ca0132_capture_pcm_delay(struct hda_pcm_stream *info,
3402 struct hda_codec *codec,
3403 struct snd_pcm_substream *substream)
3404 {
3405 struct ca0132_spec *spec = codec->spec;
3406 unsigned int latency = DSP_CAPTURE_INIT_LATENCY;
3407 struct snd_pcm_runtime *runtime = substream->runtime;
3408
3409 if (spec->dsp_state != DSP_DOWNLOADED)
3410 return 0;
3411
3412 if (spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
3413 latency += DSP_CRYSTAL_VOICE_LATENCY;
3414
3415 return (latency * runtime->rate) / 1000;
3416 }
3417
3418 /*
3419 * Controls stuffs.
3420 */
3421
3422 /*
3423 * Mixer controls helpers.
3424 */
3425 #define CA0132_CODEC_VOL_MONO(xname, nid, channel, dir) \
3426 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3427 .name = xname, \
3428 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3429 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3430 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3431 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3432 .info = ca0132_volume_info, \
3433 .get = ca0132_volume_get, \
3434 .put = ca0132_volume_put, \
3435 .tlv = { .c = ca0132_volume_tlv }, \
3436 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3437
3438 /*
3439 * Creates a mixer control that uses defaults of HDA_CODEC_VOL except for the
3440 * volume put, which is used for setting the DSP volume. This was done because
3441 * the ca0132 functions were taking too much time and causing lag.
3442 */
3443 #define CA0132_ALT_CODEC_VOL_MONO(xname, nid, channel, dir) \
3444 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3445 .name = xname, \
3446 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3447 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3448 SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
3449 SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK, \
3450 .info = snd_hda_mixer_amp_volume_info, \
3451 .get = snd_hda_mixer_amp_volume_get, \
3452 .put = ca0132_alt_volume_put, \
3453 .tlv = { .c = snd_hda_mixer_amp_tlv }, \
3454 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3455
3456 #define CA0132_CODEC_MUTE_MONO(xname, nid, channel, dir) \
3457 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3458 .name = xname, \
3459 .subdevice = HDA_SUBDEV_AMP_FLAG, \
3460 .info = snd_hda_mixer_amp_switch_info, \
3461 .get = ca0132_switch_get, \
3462 .put = ca0132_switch_put, \
3463 .private_value = HDA_COMPOSE_AMP_VAL(nid, channel, 0, dir) }
3464
3465 /* stereo */
3466 #define CA0132_CODEC_VOL(xname, nid, dir) \
3467 CA0132_CODEC_VOL_MONO(xname, nid, 3, dir)
3468 #define CA0132_ALT_CODEC_VOL(xname, nid, dir) \
3469 CA0132_ALT_CODEC_VOL_MONO(xname, nid, 3, dir)
3470 #define CA0132_CODEC_MUTE(xname, nid, dir) \
3471 CA0132_CODEC_MUTE_MONO(xname, nid, 3, dir)
3472
3473 /* lookup tables */
3474 /*
3475 * Lookup table with decibel values for the DSP. When volume is changed in
3476 * Windows, the DSP is also sent the dB value in floating point. In Windows,
3477 * these values have decimal points, probably because the Windows driver
3478 * actually uses floating point. We can't here, so I made a lookup table of
3479 * values -90 to 9. -90 is the lowest decibel value for both the ADC's and the
3480 * DAC's, and 9 is the maximum.
3481 */
3482 static const unsigned int float_vol_db_lookup[] = {
3483 0xC2B40000, 0xC2B20000, 0xC2B00000, 0xC2AE0000, 0xC2AC0000, 0xC2AA0000,
3484 0xC2A80000, 0xC2A60000, 0xC2A40000, 0xC2A20000, 0xC2A00000, 0xC29E0000,
3485 0xC29C0000, 0xC29A0000, 0xC2980000, 0xC2960000, 0xC2940000, 0xC2920000,
3486 0xC2900000, 0xC28E0000, 0xC28C0000, 0xC28A0000, 0xC2880000, 0xC2860000,
3487 0xC2840000, 0xC2820000, 0xC2800000, 0xC27C0000, 0xC2780000, 0xC2740000,
3488 0xC2700000, 0xC26C0000, 0xC2680000, 0xC2640000, 0xC2600000, 0xC25C0000,
3489 0xC2580000, 0xC2540000, 0xC2500000, 0xC24C0000, 0xC2480000, 0xC2440000,
3490 0xC2400000, 0xC23C0000, 0xC2380000, 0xC2340000, 0xC2300000, 0xC22C0000,
3491 0xC2280000, 0xC2240000, 0xC2200000, 0xC21C0000, 0xC2180000, 0xC2140000,
3492 0xC2100000, 0xC20C0000, 0xC2080000, 0xC2040000, 0xC2000000, 0xC1F80000,
3493 0xC1F00000, 0xC1E80000, 0xC1E00000, 0xC1D80000, 0xC1D00000, 0xC1C80000,
3494 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3495 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3496 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3497 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3498 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3499 0x40C00000, 0x40E00000, 0x41000000, 0x41100000
3500 };
3501
3502 /*
3503 * This table counts from float 0 to 1 in increments of .01, which is
3504 * useful for a few different sliders.
3505 */
3506 static const unsigned int float_zero_to_one_lookup[] = {
3507 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3508 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3509 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3510 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3511 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3512 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3513 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3514 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3515 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3516 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3517 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3518 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3519 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3520 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3521 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3522 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3523 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3524 };
3525
3526 /*
3527 * This table counts from float 10 to 1000, which is the range of the x-bass
3528 * crossover slider in Windows.
3529 */
3530 static const unsigned int float_xbass_xover_lookup[] = {
3531 0x41200000, 0x41A00000, 0x41F00000, 0x42200000, 0x42480000, 0x42700000,
3532 0x428C0000, 0x42A00000, 0x42B40000, 0x42C80000, 0x42DC0000, 0x42F00000,
3533 0x43020000, 0x430C0000, 0x43160000, 0x43200000, 0x432A0000, 0x43340000,
3534 0x433E0000, 0x43480000, 0x43520000, 0x435C0000, 0x43660000, 0x43700000,
3535 0x437A0000, 0x43820000, 0x43870000, 0x438C0000, 0x43910000, 0x43960000,
3536 0x439B0000, 0x43A00000, 0x43A50000, 0x43AA0000, 0x43AF0000, 0x43B40000,
3537 0x43B90000, 0x43BE0000, 0x43C30000, 0x43C80000, 0x43CD0000, 0x43D20000,
3538 0x43D70000, 0x43DC0000, 0x43E10000, 0x43E60000, 0x43EB0000, 0x43F00000,
3539 0x43F50000, 0x43FA0000, 0x43FF0000, 0x44020000, 0x44048000, 0x44070000,
3540 0x44098000, 0x440C0000, 0x440E8000, 0x44110000, 0x44138000, 0x44160000,
3541 0x44188000, 0x441B0000, 0x441D8000, 0x44200000, 0x44228000, 0x44250000,
3542 0x44278000, 0x442A0000, 0x442C8000, 0x442F0000, 0x44318000, 0x44340000,
3543 0x44368000, 0x44390000, 0x443B8000, 0x443E0000, 0x44408000, 0x44430000,
3544 0x44458000, 0x44480000, 0x444A8000, 0x444D0000, 0x444F8000, 0x44520000,
3545 0x44548000, 0x44570000, 0x44598000, 0x445C0000, 0x445E8000, 0x44610000,
3546 0x44638000, 0x44660000, 0x44688000, 0x446B0000, 0x446D8000, 0x44700000,
3547 0x44728000, 0x44750000, 0x44778000, 0x447A0000
3548 };
3549
3550 /* The following are for tuning of products */
3551 #ifdef ENABLE_TUNING_CONTROLS
3552
3553 static unsigned int voice_focus_vals_lookup[] = {
3554 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000, 0x41C00000, 0x41C80000,
3555 0x41D00000, 0x41D80000, 0x41E00000, 0x41E80000, 0x41F00000, 0x41F80000,
3556 0x42000000, 0x42040000, 0x42080000, 0x420C0000, 0x42100000, 0x42140000,
3557 0x42180000, 0x421C0000, 0x42200000, 0x42240000, 0x42280000, 0x422C0000,
3558 0x42300000, 0x42340000, 0x42380000, 0x423C0000, 0x42400000, 0x42440000,
3559 0x42480000, 0x424C0000, 0x42500000, 0x42540000, 0x42580000, 0x425C0000,
3560 0x42600000, 0x42640000, 0x42680000, 0x426C0000, 0x42700000, 0x42740000,
3561 0x42780000, 0x427C0000, 0x42800000, 0x42820000, 0x42840000, 0x42860000,
3562 0x42880000, 0x428A0000, 0x428C0000, 0x428E0000, 0x42900000, 0x42920000,
3563 0x42940000, 0x42960000, 0x42980000, 0x429A0000, 0x429C0000, 0x429E0000,
3564 0x42A00000, 0x42A20000, 0x42A40000, 0x42A60000, 0x42A80000, 0x42AA0000,
3565 0x42AC0000, 0x42AE0000, 0x42B00000, 0x42B20000, 0x42B40000, 0x42B60000,
3566 0x42B80000, 0x42BA0000, 0x42BC0000, 0x42BE0000, 0x42C00000, 0x42C20000,
3567 0x42C40000, 0x42C60000, 0x42C80000, 0x42CA0000, 0x42CC0000, 0x42CE0000,
3568 0x42D00000, 0x42D20000, 0x42D40000, 0x42D60000, 0x42D80000, 0x42DA0000,
3569 0x42DC0000, 0x42DE0000, 0x42E00000, 0x42E20000, 0x42E40000, 0x42E60000,
3570 0x42E80000, 0x42EA0000, 0x42EC0000, 0x42EE0000, 0x42F00000, 0x42F20000,
3571 0x42F40000, 0x42F60000, 0x42F80000, 0x42FA0000, 0x42FC0000, 0x42FE0000,
3572 0x43000000, 0x43010000, 0x43020000, 0x43030000, 0x43040000, 0x43050000,
3573 0x43060000, 0x43070000, 0x43080000, 0x43090000, 0x430A0000, 0x430B0000,
3574 0x430C0000, 0x430D0000, 0x430E0000, 0x430F0000, 0x43100000, 0x43110000,
3575 0x43120000, 0x43130000, 0x43140000, 0x43150000, 0x43160000, 0x43170000,
3576 0x43180000, 0x43190000, 0x431A0000, 0x431B0000, 0x431C0000, 0x431D0000,
3577 0x431E0000, 0x431F0000, 0x43200000, 0x43210000, 0x43220000, 0x43230000,
3578 0x43240000, 0x43250000, 0x43260000, 0x43270000, 0x43280000, 0x43290000,
3579 0x432A0000, 0x432B0000, 0x432C0000, 0x432D0000, 0x432E0000, 0x432F0000,
3580 0x43300000, 0x43310000, 0x43320000, 0x43330000, 0x43340000
3581 };
3582
3583 static unsigned int mic_svm_vals_lookup[] = {
3584 0x00000000, 0x3C23D70A, 0x3CA3D70A, 0x3CF5C28F, 0x3D23D70A, 0x3D4CCCCD,
3585 0x3D75C28F, 0x3D8F5C29, 0x3DA3D70A, 0x3DB851EC, 0x3DCCCCCD, 0x3DE147AE,
3586 0x3DF5C28F, 0x3E051EB8, 0x3E0F5C29, 0x3E19999A, 0x3E23D70A, 0x3E2E147B,
3587 0x3E3851EC, 0x3E428F5C, 0x3E4CCCCD, 0x3E570A3D, 0x3E6147AE, 0x3E6B851F,
3588 0x3E75C28F, 0x3E800000, 0x3E851EB8, 0x3E8A3D71, 0x3E8F5C29, 0x3E947AE1,
3589 0x3E99999A, 0x3E9EB852, 0x3EA3D70A, 0x3EA8F5C3, 0x3EAE147B, 0x3EB33333,
3590 0x3EB851EC, 0x3EBD70A4, 0x3EC28F5C, 0x3EC7AE14, 0x3ECCCCCD, 0x3ED1EB85,
3591 0x3ED70A3D, 0x3EDC28F6, 0x3EE147AE, 0x3EE66666, 0x3EEB851F, 0x3EF0A3D7,
3592 0x3EF5C28F, 0x3EFAE148, 0x3F000000, 0x3F028F5C, 0x3F051EB8, 0x3F07AE14,
3593 0x3F0A3D71, 0x3F0CCCCD, 0x3F0F5C29, 0x3F11EB85, 0x3F147AE1, 0x3F170A3D,
3594 0x3F19999A, 0x3F1C28F6, 0x3F1EB852, 0x3F2147AE, 0x3F23D70A, 0x3F266666,
3595 0x3F28F5C3, 0x3F2B851F, 0x3F2E147B, 0x3F30A3D7, 0x3F333333, 0x3F35C28F,
3596 0x3F3851EC, 0x3F3AE148, 0x3F3D70A4, 0x3F400000, 0x3F428F5C, 0x3F451EB8,
3597 0x3F47AE14, 0x3F4A3D71, 0x3F4CCCCD, 0x3F4F5C29, 0x3F51EB85, 0x3F547AE1,
3598 0x3F570A3D, 0x3F59999A, 0x3F5C28F6, 0x3F5EB852, 0x3F6147AE, 0x3F63D70A,
3599 0x3F666666, 0x3F68F5C3, 0x3F6B851F, 0x3F6E147B, 0x3F70A3D7, 0x3F733333,
3600 0x3F75C28F, 0x3F7851EC, 0x3F7AE148, 0x3F7D70A4, 0x3F800000
3601 };
3602
3603 static unsigned int equalizer_vals_lookup[] = {
3604 0xC1C00000, 0xC1B80000, 0xC1B00000, 0xC1A80000, 0xC1A00000, 0xC1980000,
3605 0xC1900000, 0xC1880000, 0xC1800000, 0xC1700000, 0xC1600000, 0xC1500000,
3606 0xC1400000, 0xC1300000, 0xC1200000, 0xC1100000, 0xC1000000, 0xC0E00000,
3607 0xC0C00000, 0xC0A00000, 0xC0800000, 0xC0400000, 0xC0000000, 0xBF800000,
3608 0x00000000, 0x3F800000, 0x40000000, 0x40400000, 0x40800000, 0x40A00000,
3609 0x40C00000, 0x40E00000, 0x41000000, 0x41100000, 0x41200000, 0x41300000,
3610 0x41400000, 0x41500000, 0x41600000, 0x41700000, 0x41800000, 0x41880000,
3611 0x41900000, 0x41980000, 0x41A00000, 0x41A80000, 0x41B00000, 0x41B80000,
3612 0x41C00000
3613 };
3614
3615 static int tuning_ctl_set(struct hda_codec *codec, hda_nid_t nid,
3616 unsigned int *lookup, int idx)
3617 {
3618 int i = 0;
3619
3620 for (i = 0; i < TUNING_CTLS_COUNT; i++)
3621 if (nid == ca0132_tuning_ctls[i].nid)
3622 break;
3623
3624 snd_hda_power_up(codec);
3625 dspio_set_param(codec, ca0132_tuning_ctls[i].mid, 0x20,
3626 ca0132_tuning_ctls[i].req,
3627 &(lookup[idx]), sizeof(unsigned int));
3628 snd_hda_power_down(codec);
3629
3630 return 1;
3631 }
3632
3633 static int tuning_ctl_get(struct snd_kcontrol *kcontrol,
3634 struct snd_ctl_elem_value *ucontrol)
3635 {
3636 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3637 struct ca0132_spec *spec = codec->spec;
3638 hda_nid_t nid = get_amp_nid(kcontrol);
3639 long *valp = ucontrol->value.integer.value;
3640 int idx = nid - TUNING_CTL_START_NID;
3641
3642 *valp = spec->cur_ctl_vals[idx];
3643 return 0;
3644 }
3645
3646 static int voice_focus_ctl_info(struct snd_kcontrol *kcontrol,
3647 struct snd_ctl_elem_info *uinfo)
3648 {
3649 int chs = get_amp_channels(kcontrol);
3650 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3651 uinfo->count = chs == 3 ? 2 : 1;
3652 uinfo->value.integer.min = 20;
3653 uinfo->value.integer.max = 180;
3654 uinfo->value.integer.step = 1;
3655
3656 return 0;
3657 }
3658
3659 static int voice_focus_ctl_put(struct snd_kcontrol *kcontrol,
3660 struct snd_ctl_elem_value *ucontrol)
3661 {
3662 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3663 struct ca0132_spec *spec = codec->spec;
3664 hda_nid_t nid = get_amp_nid(kcontrol);
3665 long *valp = ucontrol->value.integer.value;
3666 int idx;
3667
3668 idx = nid - TUNING_CTL_START_NID;
3669 /* any change? */
3670 if (spec->cur_ctl_vals[idx] == *valp)
3671 return 0;
3672
3673 spec->cur_ctl_vals[idx] = *valp;
3674
3675 idx = *valp - 20;
3676 tuning_ctl_set(codec, nid, voice_focus_vals_lookup, idx);
3677
3678 return 1;
3679 }
3680
3681 static int mic_svm_ctl_info(struct snd_kcontrol *kcontrol,
3682 struct snd_ctl_elem_info *uinfo)
3683 {
3684 int chs = get_amp_channels(kcontrol);
3685 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3686 uinfo->count = chs == 3 ? 2 : 1;
3687 uinfo->value.integer.min = 0;
3688 uinfo->value.integer.max = 100;
3689 uinfo->value.integer.step = 1;
3690
3691 return 0;
3692 }
3693
3694 static int mic_svm_ctl_put(struct snd_kcontrol *kcontrol,
3695 struct snd_ctl_elem_value *ucontrol)
3696 {
3697 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3698 struct ca0132_spec *spec = codec->spec;
3699 hda_nid_t nid = get_amp_nid(kcontrol);
3700 long *valp = ucontrol->value.integer.value;
3701 int idx;
3702
3703 idx = nid - TUNING_CTL_START_NID;
3704 /* any change? */
3705 if (spec->cur_ctl_vals[idx] == *valp)
3706 return 0;
3707
3708 spec->cur_ctl_vals[idx] = *valp;
3709
3710 idx = *valp;
3711 tuning_ctl_set(codec, nid, mic_svm_vals_lookup, idx);
3712
3713 return 0;
3714 }
3715
3716 static int equalizer_ctl_info(struct snd_kcontrol *kcontrol,
3717 struct snd_ctl_elem_info *uinfo)
3718 {
3719 int chs = get_amp_channels(kcontrol);
3720 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3721 uinfo->count = chs == 3 ? 2 : 1;
3722 uinfo->value.integer.min = 0;
3723 uinfo->value.integer.max = 48;
3724 uinfo->value.integer.step = 1;
3725
3726 return 0;
3727 }
3728
3729 static int equalizer_ctl_put(struct snd_kcontrol *kcontrol,
3730 struct snd_ctl_elem_value *ucontrol)
3731 {
3732 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
3733 struct ca0132_spec *spec = codec->spec;
3734 hda_nid_t nid = get_amp_nid(kcontrol);
3735 long *valp = ucontrol->value.integer.value;
3736 int idx;
3737
3738 idx = nid - TUNING_CTL_START_NID;
3739 /* any change? */
3740 if (spec->cur_ctl_vals[idx] == *valp)
3741 return 0;
3742
3743 spec->cur_ctl_vals[idx] = *valp;
3744
3745 idx = *valp;
3746 tuning_ctl_set(codec, nid, equalizer_vals_lookup, idx);
3747
3748 return 1;
3749 }
3750
3751 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(voice_focus_db_scale, 2000, 100, 0);
3752 static const SNDRV_CTL_TLVD_DECLARE_DB_SCALE(eq_db_scale, -2400, 100, 0);
3753
3754 static int add_tuning_control(struct hda_codec *codec,
3755 hda_nid_t pnid, hda_nid_t nid,
3756 const char *name, int dir)
3757 {
3758 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
3759 int type = dir ? HDA_INPUT : HDA_OUTPUT;
3760 struct snd_kcontrol_new knew =
3761 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
3762
3763 knew.access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
3764 SNDRV_CTL_ELEM_ACCESS_TLV_READ;
3765 knew.tlv.c = 0;
3766 knew.tlv.p = 0;
3767 switch (pnid) {
3768 case VOICE_FOCUS:
3769 knew.info = voice_focus_ctl_info;
3770 knew.get = tuning_ctl_get;
3771 knew.put = voice_focus_ctl_put;
3772 knew.tlv.p = voice_focus_db_scale;
3773 break;
3774 case MIC_SVM:
3775 knew.info = mic_svm_ctl_info;
3776 knew.get = tuning_ctl_get;
3777 knew.put = mic_svm_ctl_put;
3778 break;
3779 case EQUALIZER:
3780 knew.info = equalizer_ctl_info;
3781 knew.get = tuning_ctl_get;
3782 knew.put = equalizer_ctl_put;
3783 knew.tlv.p = eq_db_scale;
3784 break;
3785 default:
3786 return 0;
3787 }
3788 knew.private_value =
3789 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
3790 sprintf(namestr, "%s %s Volume", name, dirstr[dir]);
3791 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
3792 }
3793
3794 static int add_tuning_ctls(struct hda_codec *codec)
3795 {
3796 int i;
3797 int err;
3798
3799 for (i = 0; i < TUNING_CTLS_COUNT; i++) {
3800 err = add_tuning_control(codec,
3801 ca0132_tuning_ctls[i].parent_nid,
3802 ca0132_tuning_ctls[i].nid,
3803 ca0132_tuning_ctls[i].name,
3804 ca0132_tuning_ctls[i].direct);
3805 if (err < 0)
3806 return err;
3807 }
3808
3809 return 0;
3810 }
3811
3812 static void ca0132_init_tuning_defaults(struct hda_codec *codec)
3813 {
3814 struct ca0132_spec *spec = codec->spec;
3815 int i;
3816
3817 /* Wedge Angle defaults to 30. 10 below is 30 - 20. 20 is min. */
3818 spec->cur_ctl_vals[WEDGE_ANGLE - TUNING_CTL_START_NID] = 10;
3819 /* SVM level defaults to 0.74. */
3820 spec->cur_ctl_vals[SVM_LEVEL - TUNING_CTL_START_NID] = 74;
3821
3822 /* EQ defaults to 0dB. */
3823 for (i = 2; i < TUNING_CTLS_COUNT; i++)
3824 spec->cur_ctl_vals[i] = 24;
3825 }
3826 #endif /*ENABLE_TUNING_CONTROLS*/
3827
3828 /*
3829 * Select the active output.
3830 * If autodetect is enabled, output will be selected based on jack detection.
3831 * If jack inserted, headphone will be selected, else built-in speakers
3832 * If autodetect is disabled, output will be selected based on selection.
3833 */
3834 static int ca0132_select_out(struct hda_codec *codec)
3835 {
3836 struct ca0132_spec *spec = codec->spec;
3837 unsigned int pin_ctl;
3838 int jack_present;
3839 int auto_jack;
3840 unsigned int tmp;
3841 int err;
3842
3843 codec_dbg(codec, "ca0132_select_out\n");
3844
3845 snd_hda_power_up_pm(codec);
3846
3847 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3848
3849 if (auto_jack)
3850 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp);
3851 else
3852 jack_present =
3853 spec->vnode_lswitch[VNID_HP_SEL - VNODE_START_NID];
3854
3855 if (jack_present)
3856 spec->cur_out_type = HEADPHONE_OUT;
3857 else
3858 spec->cur_out_type = SPEAKER_OUT;
3859
3860 if (spec->cur_out_type == SPEAKER_OUT) {
3861 codec_dbg(codec, "ca0132_select_out speaker\n");
3862 /*speaker out config*/
3863 tmp = FLOAT_ONE;
3864 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3865 if (err < 0)
3866 goto exit;
3867 /*enable speaker EQ*/
3868 tmp = FLOAT_ONE;
3869 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3870 if (err < 0)
3871 goto exit;
3872
3873 /* Setup EAPD */
3874 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3875 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3876 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3877 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3878 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3879 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3880 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3881 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3882
3883 /* disable headphone node */
3884 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3885 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3886 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3887 pin_ctl & ~PIN_HP);
3888 /* enable speaker node */
3889 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3890 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3891 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3892 pin_ctl | PIN_OUT);
3893 } else {
3894 codec_dbg(codec, "ca0132_select_out hp\n");
3895 /*headphone out config*/
3896 tmp = FLOAT_ZERO;
3897 err = dspio_set_uint_param(codec, 0x80, 0x04, tmp);
3898 if (err < 0)
3899 goto exit;
3900 /*disable speaker EQ*/
3901 tmp = FLOAT_ZERO;
3902 err = dspio_set_uint_param(codec, 0x8f, 0x00, tmp);
3903 if (err < 0)
3904 goto exit;
3905
3906 /* Setup EAPD */
3907 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3908 VENDOR_CHIPIO_EAPD_SEL_SET, 0x00);
3909 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3910 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
3911 snd_hda_codec_write(codec, spec->out_pins[1], 0,
3912 VENDOR_CHIPIO_EAPD_SEL_SET, 0x02);
3913 snd_hda_codec_write(codec, spec->out_pins[0], 0,
3914 AC_VERB_SET_EAPD_BTLENABLE, 0x02);
3915
3916 /* disable speaker*/
3917 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
3918 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3919 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
3920 pin_ctl & ~PIN_HP);
3921 /* enable headphone*/
3922 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
3923 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
3924 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
3925 pin_ctl | PIN_HP);
3926 }
3927
3928 exit:
3929 snd_hda_power_down_pm(codec);
3930
3931 return err < 0 ? err : 0;
3932 }
3933
3934 /*
3935 * This function behaves similarly to the ca0132_select_out funciton above,
3936 * except with a few differences. It adds the ability to select the current
3937 * output with an enumerated control "output source" if the auto detect
3938 * mute switch is set to off. If the auto detect mute switch is enabled, it
3939 * will detect either headphone or lineout(SPEAKER_OUT) from jack detection.
3940 * It also adds the ability to auto-detect the front headphone port. The only
3941 * way to select surround is to disable auto detect, and set Surround with the
3942 * enumerated control.
3943 */
3944 static int ca0132_alt_select_out(struct hda_codec *codec)
3945 {
3946 struct ca0132_spec *spec = codec->spec;
3947 unsigned int pin_ctl;
3948 int jack_present;
3949 int auto_jack;
3950 unsigned int i;
3951 unsigned int tmp;
3952 int err;
3953 /* Default Headphone is rear headphone */
3954 hda_nid_t headphone_nid = spec->out_pins[1];
3955
3956 codec_dbg(codec, "%s\n", __func__);
3957
3958 snd_hda_power_up_pm(codec);
3959
3960 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
3961
3962 /*
3963 * If headphone rear or front is plugged in, set to headphone.
3964 * If neither is plugged in, set to rear line out. Only if
3965 * hp/speaker auto detect is enabled.
3966 */
3967 if (auto_jack) {
3968 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_hp) ||
3969 snd_hda_jack_detect(codec, spec->unsol_tag_front_hp);
3970
3971 if (jack_present)
3972 spec->cur_out_type = HEADPHONE_OUT;
3973 else
3974 spec->cur_out_type = SPEAKER_OUT;
3975 } else
3976 spec->cur_out_type = spec->out_enum_val;
3977
3978 /* Begin DSP output switch */
3979 tmp = FLOAT_ONE;
3980 err = dspio_set_uint_param(codec, 0x96, 0x3A, tmp);
3981 if (err < 0)
3982 goto exit;
3983
3984 switch (spec->cur_out_type) {
3985 case SPEAKER_OUT:
3986 codec_dbg(codec, "%s speaker\n", __func__);
3987 /*speaker out config*/
3988 switch (spec->quirk) {
3989 case QUIRK_SBZ:
3990 ca0132_mmio_gpio_set(codec, 7, false);
3991 ca0132_mmio_gpio_set(codec, 4, true);
3992 ca0132_mmio_gpio_set(codec, 1, true);
3993 chipio_set_control_param(codec, 0x0D, 0x18);
3994 break;
3995 case QUIRK_R3DI:
3996 chipio_set_control_param(codec, 0x0D, 0x24);
3997 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
3998 break;
3999 case QUIRK_R3D:
4000 chipio_set_control_param(codec, 0x0D, 0x24);
4001 ca0132_mmio_gpio_set(codec, 1, true);
4002 break;
4003 }
4004
4005 /* disable headphone node */
4006 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4007 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4008 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4009 pin_ctl & ~PIN_HP);
4010 /* enable line-out node */
4011 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4012 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4013 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4014 pin_ctl | PIN_OUT);
4015 /* Enable EAPD */
4016 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4017 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4018
4019 /* If PlayEnhancement is enabled, set different source */
4020 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4021 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4022 else
4023 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4024 break;
4025 case HEADPHONE_OUT:
4026 codec_dbg(codec, "%s hp\n", __func__);
4027 /* Headphone out config*/
4028 switch (spec->quirk) {
4029 case QUIRK_SBZ:
4030 ca0132_mmio_gpio_set(codec, 7, true);
4031 ca0132_mmio_gpio_set(codec, 4, true);
4032 ca0132_mmio_gpio_set(codec, 1, false);
4033 chipio_set_control_param(codec, 0x0D, 0x12);
4034 break;
4035 case QUIRK_R3DI:
4036 chipio_set_control_param(codec, 0x0D, 0x21);
4037 r3di_gpio_out_set(codec, R3DI_HEADPHONE_OUT);
4038 break;
4039 case QUIRK_R3D:
4040 chipio_set_control_param(codec, 0x0D, 0x21);
4041 ca0132_mmio_gpio_set(codec, 0x1, false);
4042 break;
4043 }
4044
4045 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4046 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
4047
4048 /* disable speaker*/
4049 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4050 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4051 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4052 pin_ctl & ~PIN_HP);
4053
4054 /* enable headphone, either front or rear */
4055
4056 if (snd_hda_jack_detect(codec, spec->unsol_tag_front_hp))
4057 headphone_nid = spec->out_pins[2];
4058 else if (snd_hda_jack_detect(codec, spec->unsol_tag_hp))
4059 headphone_nid = spec->out_pins[1];
4060
4061 pin_ctl = snd_hda_codec_read(codec, headphone_nid, 0,
4062 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4063 snd_hda_set_pin_ctl(codec, headphone_nid,
4064 pin_ctl | PIN_HP);
4065
4066 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4067 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4068 else
4069 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ZERO);
4070 break;
4071 case SURROUND_OUT:
4072 codec_dbg(codec, "%s surround\n", __func__);
4073 /* Surround out config*/
4074 switch (spec->quirk) {
4075 case QUIRK_SBZ:
4076 ca0132_mmio_gpio_set(codec, 7, false);
4077 ca0132_mmio_gpio_set(codec, 4, true);
4078 ca0132_mmio_gpio_set(codec, 1, true);
4079 chipio_set_control_param(codec, 0x0D, 0x18);
4080 break;
4081 case QUIRK_R3DI:
4082 chipio_set_control_param(codec, 0x0D, 0x24);
4083 r3di_gpio_out_set(codec, R3DI_LINE_OUT);
4084 break;
4085 case QUIRK_R3D:
4086 ca0132_mmio_gpio_set(codec, 1, true);
4087 chipio_set_control_param(codec, 0x0D, 0x24);
4088 break;
4089 }
4090 /* enable line out node */
4091 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[0], 0,
4092 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4093 snd_hda_set_pin_ctl(codec, spec->out_pins[0],
4094 pin_ctl | PIN_OUT);
4095 /* Disable headphone out */
4096 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[1], 0,
4097 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4098 snd_hda_set_pin_ctl(codec, spec->out_pins[1],
4099 pin_ctl & ~PIN_HP);
4100 /* Enable EAPD on line out */
4101 snd_hda_codec_write(codec, spec->out_pins[0], 0,
4102 AC_VERB_SET_EAPD_BTLENABLE, 0x01);
4103 /* enable center/lfe out node */
4104 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[2], 0,
4105 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4106 snd_hda_set_pin_ctl(codec, spec->out_pins[2],
4107 pin_ctl | PIN_OUT);
4108 /* Now set rear surround node as out. */
4109 pin_ctl = snd_hda_codec_read(codec, spec->out_pins[3], 0,
4110 AC_VERB_GET_PIN_WIDGET_CONTROL, 0);
4111 snd_hda_set_pin_ctl(codec, spec->out_pins[3],
4112 pin_ctl | PIN_OUT);
4113
4114 if (spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4115 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_ONE);
4116 else
4117 dspio_set_uint_param(codec, 0x80, 0x04, FLOAT_EIGHT);
4118 break;
4119 }
4120
4121 /* run through the output dsp commands for line-out */
4122 for (i = 0; i < alt_out_presets[spec->cur_out_type].commands; i++) {
4123 err = dspio_set_uint_param(codec,
4124 alt_out_presets[spec->cur_out_type].mids[i],
4125 alt_out_presets[spec->cur_out_type].reqs[i],
4126 alt_out_presets[spec->cur_out_type].vals[i]);
4127
4128 if (err < 0)
4129 goto exit;
4130 }
4131
4132 exit:
4133 snd_hda_power_down_pm(codec);
4134
4135 return err < 0 ? err : 0;
4136 }
4137
4138 static void ca0132_unsol_hp_delayed(struct work_struct *work)
4139 {
4140 struct ca0132_spec *spec = container_of(
4141 to_delayed_work(work), struct ca0132_spec, unsol_hp_work);
4142 struct hda_jack_tbl *jack;
4143
4144 if (spec->use_alt_functions)
4145 ca0132_alt_select_out(spec->codec);
4146 else
4147 ca0132_select_out(spec->codec);
4148
4149 jack = snd_hda_jack_tbl_get(spec->codec, spec->unsol_tag_hp);
4150 if (jack) {
4151 jack->block_report = 0;
4152 snd_hda_jack_report_sync(spec->codec);
4153 }
4154 }
4155
4156 static void ca0132_set_dmic(struct hda_codec *codec, int enable);
4157 static int ca0132_mic_boost_set(struct hda_codec *codec, long val);
4158 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val);
4159 static void resume_mic1(struct hda_codec *codec, unsigned int oldval);
4160 static int stop_mic1(struct hda_codec *codec);
4161 static int ca0132_cvoice_switch_set(struct hda_codec *codec);
4162 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val);
4163
4164 /*
4165 * Select the active VIP source
4166 */
4167 static int ca0132_set_vipsource(struct hda_codec *codec, int val)
4168 {
4169 struct ca0132_spec *spec = codec->spec;
4170 unsigned int tmp;
4171
4172 if (spec->dsp_state != DSP_DOWNLOADED)
4173 return 0;
4174
4175 /* if CrystalVoice if off, vipsource should be 0 */
4176 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4177 (val == 0)) {
4178 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4179 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4180 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4181 if (spec->cur_mic_type == DIGITAL_MIC)
4182 tmp = FLOAT_TWO;
4183 else
4184 tmp = FLOAT_ONE;
4185 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4186 tmp = FLOAT_ZERO;
4187 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4188 } else {
4189 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4190 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4191 if (spec->cur_mic_type == DIGITAL_MIC)
4192 tmp = FLOAT_TWO;
4193 else
4194 tmp = FLOAT_ONE;
4195 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4196 tmp = FLOAT_ONE;
4197 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4198 msleep(20);
4199 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4200 }
4201
4202 return 1;
4203 }
4204
4205 static int ca0132_alt_set_vipsource(struct hda_codec *codec, int val)
4206 {
4207 struct ca0132_spec *spec = codec->spec;
4208 unsigned int tmp;
4209
4210 if (spec->dsp_state != DSP_DOWNLOADED)
4211 return 0;
4212
4213 codec_dbg(codec, "%s\n", __func__);
4214
4215 chipio_set_stream_control(codec, 0x03, 0);
4216 chipio_set_stream_control(codec, 0x04, 0);
4217
4218 /* if CrystalVoice is off, vipsource should be 0 */
4219 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ||
4220 (val == 0) || spec->in_enum_val == REAR_LINE_IN) {
4221 codec_dbg(codec, "%s: off.", __func__);
4222 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
4223
4224 tmp = FLOAT_ZERO;
4225 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4226
4227 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4228 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4229 if (spec->quirk == QUIRK_R3DI)
4230 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4231
4232
4233 if (spec->in_enum_val == REAR_LINE_IN)
4234 tmp = FLOAT_ZERO;
4235 else {
4236 if (spec->quirk == QUIRK_SBZ)
4237 tmp = FLOAT_THREE;
4238 else
4239 tmp = FLOAT_ONE;
4240 }
4241
4242 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4243
4244 } else {
4245 codec_dbg(codec, "%s: on.", __func__);
4246 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_16_000);
4247 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_16_000);
4248 if (spec->quirk == QUIRK_R3DI)
4249 chipio_set_conn_rate(codec, 0x0F, SR_16_000);
4250
4251 if (spec->effects_switch[VOICE_FOCUS - EFFECT_START_NID])
4252 tmp = FLOAT_TWO;
4253 else
4254 tmp = FLOAT_ONE;
4255 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4256
4257 tmp = FLOAT_ONE;
4258 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
4259
4260 msleep(20);
4261 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, val);
4262 }
4263
4264 chipio_set_stream_control(codec, 0x03, 1);
4265 chipio_set_stream_control(codec, 0x04, 1);
4266
4267 return 1;
4268 }
4269
4270 /*
4271 * Select the active microphone.
4272 * If autodetect is enabled, mic will be selected based on jack detection.
4273 * If jack inserted, ext.mic will be selected, else built-in mic
4274 * If autodetect is disabled, mic will be selected based on selection.
4275 */
4276 static int ca0132_select_mic(struct hda_codec *codec)
4277 {
4278 struct ca0132_spec *spec = codec->spec;
4279 int jack_present;
4280 int auto_jack;
4281
4282 codec_dbg(codec, "ca0132_select_mic\n");
4283
4284 snd_hda_power_up_pm(codec);
4285
4286 auto_jack = spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4287
4288 if (auto_jack)
4289 jack_present = snd_hda_jack_detect(codec, spec->unsol_tag_amic1);
4290 else
4291 jack_present =
4292 spec->vnode_lswitch[VNID_AMIC1_SEL - VNODE_START_NID];
4293
4294 if (jack_present)
4295 spec->cur_mic_type = LINE_MIC_IN;
4296 else
4297 spec->cur_mic_type = DIGITAL_MIC;
4298
4299 if (spec->cur_mic_type == DIGITAL_MIC) {
4300 /* enable digital Mic */
4301 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_32_000);
4302 ca0132_set_dmic(codec, 1);
4303 ca0132_mic_boost_set(codec, 0);
4304 /* set voice focus */
4305 ca0132_effects_set(codec, VOICE_FOCUS,
4306 spec->effects_switch
4307 [VOICE_FOCUS - EFFECT_START_NID]);
4308 } else {
4309 /* disable digital Mic */
4310 chipio_set_conn_rate(codec, MEM_CONNID_DMIC, SR_96_000);
4311 ca0132_set_dmic(codec, 0);
4312 ca0132_mic_boost_set(codec, spec->cur_mic_boost);
4313 /* disable voice focus */
4314 ca0132_effects_set(codec, VOICE_FOCUS, 0);
4315 }
4316
4317 snd_hda_power_down_pm(codec);
4318
4319 return 0;
4320 }
4321
4322 /*
4323 * Select the active input.
4324 * Mic detection isn't used, because it's kind of pointless on the SBZ.
4325 * The front mic has no jack-detection, so the only way to switch to it
4326 * is to do it manually in alsamixer.
4327 */
4328 static int ca0132_alt_select_in(struct hda_codec *codec)
4329 {
4330 struct ca0132_spec *spec = codec->spec;
4331 unsigned int tmp;
4332
4333 codec_dbg(codec, "%s\n", __func__);
4334
4335 snd_hda_power_up_pm(codec);
4336
4337 chipio_set_stream_control(codec, 0x03, 0);
4338 chipio_set_stream_control(codec, 0x04, 0);
4339
4340 spec->cur_mic_type = spec->in_enum_val;
4341
4342 switch (spec->cur_mic_type) {
4343 case REAR_MIC:
4344 switch (spec->quirk) {
4345 case QUIRK_SBZ:
4346 case QUIRK_R3D:
4347 ca0132_mmio_gpio_set(codec, 0, false);
4348 tmp = FLOAT_THREE;
4349 break;
4350 case QUIRK_R3DI:
4351 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4352 tmp = FLOAT_ONE;
4353 break;
4354 default:
4355 tmp = FLOAT_ONE;
4356 break;
4357 }
4358
4359 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4360 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4361 if (spec->quirk == QUIRK_R3DI)
4362 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4363
4364 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4365
4366 chipio_set_stream_control(codec, 0x03, 1);
4367 chipio_set_stream_control(codec, 0x04, 1);
4368
4369 if (spec->quirk == QUIRK_SBZ) {
4370 chipio_write(codec, 0x18B098, 0x0000000C);
4371 chipio_write(codec, 0x18B09C, 0x0000000C);
4372 }
4373 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4374 break;
4375 case REAR_LINE_IN:
4376 ca0132_mic_boost_set(codec, 0);
4377 switch (spec->quirk) {
4378 case QUIRK_SBZ:
4379 case QUIRK_R3D:
4380 ca0132_mmio_gpio_set(codec, 0, false);
4381 break;
4382 case QUIRK_R3DI:
4383 r3di_gpio_mic_set(codec, R3DI_REAR_MIC);
4384 break;
4385 }
4386
4387 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4388 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4389 if (spec->quirk == QUIRK_R3DI)
4390 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4391
4392 tmp = FLOAT_ZERO;
4393 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4394
4395 if (spec->quirk == QUIRK_SBZ) {
4396 chipio_write(codec, 0x18B098, 0x00000000);
4397 chipio_write(codec, 0x18B09C, 0x00000000);
4398 }
4399
4400 chipio_set_stream_control(codec, 0x03, 1);
4401 chipio_set_stream_control(codec, 0x04, 1);
4402 break;
4403 case FRONT_MIC:
4404 switch (spec->quirk) {
4405 case QUIRK_SBZ:
4406 case QUIRK_R3D:
4407 ca0132_mmio_gpio_set(codec, 0, true);
4408 ca0132_mmio_gpio_set(codec, 5, false);
4409 tmp = FLOAT_THREE;
4410 break;
4411 case QUIRK_R3DI:
4412 r3di_gpio_mic_set(codec, R3DI_FRONT_MIC);
4413 tmp = FLOAT_ONE;
4414 break;
4415 default:
4416 tmp = FLOAT_ONE;
4417 break;
4418 }
4419
4420 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
4421 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
4422 if (spec->quirk == QUIRK_R3DI)
4423 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
4424
4425 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4426
4427 chipio_set_stream_control(codec, 0x03, 1);
4428 chipio_set_stream_control(codec, 0x04, 1);
4429
4430 if (spec->quirk == QUIRK_SBZ) {
4431 chipio_write(codec, 0x18B098, 0x0000000C);
4432 chipio_write(codec, 0x18B09C, 0x000000CC);
4433 }
4434 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4435 break;
4436 }
4437 ca0132_cvoice_switch_set(codec);
4438
4439 snd_hda_power_down_pm(codec);
4440 return 0;
4441
4442 }
4443
4444 /*
4445 * Check if VNODE settings take effect immediately.
4446 */
4447 static bool ca0132_is_vnode_effective(struct hda_codec *codec,
4448 hda_nid_t vnid,
4449 hda_nid_t *shared_nid)
4450 {
4451 struct ca0132_spec *spec = codec->spec;
4452 hda_nid_t nid;
4453
4454 switch (vnid) {
4455 case VNID_SPK:
4456 nid = spec->shared_out_nid;
4457 break;
4458 case VNID_MIC:
4459 nid = spec->shared_mic_nid;
4460 break;
4461 default:
4462 return false;
4463 }
4464
4465 if (shared_nid)
4466 *shared_nid = nid;
4467
4468 return true;
4469 }
4470
4471 /*
4472 * The following functions are control change helpers.
4473 * They return 0 if no changed. Return 1 if changed.
4474 */
4475 static int ca0132_voicefx_set(struct hda_codec *codec, int enable)
4476 {
4477 struct ca0132_spec *spec = codec->spec;
4478 unsigned int tmp;
4479
4480 /* based on CrystalVoice state to enable VoiceFX. */
4481 if (enable) {
4482 tmp = spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] ?
4483 FLOAT_ONE : FLOAT_ZERO;
4484 } else {
4485 tmp = FLOAT_ZERO;
4486 }
4487
4488 dspio_set_uint_param(codec, ca0132_voicefx.mid,
4489 ca0132_voicefx.reqs[0], tmp);
4490
4491 return 1;
4492 }
4493
4494 /*
4495 * Set the effects parameters
4496 */
4497 static int ca0132_effects_set(struct hda_codec *codec, hda_nid_t nid, long val)
4498 {
4499 struct ca0132_spec *spec = codec->spec;
4500 unsigned int on, tmp;
4501 int num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
4502 int err = 0;
4503 int idx = nid - EFFECT_START_NID;
4504
4505 if ((idx < 0) || (idx >= num_fx))
4506 return 0; /* no changed */
4507
4508 /* for out effect, qualify with PE */
4509 if ((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) {
4510 /* if PE if off, turn off out effects. */
4511 if (!spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID])
4512 val = 0;
4513 }
4514
4515 /* for in effect, qualify with CrystalVoice */
4516 if ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID)) {
4517 /* if CrystalVoice if off, turn off in effects. */
4518 if (!spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID])
4519 val = 0;
4520
4521 /* Voice Focus applies to 2-ch Mic, Digital Mic */
4522 if ((nid == VOICE_FOCUS) && (spec->cur_mic_type != DIGITAL_MIC))
4523 val = 0;
4524
4525 /* If Voice Focus on SBZ, set to two channel. */
4526 if ((nid == VOICE_FOCUS) && (spec->use_pci_mmio)
4527 && (spec->cur_mic_type != REAR_LINE_IN)) {
4528 if (spec->effects_switch[CRYSTAL_VOICE -
4529 EFFECT_START_NID]) {
4530
4531 if (spec->effects_switch[VOICE_FOCUS -
4532 EFFECT_START_NID]) {
4533 tmp = FLOAT_TWO;
4534 val = 1;
4535 } else
4536 tmp = FLOAT_ONE;
4537
4538 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
4539 }
4540 }
4541 /*
4542 * For SBZ noise reduction, there's an extra command
4543 * to module ID 0x47. No clue why.
4544 */
4545 if ((nid == NOISE_REDUCTION) && (spec->use_pci_mmio)
4546 && (spec->cur_mic_type != REAR_LINE_IN)) {
4547 if (spec->effects_switch[CRYSTAL_VOICE -
4548 EFFECT_START_NID]) {
4549 if (spec->effects_switch[NOISE_REDUCTION -
4550 EFFECT_START_NID])
4551 tmp = FLOAT_ONE;
4552 else
4553 tmp = FLOAT_ZERO;
4554 } else
4555 tmp = FLOAT_ZERO;
4556
4557 dspio_set_uint_param(codec, 0x47, 0x00, tmp);
4558 }
4559
4560 /* If rear line in disable effects. */
4561 if (spec->use_alt_functions &&
4562 spec->in_enum_val == REAR_LINE_IN)
4563 val = 0;
4564 }
4565
4566 codec_dbg(codec, "ca0132_effect_set: nid=0x%x, val=%ld\n",
4567 nid, val);
4568
4569 on = (val == 0) ? FLOAT_ZERO : FLOAT_ONE;
4570 err = dspio_set_uint_param(codec, ca0132_effects[idx].mid,
4571 ca0132_effects[idx].reqs[0], on);
4572
4573 if (err < 0)
4574 return 0; /* no changed */
4575
4576 return 1;
4577 }
4578
4579 /*
4580 * Turn on/off Playback Enhancements
4581 */
4582 static int ca0132_pe_switch_set(struct hda_codec *codec)
4583 {
4584 struct ca0132_spec *spec = codec->spec;
4585 hda_nid_t nid;
4586 int i, ret = 0;
4587
4588 codec_dbg(codec, "ca0132_pe_switch_set: val=%ld\n",
4589 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID]);
4590
4591 if (spec->use_alt_functions)
4592 ca0132_alt_select_out(codec);
4593
4594 i = OUT_EFFECT_START_NID - EFFECT_START_NID;
4595 nid = OUT_EFFECT_START_NID;
4596 /* PE affects all out effects */
4597 for (; nid < OUT_EFFECT_END_NID; nid++, i++)
4598 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4599
4600 return ret;
4601 }
4602
4603 /* Check if Mic1 is streaming, if so, stop streaming */
4604 static int stop_mic1(struct hda_codec *codec)
4605 {
4606 struct ca0132_spec *spec = codec->spec;
4607 unsigned int oldval = snd_hda_codec_read(codec, spec->adcs[0], 0,
4608 AC_VERB_GET_CONV, 0);
4609 if (oldval != 0)
4610 snd_hda_codec_write(codec, spec->adcs[0], 0,
4611 AC_VERB_SET_CHANNEL_STREAMID,
4612 0);
4613 return oldval;
4614 }
4615
4616 /* Resume Mic1 streaming if it was stopped. */
4617 static void resume_mic1(struct hda_codec *codec, unsigned int oldval)
4618 {
4619 struct ca0132_spec *spec = codec->spec;
4620 /* Restore the previous stream and channel */
4621 if (oldval != 0)
4622 snd_hda_codec_write(codec, spec->adcs[0], 0,
4623 AC_VERB_SET_CHANNEL_STREAMID,
4624 oldval);
4625 }
4626
4627 /*
4628 * Turn on/off CrystalVoice
4629 */
4630 static int ca0132_cvoice_switch_set(struct hda_codec *codec)
4631 {
4632 struct ca0132_spec *spec = codec->spec;
4633 hda_nid_t nid;
4634 int i, ret = 0;
4635 unsigned int oldval;
4636
4637 codec_dbg(codec, "ca0132_cvoice_switch_set: val=%ld\n",
4638 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID]);
4639
4640 i = IN_EFFECT_START_NID - EFFECT_START_NID;
4641 nid = IN_EFFECT_START_NID;
4642 /* CrystalVoice affects all in effects */
4643 for (; nid < IN_EFFECT_END_NID; nid++, i++)
4644 ret |= ca0132_effects_set(codec, nid, spec->effects_switch[i]);
4645
4646 /* including VoiceFX */
4647 ret |= ca0132_voicefx_set(codec, (spec->voicefx_val ? 1 : 0));
4648
4649 /* set correct vipsource */
4650 oldval = stop_mic1(codec);
4651 if (spec->use_alt_functions)
4652 ret |= ca0132_alt_set_vipsource(codec, 1);
4653 else
4654 ret |= ca0132_set_vipsource(codec, 1);
4655 resume_mic1(codec, oldval);
4656 return ret;
4657 }
4658
4659 static int ca0132_mic_boost_set(struct hda_codec *codec, long val)
4660 {
4661 struct ca0132_spec *spec = codec->spec;
4662 int ret = 0;
4663
4664 if (val) /* on */
4665 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4666 HDA_INPUT, 0, HDA_AMP_VOLMASK, 3);
4667 else /* off */
4668 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4669 HDA_INPUT, 0, HDA_AMP_VOLMASK, 0);
4670
4671 return ret;
4672 }
4673
4674 static int ca0132_alt_mic_boost_set(struct hda_codec *codec, long val)
4675 {
4676 struct ca0132_spec *spec = codec->spec;
4677 int ret = 0;
4678
4679 ret = snd_hda_codec_amp_update(codec, spec->input_pins[0], 0,
4680 HDA_INPUT, 0, HDA_AMP_VOLMASK, val);
4681 return ret;
4682 }
4683
4684 static int ca0132_vnode_switch_set(struct snd_kcontrol *kcontrol,
4685 struct snd_ctl_elem_value *ucontrol)
4686 {
4687 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4688 hda_nid_t nid = get_amp_nid(kcontrol);
4689 hda_nid_t shared_nid = 0;
4690 bool effective;
4691 int ret = 0;
4692 struct ca0132_spec *spec = codec->spec;
4693 int auto_jack;
4694
4695 if (nid == VNID_HP_SEL) {
4696 auto_jack =
4697 spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
4698 if (!auto_jack) {
4699 if (spec->use_alt_functions)
4700 ca0132_alt_select_out(codec);
4701 else
4702 ca0132_select_out(codec);
4703 }
4704 return 1;
4705 }
4706
4707 if (nid == VNID_AMIC1_SEL) {
4708 auto_jack =
4709 spec->vnode_lswitch[VNID_AMIC1_ASEL - VNODE_START_NID];
4710 if (!auto_jack)
4711 ca0132_select_mic(codec);
4712 return 1;
4713 }
4714
4715 if (nid == VNID_HP_ASEL) {
4716 if (spec->use_alt_functions)
4717 ca0132_alt_select_out(codec);
4718 else
4719 ca0132_select_out(codec);
4720 return 1;
4721 }
4722
4723 if (nid == VNID_AMIC1_ASEL) {
4724 ca0132_select_mic(codec);
4725 return 1;
4726 }
4727
4728 /* if effective conditions, then update hw immediately. */
4729 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
4730 if (effective) {
4731 int dir = get_amp_direction(kcontrol);
4732 int ch = get_amp_channels(kcontrol);
4733 unsigned long pval;
4734
4735 mutex_lock(&codec->control_mutex);
4736 pval = kcontrol->private_value;
4737 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
4738 0, dir);
4739 ret = snd_hda_mixer_amp_switch_put(kcontrol, ucontrol);
4740 kcontrol->private_value = pval;
4741 mutex_unlock(&codec->control_mutex);
4742 }
4743
4744 return ret;
4745 }
4746 /* End of control change helpers. */
4747 /*
4748 * Below I've added controls to mess with the effect levels, I've only enabled
4749 * them on the Sound Blaster Z, but they would probably also work on the
4750 * Chromebook. I figured they were probably tuned specifically for it, and left
4751 * out for a reason.
4752 */
4753
4754 /* Sets DSP effect level from the sliders above the controls */
4755 static int ca0132_alt_slider_ctl_set(struct hda_codec *codec, hda_nid_t nid,
4756 const unsigned int *lookup, int idx)
4757 {
4758 int i = 0;
4759 unsigned int y;
4760 /*
4761 * For X_BASS, req 2 is actually crossover freq instead of
4762 * effect level
4763 */
4764 if (nid == X_BASS)
4765 y = 2;
4766 else
4767 y = 1;
4768
4769 snd_hda_power_up(codec);
4770 if (nid == XBASS_XOVER) {
4771 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4772 if (ca0132_effects[i].nid == X_BASS)
4773 break;
4774
4775 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4776 ca0132_effects[i].reqs[1],
4777 &(lookup[idx - 1]), sizeof(unsigned int));
4778 } else {
4779 /* Find the actual effect structure */
4780 for (i = 0; i < OUT_EFFECTS_COUNT; i++)
4781 if (nid == ca0132_effects[i].nid)
4782 break;
4783
4784 dspio_set_param(codec, ca0132_effects[i].mid, 0x20,
4785 ca0132_effects[i].reqs[y],
4786 &(lookup[idx]), sizeof(unsigned int));
4787 }
4788
4789 snd_hda_power_down(codec);
4790
4791 return 0;
4792 }
4793
4794 static int ca0132_alt_xbass_xover_slider_ctl_get(struct snd_kcontrol *kcontrol,
4795 struct snd_ctl_elem_value *ucontrol)
4796 {
4797 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4798 struct ca0132_spec *spec = codec->spec;
4799 long *valp = ucontrol->value.integer.value;
4800
4801 *valp = spec->xbass_xover_freq;
4802 return 0;
4803 }
4804
4805 static int ca0132_alt_slider_ctl_get(struct snd_kcontrol *kcontrol,
4806 struct snd_ctl_elem_value *ucontrol)
4807 {
4808 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4809 struct ca0132_spec *spec = codec->spec;
4810 hda_nid_t nid = get_amp_nid(kcontrol);
4811 long *valp = ucontrol->value.integer.value;
4812 int idx = nid - OUT_EFFECT_START_NID;
4813
4814 *valp = spec->fx_ctl_val[idx];
4815 return 0;
4816 }
4817
4818 /*
4819 * The X-bass crossover starts at 10hz, so the min is 1. The
4820 * frequency is set in multiples of 10.
4821 */
4822 static int ca0132_alt_xbass_xover_slider_info(struct snd_kcontrol *kcontrol,
4823 struct snd_ctl_elem_info *uinfo)
4824 {
4825 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4826 uinfo->count = 1;
4827 uinfo->value.integer.min = 1;
4828 uinfo->value.integer.max = 100;
4829 uinfo->value.integer.step = 1;
4830
4831 return 0;
4832 }
4833
4834 static int ca0132_alt_effect_slider_info(struct snd_kcontrol *kcontrol,
4835 struct snd_ctl_elem_info *uinfo)
4836 {
4837 int chs = get_amp_channels(kcontrol);
4838
4839 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
4840 uinfo->count = chs == 3 ? 2 : 1;
4841 uinfo->value.integer.min = 0;
4842 uinfo->value.integer.max = 100;
4843 uinfo->value.integer.step = 1;
4844
4845 return 0;
4846 }
4847
4848 static int ca0132_alt_xbass_xover_slider_put(struct snd_kcontrol *kcontrol,
4849 struct snd_ctl_elem_value *ucontrol)
4850 {
4851 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4852 struct ca0132_spec *spec = codec->spec;
4853 hda_nid_t nid = get_amp_nid(kcontrol);
4854 long *valp = ucontrol->value.integer.value;
4855 int idx;
4856
4857 /* any change? */
4858 if (spec->xbass_xover_freq == *valp)
4859 return 0;
4860
4861 spec->xbass_xover_freq = *valp;
4862
4863 idx = *valp;
4864 ca0132_alt_slider_ctl_set(codec, nid, float_xbass_xover_lookup, idx);
4865
4866 return 0;
4867 }
4868
4869 static int ca0132_alt_effect_slider_put(struct snd_kcontrol *kcontrol,
4870 struct snd_ctl_elem_value *ucontrol)
4871 {
4872 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4873 struct ca0132_spec *spec = codec->spec;
4874 hda_nid_t nid = get_amp_nid(kcontrol);
4875 long *valp = ucontrol->value.integer.value;
4876 int idx;
4877
4878 idx = nid - EFFECT_START_NID;
4879 /* any change? */
4880 if (spec->fx_ctl_val[idx] == *valp)
4881 return 0;
4882
4883 spec->fx_ctl_val[idx] = *valp;
4884
4885 idx = *valp;
4886 ca0132_alt_slider_ctl_set(codec, nid, float_zero_to_one_lookup, idx);
4887
4888 return 0;
4889 }
4890
4891
4892 /*
4893 * Mic Boost Enum for alternative ca0132 codecs. I didn't like that the original
4894 * only has off or full 30 dB, and didn't like making a volume slider that has
4895 * traditional 0-100 in alsamixer that goes in big steps. I like enum better.
4896 */
4897 #define MIC_BOOST_NUM_OF_STEPS 4
4898 #define MIC_BOOST_ENUM_MAX_STRLEN 10
4899
4900 static int ca0132_alt_mic_boost_info(struct snd_kcontrol *kcontrol,
4901 struct snd_ctl_elem_info *uinfo)
4902 {
4903 char *sfx = "dB";
4904 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
4905
4906 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4907 uinfo->count = 1;
4908 uinfo->value.enumerated.items = MIC_BOOST_NUM_OF_STEPS;
4909 if (uinfo->value.enumerated.item >= MIC_BOOST_NUM_OF_STEPS)
4910 uinfo->value.enumerated.item = MIC_BOOST_NUM_OF_STEPS - 1;
4911 sprintf(namestr, "%d %s", (uinfo->value.enumerated.item * 10), sfx);
4912 strcpy(uinfo->value.enumerated.name, namestr);
4913 return 0;
4914 }
4915
4916 static int ca0132_alt_mic_boost_get(struct snd_kcontrol *kcontrol,
4917 struct snd_ctl_elem_value *ucontrol)
4918 {
4919 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4920 struct ca0132_spec *spec = codec->spec;
4921
4922 ucontrol->value.enumerated.item[0] = spec->mic_boost_enum_val;
4923 return 0;
4924 }
4925
4926 static int ca0132_alt_mic_boost_put(struct snd_kcontrol *kcontrol,
4927 struct snd_ctl_elem_value *ucontrol)
4928 {
4929 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4930 struct ca0132_spec *spec = codec->spec;
4931 int sel = ucontrol->value.enumerated.item[0];
4932 unsigned int items = MIC_BOOST_NUM_OF_STEPS;
4933
4934 if (sel >= items)
4935 return 0;
4936
4937 codec_dbg(codec, "ca0132_alt_mic_boost: boost=%d\n",
4938 sel);
4939
4940 spec->mic_boost_enum_val = sel;
4941
4942 if (spec->in_enum_val != REAR_LINE_IN)
4943 ca0132_alt_mic_boost_set(codec, spec->mic_boost_enum_val);
4944
4945 return 1;
4946 }
4947
4948
4949 /*
4950 * Input Select Control for alternative ca0132 codecs. This exists because
4951 * front microphone has no auto-detect, and we need a way to set the rear
4952 * as line-in
4953 */
4954 static int ca0132_alt_input_source_info(struct snd_kcontrol *kcontrol,
4955 struct snd_ctl_elem_info *uinfo)
4956 {
4957 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
4958 uinfo->count = 1;
4959 uinfo->value.enumerated.items = IN_SRC_NUM_OF_INPUTS;
4960 if (uinfo->value.enumerated.item >= IN_SRC_NUM_OF_INPUTS)
4961 uinfo->value.enumerated.item = IN_SRC_NUM_OF_INPUTS - 1;
4962 strcpy(uinfo->value.enumerated.name,
4963 in_src_str[uinfo->value.enumerated.item]);
4964 return 0;
4965 }
4966
4967 static int ca0132_alt_input_source_get(struct snd_kcontrol *kcontrol,
4968 struct snd_ctl_elem_value *ucontrol)
4969 {
4970 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4971 struct ca0132_spec *spec = codec->spec;
4972
4973 ucontrol->value.enumerated.item[0] = spec->in_enum_val;
4974 return 0;
4975 }
4976
4977 static int ca0132_alt_input_source_put(struct snd_kcontrol *kcontrol,
4978 struct snd_ctl_elem_value *ucontrol)
4979 {
4980 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
4981 struct ca0132_spec *spec = codec->spec;
4982 int sel = ucontrol->value.enumerated.item[0];
4983 unsigned int items = IN_SRC_NUM_OF_INPUTS;
4984
4985 if (sel >= items)
4986 return 0;
4987
4988 codec_dbg(codec, "ca0132_alt_input_select: sel=%d, preset=%s\n",
4989 sel, in_src_str[sel]);
4990
4991 spec->in_enum_val = sel;
4992
4993 ca0132_alt_select_in(codec);
4994
4995 return 1;
4996 }
4997
4998 /* Sound Blaster Z Output Select Control */
4999 static int ca0132_alt_output_select_get_info(struct snd_kcontrol *kcontrol,
5000 struct snd_ctl_elem_info *uinfo)
5001 {
5002 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5003 uinfo->count = 1;
5004 uinfo->value.enumerated.items = NUM_OF_OUTPUTS;
5005 if (uinfo->value.enumerated.item >= NUM_OF_OUTPUTS)
5006 uinfo->value.enumerated.item = NUM_OF_OUTPUTS - 1;
5007 strcpy(uinfo->value.enumerated.name,
5008 alt_out_presets[uinfo->value.enumerated.item].name);
5009 return 0;
5010 }
5011
5012 static int ca0132_alt_output_select_get(struct snd_kcontrol *kcontrol,
5013 struct snd_ctl_elem_value *ucontrol)
5014 {
5015 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5016 struct ca0132_spec *spec = codec->spec;
5017
5018 ucontrol->value.enumerated.item[0] = spec->out_enum_val;
5019 return 0;
5020 }
5021
5022 static int ca0132_alt_output_select_put(struct snd_kcontrol *kcontrol,
5023 struct snd_ctl_elem_value *ucontrol)
5024 {
5025 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5026 struct ca0132_spec *spec = codec->spec;
5027 int sel = ucontrol->value.enumerated.item[0];
5028 unsigned int items = NUM_OF_OUTPUTS;
5029 unsigned int auto_jack;
5030
5031 if (sel >= items)
5032 return 0;
5033
5034 codec_dbg(codec, "ca0132_alt_output_select: sel=%d, preset=%s\n",
5035 sel, alt_out_presets[sel].name);
5036
5037 spec->out_enum_val = sel;
5038
5039 auto_jack = spec->vnode_lswitch[VNID_HP_ASEL - VNODE_START_NID];
5040
5041 if (!auto_jack)
5042 ca0132_alt_select_out(codec);
5043
5044 return 1;
5045 }
5046
5047 /*
5048 * Smart Volume output setting control. Three different settings, Normal,
5049 * which takes the value from the smart volume slider. The two others, loud
5050 * and night, disregard the slider value and have uneditable values.
5051 */
5052 #define NUM_OF_SVM_SETTINGS 3
5053 static const char *const out_svm_set_enum_str[3] = {"Normal", "Loud", "Night" };
5054
5055 static int ca0132_alt_svm_setting_info(struct snd_kcontrol *kcontrol,
5056 struct snd_ctl_elem_info *uinfo)
5057 {
5058 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5059 uinfo->count = 1;
5060 uinfo->value.enumerated.items = NUM_OF_SVM_SETTINGS;
5061 if (uinfo->value.enumerated.item >= NUM_OF_SVM_SETTINGS)
5062 uinfo->value.enumerated.item = NUM_OF_SVM_SETTINGS - 1;
5063 strcpy(uinfo->value.enumerated.name,
5064 out_svm_set_enum_str[uinfo->value.enumerated.item]);
5065 return 0;
5066 }
5067
5068 static int ca0132_alt_svm_setting_get(struct snd_kcontrol *kcontrol,
5069 struct snd_ctl_elem_value *ucontrol)
5070 {
5071 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5072 struct ca0132_spec *spec = codec->spec;
5073
5074 ucontrol->value.enumerated.item[0] = spec->smart_volume_setting;
5075 return 0;
5076 }
5077
5078 static int ca0132_alt_svm_setting_put(struct snd_kcontrol *kcontrol,
5079 struct snd_ctl_elem_value *ucontrol)
5080 {
5081 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5082 struct ca0132_spec *spec = codec->spec;
5083 int sel = ucontrol->value.enumerated.item[0];
5084 unsigned int items = NUM_OF_SVM_SETTINGS;
5085 unsigned int idx = SMART_VOLUME - EFFECT_START_NID;
5086 unsigned int tmp;
5087
5088 if (sel >= items)
5089 return 0;
5090
5091 codec_dbg(codec, "ca0132_alt_svm_setting: sel=%d, preset=%s\n",
5092 sel, out_svm_set_enum_str[sel]);
5093
5094 spec->smart_volume_setting = sel;
5095
5096 switch (sel) {
5097 case 0:
5098 tmp = FLOAT_ZERO;
5099 break;
5100 case 1:
5101 tmp = FLOAT_ONE;
5102 break;
5103 case 2:
5104 tmp = FLOAT_TWO;
5105 break;
5106 default:
5107 tmp = FLOAT_ZERO;
5108 break;
5109 }
5110 /* Req 2 is the Smart Volume Setting req. */
5111 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
5112 ca0132_effects[idx].reqs[2], tmp);
5113 return 1;
5114 }
5115
5116 /* Sound Blaster Z EQ preset controls */
5117 static int ca0132_alt_eq_preset_info(struct snd_kcontrol *kcontrol,
5118 struct snd_ctl_elem_info *uinfo)
5119 {
5120 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5121
5122 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5123 uinfo->count = 1;
5124 uinfo->value.enumerated.items = items;
5125 if (uinfo->value.enumerated.item >= items)
5126 uinfo->value.enumerated.item = items - 1;
5127 strcpy(uinfo->value.enumerated.name,
5128 ca0132_alt_eq_presets[uinfo->value.enumerated.item].name);
5129 return 0;
5130 }
5131
5132 static int ca0132_alt_eq_preset_get(struct snd_kcontrol *kcontrol,
5133 struct snd_ctl_elem_value *ucontrol)
5134 {
5135 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5136 struct ca0132_spec *spec = codec->spec;
5137
5138 ucontrol->value.enumerated.item[0] = spec->eq_preset_val;
5139 return 0;
5140 }
5141
5142 static int ca0132_alt_eq_preset_put(struct snd_kcontrol *kcontrol,
5143 struct snd_ctl_elem_value *ucontrol)
5144 {
5145 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5146 struct ca0132_spec *spec = codec->spec;
5147 int i, err = 0;
5148 int sel = ucontrol->value.enumerated.item[0];
5149 unsigned int items = ARRAY_SIZE(ca0132_alt_eq_presets);
5150
5151 if (sel >= items)
5152 return 0;
5153
5154 codec_dbg(codec, "%s: sel=%d, preset=%s\n", __func__, sel,
5155 ca0132_alt_eq_presets[sel].name);
5156 /*
5157 * Idx 0 is default.
5158 * Default needs to qualify with CrystalVoice state.
5159 */
5160 for (i = 0; i < EQ_PRESET_MAX_PARAM_COUNT; i++) {
5161 err = dspio_set_uint_param(codec, ca0132_alt_eq_enum.mid,
5162 ca0132_alt_eq_enum.reqs[i],
5163 ca0132_alt_eq_presets[sel].vals[i]);
5164 if (err < 0)
5165 break;
5166 }
5167
5168 if (err >= 0)
5169 spec->eq_preset_val = sel;
5170
5171 return 1;
5172 }
5173
5174 static int ca0132_voicefx_info(struct snd_kcontrol *kcontrol,
5175 struct snd_ctl_elem_info *uinfo)
5176 {
5177 unsigned int items = ARRAY_SIZE(ca0132_voicefx_presets);
5178
5179 uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
5180 uinfo->count = 1;
5181 uinfo->value.enumerated.items = items;
5182 if (uinfo->value.enumerated.item >= items)
5183 uinfo->value.enumerated.item = items - 1;
5184 strcpy(uinfo->value.enumerated.name,
5185 ca0132_voicefx_presets[uinfo->value.enumerated.item].name);
5186 return 0;
5187 }
5188
5189 static int ca0132_voicefx_get(struct snd_kcontrol *kcontrol,
5190 struct snd_ctl_elem_value *ucontrol)
5191 {
5192 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5193 struct ca0132_spec *spec = codec->spec;
5194
5195 ucontrol->value.enumerated.item[0] = spec->voicefx_val;
5196 return 0;
5197 }
5198
5199 static int ca0132_voicefx_put(struct snd_kcontrol *kcontrol,
5200 struct snd_ctl_elem_value *ucontrol)
5201 {
5202 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5203 struct ca0132_spec *spec = codec->spec;
5204 int i, err = 0;
5205 int sel = ucontrol->value.enumerated.item[0];
5206
5207 if (sel >= ARRAY_SIZE(ca0132_voicefx_presets))
5208 return 0;
5209
5210 codec_dbg(codec, "ca0132_voicefx_put: sel=%d, preset=%s\n",
5211 sel, ca0132_voicefx_presets[sel].name);
5212
5213 /*
5214 * Idx 0 is default.
5215 * Default needs to qualify with CrystalVoice state.
5216 */
5217 for (i = 0; i < VOICEFX_MAX_PARAM_COUNT; i++) {
5218 err = dspio_set_uint_param(codec, ca0132_voicefx.mid,
5219 ca0132_voicefx.reqs[i],
5220 ca0132_voicefx_presets[sel].vals[i]);
5221 if (err < 0)
5222 break;
5223 }
5224
5225 if (err >= 0) {
5226 spec->voicefx_val = sel;
5227 /* enable voice fx */
5228 ca0132_voicefx_set(codec, (sel ? 1 : 0));
5229 }
5230
5231 return 1;
5232 }
5233
5234 static int ca0132_switch_get(struct snd_kcontrol *kcontrol,
5235 struct snd_ctl_elem_value *ucontrol)
5236 {
5237 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5238 struct ca0132_spec *spec = codec->spec;
5239 hda_nid_t nid = get_amp_nid(kcontrol);
5240 int ch = get_amp_channels(kcontrol);
5241 long *valp = ucontrol->value.integer.value;
5242
5243 /* vnode */
5244 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5245 if (ch & 1) {
5246 *valp = spec->vnode_lswitch[nid - VNODE_START_NID];
5247 valp++;
5248 }
5249 if (ch & 2) {
5250 *valp = spec->vnode_rswitch[nid - VNODE_START_NID];
5251 valp++;
5252 }
5253 return 0;
5254 }
5255
5256 /* effects, include PE and CrystalVoice */
5257 if ((nid >= EFFECT_START_NID) && (nid < EFFECT_END_NID)) {
5258 *valp = spec->effects_switch[nid - EFFECT_START_NID];
5259 return 0;
5260 }
5261
5262 /* mic boost */
5263 if (nid == spec->input_pins[0]) {
5264 *valp = spec->cur_mic_boost;
5265 return 0;
5266 }
5267
5268 return 0;
5269 }
5270
5271 static int ca0132_switch_put(struct snd_kcontrol *kcontrol,
5272 struct snd_ctl_elem_value *ucontrol)
5273 {
5274 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5275 struct ca0132_spec *spec = codec->spec;
5276 hda_nid_t nid = get_amp_nid(kcontrol);
5277 int ch = get_amp_channels(kcontrol);
5278 long *valp = ucontrol->value.integer.value;
5279 int changed = 1;
5280
5281 codec_dbg(codec, "ca0132_switch_put: nid=0x%x, val=%ld\n",
5282 nid, *valp);
5283
5284 snd_hda_power_up(codec);
5285 /* vnode */
5286 if ((nid >= VNODE_START_NID) && (nid < VNODE_END_NID)) {
5287 if (ch & 1) {
5288 spec->vnode_lswitch[nid - VNODE_START_NID] = *valp;
5289 valp++;
5290 }
5291 if (ch & 2) {
5292 spec->vnode_rswitch[nid - VNODE_START_NID] = *valp;
5293 valp++;
5294 }
5295 changed = ca0132_vnode_switch_set(kcontrol, ucontrol);
5296 goto exit;
5297 }
5298
5299 /* PE */
5300 if (nid == PLAY_ENHANCEMENT) {
5301 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5302 changed = ca0132_pe_switch_set(codec);
5303 goto exit;
5304 }
5305
5306 /* CrystalVoice */
5307 if (nid == CRYSTAL_VOICE) {
5308 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5309 changed = ca0132_cvoice_switch_set(codec);
5310 goto exit;
5311 }
5312
5313 /* out and in effects */
5314 if (((nid >= OUT_EFFECT_START_NID) && (nid < OUT_EFFECT_END_NID)) ||
5315 ((nid >= IN_EFFECT_START_NID) && (nid < IN_EFFECT_END_NID))) {
5316 spec->effects_switch[nid - EFFECT_START_NID] = *valp;
5317 changed = ca0132_effects_set(codec, nid, *valp);
5318 goto exit;
5319 }
5320
5321 /* mic boost */
5322 if (nid == spec->input_pins[0]) {
5323 spec->cur_mic_boost = *valp;
5324 if (spec->use_alt_functions) {
5325 if (spec->in_enum_val != REAR_LINE_IN)
5326 changed = ca0132_mic_boost_set(codec, *valp);
5327 } else {
5328 /* Mic boost does not apply to Digital Mic */
5329 if (spec->cur_mic_type != DIGITAL_MIC)
5330 changed = ca0132_mic_boost_set(codec, *valp);
5331 }
5332
5333 goto exit;
5334 }
5335
5336 exit:
5337 snd_hda_power_down(codec);
5338 return changed;
5339 }
5340
5341 /*
5342 * Volume related
5343 */
5344 /*
5345 * Sets the internal DSP decibel level to match the DAC for output, and the
5346 * ADC for input. Currently only the SBZ sets dsp capture volume level, and
5347 * all alternative codecs set DSP playback volume.
5348 */
5349 static void ca0132_alt_dsp_volume_put(struct hda_codec *codec, hda_nid_t nid)
5350 {
5351 struct ca0132_spec *spec = codec->spec;
5352 unsigned int dsp_dir;
5353 unsigned int lookup_val;
5354
5355 if (nid == VNID_SPK)
5356 dsp_dir = DSP_VOL_OUT;
5357 else
5358 dsp_dir = DSP_VOL_IN;
5359
5360 lookup_val = spec->vnode_lvol[nid - VNODE_START_NID];
5361
5362 dspio_set_uint_param(codec,
5363 ca0132_alt_vol_ctls[dsp_dir].mid,
5364 ca0132_alt_vol_ctls[dsp_dir].reqs[0],
5365 float_vol_db_lookup[lookup_val]);
5366
5367 lookup_val = spec->vnode_rvol[nid - VNODE_START_NID];
5368
5369 dspio_set_uint_param(codec,
5370 ca0132_alt_vol_ctls[dsp_dir].mid,
5371 ca0132_alt_vol_ctls[dsp_dir].reqs[1],
5372 float_vol_db_lookup[lookup_val]);
5373
5374 dspio_set_uint_param(codec,
5375 ca0132_alt_vol_ctls[dsp_dir].mid,
5376 ca0132_alt_vol_ctls[dsp_dir].reqs[2], FLOAT_ZERO);
5377 }
5378
5379 static int ca0132_volume_info(struct snd_kcontrol *kcontrol,
5380 struct snd_ctl_elem_info *uinfo)
5381 {
5382 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5383 struct ca0132_spec *spec = codec->spec;
5384 hda_nid_t nid = get_amp_nid(kcontrol);
5385 int ch = get_amp_channels(kcontrol);
5386 int dir = get_amp_direction(kcontrol);
5387 unsigned long pval;
5388 int err;
5389
5390 switch (nid) {
5391 case VNID_SPK:
5392 /* follow shared_out info */
5393 nid = spec->shared_out_nid;
5394 mutex_lock(&codec->control_mutex);
5395 pval = kcontrol->private_value;
5396 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5397 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5398 kcontrol->private_value = pval;
5399 mutex_unlock(&codec->control_mutex);
5400 break;
5401 case VNID_MIC:
5402 /* follow shared_mic info */
5403 nid = spec->shared_mic_nid;
5404 mutex_lock(&codec->control_mutex);
5405 pval = kcontrol->private_value;
5406 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5407 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5408 kcontrol->private_value = pval;
5409 mutex_unlock(&codec->control_mutex);
5410 break;
5411 default:
5412 err = snd_hda_mixer_amp_volume_info(kcontrol, uinfo);
5413 }
5414 return err;
5415 }
5416
5417 static int ca0132_volume_get(struct snd_kcontrol *kcontrol,
5418 struct snd_ctl_elem_value *ucontrol)
5419 {
5420 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5421 struct ca0132_spec *spec = codec->spec;
5422 hda_nid_t nid = get_amp_nid(kcontrol);
5423 int ch = get_amp_channels(kcontrol);
5424 long *valp = ucontrol->value.integer.value;
5425
5426 /* store the left and right volume */
5427 if (ch & 1) {
5428 *valp = spec->vnode_lvol[nid - VNODE_START_NID];
5429 valp++;
5430 }
5431 if (ch & 2) {
5432 *valp = spec->vnode_rvol[nid - VNODE_START_NID];
5433 valp++;
5434 }
5435 return 0;
5436 }
5437
5438 static int ca0132_volume_put(struct snd_kcontrol *kcontrol,
5439 struct snd_ctl_elem_value *ucontrol)
5440 {
5441 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5442 struct ca0132_spec *spec = codec->spec;
5443 hda_nid_t nid = get_amp_nid(kcontrol);
5444 int ch = get_amp_channels(kcontrol);
5445 long *valp = ucontrol->value.integer.value;
5446 hda_nid_t shared_nid = 0;
5447 bool effective;
5448 int changed = 1;
5449
5450 /* store the left and right volume */
5451 if (ch & 1) {
5452 spec->vnode_lvol[nid - VNODE_START_NID] = *valp;
5453 valp++;
5454 }
5455 if (ch & 2) {
5456 spec->vnode_rvol[nid - VNODE_START_NID] = *valp;
5457 valp++;
5458 }
5459
5460 /* if effective conditions, then update hw immediately. */
5461 effective = ca0132_is_vnode_effective(codec, nid, &shared_nid);
5462 if (effective) {
5463 int dir = get_amp_direction(kcontrol);
5464 unsigned long pval;
5465
5466 snd_hda_power_up(codec);
5467 mutex_lock(&codec->control_mutex);
5468 pval = kcontrol->private_value;
5469 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(shared_nid, ch,
5470 0, dir);
5471 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5472 kcontrol->private_value = pval;
5473 mutex_unlock(&codec->control_mutex);
5474 snd_hda_power_down(codec);
5475 }
5476
5477 return changed;
5478 }
5479
5480 /*
5481 * This function is the same as the one above, because using an if statement
5482 * inside of the above volume control for the DSP volume would cause too much
5483 * lag. This is a lot more smooth.
5484 */
5485 static int ca0132_alt_volume_put(struct snd_kcontrol *kcontrol,
5486 struct snd_ctl_elem_value *ucontrol)
5487 {
5488 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5489 struct ca0132_spec *spec = codec->spec;
5490 hda_nid_t nid = get_amp_nid(kcontrol);
5491 int ch = get_amp_channels(kcontrol);
5492 long *valp = ucontrol->value.integer.value;
5493 hda_nid_t vnid = 0;
5494 int changed = 1;
5495
5496 switch (nid) {
5497 case 0x02:
5498 vnid = VNID_SPK;
5499 break;
5500 case 0x07:
5501 vnid = VNID_MIC;
5502 break;
5503 }
5504
5505 /* store the left and right volume */
5506 if (ch & 1) {
5507 spec->vnode_lvol[vnid - VNODE_START_NID] = *valp;
5508 valp++;
5509 }
5510 if (ch & 2) {
5511 spec->vnode_rvol[vnid - VNODE_START_NID] = *valp;
5512 valp++;
5513 }
5514
5515 snd_hda_power_up(codec);
5516 ca0132_alt_dsp_volume_put(codec, vnid);
5517 mutex_lock(&codec->control_mutex);
5518 changed = snd_hda_mixer_amp_volume_put(kcontrol, ucontrol);
5519 mutex_unlock(&codec->control_mutex);
5520 snd_hda_power_down(codec);
5521
5522 return changed;
5523 }
5524
5525 static int ca0132_volume_tlv(struct snd_kcontrol *kcontrol, int op_flag,
5526 unsigned int size, unsigned int __user *tlv)
5527 {
5528 struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
5529 struct ca0132_spec *spec = codec->spec;
5530 hda_nid_t nid = get_amp_nid(kcontrol);
5531 int ch = get_amp_channels(kcontrol);
5532 int dir = get_amp_direction(kcontrol);
5533 unsigned long pval;
5534 int err;
5535
5536 switch (nid) {
5537 case VNID_SPK:
5538 /* follow shared_out tlv */
5539 nid = spec->shared_out_nid;
5540 mutex_lock(&codec->control_mutex);
5541 pval = kcontrol->private_value;
5542 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5543 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5544 kcontrol->private_value = pval;
5545 mutex_unlock(&codec->control_mutex);
5546 break;
5547 case VNID_MIC:
5548 /* follow shared_mic tlv */
5549 nid = spec->shared_mic_nid;
5550 mutex_lock(&codec->control_mutex);
5551 pval = kcontrol->private_value;
5552 kcontrol->private_value = HDA_COMPOSE_AMP_VAL(nid, ch, 0, dir);
5553 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5554 kcontrol->private_value = pval;
5555 mutex_unlock(&codec->control_mutex);
5556 break;
5557 default:
5558 err = snd_hda_mixer_amp_tlv(kcontrol, op_flag, size, tlv);
5559 }
5560 return err;
5561 }
5562
5563 /* Add volume slider control for effect level */
5564 static int ca0132_alt_add_effect_slider(struct hda_codec *codec, hda_nid_t nid,
5565 const char *pfx, int dir)
5566 {
5567 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5568 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5569 struct snd_kcontrol_new knew =
5570 HDA_CODEC_VOLUME_MONO(namestr, nid, 1, 0, type);
5571
5572 sprintf(namestr, "FX: %s %s Volume", pfx, dirstr[dir]);
5573
5574 knew.tlv.c = NULL;
5575
5576 switch (nid) {
5577 case XBASS_XOVER:
5578 knew.info = ca0132_alt_xbass_xover_slider_info;
5579 knew.get = ca0132_alt_xbass_xover_slider_ctl_get;
5580 knew.put = ca0132_alt_xbass_xover_slider_put;
5581 break;
5582 default:
5583 knew.info = ca0132_alt_effect_slider_info;
5584 knew.get = ca0132_alt_slider_ctl_get;
5585 knew.put = ca0132_alt_effect_slider_put;
5586 knew.private_value =
5587 HDA_COMPOSE_AMP_VAL(nid, 1, 0, type);
5588 break;
5589 }
5590
5591 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5592 }
5593
5594 /*
5595 * Added FX: prefix for the alternative codecs, because otherwise the surround
5596 * effect would conflict with the Surround sound volume control. Also seems more
5597 * clear as to what the switches do. Left alone for others.
5598 */
5599 static int add_fx_switch(struct hda_codec *codec, hda_nid_t nid,
5600 const char *pfx, int dir)
5601 {
5602 struct ca0132_spec *spec = codec->spec;
5603 char namestr[SNDRV_CTL_ELEM_ID_NAME_MAXLEN];
5604 int type = dir ? HDA_INPUT : HDA_OUTPUT;
5605 struct snd_kcontrol_new knew =
5606 CA0132_CODEC_MUTE_MONO(namestr, nid, 1, type);
5607 /* If using alt_controls, add FX: prefix. But, don't add FX:
5608 * prefix to OutFX or InFX enable controls.
5609 */
5610 if ((spec->use_alt_controls) && (nid <= IN_EFFECT_END_NID))
5611 sprintf(namestr, "FX: %s %s Switch", pfx, dirstr[dir]);
5612 else
5613 sprintf(namestr, "%s %s Switch", pfx, dirstr[dir]);
5614
5615 return snd_hda_ctl_add(codec, nid, snd_ctl_new1(&knew, codec));
5616 }
5617
5618 static int add_voicefx(struct hda_codec *codec)
5619 {
5620 struct snd_kcontrol_new knew =
5621 HDA_CODEC_MUTE_MONO(ca0132_voicefx.name,
5622 VOICEFX, 1, 0, HDA_INPUT);
5623 knew.info = ca0132_voicefx_info;
5624 knew.get = ca0132_voicefx_get;
5625 knew.put = ca0132_voicefx_put;
5626 return snd_hda_ctl_add(codec, VOICEFX, snd_ctl_new1(&knew, codec));
5627 }
5628
5629 /* Create the EQ Preset control */
5630 static int add_ca0132_alt_eq_presets(struct hda_codec *codec)
5631 {
5632 struct snd_kcontrol_new knew =
5633 HDA_CODEC_MUTE_MONO(ca0132_alt_eq_enum.name,
5634 EQ_PRESET_ENUM, 1, 0, HDA_OUTPUT);
5635 knew.info = ca0132_alt_eq_preset_info;
5636 knew.get = ca0132_alt_eq_preset_get;
5637 knew.put = ca0132_alt_eq_preset_put;
5638 return snd_hda_ctl_add(codec, EQ_PRESET_ENUM,
5639 snd_ctl_new1(&knew, codec));
5640 }
5641
5642 /*
5643 * Add enumerated control for the three different settings of the smart volume
5644 * output effect. Normal just uses the slider value, and loud and night are
5645 * their own things that ignore that value.
5646 */
5647 static int ca0132_alt_add_svm_enum(struct hda_codec *codec)
5648 {
5649 struct snd_kcontrol_new knew =
5650 HDA_CODEC_MUTE_MONO("FX: Smart Volume Setting",
5651 SMART_VOLUME_ENUM, 1, 0, HDA_OUTPUT);
5652 knew.info = ca0132_alt_svm_setting_info;
5653 knew.get = ca0132_alt_svm_setting_get;
5654 knew.put = ca0132_alt_svm_setting_put;
5655 return snd_hda_ctl_add(codec, SMART_VOLUME_ENUM,
5656 snd_ctl_new1(&knew, codec));
5657
5658 }
5659
5660 /*
5661 * Create an Output Select enumerated control for codecs with surround
5662 * out capabilities.
5663 */
5664 static int ca0132_alt_add_output_enum(struct hda_codec *codec)
5665 {
5666 struct snd_kcontrol_new knew =
5667 HDA_CODEC_MUTE_MONO("Output Select",
5668 OUTPUT_SOURCE_ENUM, 1, 0, HDA_OUTPUT);
5669 knew.info = ca0132_alt_output_select_get_info;
5670 knew.get = ca0132_alt_output_select_get;
5671 knew.put = ca0132_alt_output_select_put;
5672 return snd_hda_ctl_add(codec, OUTPUT_SOURCE_ENUM,
5673 snd_ctl_new1(&knew, codec));
5674 }
5675
5676 /*
5677 * Create an Input Source enumerated control for the alternate ca0132 codecs
5678 * because the front microphone has no auto-detect, and Line-in has to be set
5679 * somehow.
5680 */
5681 static int ca0132_alt_add_input_enum(struct hda_codec *codec)
5682 {
5683 struct snd_kcontrol_new knew =
5684 HDA_CODEC_MUTE_MONO("Input Source",
5685 INPUT_SOURCE_ENUM, 1, 0, HDA_INPUT);
5686 knew.info = ca0132_alt_input_source_info;
5687 knew.get = ca0132_alt_input_source_get;
5688 knew.put = ca0132_alt_input_source_put;
5689 return snd_hda_ctl_add(codec, INPUT_SOURCE_ENUM,
5690 snd_ctl_new1(&knew, codec));
5691 }
5692
5693 /*
5694 * Add mic boost enumerated control. Switches through 0dB to 30dB. This adds
5695 * more control than the original mic boost, which is either full 30dB or off.
5696 */
5697 static int ca0132_alt_add_mic_boost_enum(struct hda_codec *codec)
5698 {
5699 struct snd_kcontrol_new knew =
5700 HDA_CODEC_MUTE_MONO("Mic Boost Capture Switch",
5701 MIC_BOOST_ENUM, 1, 0, HDA_INPUT);
5702 knew.info = ca0132_alt_mic_boost_info;
5703 knew.get = ca0132_alt_mic_boost_get;
5704 knew.put = ca0132_alt_mic_boost_put;
5705 return snd_hda_ctl_add(codec, MIC_BOOST_ENUM,
5706 snd_ctl_new1(&knew, codec));
5707
5708 }
5709
5710 /*
5711 * Need to create slave controls for the alternate codecs that have surround
5712 * capabilities.
5713 */
5714 static const char * const ca0132_alt_slave_pfxs[] = {
5715 "Front", "Surround", "Center", "LFE", NULL,
5716 };
5717
5718 /*
5719 * Also need special channel map, because the default one is incorrect.
5720 * I think this has to do with the pin for rear surround being 0x11,
5721 * and the center/lfe being 0x10. Usually the pin order is the opposite.
5722 */
5723 static const struct snd_pcm_chmap_elem ca0132_alt_chmaps[] = {
5724 { .channels = 2,
5725 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
5726 { .channels = 4,
5727 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5728 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5729 { .channels = 6,
5730 .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
5731 SNDRV_CHMAP_FC, SNDRV_CHMAP_LFE,
5732 SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
5733 { }
5734 };
5735
5736 /* Add the correct chmap for streams with 6 channels. */
5737 static void ca0132_alt_add_chmap_ctls(struct hda_codec *codec)
5738 {
5739 int err = 0;
5740 struct hda_pcm *pcm;
5741
5742 list_for_each_entry(pcm, &codec->pcm_list_head, list) {
5743 struct hda_pcm_stream *hinfo =
5744 &pcm->stream[SNDRV_PCM_STREAM_PLAYBACK];
5745 struct snd_pcm_chmap *chmap;
5746 const struct snd_pcm_chmap_elem *elem;
5747
5748 elem = ca0132_alt_chmaps;
5749 if (hinfo->channels_max == 6) {
5750 err = snd_pcm_add_chmap_ctls(pcm->pcm,
5751 SNDRV_PCM_STREAM_PLAYBACK,
5752 elem, hinfo->channels_max, 0, &chmap);
5753 if (err < 0)
5754 codec_dbg(codec, "snd_pcm_add_chmap_ctls failed!");
5755 }
5756 }
5757 }
5758
5759 /*
5760 * When changing Node IDs for Mixer Controls below, make sure to update
5761 * Node IDs in ca0132_config() as well.
5762 */
5763 static const struct snd_kcontrol_new ca0132_mixer[] = {
5764 CA0132_CODEC_VOL("Master Playback Volume", VNID_SPK, HDA_OUTPUT),
5765 CA0132_CODEC_MUTE("Master Playback Switch", VNID_SPK, HDA_OUTPUT),
5766 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5767 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5768 HDA_CODEC_VOLUME("Analog-Mic2 Capture Volume", 0x08, 0, HDA_INPUT),
5769 HDA_CODEC_MUTE("Analog-Mic2 Capture Switch", 0x08, 0, HDA_INPUT),
5770 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5771 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5772 CA0132_CODEC_MUTE_MONO("Mic1-Boost (30dB) Capture Switch",
5773 0x12, 1, HDA_INPUT),
5774 CA0132_CODEC_MUTE_MONO("HP/Speaker Playback Switch",
5775 VNID_HP_SEL, 1, HDA_OUTPUT),
5776 CA0132_CODEC_MUTE_MONO("AMic1/DMic Capture Switch",
5777 VNID_AMIC1_SEL, 1, HDA_INPUT),
5778 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5779 VNID_HP_ASEL, 1, HDA_OUTPUT),
5780 CA0132_CODEC_MUTE_MONO("AMic1/DMic Auto Detect Capture Switch",
5781 VNID_AMIC1_ASEL, 1, HDA_INPUT),
5782 { } /* end */
5783 };
5784
5785 /*
5786 * Desktop specific control mixer. Removes auto-detect for mic, and adds
5787 * surround controls. Also sets both the Front Playback and Capture Volume
5788 * controls to alt so they set the DSP's decibel level.
5789 */
5790 static const struct snd_kcontrol_new desktop_mixer[] = {
5791 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5792 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5793 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5794 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5795 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5796 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5797 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5798 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5799 CA0132_ALT_CODEC_VOL("Capture Volume", 0x07, HDA_INPUT),
5800 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5801 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5802 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5803 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5804 VNID_HP_ASEL, 1, HDA_OUTPUT),
5805 { } /* end */
5806 };
5807
5808 /*
5809 * Same as the Sound Blaster Z, except doesn't use the alt volume for capture
5810 * because it doesn't set decibel levels for the DSP for capture.
5811 */
5812 static const struct snd_kcontrol_new r3di_mixer[] = {
5813 CA0132_ALT_CODEC_VOL("Front Playback Volume", 0x02, HDA_OUTPUT),
5814 CA0132_CODEC_MUTE("Front Playback Switch", VNID_SPK, HDA_OUTPUT),
5815 HDA_CODEC_VOLUME("Surround Playback Volume", 0x04, 0, HDA_OUTPUT),
5816 HDA_CODEC_MUTE("Surround Playback Switch", 0x04, 0, HDA_OUTPUT),
5817 HDA_CODEC_VOLUME_MONO("Center Playback Volume", 0x03, 1, 0, HDA_OUTPUT),
5818 HDA_CODEC_MUTE_MONO("Center Playback Switch", 0x03, 1, 0, HDA_OUTPUT),
5819 HDA_CODEC_VOLUME_MONO("LFE Playback Volume", 0x03, 2, 0, HDA_OUTPUT),
5820 HDA_CODEC_MUTE_MONO("LFE Playback Switch", 0x03, 2, 0, HDA_OUTPUT),
5821 CA0132_CODEC_VOL("Capture Volume", VNID_MIC, HDA_INPUT),
5822 CA0132_CODEC_MUTE("Capture Switch", VNID_MIC, HDA_INPUT),
5823 HDA_CODEC_VOLUME("What U Hear Capture Volume", 0x0a, 0, HDA_INPUT),
5824 HDA_CODEC_MUTE("What U Hear Capture Switch", 0x0a, 0, HDA_INPUT),
5825 CA0132_CODEC_MUTE_MONO("HP/Speaker Auto Detect Playback Switch",
5826 VNID_HP_ASEL, 1, HDA_OUTPUT),
5827 { } /* end */
5828 };
5829
5830 static int ca0132_build_controls(struct hda_codec *codec)
5831 {
5832 struct ca0132_spec *spec = codec->spec;
5833 int i, num_fx, num_sliders;
5834 int err = 0;
5835
5836 /* Add Mixer controls */
5837 for (i = 0; i < spec->num_mixers; i++) {
5838 err = snd_hda_add_new_ctls(codec, spec->mixers[i]);
5839 if (err < 0)
5840 return err;
5841 }
5842 /* Setup vmaster with surround slaves for desktop ca0132 devices */
5843 if (spec->use_alt_functions) {
5844 snd_hda_set_vmaster_tlv(codec, spec->dacs[0], HDA_OUTPUT,
5845 spec->tlv);
5846 snd_hda_add_vmaster(codec, "Master Playback Volume",
5847 spec->tlv, ca0132_alt_slave_pfxs,
5848 "Playback Volume");
5849 err = __snd_hda_add_vmaster(codec, "Master Playback Switch",
5850 NULL, ca0132_alt_slave_pfxs,
5851 "Playback Switch",
5852 true, &spec->vmaster_mute.sw_kctl);
5853
5854 }
5855
5856 /* Add in and out effects controls.
5857 * VoiceFX, PE and CrystalVoice are added separately.
5858 */
5859 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
5860 for (i = 0; i < num_fx; i++) {
5861 /* Desktop cards break if Echo Cancellation is used. */
5862 if (spec->use_pci_mmio) {
5863 if (i == (ECHO_CANCELLATION - IN_EFFECT_START_NID +
5864 OUT_EFFECTS_COUNT))
5865 continue;
5866 }
5867
5868 err = add_fx_switch(codec, ca0132_effects[i].nid,
5869 ca0132_effects[i].name,
5870 ca0132_effects[i].direct);
5871 if (err < 0)
5872 return err;
5873 }
5874 /*
5875 * If codec has use_alt_controls set to true, add effect level sliders,
5876 * EQ presets, and Smart Volume presets. Also, change names to add FX
5877 * prefix, and change PlayEnhancement and CrystalVoice to match.
5878 */
5879 if (spec->use_alt_controls) {
5880 ca0132_alt_add_svm_enum(codec);
5881 add_ca0132_alt_eq_presets(codec);
5882 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5883 "Enable OutFX", 0);
5884 if (err < 0)
5885 return err;
5886
5887 err = add_fx_switch(codec, CRYSTAL_VOICE,
5888 "Enable InFX", 1);
5889 if (err < 0)
5890 return err;
5891
5892 num_sliders = OUT_EFFECTS_COUNT - 1;
5893 for (i = 0; i < num_sliders; i++) {
5894 err = ca0132_alt_add_effect_slider(codec,
5895 ca0132_effects[i].nid,
5896 ca0132_effects[i].name,
5897 ca0132_effects[i].direct);
5898 if (err < 0)
5899 return err;
5900 }
5901
5902 err = ca0132_alt_add_effect_slider(codec, XBASS_XOVER,
5903 "X-Bass Crossover", EFX_DIR_OUT);
5904
5905 if (err < 0)
5906 return err;
5907 } else {
5908 err = add_fx_switch(codec, PLAY_ENHANCEMENT,
5909 "PlayEnhancement", 0);
5910 if (err < 0)
5911 return err;
5912
5913 err = add_fx_switch(codec, CRYSTAL_VOICE,
5914 "CrystalVoice", 1);
5915 if (err < 0)
5916 return err;
5917 }
5918 add_voicefx(codec);
5919
5920 /*
5921 * If the codec uses alt_functions, you need the enumerated controls
5922 * to select the new outputs and inputs, plus add the new mic boost
5923 * setting control.
5924 */
5925 if (spec->use_alt_functions) {
5926 ca0132_alt_add_output_enum(codec);
5927 ca0132_alt_add_input_enum(codec);
5928 ca0132_alt_add_mic_boost_enum(codec);
5929 }
5930 #ifdef ENABLE_TUNING_CONTROLS
5931 add_tuning_ctls(codec);
5932 #endif
5933
5934 err = snd_hda_jack_add_kctls(codec, &spec->autocfg);
5935 if (err < 0)
5936 return err;
5937
5938 if (spec->dig_out) {
5939 err = snd_hda_create_spdif_out_ctls(codec, spec->dig_out,
5940 spec->dig_out);
5941 if (err < 0)
5942 return err;
5943 err = snd_hda_create_spdif_share_sw(codec, &spec->multiout);
5944 if (err < 0)
5945 return err;
5946 /* spec->multiout.share_spdif = 1; */
5947 }
5948
5949 if (spec->dig_in) {
5950 err = snd_hda_create_spdif_in_ctls(codec, spec->dig_in);
5951 if (err < 0)
5952 return err;
5953 }
5954
5955 if (spec->use_alt_functions)
5956 ca0132_alt_add_chmap_ctls(codec);
5957
5958 return 0;
5959 }
5960
5961 /*
5962 * PCM
5963 */
5964 static const struct hda_pcm_stream ca0132_pcm_analog_playback = {
5965 .substreams = 1,
5966 .channels_min = 2,
5967 .channels_max = 6,
5968 .ops = {
5969 .prepare = ca0132_playback_pcm_prepare,
5970 .cleanup = ca0132_playback_pcm_cleanup,
5971 .get_delay = ca0132_playback_pcm_delay,
5972 },
5973 };
5974
5975 static const struct hda_pcm_stream ca0132_pcm_analog_capture = {
5976 .substreams = 1,
5977 .channels_min = 2,
5978 .channels_max = 2,
5979 .ops = {
5980 .prepare = ca0132_capture_pcm_prepare,
5981 .cleanup = ca0132_capture_pcm_cleanup,
5982 .get_delay = ca0132_capture_pcm_delay,
5983 },
5984 };
5985
5986 static const struct hda_pcm_stream ca0132_pcm_digital_playback = {
5987 .substreams = 1,
5988 .channels_min = 2,
5989 .channels_max = 2,
5990 .ops = {
5991 .open = ca0132_dig_playback_pcm_open,
5992 .close = ca0132_dig_playback_pcm_close,
5993 .prepare = ca0132_dig_playback_pcm_prepare,
5994 .cleanup = ca0132_dig_playback_pcm_cleanup
5995 },
5996 };
5997
5998 static const struct hda_pcm_stream ca0132_pcm_digital_capture = {
5999 .substreams = 1,
6000 .channels_min = 2,
6001 .channels_max = 2,
6002 };
6003
6004 static int ca0132_build_pcms(struct hda_codec *codec)
6005 {
6006 struct ca0132_spec *spec = codec->spec;
6007 struct hda_pcm *info;
6008
6009 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog");
6010 if (!info)
6011 return -ENOMEM;
6012 if (spec->use_alt_functions) {
6013 info->own_chmap = true;
6014 info->stream[SNDRV_PCM_STREAM_PLAYBACK].chmap
6015 = ca0132_alt_chmaps;
6016 }
6017 info->stream[SNDRV_PCM_STREAM_PLAYBACK] = ca0132_pcm_analog_playback;
6018 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dacs[0];
6019 info->stream[SNDRV_PCM_STREAM_PLAYBACK].channels_max =
6020 spec->multiout.max_channels;
6021 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6022 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6023 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[0];
6024
6025 /* With the DSP enabled, desktops don't use this ADC. */
6026 if (!spec->use_alt_functions) {
6027 info = snd_hda_codec_pcm_new(codec, "CA0132 Analog Mic-In2");
6028 if (!info)
6029 return -ENOMEM;
6030 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6031 ca0132_pcm_analog_capture;
6032 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6033 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[1];
6034 }
6035
6036 info = snd_hda_codec_pcm_new(codec, "CA0132 What U Hear");
6037 if (!info)
6038 return -ENOMEM;
6039 info->stream[SNDRV_PCM_STREAM_CAPTURE] = ca0132_pcm_analog_capture;
6040 info->stream[SNDRV_PCM_STREAM_CAPTURE].substreams = 1;
6041 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->adcs[2];
6042
6043 if (!spec->dig_out && !spec->dig_in)
6044 return 0;
6045
6046 info = snd_hda_codec_pcm_new(codec, "CA0132 Digital");
6047 if (!info)
6048 return -ENOMEM;
6049 info->pcm_type = HDA_PCM_TYPE_SPDIF;
6050 if (spec->dig_out) {
6051 info->stream[SNDRV_PCM_STREAM_PLAYBACK] =
6052 ca0132_pcm_digital_playback;
6053 info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = spec->dig_out;
6054 }
6055 if (spec->dig_in) {
6056 info->stream[SNDRV_PCM_STREAM_CAPTURE] =
6057 ca0132_pcm_digital_capture;
6058 info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = spec->dig_in;
6059 }
6060
6061 return 0;
6062 }
6063
6064 static void init_output(struct hda_codec *codec, hda_nid_t pin, hda_nid_t dac)
6065 {
6066 if (pin) {
6067 snd_hda_set_pin_ctl(codec, pin, PIN_HP);
6068 if (get_wcaps(codec, pin) & AC_WCAP_OUT_AMP)
6069 snd_hda_codec_write(codec, pin, 0,
6070 AC_VERB_SET_AMP_GAIN_MUTE,
6071 AMP_OUT_UNMUTE);
6072 }
6073 if (dac && (get_wcaps(codec, dac) & AC_WCAP_OUT_AMP))
6074 snd_hda_codec_write(codec, dac, 0,
6075 AC_VERB_SET_AMP_GAIN_MUTE, AMP_OUT_ZERO);
6076 }
6077
6078 static void init_input(struct hda_codec *codec, hda_nid_t pin, hda_nid_t adc)
6079 {
6080 if (pin) {
6081 snd_hda_set_pin_ctl(codec, pin, PIN_VREF80);
6082 if (get_wcaps(codec, pin) & AC_WCAP_IN_AMP)
6083 snd_hda_codec_write(codec, pin, 0,
6084 AC_VERB_SET_AMP_GAIN_MUTE,
6085 AMP_IN_UNMUTE(0));
6086 }
6087 if (adc && (get_wcaps(codec, adc) & AC_WCAP_IN_AMP)) {
6088 snd_hda_codec_write(codec, adc, 0, AC_VERB_SET_AMP_GAIN_MUTE,
6089 AMP_IN_UNMUTE(0));
6090
6091 /* init to 0 dB and unmute. */
6092 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6093 HDA_AMP_VOLMASK, 0x5a);
6094 snd_hda_codec_amp_stereo(codec, adc, HDA_INPUT, 0,
6095 HDA_AMP_MUTE, 0);
6096 }
6097 }
6098
6099 static void refresh_amp_caps(struct hda_codec *codec, hda_nid_t nid, int dir)
6100 {
6101 unsigned int caps;
6102
6103 caps = snd_hda_param_read(codec, nid, dir == HDA_OUTPUT ?
6104 AC_PAR_AMP_OUT_CAP : AC_PAR_AMP_IN_CAP);
6105 snd_hda_override_amp_caps(codec, nid, dir, caps);
6106 }
6107
6108 /*
6109 * Switch between Digital built-in mic and analog mic.
6110 */
6111 static void ca0132_set_dmic(struct hda_codec *codec, int enable)
6112 {
6113 struct ca0132_spec *spec = codec->spec;
6114 unsigned int tmp;
6115 u8 val;
6116 unsigned int oldval;
6117
6118 codec_dbg(codec, "ca0132_set_dmic: enable=%d\n", enable);
6119
6120 oldval = stop_mic1(codec);
6121 ca0132_set_vipsource(codec, 0);
6122 if (enable) {
6123 /* set DMic input as 2-ch */
6124 tmp = FLOAT_TWO;
6125 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6126
6127 val = spec->dmic_ctl;
6128 val |= 0x80;
6129 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6130 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6131
6132 if (!(spec->dmic_ctl & 0x20))
6133 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 1);
6134 } else {
6135 /* set AMic input as mono */
6136 tmp = FLOAT_ONE;
6137 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6138
6139 val = spec->dmic_ctl;
6140 /* clear bit7 and bit5 to disable dmic */
6141 val &= 0x5f;
6142 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6143 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6144
6145 if (!(spec->dmic_ctl & 0x20))
6146 chipio_set_control_flag(codec, CONTROL_FLAG_DMIC, 0);
6147 }
6148 ca0132_set_vipsource(codec, 1);
6149 resume_mic1(codec, oldval);
6150 }
6151
6152 /*
6153 * Initialization for Digital Mic.
6154 */
6155 static void ca0132_init_dmic(struct hda_codec *codec)
6156 {
6157 struct ca0132_spec *spec = codec->spec;
6158 u8 val;
6159
6160 /* Setup Digital Mic here, but don't enable.
6161 * Enable based on jack detect.
6162 */
6163
6164 /* MCLK uses MPIO1, set to enable.
6165 * Bit 2-0: MPIO select
6166 * Bit 3: set to disable
6167 * Bit 7-4: reserved
6168 */
6169 val = 0x01;
6170 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6171 VENDOR_CHIPIO_DMIC_MCLK_SET, val);
6172
6173 /* Data1 uses MPIO3. Data2 not use
6174 * Bit 2-0: Data1 MPIO select
6175 * Bit 3: set disable Data1
6176 * Bit 6-4: Data2 MPIO select
6177 * Bit 7: set disable Data2
6178 */
6179 val = 0x83;
6180 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6181 VENDOR_CHIPIO_DMIC_PIN_SET, val);
6182
6183 /* Use Ch-0 and Ch-1. Rate is 48K, mode 1. Disable DMic first.
6184 * Bit 3-0: Channel mask
6185 * Bit 4: set for 48KHz, clear for 32KHz
6186 * Bit 5: mode
6187 * Bit 6: set to select Data2, clear for Data1
6188 * Bit 7: set to enable DMic, clear for AMic
6189 */
6190 if (spec->quirk == QUIRK_ALIENWARE_M17XR4)
6191 val = 0x33;
6192 else
6193 val = 0x23;
6194 /* keep a copy of dmic ctl val for enable/disable dmic purpuse */
6195 spec->dmic_ctl = val;
6196 snd_hda_codec_write(codec, spec->input_pins[0], 0,
6197 VENDOR_CHIPIO_DMIC_CTL_SET, val);
6198 }
6199
6200 /*
6201 * Initialization for Analog Mic 2
6202 */
6203 static void ca0132_init_analog_mic2(struct hda_codec *codec)
6204 {
6205 struct ca0132_spec *spec = codec->spec;
6206
6207 mutex_lock(&spec->chipio_mutex);
6208 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6209 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
6210 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6211 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6212 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6213 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6214 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6215 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x2D);
6216 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6217 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
6218 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
6219 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
6220 mutex_unlock(&spec->chipio_mutex);
6221 }
6222
6223 static void ca0132_refresh_widget_caps(struct hda_codec *codec)
6224 {
6225 struct ca0132_spec *spec = codec->spec;
6226 int i;
6227
6228 codec_dbg(codec, "ca0132_refresh_widget_caps.\n");
6229 snd_hda_codec_update_widgets(codec);
6230
6231 for (i = 0; i < spec->multiout.num_dacs; i++)
6232 refresh_amp_caps(codec, spec->dacs[i], HDA_OUTPUT);
6233
6234 for (i = 0; i < spec->num_outputs; i++)
6235 refresh_amp_caps(codec, spec->out_pins[i], HDA_OUTPUT);
6236
6237 for (i = 0; i < spec->num_inputs; i++) {
6238 refresh_amp_caps(codec, spec->adcs[i], HDA_INPUT);
6239 refresh_amp_caps(codec, spec->input_pins[i], HDA_INPUT);
6240 }
6241 }
6242
6243 /*
6244 * Recon3D r3d_setup_defaults sub functions.
6245 */
6246
6247 static void r3d_dsp_scp_startup(struct hda_codec *codec)
6248 {
6249 unsigned int tmp;
6250
6251 tmp = 0x00000000;
6252 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6253
6254 tmp = 0x00000001;
6255 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6256
6257 tmp = 0x00000004;
6258 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6259
6260 tmp = 0x00000005;
6261 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6262
6263 tmp = 0x00000000;
6264 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6265
6266 }
6267
6268 static void r3d_dsp_initial_mic_setup(struct hda_codec *codec)
6269 {
6270 unsigned int tmp;
6271
6272 /* Mic 1 Setup */
6273 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6274 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6275 /* This ConnPointID is unique to Recon3Di. Haven't seen it elsewhere */
6276 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6277 tmp = FLOAT_ONE;
6278 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6279
6280 /* Mic 2 Setup, even though it isn't connected on SBZ */
6281 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6282 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6283 chipio_set_conn_rate(codec, 0x0F, SR_96_000);
6284 tmp = FLOAT_ZERO;
6285 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6286 }
6287
6288 /*
6289 * Initialize Sound Blaster Z analog microphones.
6290 */
6291 static void sbz_init_analog_mics(struct hda_codec *codec)
6292 {
6293 unsigned int tmp;
6294
6295 /* Mic 1 Setup */
6296 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6297 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6298 tmp = FLOAT_THREE;
6299 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6300
6301 /* Mic 2 Setup, even though it isn't connected on SBZ */
6302 chipio_set_conn_rate(codec, MEM_CONNID_MICIN2, SR_96_000);
6303 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT2, SR_96_000);
6304 tmp = FLOAT_ZERO;
6305 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6306
6307 }
6308
6309 /*
6310 * Sets the source of stream 0x14 to connpointID 0x48, and the destination
6311 * connpointID to 0x91. If this isn't done, the destination is 0x71, and
6312 * you get no sound. I'm guessing this has to do with the Sound Blaster Z
6313 * having an updated DAC, which changes the destination to that DAC.
6314 */
6315 static void sbz_connect_streams(struct hda_codec *codec)
6316 {
6317 struct ca0132_spec *spec = codec->spec;
6318
6319 mutex_lock(&spec->chipio_mutex);
6320
6321 codec_dbg(codec, "Connect Streams entered, mutex locked and loaded.\n");
6322
6323 chipio_set_stream_channels(codec, 0x0C, 6);
6324 chipio_set_stream_control(codec, 0x0C, 1);
6325
6326 /* This value is 0x43 for 96khz, and 0x83 for 192khz. */
6327 chipio_write_no_mutex(codec, 0x18a020, 0x00000043);
6328
6329 /* Setup stream 0x14 with it's source and destination points */
6330 chipio_set_stream_source_dest(codec, 0x14, 0x48, 0x91);
6331 chipio_set_conn_rate_no_mutex(codec, 0x48, SR_96_000);
6332 chipio_set_conn_rate_no_mutex(codec, 0x91, SR_96_000);
6333 chipio_set_stream_channels(codec, 0x14, 2);
6334 chipio_set_stream_control(codec, 0x14, 1);
6335
6336 codec_dbg(codec, "Connect Streams exited, mutex released.\n");
6337
6338 mutex_unlock(&spec->chipio_mutex);
6339
6340 }
6341
6342 /*
6343 * Write data through ChipIO to setup proper stream destinations.
6344 * Not sure how it exactly works, but it seems to direct data
6345 * to different destinations. Example is f8 to c0, e0 to c0.
6346 * All I know is, if you don't set these, you get no sound.
6347 */
6348 static void sbz_chipio_startup_data(struct hda_codec *codec)
6349 {
6350 struct ca0132_spec *spec = codec->spec;
6351
6352 mutex_lock(&spec->chipio_mutex);
6353 codec_dbg(codec, "Startup Data entered, mutex locked and loaded.\n");
6354
6355 /* These control audio output */
6356 chipio_write_no_mutex(codec, 0x190060, 0x0001f8c0);
6357 chipio_write_no_mutex(codec, 0x190064, 0x0001f9c1);
6358 chipio_write_no_mutex(codec, 0x190068, 0x0001fac6);
6359 chipio_write_no_mutex(codec, 0x19006c, 0x0001fbc7);
6360 /* Signal to update I think */
6361 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6362
6363 chipio_set_stream_channels(codec, 0x0C, 6);
6364 chipio_set_stream_control(codec, 0x0C, 1);
6365 /* No clue what these control */
6366 chipio_write_no_mutex(codec, 0x190030, 0x0001e0c0);
6367 chipio_write_no_mutex(codec, 0x190034, 0x0001e1c1);
6368 chipio_write_no_mutex(codec, 0x190038, 0x0001e4c2);
6369 chipio_write_no_mutex(codec, 0x19003c, 0x0001e5c3);
6370 chipio_write_no_mutex(codec, 0x190040, 0x0001e2c4);
6371 chipio_write_no_mutex(codec, 0x190044, 0x0001e3c5);
6372 chipio_write_no_mutex(codec, 0x190048, 0x0001e8c6);
6373 chipio_write_no_mutex(codec, 0x19004c, 0x0001e9c7);
6374 chipio_write_no_mutex(codec, 0x190050, 0x0001ecc8);
6375 chipio_write_no_mutex(codec, 0x190054, 0x0001edc9);
6376 chipio_write_no_mutex(codec, 0x190058, 0x0001eaca);
6377 chipio_write_no_mutex(codec, 0x19005c, 0x0001ebcb);
6378
6379 chipio_write_no_mutex(codec, 0x19042c, 0x00000001);
6380
6381 codec_dbg(codec, "Startup Data exited, mutex released.\n");
6382 mutex_unlock(&spec->chipio_mutex);
6383 }
6384
6385 /*
6386 * Sound Blaster Z uses these after DSP is loaded. Weird SCP commands
6387 * without a 0x20 source like normal.
6388 */
6389 static void sbz_dsp_scp_startup(struct hda_codec *codec)
6390 {
6391 unsigned int tmp;
6392
6393 tmp = 0x00000003;
6394 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6395
6396 tmp = 0x00000000;
6397 dspio_set_uint_param_no_source(codec, 0x80, 0x0A, tmp);
6398
6399 tmp = 0x00000001;
6400 dspio_set_uint_param_no_source(codec, 0x80, 0x0B, tmp);
6401
6402 tmp = 0x00000004;
6403 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6404
6405 tmp = 0x00000005;
6406 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6407
6408 tmp = 0x00000000;
6409 dspio_set_uint_param_no_source(codec, 0x80, 0x0C, tmp);
6410
6411 }
6412
6413 static void sbz_dsp_initial_mic_setup(struct hda_codec *codec)
6414 {
6415 unsigned int tmp;
6416
6417 chipio_set_stream_control(codec, 0x03, 0);
6418 chipio_set_stream_control(codec, 0x04, 0);
6419
6420 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6421 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6422
6423 tmp = FLOAT_THREE;
6424 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6425
6426 chipio_set_stream_control(codec, 0x03, 1);
6427 chipio_set_stream_control(codec, 0x04, 1);
6428
6429 chipio_write(codec, 0x18b098, 0x0000000c);
6430 chipio_write(codec, 0x18b09C, 0x0000000c);
6431 }
6432
6433 /*
6434 * Setup default parameters for DSP
6435 */
6436 static void ca0132_setup_defaults(struct hda_codec *codec)
6437 {
6438 struct ca0132_spec *spec = codec->spec;
6439 unsigned int tmp;
6440 int num_fx;
6441 int idx, i;
6442
6443 if (spec->dsp_state != DSP_DOWNLOADED)
6444 return;
6445
6446 /* out, in effects + voicefx */
6447 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6448 for (idx = 0; idx < num_fx; idx++) {
6449 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6450 dspio_set_uint_param(codec, ca0132_effects[idx].mid,
6451 ca0132_effects[idx].reqs[i],
6452 ca0132_effects[idx].def_vals[i]);
6453 }
6454 }
6455
6456 /*remove DSP headroom*/
6457 tmp = FLOAT_ZERO;
6458 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6459
6460 /*set speaker EQ bypass attenuation*/
6461 dspio_set_uint_param(codec, 0x8f, 0x01, tmp);
6462
6463 /* set AMic1 and AMic2 as mono mic */
6464 tmp = FLOAT_ONE;
6465 dspio_set_uint_param(codec, 0x80, 0x00, tmp);
6466 dspio_set_uint_param(codec, 0x80, 0x01, tmp);
6467
6468 /* set AMic1 as CrystalVoice input */
6469 tmp = FLOAT_ONE;
6470 dspio_set_uint_param(codec, 0x80, 0x05, tmp);
6471
6472 /* set WUH source */
6473 tmp = FLOAT_TWO;
6474 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6475 }
6476
6477 /*
6478 * Setup default parameters for Recon3D/Recon3Di DSP.
6479 */
6480
6481 static void r3d_setup_defaults(struct hda_codec *codec)
6482 {
6483 struct ca0132_spec *spec = codec->spec;
6484 unsigned int tmp;
6485 int num_fx;
6486 int idx, i;
6487
6488 if (spec->dsp_state != DSP_DOWNLOADED)
6489 return;
6490
6491 r3d_dsp_scp_startup(codec);
6492
6493 r3d_dsp_initial_mic_setup(codec);
6494
6495 /*remove DSP headroom*/
6496 tmp = FLOAT_ZERO;
6497 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6498
6499 /* set WUH source */
6500 tmp = FLOAT_TWO;
6501 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6502 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6503
6504 /* Set speaker source? */
6505 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6506
6507 if (spec->quirk == QUIRK_R3DI)
6508 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADED);
6509
6510 /* Setup effect defaults */
6511 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6512 for (idx = 0; idx < num_fx; idx++) {
6513 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6514 dspio_set_uint_param(codec,
6515 ca0132_effects[idx].mid,
6516 ca0132_effects[idx].reqs[i],
6517 ca0132_effects[idx].def_vals[i]);
6518 }
6519 }
6520 }
6521
6522 /*
6523 * Setup default parameters for the Sound Blaster Z DSP. A lot more going on
6524 * than the Chromebook setup.
6525 */
6526 static void sbz_setup_defaults(struct hda_codec *codec)
6527 {
6528 struct ca0132_spec *spec = codec->spec;
6529 unsigned int tmp, stream_format;
6530 int num_fx;
6531 int idx, i;
6532
6533 if (spec->dsp_state != DSP_DOWNLOADED)
6534 return;
6535
6536 sbz_dsp_scp_startup(codec);
6537
6538 sbz_init_analog_mics(codec);
6539
6540 sbz_connect_streams(codec);
6541
6542 sbz_chipio_startup_data(codec);
6543
6544 chipio_set_stream_control(codec, 0x03, 1);
6545 chipio_set_stream_control(codec, 0x04, 1);
6546
6547 /*
6548 * Sets internal input loopback to off, used to have a switch to
6549 * enable input loopback, but turned out to be way too buggy.
6550 */
6551 tmp = FLOAT_ONE;
6552 dspio_set_uint_param(codec, 0x37, 0x08, tmp);
6553 dspio_set_uint_param(codec, 0x37, 0x10, tmp);
6554
6555 /*remove DSP headroom*/
6556 tmp = FLOAT_ZERO;
6557 dspio_set_uint_param(codec, 0x96, 0x3C, tmp);
6558
6559 /* set WUH source */
6560 tmp = FLOAT_TWO;
6561 dspio_set_uint_param(codec, 0x31, 0x00, tmp);
6562 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6563
6564 /* Set speaker source? */
6565 dspio_set_uint_param(codec, 0x32, 0x00, tmp);
6566
6567 sbz_dsp_initial_mic_setup(codec);
6568
6569
6570 /* out, in effects + voicefx */
6571 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT + 1;
6572 for (idx = 0; idx < num_fx; idx++) {
6573 for (i = 0; i <= ca0132_effects[idx].params; i++) {
6574 dspio_set_uint_param(codec,
6575 ca0132_effects[idx].mid,
6576 ca0132_effects[idx].reqs[i],
6577 ca0132_effects[idx].def_vals[i]);
6578 }
6579 }
6580
6581 /*
6582 * Have to make a stream to bind the sound output to, otherwise
6583 * you'll get dead audio. Before I did this, it would bind to an
6584 * audio input, and would never work
6585 */
6586 stream_format = snd_hdac_calc_stream_format(48000, 2,
6587 SNDRV_PCM_FORMAT_S32_LE, 32, 0);
6588
6589 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6590 0, stream_format);
6591
6592 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6593
6594 snd_hda_codec_setup_stream(codec, spec->dacs[0], spec->dsp_stream_id,
6595 0, stream_format);
6596
6597 snd_hda_codec_cleanup_stream(codec, spec->dacs[0]);
6598 }
6599
6600 /*
6601 * Initialization of flags in chip
6602 */
6603 static void ca0132_init_flags(struct hda_codec *codec)
6604 {
6605 struct ca0132_spec *spec = codec->spec;
6606
6607 if (spec->use_alt_functions) {
6608 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, 1);
6609 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, 1);
6610 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, 1);
6611 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, 1);
6612 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, 1);
6613 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6614 chipio_set_control_flag(codec, CONTROL_FLAG_SPDIF2OUT, 0);
6615 chipio_set_control_flag(codec,
6616 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6617 chipio_set_control_flag(codec,
6618 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 1);
6619 } else {
6620 chipio_set_control_flag(codec, CONTROL_FLAG_IDLE_ENABLE, 0);
6621 chipio_set_control_flag(codec,
6622 CONTROL_FLAG_PORT_A_COMMON_MODE, 0);
6623 chipio_set_control_flag(codec,
6624 CONTROL_FLAG_PORT_D_COMMON_MODE, 0);
6625 chipio_set_control_flag(codec,
6626 CONTROL_FLAG_PORT_A_10KOHM_LOAD, 0);
6627 chipio_set_control_flag(codec,
6628 CONTROL_FLAG_PORT_D_10KOHM_LOAD, 0);
6629 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_HIGH_PASS, 1);
6630 }
6631 }
6632
6633 /*
6634 * Initialization of parameters in chip
6635 */
6636 static void ca0132_init_params(struct hda_codec *codec)
6637 {
6638 struct ca0132_spec *spec = codec->spec;
6639
6640 if (spec->use_alt_functions) {
6641 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6642 chipio_set_conn_rate(codec, 0x0B, SR_48_000);
6643 chipio_set_control_param(codec, CONTROL_PARAM_SPDIF1_SOURCE, 0);
6644 chipio_set_control_param(codec, 0, 0);
6645 chipio_set_control_param(codec, CONTROL_PARAM_VIP_SOURCE, 0);
6646 }
6647
6648 chipio_set_control_param(codec, CONTROL_PARAM_PORTA_160OHM_GAIN, 6);
6649 chipio_set_control_param(codec, CONTROL_PARAM_PORTD_160OHM_GAIN, 6);
6650 }
6651
6652 static void ca0132_set_dsp_msr(struct hda_codec *codec, bool is96k)
6653 {
6654 chipio_set_control_flag(codec, CONTROL_FLAG_DSP_96KHZ, is96k);
6655 chipio_set_control_flag(codec, CONTROL_FLAG_DAC_96KHZ, is96k);
6656 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_RATE_96KHZ, is96k);
6657 chipio_set_control_flag(codec, CONTROL_FLAG_SRC_CLOCK_196MHZ, is96k);
6658 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_B_96KHZ, is96k);
6659 chipio_set_control_flag(codec, CONTROL_FLAG_ADC_C_96KHZ, is96k);
6660
6661 chipio_set_conn_rate(codec, MEM_CONNID_MICIN1, SR_96_000);
6662 chipio_set_conn_rate(codec, MEM_CONNID_MICOUT1, SR_96_000);
6663 chipio_set_conn_rate(codec, MEM_CONNID_WUH, SR_48_000);
6664 }
6665
6666 static bool ca0132_download_dsp_images(struct hda_codec *codec)
6667 {
6668 bool dsp_loaded = false;
6669 struct ca0132_spec *spec = codec->spec;
6670 const struct dsp_image_seg *dsp_os_image;
6671 const struct firmware *fw_entry;
6672 /*
6673 * Alternate firmwares for different variants. The Recon3Di apparently
6674 * can use the default firmware, but I'll leave the option in case
6675 * it needs it again.
6676 */
6677 switch (spec->quirk) {
6678 case QUIRK_SBZ:
6679 if (request_firmware(&fw_entry, SBZ_EFX_FILE,
6680 codec->card->dev) != 0) {
6681 codec_dbg(codec, "SBZ alt firmware not detected. ");
6682 spec->alt_firmware_present = false;
6683 } else {
6684 codec_dbg(codec, "Sound Blaster Z firmware selected.");
6685 spec->alt_firmware_present = true;
6686 }
6687 break;
6688 case QUIRK_R3DI:
6689 if (request_firmware(&fw_entry, R3DI_EFX_FILE,
6690 codec->card->dev) != 0) {
6691 codec_dbg(codec, "Recon3Di alt firmware not detected.");
6692 spec->alt_firmware_present = false;
6693 } else {
6694 codec_dbg(codec, "Recon3Di firmware selected.");
6695 spec->alt_firmware_present = true;
6696 }
6697 break;
6698 default:
6699 spec->alt_firmware_present = false;
6700 break;
6701 }
6702 /*
6703 * Use default ctefx.bin if no alt firmware is detected, or if none
6704 * exists for your particular codec.
6705 */
6706 if (!spec->alt_firmware_present) {
6707 codec_dbg(codec, "Default firmware selected.");
6708 if (request_firmware(&fw_entry, EFX_FILE,
6709 codec->card->dev) != 0)
6710 return false;
6711 }
6712
6713 dsp_os_image = (struct dsp_image_seg *)(fw_entry->data);
6714 if (dspload_image(codec, dsp_os_image, 0, 0, true, 0)) {
6715 codec_err(codec, "ca0132 DSP load image failed\n");
6716 goto exit_download;
6717 }
6718
6719 dsp_loaded = dspload_wait_loaded(codec);
6720
6721 exit_download:
6722 release_firmware(fw_entry);
6723
6724 return dsp_loaded;
6725 }
6726
6727 static void ca0132_download_dsp(struct hda_codec *codec)
6728 {
6729 struct ca0132_spec *spec = codec->spec;
6730
6731 #ifndef CONFIG_SND_HDA_CODEC_CA0132_DSP
6732 return; /* NOP */
6733 #endif
6734
6735 if (spec->dsp_state == DSP_DOWNLOAD_FAILED)
6736 return; /* don't retry failures */
6737
6738 chipio_enable_clocks(codec);
6739 if (spec->dsp_state != DSP_DOWNLOADED) {
6740 spec->dsp_state = DSP_DOWNLOADING;
6741
6742 if (!ca0132_download_dsp_images(codec))
6743 spec->dsp_state = DSP_DOWNLOAD_FAILED;
6744 else
6745 spec->dsp_state = DSP_DOWNLOADED;
6746 }
6747
6748 /* For codecs using alt functions, this is already done earlier */
6749 if (spec->dsp_state == DSP_DOWNLOADED && (!spec->use_alt_functions))
6750 ca0132_set_dsp_msr(codec, true);
6751 }
6752
6753 static void ca0132_process_dsp_response(struct hda_codec *codec,
6754 struct hda_jack_callback *callback)
6755 {
6756 struct ca0132_spec *spec = codec->spec;
6757
6758 codec_dbg(codec, "ca0132_process_dsp_response\n");
6759 snd_hda_power_up_pm(codec);
6760 if (spec->wait_scp) {
6761 if (dspio_get_response_data(codec) >= 0)
6762 spec->wait_scp = 0;
6763 }
6764
6765 dspio_clear_response_queue(codec);
6766 snd_hda_power_down_pm(codec);
6767 }
6768
6769 static void hp_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6770 {
6771 struct ca0132_spec *spec = codec->spec;
6772 struct hda_jack_tbl *tbl;
6773
6774 /* Delay enabling the HP amp, to let the mic-detection
6775 * state machine run.
6776 */
6777 tbl = snd_hda_jack_tbl_get(codec, cb->nid);
6778 if (tbl)
6779 tbl->block_report = 1;
6780 schedule_delayed_work(&spec->unsol_hp_work, msecs_to_jiffies(500));
6781 }
6782
6783 static void amic_callback(struct hda_codec *codec, struct hda_jack_callback *cb)
6784 {
6785 struct ca0132_spec *spec = codec->spec;
6786
6787 if (spec->use_alt_functions)
6788 ca0132_alt_select_in(codec);
6789 else
6790 ca0132_select_mic(codec);
6791 }
6792
6793 static void ca0132_init_unsol(struct hda_codec *codec)
6794 {
6795 struct ca0132_spec *spec = codec->spec;
6796 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_hp, hp_callback);
6797 snd_hda_jack_detect_enable_callback(codec, spec->unsol_tag_amic1,
6798 amic_callback);
6799 snd_hda_jack_detect_enable_callback(codec, UNSOL_TAG_DSP,
6800 ca0132_process_dsp_response);
6801 /* Front headphone jack detection */
6802 if (spec->use_alt_functions)
6803 snd_hda_jack_detect_enable_callback(codec,
6804 spec->unsol_tag_front_hp, hp_callback);
6805 }
6806
6807 /*
6808 * Verbs tables.
6809 */
6810
6811 /* Sends before DSP download. */
6812 static struct hda_verb ca0132_base_init_verbs[] = {
6813 /*enable ct extension*/
6814 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0x1},
6815 {}
6816 };
6817
6818 /* Send at exit. */
6819 static struct hda_verb ca0132_base_exit_verbs[] = {
6820 /*set afg to D3*/
6821 {0x01, AC_VERB_SET_POWER_STATE, 0x03},
6822 /*disable ct extension*/
6823 {0x15, VENDOR_CHIPIO_CT_EXTENSIONS_ENABLE, 0},
6824 {}
6825 };
6826
6827 /* Other verbs tables. Sends after DSP download. */
6828
6829 static struct hda_verb ca0132_init_verbs0[] = {
6830 /* chip init verbs */
6831 {0x15, 0x70D, 0xF0},
6832 {0x15, 0x70E, 0xFE},
6833 {0x15, 0x707, 0x75},
6834 {0x15, 0x707, 0xD3},
6835 {0x15, 0x707, 0x09},
6836 {0x15, 0x707, 0x53},
6837 {0x15, 0x707, 0xD4},
6838 {0x15, 0x707, 0xEF},
6839 {0x15, 0x707, 0x75},
6840 {0x15, 0x707, 0xD3},
6841 {0x15, 0x707, 0x09},
6842 {0x15, 0x707, 0x02},
6843 {0x15, 0x707, 0x37},
6844 {0x15, 0x707, 0x78},
6845 {0x15, 0x53C, 0xCE},
6846 {0x15, 0x575, 0xC9},
6847 {0x15, 0x53D, 0xCE},
6848 {0x15, 0x5B7, 0xC9},
6849 {0x15, 0x70D, 0xE8},
6850 {0x15, 0x70E, 0xFE},
6851 {0x15, 0x707, 0x02},
6852 {0x15, 0x707, 0x68},
6853 {0x15, 0x707, 0x62},
6854 {0x15, 0x53A, 0xCE},
6855 {0x15, 0x546, 0xC9},
6856 {0x15, 0x53B, 0xCE},
6857 {0x15, 0x5E8, 0xC9},
6858 {}
6859 };
6860
6861 /* Extra init verbs for desktop cards. */
6862 static struct hda_verb ca0132_init_verbs1[] = {
6863 {0x15, 0x70D, 0x20},
6864 {0x15, 0x70E, 0x19},
6865 {0x15, 0x707, 0x00},
6866 {0x15, 0x539, 0xCE},
6867 {0x15, 0x546, 0xC9},
6868 {0x15, 0x70D, 0xB7},
6869 {0x15, 0x70E, 0x09},
6870 {0x15, 0x707, 0x10},
6871 {0x15, 0x70D, 0xAF},
6872 {0x15, 0x70E, 0x09},
6873 {0x15, 0x707, 0x01},
6874 {0x15, 0x707, 0x05},
6875 {0x15, 0x70D, 0x73},
6876 {0x15, 0x70E, 0x09},
6877 {0x15, 0x707, 0x14},
6878 {0x15, 0x6FF, 0xC4},
6879 {}
6880 };
6881
6882 static void ca0132_init_chip(struct hda_codec *codec)
6883 {
6884 struct ca0132_spec *spec = codec->spec;
6885 int num_fx;
6886 int i;
6887 unsigned int on;
6888
6889 mutex_init(&spec->chipio_mutex);
6890
6891 spec->cur_out_type = SPEAKER_OUT;
6892 if (!spec->use_alt_functions)
6893 spec->cur_mic_type = DIGITAL_MIC;
6894 else
6895 spec->cur_mic_type = REAR_MIC;
6896
6897 spec->cur_mic_boost = 0;
6898
6899 for (i = 0; i < VNODES_COUNT; i++) {
6900 spec->vnode_lvol[i] = 0x5a;
6901 spec->vnode_rvol[i] = 0x5a;
6902 spec->vnode_lswitch[i] = 0;
6903 spec->vnode_rswitch[i] = 0;
6904 }
6905
6906 /*
6907 * Default states for effects are in ca0132_effects[].
6908 */
6909 num_fx = OUT_EFFECTS_COUNT + IN_EFFECTS_COUNT;
6910 for (i = 0; i < num_fx; i++) {
6911 on = (unsigned int)ca0132_effects[i].reqs[0];
6912 spec->effects_switch[i] = on ? 1 : 0;
6913 }
6914 /*
6915 * Sets defaults for the effect slider controls, only for alternative
6916 * ca0132 codecs. Also sets x-bass crossover frequency to 80hz.
6917 */
6918 if (spec->use_alt_controls) {
6919 spec->xbass_xover_freq = 8;
6920 for (i = 0; i < EFFECT_LEVEL_SLIDERS; i++)
6921 spec->fx_ctl_val[i] = effect_slider_defaults[i];
6922 }
6923
6924 spec->voicefx_val = 0;
6925 spec->effects_switch[PLAY_ENHANCEMENT - EFFECT_START_NID] = 1;
6926 spec->effects_switch[CRYSTAL_VOICE - EFFECT_START_NID] = 0;
6927
6928 #ifdef ENABLE_TUNING_CONTROLS
6929 ca0132_init_tuning_defaults(codec);
6930 #endif
6931 }
6932
6933 /*
6934 * Recon3Di exit specific commands.
6935 */
6936 /* prevents popping noise on shutdown */
6937 static void r3di_gpio_shutdown(struct hda_codec *codec)
6938 {
6939 snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA, 0x00);
6940 }
6941
6942 /*
6943 * Sound Blaster Z exit specific commands.
6944 */
6945 static void sbz_region2_exit(struct hda_codec *codec)
6946 {
6947 struct ca0132_spec *spec = codec->spec;
6948 unsigned int i;
6949
6950 for (i = 0; i < 4; i++)
6951 writeb(0x0, spec->mem_base + 0x100);
6952 for (i = 0; i < 8; i++)
6953 writeb(0xb3, spec->mem_base + 0x304);
6954
6955 ca0132_mmio_gpio_set(codec, 0, false);
6956 ca0132_mmio_gpio_set(codec, 1, false);
6957 ca0132_mmio_gpio_set(codec, 4, true);
6958 ca0132_mmio_gpio_set(codec, 5, false);
6959 ca0132_mmio_gpio_set(codec, 7, false);
6960 }
6961
6962 static void sbz_set_pin_ctl_default(struct hda_codec *codec)
6963 {
6964 hda_nid_t pins[5] = {0x0B, 0x0C, 0x0E, 0x12, 0x13};
6965 unsigned int i;
6966
6967 snd_hda_codec_write(codec, 0x11, 0,
6968 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x40);
6969
6970 for (i = 0; i < 5; i++)
6971 snd_hda_codec_write(codec, pins[i], 0,
6972 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x00);
6973 }
6974
6975 static void ca0132_clear_unsolicited(struct hda_codec *codec)
6976 {
6977 hda_nid_t pins[7] = {0x0B, 0x0E, 0x0F, 0x10, 0x11, 0x12, 0x13};
6978 unsigned int i;
6979
6980 for (i = 0; i < 7; i++) {
6981 snd_hda_codec_write(codec, pins[i], 0,
6982 AC_VERB_SET_UNSOLICITED_ENABLE, 0x00);
6983 }
6984 }
6985
6986 /* On shutdown, sends commands in sets of three */
6987 static void sbz_gpio_shutdown_commands(struct hda_codec *codec, int dir,
6988 int mask, int data)
6989 {
6990 if (dir >= 0)
6991 snd_hda_codec_write(codec, 0x01, 0,
6992 AC_VERB_SET_GPIO_DIRECTION, dir);
6993 if (mask >= 0)
6994 snd_hda_codec_write(codec, 0x01, 0,
6995 AC_VERB_SET_GPIO_MASK, mask);
6996
6997 if (data >= 0)
6998 snd_hda_codec_write(codec, 0x01, 0,
6999 AC_VERB_SET_GPIO_DATA, data);
7000 }
7001
7002 static void sbz_exit_chip(struct hda_codec *codec)
7003 {
7004 chipio_set_stream_control(codec, 0x03, 0);
7005 chipio_set_stream_control(codec, 0x04, 0);
7006
7007 /* Mess with GPIO */
7008 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, -1);
7009 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x05);
7010 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x01);
7011
7012 chipio_set_stream_control(codec, 0x14, 0);
7013 chipio_set_stream_control(codec, 0x0C, 0);
7014
7015 chipio_set_conn_rate(codec, 0x41, SR_192_000);
7016 chipio_set_conn_rate(codec, 0x91, SR_192_000);
7017
7018 chipio_write(codec, 0x18a020, 0x00000083);
7019
7020 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x03);
7021 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x07);
7022 sbz_gpio_shutdown_commands(codec, 0x07, 0x07, 0x06);
7023
7024 chipio_set_stream_control(codec, 0x0C, 0);
7025
7026 chipio_set_control_param(codec, 0x0D, 0x24);
7027
7028 ca0132_clear_unsolicited(codec);
7029 sbz_set_pin_ctl_default(codec);
7030
7031 snd_hda_codec_write(codec, 0x0B, 0,
7032 AC_VERB_SET_EAPD_BTLENABLE, 0x00);
7033
7034 sbz_region2_exit(codec);
7035 }
7036
7037 static void r3d_exit_chip(struct hda_codec *codec)
7038 {
7039 ca0132_clear_unsolicited(codec);
7040 snd_hda_codec_write(codec, 0x01, 0, 0x793, 0x00);
7041 snd_hda_codec_write(codec, 0x01, 0, 0x794, 0x5b);
7042 }
7043
7044 static void ca0132_exit_chip(struct hda_codec *codec)
7045 {
7046 /* put any chip cleanup stuffs here. */
7047
7048 if (dspload_is_loaded(codec))
7049 dsp_reset(codec);
7050 }
7051
7052 /*
7053 * This fixes a problem that was hard to reproduce. Very rarely, I would
7054 * boot up, and there would be no sound, but the DSP indicated it had loaded
7055 * properly. I did a few memory dumps to see if anything was different, and
7056 * there were a few areas of memory uninitialized with a1a2a3a4. This function
7057 * checks if those areas are uninitialized, and if they are, it'll attempt to
7058 * reload the card 3 times. Usually it fixes by the second.
7059 */
7060 static void sbz_dsp_startup_check(struct hda_codec *codec)
7061 {
7062 struct ca0132_spec *spec = codec->spec;
7063 unsigned int dsp_data_check[4];
7064 unsigned int cur_address = 0x390;
7065 unsigned int i;
7066 unsigned int failure = 0;
7067 unsigned int reload = 3;
7068
7069 if (spec->startup_check_entered)
7070 return;
7071
7072 spec->startup_check_entered = true;
7073
7074 for (i = 0; i < 4; i++) {
7075 chipio_read(codec, cur_address, &dsp_data_check[i]);
7076 cur_address += 0x4;
7077 }
7078 for (i = 0; i < 4; i++) {
7079 if (dsp_data_check[i] == 0xa1a2a3a4)
7080 failure = 1;
7081 }
7082
7083 codec_dbg(codec, "Startup Check: %d ", failure);
7084 if (failure)
7085 codec_info(codec, "DSP not initialized properly. Attempting to fix.");
7086 /*
7087 * While the failure condition is true, and we haven't reached our
7088 * three reload limit, continue trying to reload the driver and
7089 * fix the issue.
7090 */
7091 while (failure && (reload != 0)) {
7092 codec_info(codec, "Reloading... Tries left: %d", reload);
7093 sbz_exit_chip(codec);
7094 spec->dsp_state = DSP_DOWNLOAD_INIT;
7095 codec->patch_ops.init(codec);
7096 failure = 0;
7097 for (i = 0; i < 4; i++) {
7098 chipio_read(codec, cur_address, &dsp_data_check[i]);
7099 cur_address += 0x4;
7100 }
7101 for (i = 0; i < 4; i++) {
7102 if (dsp_data_check[i] == 0xa1a2a3a4)
7103 failure = 1;
7104 }
7105 reload--;
7106 }
7107
7108 if (!failure && reload < 3)
7109 codec_info(codec, "DSP fixed.");
7110
7111 if (!failure)
7112 return;
7113
7114 codec_info(codec, "DSP failed to initialize properly. Either try a full shutdown or a suspend to clear the internal memory.");
7115 }
7116
7117 /*
7118 * This is for the extra volume verbs 0x797 (left) and 0x798 (right). These add
7119 * extra precision for decibel values. If you had the dB value in floating point
7120 * you would take the value after the decimal point, multiply by 64, and divide
7121 * by 2. So for 8.59, it's (59 * 64) / 100. Useful if someone wanted to
7122 * implement fixed point or floating point dB volumes. For now, I'll set them
7123 * to 0 just incase a value has lingered from a boot into Windows.
7124 */
7125 static void ca0132_alt_vol_setup(struct hda_codec *codec)
7126 {
7127 snd_hda_codec_write(codec, 0x02, 0, 0x797, 0x00);
7128 snd_hda_codec_write(codec, 0x02, 0, 0x798, 0x00);
7129 snd_hda_codec_write(codec, 0x03, 0, 0x797, 0x00);
7130 snd_hda_codec_write(codec, 0x03, 0, 0x798, 0x00);
7131 snd_hda_codec_write(codec, 0x04, 0, 0x797, 0x00);
7132 snd_hda_codec_write(codec, 0x04, 0, 0x798, 0x00);
7133 snd_hda_codec_write(codec, 0x07, 0, 0x797, 0x00);
7134 snd_hda_codec_write(codec, 0x07, 0, 0x798, 0x00);
7135 }
7136
7137 /*
7138 * Extra commands that don't really fit anywhere else.
7139 */
7140 static void sbz_pre_dsp_setup(struct hda_codec *codec)
7141 {
7142 struct ca0132_spec *spec = codec->spec;
7143
7144 writel(0x00820680, spec->mem_base + 0x01C);
7145 writel(0x00820680, spec->mem_base + 0x01C);
7146
7147 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7148 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7149 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7150 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7151
7152 chipio_write(codec, 0x18b0a4, 0x000000c2);
7153
7154 snd_hda_codec_write(codec, 0x11, 0,
7155 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7156 }
7157
7158 static void r3d_pre_dsp_setup(struct hda_codec *codec)
7159 {
7160
7161 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfc);
7162 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfd);
7163 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xfe);
7164 snd_hda_codec_write(codec, 0x15, 0, 0xd00, 0xff);
7165
7166 chipio_write(codec, 0x18b0a4, 0x000000c2);
7167
7168 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7169 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7170 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7171 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7172 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7173 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7174
7175 snd_hda_codec_write(codec, 0x11, 0,
7176 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x44);
7177 }
7178
7179 static void r3di_pre_dsp_setup(struct hda_codec *codec)
7180 {
7181 chipio_write(codec, 0x18b0a4, 0x000000c2);
7182
7183 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7184 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x1E);
7185 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7186 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x1C);
7187 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7188 VENDOR_CHIPIO_8051_DATA_WRITE, 0x5B);
7189
7190 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7191 VENDOR_CHIPIO_8051_ADDRESS_LOW, 0x20);
7192 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7193 VENDOR_CHIPIO_8051_ADDRESS_HIGH, 0x19);
7194 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7195 VENDOR_CHIPIO_8051_DATA_WRITE, 0x00);
7196 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7197 VENDOR_CHIPIO_8051_DATA_WRITE, 0x40);
7198
7199 snd_hda_codec_write(codec, 0x11, 0,
7200 AC_VERB_SET_PIN_WIDGET_CONTROL, 0x04);
7201 }
7202
7203 /*
7204 * These are sent before the DSP is downloaded. Not sure
7205 * what they do, or if they're necessary. Could possibly
7206 * be removed. Figure they're better to leave in.
7207 */
7208 static void ca0132_mmio_init(struct hda_codec *codec)
7209 {
7210 struct ca0132_spec *spec = codec->spec;
7211
7212 writel(0x00000000, spec->mem_base + 0x400);
7213 writel(0x00000000, spec->mem_base + 0x408);
7214 writel(0x00000000, spec->mem_base + 0x40C);
7215 writel(0x00880680, spec->mem_base + 0x01C);
7216 writel(0x00000083, spec->mem_base + 0xC0C);
7217 writel(0x00000030, spec->mem_base + 0xC00);
7218 writel(0x00000000, spec->mem_base + 0xC04);
7219 writel(0x00000003, spec->mem_base + 0xC0C);
7220 writel(0x00000003, spec->mem_base + 0xC0C);
7221 writel(0x00000003, spec->mem_base + 0xC0C);
7222 writel(0x00000003, spec->mem_base + 0xC0C);
7223 writel(0x000000C1, spec->mem_base + 0xC08);
7224 writel(0x000000F1, spec->mem_base + 0xC08);
7225 writel(0x00000001, spec->mem_base + 0xC08);
7226 writel(0x000000C7, spec->mem_base + 0xC08);
7227 writel(0x000000C1, spec->mem_base + 0xC08);
7228 writel(0x00000080, spec->mem_base + 0xC04);
7229 }
7230
7231 /*
7232 * Extra init functions for alternative ca0132 codecs. Done
7233 * here so they don't clutter up the main ca0132_init function
7234 * anymore than they have to.
7235 */
7236 static void ca0132_alt_init(struct hda_codec *codec)
7237 {
7238 struct ca0132_spec *spec = codec->spec;
7239
7240 ca0132_alt_vol_setup(codec);
7241
7242 switch (spec->quirk) {
7243 case QUIRK_SBZ:
7244 codec_dbg(codec, "SBZ alt_init");
7245 ca0132_gpio_init(codec);
7246 sbz_pre_dsp_setup(codec);
7247 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7248 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7249 break;
7250 case QUIRK_R3DI:
7251 codec_dbg(codec, "R3DI alt_init");
7252 ca0132_gpio_init(codec);
7253 ca0132_gpio_setup(codec);
7254 r3di_gpio_dsp_status_set(codec, R3DI_DSP_DOWNLOADING);
7255 r3di_pre_dsp_setup(codec);
7256 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7257 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0, 0x6FF, 0xC4);
7258 break;
7259 case QUIRK_R3D:
7260 r3d_pre_dsp_setup(codec);
7261 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7262 snd_hda_sequence_write(codec, spec->desktop_init_verbs);
7263 break;
7264 }
7265 }
7266
7267 static int ca0132_init(struct hda_codec *codec)
7268 {
7269 struct ca0132_spec *spec = codec->spec;
7270 struct auto_pin_cfg *cfg = &spec->autocfg;
7271 int i;
7272 bool dsp_loaded;
7273
7274 /*
7275 * If the DSP is already downloaded, and init has been entered again,
7276 * there's only two reasons for it. One, the codec has awaken from a
7277 * suspended state, and in that case dspload_is_loaded will return
7278 * false, and the init will be ran again. The other reason it gets
7279 * re entered is on startup for some reason it triggers a suspend and
7280 * resume state. In this case, it will check if the DSP is downloaded,
7281 * and not run the init function again. For codecs using alt_functions,
7282 * it will check if the DSP is loaded properly.
7283 */
7284 if (spec->dsp_state == DSP_DOWNLOADED) {
7285 dsp_loaded = dspload_is_loaded(codec);
7286 if (!dsp_loaded) {
7287 spec->dsp_reload = true;
7288 spec->dsp_state = DSP_DOWNLOAD_INIT;
7289 } else {
7290 if (spec->quirk == QUIRK_SBZ)
7291 sbz_dsp_startup_check(codec);
7292 return 0;
7293 }
7294 }
7295
7296 if (spec->dsp_state != DSP_DOWNLOAD_FAILED)
7297 spec->dsp_state = DSP_DOWNLOAD_INIT;
7298 spec->curr_chip_addx = INVALID_CHIP_ADDRESS;
7299
7300 if (spec->use_pci_mmio)
7301 ca0132_mmio_init(codec);
7302
7303 snd_hda_power_up_pm(codec);
7304
7305 ca0132_init_unsol(codec);
7306 ca0132_init_params(codec);
7307 ca0132_init_flags(codec);
7308
7309 snd_hda_sequence_write(codec, spec->base_init_verbs);
7310
7311 if (spec->use_alt_functions)
7312 ca0132_alt_init(codec);
7313
7314 ca0132_download_dsp(codec);
7315
7316 ca0132_refresh_widget_caps(codec);
7317
7318 switch (spec->quirk) {
7319 case QUIRK_R3DI:
7320 case QUIRK_R3D:
7321 r3d_setup_defaults(codec);
7322 break;
7323 case QUIRK_SBZ:
7324 sbz_setup_defaults(codec);
7325 break;
7326 default:
7327 ca0132_setup_defaults(codec);
7328 ca0132_init_analog_mic2(codec);
7329 ca0132_init_dmic(codec);
7330 break;
7331 }
7332
7333 for (i = 0; i < spec->num_outputs; i++)
7334 init_output(codec, spec->out_pins[i], spec->dacs[0]);
7335
7336 init_output(codec, cfg->dig_out_pins[0], spec->dig_out);
7337
7338 for (i = 0; i < spec->num_inputs; i++)
7339 init_input(codec, spec->input_pins[i], spec->adcs[i]);
7340
7341 init_input(codec, cfg->dig_in_pin, spec->dig_in);
7342
7343 if (!spec->use_alt_functions) {
7344 snd_hda_sequence_write(codec, spec->chip_init_verbs);
7345 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7346 VENDOR_CHIPIO_PARAM_EX_ID_SET, 0x0D);
7347 snd_hda_codec_write(codec, WIDGET_CHIP_CTRL, 0,
7348 VENDOR_CHIPIO_PARAM_EX_VALUE_SET, 0x20);
7349 }
7350
7351 if (spec->quirk == QUIRK_SBZ)
7352 ca0132_gpio_setup(codec);
7353
7354 snd_hda_sequence_write(codec, spec->spec_init_verbs);
7355 if (spec->use_alt_functions) {
7356 ca0132_alt_select_out(codec);
7357 ca0132_alt_select_in(codec);
7358 } else {
7359 ca0132_select_out(codec);
7360 ca0132_select_mic(codec);
7361 }
7362
7363 snd_hda_jack_report_sync(codec);
7364
7365 /*
7366 * Re set the PlayEnhancement switch on a resume event, because the
7367 * controls will not be reloaded.
7368 */
7369 if (spec->dsp_reload) {
7370 spec->dsp_reload = false;
7371 ca0132_pe_switch_set(codec);
7372 }
7373
7374 snd_hda_power_down_pm(codec);
7375
7376 return 0;
7377 }
7378
7379 static void ca0132_free(struct hda_codec *codec)
7380 {
7381 struct ca0132_spec *spec = codec->spec;
7382
7383 cancel_delayed_work_sync(&spec->unsol_hp_work);
7384 snd_hda_power_up(codec);
7385 switch (spec->quirk) {
7386 case QUIRK_SBZ:
7387 sbz_exit_chip(codec);
7388 break;
7389 case QUIRK_R3D:
7390 r3d_exit_chip(codec);
7391 break;
7392 case QUIRK_R3DI:
7393 r3di_gpio_shutdown(codec);
7394 break;
7395 }
7396
7397 snd_hda_sequence_write(codec, spec->base_exit_verbs);
7398 ca0132_exit_chip(codec);
7399
7400 snd_hda_power_down(codec);
7401 #ifdef CONFIG_PCI
7402 if (spec->mem_base)
7403 pci_iounmap(codec->bus->pci, spec->mem_base);
7404 #endif
7405 kfree(spec->spec_init_verbs);
7406 kfree(codec->spec);
7407 }
7408
7409 static void ca0132_reboot_notify(struct hda_codec *codec)
7410 {
7411 codec->patch_ops.free(codec);
7412 }
7413
7414 #ifdef CONFIG_PM
7415 static int ca0132_suspend(struct hda_codec *codec)
7416 {
7417 struct ca0132_spec *spec = codec->spec;
7418
7419 cancel_delayed_work_sync(&spec->unsol_hp_work);
7420 return 0;
7421 }
7422 #endif
7423
7424 static const struct hda_codec_ops ca0132_patch_ops = {
7425 .build_controls = ca0132_build_controls,
7426 .build_pcms = ca0132_build_pcms,
7427 .init = ca0132_init,
7428 .free = ca0132_free,
7429 .unsol_event = snd_hda_jack_unsol_event,
7430 #ifdef CONFIG_PM
7431 .suspend = ca0132_suspend,
7432 #endif
7433 .reboot_notify = ca0132_reboot_notify,
7434 };
7435
7436 static void ca0132_config(struct hda_codec *codec)
7437 {
7438 struct ca0132_spec *spec = codec->spec;
7439
7440 spec->dacs[0] = 0x2;
7441 spec->dacs[1] = 0x3;
7442 spec->dacs[2] = 0x4;
7443
7444 spec->multiout.dac_nids = spec->dacs;
7445 spec->multiout.num_dacs = 3;
7446
7447 if (!spec->use_alt_functions)
7448 spec->multiout.max_channels = 2;
7449 else
7450 spec->multiout.max_channels = 6;
7451
7452 switch (spec->quirk) {
7453 case QUIRK_ALIENWARE:
7454 codec_dbg(codec, "ca0132_config: QUIRK_ALIENWARE applied.\n");
7455 snd_hda_apply_pincfgs(codec, alienware_pincfgs);
7456
7457 spec->num_outputs = 2;
7458 spec->out_pins[0] = 0x0b; /* speaker out */
7459 spec->out_pins[1] = 0x0f;
7460 spec->shared_out_nid = 0x2;
7461 spec->unsol_tag_hp = 0x0f;
7462
7463 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7464 spec->adcs[1] = 0x8; /* analog mic2 */
7465 spec->adcs[2] = 0xa; /* what u hear */
7466
7467 spec->num_inputs = 3;
7468 spec->input_pins[0] = 0x12;
7469 spec->input_pins[1] = 0x11;
7470 spec->input_pins[2] = 0x13;
7471 spec->shared_mic_nid = 0x7;
7472 spec->unsol_tag_amic1 = 0x11;
7473 break;
7474 case QUIRK_SBZ:
7475 case QUIRK_R3D:
7476 if (spec->quirk == QUIRK_SBZ) {
7477 codec_dbg(codec, "%s: QUIRK_SBZ applied.\n", __func__);
7478 snd_hda_apply_pincfgs(codec, sbz_pincfgs);
7479 }
7480 if (spec->quirk == QUIRK_R3D) {
7481 codec_dbg(codec, "%s: QUIRK_R3D applied.\n", __func__);
7482 snd_hda_apply_pincfgs(codec, r3d_pincfgs);
7483 }
7484
7485 spec->num_outputs = 2;
7486 spec->out_pins[0] = 0x0B; /* Line out */
7487 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7488 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7489 spec->out_pins[3] = 0x11; /* Rear surround */
7490 spec->shared_out_nid = 0x2;
7491 spec->unsol_tag_hp = spec->out_pins[1];
7492 spec->unsol_tag_front_hp = spec->out_pins[2];
7493
7494 spec->adcs[0] = 0x7; /* Rear Mic / Line-in */
7495 spec->adcs[1] = 0x8; /* Front Mic, but only if no DSP */
7496 spec->adcs[2] = 0xa; /* what u hear */
7497
7498 spec->num_inputs = 2;
7499 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7500 spec->input_pins[1] = 0x13; /* What U Hear */
7501 spec->shared_mic_nid = 0x7;
7502 spec->unsol_tag_amic1 = spec->input_pins[0];
7503
7504 /* SPDIF I/O */
7505 spec->dig_out = 0x05;
7506 spec->multiout.dig_out_nid = spec->dig_out;
7507 spec->dig_in = 0x09;
7508 break;
7509 case QUIRK_R3DI:
7510 codec_dbg(codec, "%s: QUIRK_R3DI applied.\n", __func__);
7511 snd_hda_apply_pincfgs(codec, r3di_pincfgs);
7512
7513 spec->num_outputs = 2;
7514 spec->out_pins[0] = 0x0B; /* Line out */
7515 spec->out_pins[1] = 0x0F; /* Rear headphone out */
7516 spec->out_pins[2] = 0x10; /* Front Headphone / Center/LFE*/
7517 spec->out_pins[3] = 0x11; /* Rear surround */
7518 spec->shared_out_nid = 0x2;
7519 spec->unsol_tag_hp = spec->out_pins[1];
7520 spec->unsol_tag_front_hp = spec->out_pins[2];
7521
7522 spec->adcs[0] = 0x07; /* Rear Mic / Line-in */
7523 spec->adcs[1] = 0x08; /* Front Mic, but only if no DSP */
7524 spec->adcs[2] = 0x0a; /* what u hear */
7525
7526 spec->num_inputs = 2;
7527 spec->input_pins[0] = 0x12; /* Rear Mic / Line-in */
7528 spec->input_pins[1] = 0x13; /* What U Hear */
7529 spec->shared_mic_nid = 0x7;
7530 spec->unsol_tag_amic1 = spec->input_pins[0];
7531
7532 /* SPDIF I/O */
7533 spec->dig_out = 0x05;
7534 spec->multiout.dig_out_nid = spec->dig_out;
7535 break;
7536 default:
7537 spec->num_outputs = 2;
7538 spec->out_pins[0] = 0x0b; /* speaker out */
7539 spec->out_pins[1] = 0x10; /* headphone out */
7540 spec->shared_out_nid = 0x2;
7541 spec->unsol_tag_hp = spec->out_pins[1];
7542
7543 spec->adcs[0] = 0x7; /* digital mic / analog mic1 */
7544 spec->adcs[1] = 0x8; /* analog mic2 */
7545 spec->adcs[2] = 0xa; /* what u hear */
7546
7547 spec->num_inputs = 3;
7548 spec->input_pins[0] = 0x12;
7549 spec->input_pins[1] = 0x11;
7550 spec->input_pins[2] = 0x13;
7551 spec->shared_mic_nid = 0x7;
7552 spec->unsol_tag_amic1 = spec->input_pins[0];
7553
7554 /* SPDIF I/O */
7555 spec->dig_out = 0x05;
7556 spec->multiout.dig_out_nid = spec->dig_out;
7557 spec->dig_in = 0x09;
7558 break;
7559 }
7560 }
7561
7562 static int ca0132_prepare_verbs(struct hda_codec *codec)
7563 {
7564 /* Verbs + terminator (an empty element) */
7565 #define NUM_SPEC_VERBS 2
7566 struct ca0132_spec *spec = codec->spec;
7567
7568 spec->chip_init_verbs = ca0132_init_verbs0;
7569 if (spec->quirk == QUIRK_SBZ || spec->quirk == QUIRK_R3D)
7570 spec->desktop_init_verbs = ca0132_init_verbs1;
7571 spec->spec_init_verbs = kcalloc(NUM_SPEC_VERBS,
7572 sizeof(struct hda_verb),
7573 GFP_KERNEL);
7574 if (!spec->spec_init_verbs)
7575 return -ENOMEM;
7576
7577 /* config EAPD */
7578 spec->spec_init_verbs[0].nid = 0x0b;
7579 spec->spec_init_verbs[0].param = 0x78D;
7580 spec->spec_init_verbs[0].verb = 0x00;
7581
7582 /* Previously commented configuration */
7583 /*
7584 spec->spec_init_verbs[2].nid = 0x0b;
7585 spec->spec_init_verbs[2].param = AC_VERB_SET_EAPD_BTLENABLE;
7586 spec->spec_init_verbs[2].verb = 0x02;
7587
7588 spec->spec_init_verbs[3].nid = 0x10;
7589 spec->spec_init_verbs[3].param = 0x78D;
7590 spec->spec_init_verbs[3].verb = 0x02;
7591
7592 spec->spec_init_verbs[4].nid = 0x10;
7593 spec->spec_init_verbs[4].param = AC_VERB_SET_EAPD_BTLENABLE;
7594 spec->spec_init_verbs[4].verb = 0x02;
7595 */
7596
7597 /* Terminator: spec->spec_init_verbs[NUM_SPEC_VERBS-1] */
7598 return 0;
7599 }
7600
7601 static int patch_ca0132(struct hda_codec *codec)
7602 {
7603 struct ca0132_spec *spec;
7604 int err;
7605 const struct snd_pci_quirk *quirk;
7606
7607 codec_dbg(codec, "patch_ca0132\n");
7608
7609 spec = kzalloc(sizeof(*spec), GFP_KERNEL);
7610 if (!spec)
7611 return -ENOMEM;
7612 codec->spec = spec;
7613 spec->codec = codec;
7614
7615 codec->patch_ops = ca0132_patch_ops;
7616 codec->pcm_format_first = 1;
7617 codec->no_sticky_stream = 1;
7618
7619 /* Detect codec quirk */
7620 quirk = snd_pci_quirk_lookup(codec->bus->pci, ca0132_quirks);
7621 if (quirk)
7622 spec->quirk = quirk->value;
7623 else
7624 spec->quirk = QUIRK_NONE;
7625
7626 spec->dsp_state = DSP_DOWNLOAD_INIT;
7627 spec->num_mixers = 1;
7628
7629 /* Set which mixers each quirk uses. */
7630 switch (spec->quirk) {
7631 case QUIRK_SBZ:
7632 spec->mixers[0] = desktop_mixer;
7633 snd_hda_codec_set_name(codec, "Sound Blaster Z");
7634 break;
7635 case QUIRK_R3D:
7636 spec->mixers[0] = desktop_mixer;
7637 snd_hda_codec_set_name(codec, "Recon3D");
7638 break;
7639 case QUIRK_R3DI:
7640 spec->mixers[0] = r3di_mixer;
7641 snd_hda_codec_set_name(codec, "Recon3Di");
7642 break;
7643 default:
7644 spec->mixers[0] = ca0132_mixer;
7645 break;
7646 }
7647
7648 /* Setup whether or not to use alt functions/controls/pci_mmio */
7649 switch (spec->quirk) {
7650 case QUIRK_SBZ:
7651 case QUIRK_R3D:
7652 spec->use_alt_controls = true;
7653 spec->use_alt_functions = true;
7654 spec->use_pci_mmio = true;
7655 break;
7656 case QUIRK_R3DI:
7657 spec->use_alt_controls = true;
7658 spec->use_alt_functions = true;
7659 spec->use_pci_mmio = false;
7660 break;
7661 default:
7662 spec->use_alt_controls = false;
7663 spec->use_alt_functions = false;
7664 spec->use_pci_mmio = false;
7665 break;
7666 }
7667
7668 if (spec->use_pci_mmio) {
7669 spec->mem_base = pci_iomap(codec->bus->pci, 2, 0xC20);
7670 if (spec->mem_base == NULL) {
7671 codec_warn(codec, "pci_iomap failed! Setting quirk to QUIRK_NONE.");
7672 spec->quirk = QUIRK_NONE;
7673 }
7674 }
7675
7676 spec->base_init_verbs = ca0132_base_init_verbs;
7677 spec->base_exit_verbs = ca0132_base_exit_verbs;
7678
7679 INIT_DELAYED_WORK(&spec->unsol_hp_work, ca0132_unsol_hp_delayed);
7680
7681 ca0132_init_chip(codec);
7682
7683 ca0132_config(codec);
7684
7685 err = ca0132_prepare_verbs(codec);
7686 if (err < 0)
7687 goto error;
7688
7689 err = snd_hda_parse_pin_def_config(codec, &spec->autocfg, NULL);
7690 if (err < 0)
7691 goto error;
7692
7693 return 0;
7694
7695 error:
7696 ca0132_free(codec);
7697 return err;
7698 }
7699
7700 /*
7701 * patch entries
7702 */
7703 static struct hda_device_id snd_hda_id_ca0132[] = {
7704 HDA_CODEC_ENTRY(0x11020011, "CA0132", patch_ca0132),
7705 {} /* terminator */
7706 };
7707 MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_ca0132);
7708
7709 MODULE_LICENSE("GPL");
7710 MODULE_DESCRIPTION("Creative Sound Core3D codec");
7711
7712 static struct hda_codec_driver ca0132_driver = {
7713 .id = snd_hda_id_ca0132,
7714 };
7715
7716 module_hda_codec_driver(ca0132_driver);
Linux with added FPC-III support