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net: dsa: mt7530: set CPU port to fallback mode
[linux/fpc-iii.git] / sound / pci / rme9652 / hdspm.c
blob11b5b5e0e0580fd3a3d33cf99dd71728db1bdd3a
1 /*
2 * ALSA driver for RME Hammerfall DSP MADI audio interface(s)
3 *
4 * Copyright (c) 2003 Winfried Ritsch (IEM)
5 * code based on hdsp.c Paul Davis
6 * Marcus Andersson
7 * Thomas Charbonnel
8 * Modified 2006-06-01 for AES32 support by Remy Bruno
9 * <remy.bruno@trinnov.com>
10 *
11 * Modified 2009-04-13 for proper metering by Florian Faber
12 * <faber@faberman.de>
13 *
14 * Modified 2009-04-14 for native float support by Florian Faber
15 * <faber@faberman.de>
16 *
17 * Modified 2009-04-26 fixed bug in rms metering by Florian Faber
18 * <faber@faberman.de>
19 *
20 * Modified 2009-04-30 added hw serial number support by Florian Faber
21 *
22 * Modified 2011-01-14 added S/PDIF input on RayDATs by Adrian Knoth
23 *
24 * Modified 2011-01-25 variable period sizes on RayDAT/AIO by Adrian Knoth
25 *
26 * This program is free software; you can redistribute it and/or modify
27 * it under the terms of the GNU General Public License as published by
28 * the Free Software Foundation; either version 2 of the License, or
29 * (at your option) any later version.
30 *
31 * This program is distributed in the hope that it will be useful,
32 * but WITHOUT ANY WARRANTY; without even the implied warranty of
33 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
34 * GNU General Public License for more details.
35 *
36 * You should have received a copy of the GNU General Public License
37 * along with this program; if not, write to the Free Software
38 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
39 *
40 */
41
42 /* ************* Register Documentation *******************************************************
43 *
44 * Work in progress! Documentation is based on the code in this file.
45 *
46 * --------- HDSPM_controlRegister ---------
47 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
48 * :||||.||||:||||.||||:||||.||||:||||.||||:
49 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
50 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
51 * :||||.||||:||||.||||:||||.||||:||||.||||:
52 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
53 * : . : . : . : x . : HDSPM_AudioInterruptEnable \_ setting both bits
54 * : . : . : . : . x: HDSPM_Start / enables audio IO
55 * : . : . : . : x. : HDSPM_ClockModeMaster - 1: Master, 0: Slave
56 * : . : . : . : .210 : HDSPM_LatencyMask - 3 Bit value for latency
57 * : . : . : . : . : 0:64, 1:128, 2:256, 3:512,
58 * : . : . : . : . : 4:1024, 5:2048, 6:4096, 7:8192
59 * :x . : . : . x:xx . : HDSPM_FrequencyMask
60 * : . : . : . :10 . : HDSPM_Frequency1|HDSPM_Frequency0: 1=32K,2=44.1K,3=48K,0=??
61 * : . : . : . x: . : <MADI> HDSPM_DoubleSpeed
62 * :x . : . : . : . : <MADI> HDSPM_QuadSpeed
63 * : . 3 : . 10: 2 . : . : HDSPM_SyncRefMask :
64 * : . : . x: . : . : HDSPM_SyncRef0
65 * : . : . x : . : . : HDSPM_SyncRef1
66 * : . : . : x . : . : <AES32> HDSPM_SyncRef2
67 * : . x : . : . : . : <AES32> HDSPM_SyncRef3
68 * : . : . 10: . : . : <MADI> sync ref: 0:WC, 1:Madi, 2:TCO, 3:SyncIn
69 * : . 3 : . 10: 2 . : . : <AES32> 0:WC, 1:AES1 ... 8:AES8, 9: TCO, 10:SyncIn?
70 * : . x : . : . : . : <MADIe> HDSPe_FLOAT_FORMAT
71 * : . : . : x . : . : <MADI> HDSPM_InputSelect0 : 0=optical,1=coax
72 * : . : . :x . : . : <MADI> HDSPM_InputSelect1
73 * : . : .x : . : . : <MADI> HDSPM_clr_tms
74 * : . : . : . x : . : <MADI> HDSPM_TX_64ch
75 * : . : . : . x : . : <AES32> HDSPM_Emphasis
76 * : . : . : .x : . : <MADI> HDSPM_AutoInp
77 * : . : . x : . : . : <MADI> HDSPM_SMUX
78 * : . : .x : . : . : <MADI> HDSPM_clr_tms
79 * : . : x. : . : . : <MADI> HDSPM_taxi_reset
80 * : . x: . : . : . : <MADI> HDSPM_LineOut
81 * : . x: . : . : . : <AES32> ??????????????????
82 * : . : x. : . : . : <AES32> HDSPM_WCK48
83 * : . : . : .x : . : <AES32> HDSPM_Dolby
84 * : . : x . : . : . : HDSPM_Midi0InterruptEnable
85 * : . :x . : . : . : HDSPM_Midi1InterruptEnable
86 * : . : x . : . : . : HDSPM_Midi2InterruptEnable
87 * : . x : . : . : . : <MADI> HDSPM_Midi3InterruptEnable
88 * : . x : . : . : . : <AES32> HDSPM_DS_DoubleWire
89 * : .x : . : . : . : <AES32> HDSPM_QS_DoubleWire
90 * : x. : . : . : . : <AES32> HDSPM_QS_QuadWire
91 * : . : . : . x : . : <AES32> HDSPM_Professional
92 * : x . : . : . : . : HDSPM_wclk_sel
93 * : . : . : . : . :
94 * :7654.3210:7654.3210:7654.3210:7654.3210: bit number per byte
95 * :||||.||||:||||.||||:||||.||||:||||.||||:
96 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number
97 * :1098.7654:3210.9876:5432.1098:7654.3210: 0..31
98 * :||||.||||:||||.||||:||||.||||:||||.||||:
99 * :8421.8421:8421.8421:8421.8421:8421.8421:hex digit
100 *
101 *
102 *
103 * AIO / RayDAT only
104 *
105 * ------------ HDSPM_WR_SETTINGS ----------
106 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
107 * :1098.7654:3210.9876:5432.1098:7654.3210:
108 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
109 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
110 * :||||.||||:||||.||||:||||.||||:||||.||||:
111 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
112 * : . : . : . : . x: HDSPM_c0Master 1: Master, 0: Slave
113 * : . : . : . : . x : HDSPM_c0_SyncRef0
114 * : . : . : . : . x : HDSPM_c0_SyncRef1
115 * : . : . : . : .x : HDSPM_c0_SyncRef2
116 * : . : . : . : x. : HDSPM_c0_SyncRef3
117 * : . : . : . : 3.210 : HDSPM_c0_SyncRefMask:
118 * : . : . : . : . : RayDat: 0:WC, 1:AES, 2:SPDIF, 3..6: ADAT1..4,
119 * : . : . : . : . : 9:TCO, 10:SyncIn
120 * : . : . : . : . : AIO: 0:WC, 1:AES, 2: SPDIF, 3: ATAT,
121 * : . : . : . : . : 9:TCO, 10:SyncIn
122 * : . : . : . : . :
123 * : . : . : . : . :
124 * :3322.2222:2222.1111:1111.1100:0000.0000: bit number per byte
125 * :1098.7654:3210.9876:5432.1098:7654.3210:
126 * :||||.||||:||||.||||:||||.||||:||||.||||: bit number
127 * :7654.3210:7654.3210:7654.3210:7654.3210: 0..31
128 * :||||.||||:||||.||||:||||.||||:||||.||||:
129 * :8421.8421:8421.8421:8421.8421:8421.8421: hex digit
130 *
131 */
132 #include <linux/init.h>
133 #include <linux/delay.h>
134 #include <linux/interrupt.h>
135 #include <linux/module.h>
136 #include <linux/slab.h>
137 #include <linux/pci.h>
138 #include <linux/math64.h>
139 #include <linux/io.h>
140 #include <linux/nospec.h>
141
142 #include <sound/core.h>
143 #include <sound/control.h>
144 #include <sound/pcm.h>
145 #include <sound/pcm_params.h>
146 #include <sound/info.h>
147 #include <sound/asoundef.h>
148 #include <sound/rawmidi.h>
149 #include <sound/hwdep.h>
150 #include <sound/initval.h>
151
152 #include <sound/hdspm.h>
153
154 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
155 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
156 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;/* Enable this card */
157
158 module_param_array(index, int, NULL, 0444);
159 MODULE_PARM_DESC(index, "Index value for RME HDSPM interface.");
160
161 module_param_array(id, charp, NULL, 0444);
162 MODULE_PARM_DESC(id, "ID string for RME HDSPM interface.");
163
164 module_param_array(enable, bool, NULL, 0444);
165 MODULE_PARM_DESC(enable, "Enable/disable specific HDSPM soundcards.");
166
167
168 MODULE_AUTHOR
169 (
170 "Winfried Ritsch <ritsch_AT_iem.at>, "
171 "Paul Davis <paul@linuxaudiosystems.com>, "
172 "Marcus Andersson, Thomas Charbonnel <thomas@undata.org>, "
173 "Remy Bruno <remy.bruno@trinnov.com>, "
174 "Florian Faber <faberman@linuxproaudio.org>, "
175 "Adrian Knoth <adi@drcomp.erfurt.thur.de>"
176 );
177 MODULE_DESCRIPTION("RME HDSPM");
178 MODULE_LICENSE("GPL");
179 MODULE_SUPPORTED_DEVICE("{{RME HDSPM-MADI}}");
180
181 /* --- Write registers. ---
182 These are defined as byte-offsets from the iobase value. */
183
184 #define HDSPM_WR_SETTINGS 0
185 #define HDSPM_outputBufferAddress 32
186 #define HDSPM_inputBufferAddress 36
187 #define HDSPM_controlRegister 64
188 #define HDSPM_interruptConfirmation 96
189 #define HDSPM_control2Reg 256 /* not in specs ???????? */
190 #define HDSPM_freqReg 256 /* for setting arbitrary clock values (DDS feature) */
191 #define HDSPM_midiDataOut0 352 /* just believe in old code */
192 #define HDSPM_midiDataOut1 356
193 #define HDSPM_eeprom_wr 384 /* for AES32 */
194
195 /* DMA enable for 64 channels, only Bit 0 is relevant */
196 #define HDSPM_outputEnableBase 512 /* 512-767 input DMA */
197 #define HDSPM_inputEnableBase 768 /* 768-1023 output DMA */
198
199 /* 16 page addresses for each of the 64 channels DMA buffer in and out
200 (each 64k=16*4k) Buffer must be 4k aligned (which is default i386 ????) */
201 #define HDSPM_pageAddressBufferOut 8192
202 #define HDSPM_pageAddressBufferIn (HDSPM_pageAddressBufferOut+64*16*4)
203
204 #define HDSPM_MADI_mixerBase 32768 /* 32768-65535 for 2x64x64 Fader */
205
206 #define HDSPM_MATRIX_MIXER_SIZE 8192 /* = 2*64*64 * 4 Byte => 32kB */
207
208 /* --- Read registers. ---
209 These are defined as byte-offsets from the iobase value */
210 #define HDSPM_statusRegister 0
211 /*#define HDSPM_statusRegister2 96 */
212 /* after RME Windows driver sources, status2 is 4-byte word # 48 = word at
213 * offset 192, for AES32 *and* MADI
214 * => need to check that offset 192 is working on MADI */
215 #define HDSPM_statusRegister2 192
216 #define HDSPM_timecodeRegister 128
217
218 /* AIO, RayDAT */
219 #define HDSPM_RD_STATUS_0 0
220 #define HDSPM_RD_STATUS_1 64
221 #define HDSPM_RD_STATUS_2 128
222 #define HDSPM_RD_STATUS_3 192
223
224 #define HDSPM_RD_TCO 256
225 #define HDSPM_RD_PLL_FREQ 512
226 #define HDSPM_WR_TCO 128
227
228 #define HDSPM_TCO1_TCO_lock 0x00000001
229 #define HDSPM_TCO1_WCK_Input_Range_LSB 0x00000002
230 #define HDSPM_TCO1_WCK_Input_Range_MSB 0x00000004
231 #define HDSPM_TCO1_LTC_Input_valid 0x00000008
232 #define HDSPM_TCO1_WCK_Input_valid 0x00000010
233 #define HDSPM_TCO1_Video_Input_Format_NTSC 0x00000020
234 #define HDSPM_TCO1_Video_Input_Format_PAL 0x00000040
235
236 #define HDSPM_TCO1_set_TC 0x00000100
237 #define HDSPM_TCO1_set_drop_frame_flag 0x00000200
238 #define HDSPM_TCO1_LTC_Format_LSB 0x00000400
239 #define HDSPM_TCO1_LTC_Format_MSB 0x00000800
240
241 #define HDSPM_TCO2_TC_run 0x00010000
242 #define HDSPM_TCO2_WCK_IO_ratio_LSB 0x00020000
243 #define HDSPM_TCO2_WCK_IO_ratio_MSB 0x00040000
244 #define HDSPM_TCO2_set_num_drop_frames_LSB 0x00080000
245 #define HDSPM_TCO2_set_num_drop_frames_MSB 0x00100000
246 #define HDSPM_TCO2_set_jam_sync 0x00200000
247 #define HDSPM_TCO2_set_flywheel 0x00400000
248
249 #define HDSPM_TCO2_set_01_4 0x01000000
250 #define HDSPM_TCO2_set_pull_down 0x02000000
251 #define HDSPM_TCO2_set_pull_up 0x04000000
252 #define HDSPM_TCO2_set_freq 0x08000000
253 #define HDSPM_TCO2_set_term_75R 0x10000000
254 #define HDSPM_TCO2_set_input_LSB 0x20000000
255 #define HDSPM_TCO2_set_input_MSB 0x40000000
256 #define HDSPM_TCO2_set_freq_from_app 0x80000000
257
258
259 #define HDSPM_midiDataOut0 352
260 #define HDSPM_midiDataOut1 356
261 #define HDSPM_midiDataOut2 368
262
263 #define HDSPM_midiDataIn0 360
264 #define HDSPM_midiDataIn1 364
265 #define HDSPM_midiDataIn2 372
266 #define HDSPM_midiDataIn3 376
267
268 /* status is data bytes in MIDI-FIFO (0-128) */
269 #define HDSPM_midiStatusOut0 384
270 #define HDSPM_midiStatusOut1 388
271 #define HDSPM_midiStatusOut2 400
272
273 #define HDSPM_midiStatusIn0 392
274 #define HDSPM_midiStatusIn1 396
275 #define HDSPM_midiStatusIn2 404
276 #define HDSPM_midiStatusIn3 408
277
278
279 /* the meters are regular i/o-mapped registers, but offset
280 considerably from the rest. the peak registers are reset
281 when read; the least-significant 4 bits are full-scale counters;
282 the actual peak value is in the most-significant 24 bits.
283 */
284
285 #define HDSPM_MADI_INPUT_PEAK 4096
286 #define HDSPM_MADI_PLAYBACK_PEAK 4352
287 #define HDSPM_MADI_OUTPUT_PEAK 4608
288
289 #define HDSPM_MADI_INPUT_RMS_L 6144
290 #define HDSPM_MADI_PLAYBACK_RMS_L 6400
291 #define HDSPM_MADI_OUTPUT_RMS_L 6656
292
293 #define HDSPM_MADI_INPUT_RMS_H 7168
294 #define HDSPM_MADI_PLAYBACK_RMS_H 7424
295 #define HDSPM_MADI_OUTPUT_RMS_H 7680
296
297 /* --- Control Register bits --------- */
298 #define HDSPM_Start (1<<0) /* start engine */
299
300 #define HDSPM_Latency0 (1<<1) /* buffer size = 2^n */
301 #define HDSPM_Latency1 (1<<2) /* where n is defined */
302 #define HDSPM_Latency2 (1<<3) /* by Latency{2,1,0} */
303
304 #define HDSPM_ClockModeMaster (1<<4) /* 1=Master, 0=Autosync */
305 #define HDSPM_c0Master 0x1 /* Master clock bit in settings
306 register [RayDAT, AIO] */
307
308 #define HDSPM_AudioInterruptEnable (1<<5) /* what do you think ? */
309
310 #define HDSPM_Frequency0 (1<<6) /* 0=44.1kHz/88.2kHz 1=48kHz/96kHz */
311 #define HDSPM_Frequency1 (1<<7) /* 0=32kHz/64kHz */
312 #define HDSPM_DoubleSpeed (1<<8) /* 0=normal speed, 1=double speed */
313 #define HDSPM_QuadSpeed (1<<31) /* quad speed bit */
314
315 #define HDSPM_Professional (1<<9) /* Professional */ /* AES32 ONLY */
316 #define HDSPM_TX_64ch (1<<10) /* Output 64channel MODE=1,
317 56channelMODE=0 */ /* MADI ONLY*/
318 #define HDSPM_Emphasis (1<<10) /* Emphasis */ /* AES32 ONLY */
319
320 #define HDSPM_AutoInp (1<<11) /* Auto Input (takeover) == Safe Mode,
321 0=off, 1=on */ /* MADI ONLY */
322 #define HDSPM_Dolby (1<<11) /* Dolby = "NonAudio" ?? */ /* AES32 ONLY */
323
324 #define HDSPM_InputSelect0 (1<<14) /* Input select 0= optical, 1=coax
325 * -- MADI ONLY
326 */
327 #define HDSPM_InputSelect1 (1<<15) /* should be 0 */
328
329 #define HDSPM_SyncRef2 (1<<13)
330 #define HDSPM_SyncRef3 (1<<25)
331
332 #define HDSPM_SMUX (1<<18) /* Frame ??? */ /* MADI ONY */
333 #define HDSPM_clr_tms (1<<19) /* clear track marker, do not use
334 AES additional bits in
335 lower 5 Audiodatabits ??? */
336 #define HDSPM_taxi_reset (1<<20) /* ??? */ /* MADI ONLY ? */
337 #define HDSPM_WCK48 (1<<20) /* Frame ??? = HDSPM_SMUX */ /* AES32 ONLY */
338
339 #define HDSPM_Midi0InterruptEnable 0x0400000
340 #define HDSPM_Midi1InterruptEnable 0x0800000
341 #define HDSPM_Midi2InterruptEnable 0x0200000
342 #define HDSPM_Midi3InterruptEnable 0x4000000
343
344 #define HDSPM_LineOut (1<<24) /* Analog Out on channel 63/64 on=1, mute=0 */
345 #define HDSPe_FLOAT_FORMAT 0x2000000
346
347 #define HDSPM_DS_DoubleWire (1<<26) /* AES32 ONLY */
348 #define HDSPM_QS_DoubleWire (1<<27) /* AES32 ONLY */
349 #define HDSPM_QS_QuadWire (1<<28) /* AES32 ONLY */
350
351 #define HDSPM_wclk_sel (1<<30)
352
353 /* additional control register bits for AIO*/
354 #define HDSPM_c0_Wck48 0x20 /* also RayDAT */
355 #define HDSPM_c0_Input0 0x1000
356 #define HDSPM_c0_Input1 0x2000
357 #define HDSPM_c0_Spdif_Opt 0x4000
358 #define HDSPM_c0_Pro 0x8000
359 #define HDSPM_c0_clr_tms 0x10000
360 #define HDSPM_c0_AEB1 0x20000
361 #define HDSPM_c0_AEB2 0x40000
362 #define HDSPM_c0_LineOut 0x80000
363 #define HDSPM_c0_AD_GAIN0 0x100000
364 #define HDSPM_c0_AD_GAIN1 0x200000
365 #define HDSPM_c0_DA_GAIN0 0x400000
366 #define HDSPM_c0_DA_GAIN1 0x800000
367 #define HDSPM_c0_PH_GAIN0 0x1000000
368 #define HDSPM_c0_PH_GAIN1 0x2000000
369 #define HDSPM_c0_Sym6db 0x4000000
370
371
372 /* --- bit helper defines */
373 #define HDSPM_LatencyMask (HDSPM_Latency0|HDSPM_Latency1|HDSPM_Latency2)
374 #define HDSPM_FrequencyMask (HDSPM_Frequency0|HDSPM_Frequency1|\
375 HDSPM_DoubleSpeed|HDSPM_QuadSpeed)
376 #define HDSPM_InputMask (HDSPM_InputSelect0|HDSPM_InputSelect1)
377 #define HDSPM_InputOptical 0
378 #define HDSPM_InputCoaxial (HDSPM_InputSelect0)
379 #define HDSPM_SyncRefMask (HDSPM_SyncRef0|HDSPM_SyncRef1|\
380 HDSPM_SyncRef2|HDSPM_SyncRef3)
381
382 #define HDSPM_c0_SyncRef0 0x2
383 #define HDSPM_c0_SyncRef1 0x4
384 #define HDSPM_c0_SyncRef2 0x8
385 #define HDSPM_c0_SyncRef3 0x10
386 #define HDSPM_c0_SyncRefMask (HDSPM_c0_SyncRef0 | HDSPM_c0_SyncRef1 |\
387 HDSPM_c0_SyncRef2 | HDSPM_c0_SyncRef3)
388
389 #define HDSPM_SYNC_FROM_WORD 0 /* Preferred sync reference */
390 #define HDSPM_SYNC_FROM_MADI 1 /* choices - used by "pref_sync_ref" */
391 #define HDSPM_SYNC_FROM_TCO 2
392 #define HDSPM_SYNC_FROM_SYNC_IN 3
393
394 #define HDSPM_Frequency32KHz HDSPM_Frequency0
395 #define HDSPM_Frequency44_1KHz HDSPM_Frequency1
396 #define HDSPM_Frequency48KHz (HDSPM_Frequency1|HDSPM_Frequency0)
397 #define HDSPM_Frequency64KHz (HDSPM_DoubleSpeed|HDSPM_Frequency0)
398 #define HDSPM_Frequency88_2KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1)
399 #define HDSPM_Frequency96KHz (HDSPM_DoubleSpeed|HDSPM_Frequency1|\
400 HDSPM_Frequency0)
401 #define HDSPM_Frequency128KHz (HDSPM_QuadSpeed|HDSPM_Frequency0)
402 #define HDSPM_Frequency176_4KHz (HDSPM_QuadSpeed|HDSPM_Frequency1)
403 #define HDSPM_Frequency192KHz (HDSPM_QuadSpeed|HDSPM_Frequency1|\
404 HDSPM_Frequency0)
405
406
407 /* Synccheck Status */
408 #define HDSPM_SYNC_CHECK_NO_LOCK 0
409 #define HDSPM_SYNC_CHECK_LOCK 1
410 #define HDSPM_SYNC_CHECK_SYNC 2
411
412 /* AutoSync References - used by "autosync_ref" control switch */
413 #define HDSPM_AUTOSYNC_FROM_WORD 0
414 #define HDSPM_AUTOSYNC_FROM_MADI 1
415 #define HDSPM_AUTOSYNC_FROM_TCO 2
416 #define HDSPM_AUTOSYNC_FROM_SYNC_IN 3
417 #define HDSPM_AUTOSYNC_FROM_NONE 4
418
419 /* Possible sources of MADI input */
420 #define HDSPM_OPTICAL 0 /* optical */
421 #define HDSPM_COAXIAL 1 /* BNC */
422
423 #define hdspm_encode_latency(x) (((x)<<1) & HDSPM_LatencyMask)
424 #define hdspm_decode_latency(x) ((((x) & HDSPM_LatencyMask)>>1))
425
426 #define hdspm_encode_in(x) (((x)&0x3)<<14)
427 #define hdspm_decode_in(x) (((x)>>14)&0x3)
428
429 /* --- control2 register bits --- */
430 #define HDSPM_TMS (1<<0)
431 #define HDSPM_TCK (1<<1)
432 #define HDSPM_TDI (1<<2)
433 #define HDSPM_JTAG (1<<3)
434 #define HDSPM_PWDN (1<<4)
435 #define HDSPM_PROGRAM (1<<5)
436 #define HDSPM_CONFIG_MODE_0 (1<<6)
437 #define HDSPM_CONFIG_MODE_1 (1<<7)
438 /*#define HDSPM_VERSION_BIT (1<<8) not defined any more*/
439 #define HDSPM_BIGENDIAN_MODE (1<<9)
440 #define HDSPM_RD_MULTIPLE (1<<10)
441
442 /* --- Status Register bits --- */ /* MADI ONLY */ /* Bits defined here and
443 that do not conflict with specific bits for AES32 seem to be valid also
444 for the AES32
445 */
446 #define HDSPM_audioIRQPending (1<<0) /* IRQ is high and pending */
447 #define HDSPM_RX_64ch (1<<1) /* Input 64chan. MODE=1, 56chn MODE=0 */
448 #define HDSPM_AB_int (1<<2) /* InputChannel Opt=0, Coax=1
449 * (like inp0)
450 */
451
452 #define HDSPM_madiLock (1<<3) /* MADI Locked =1, no=0 */
453 #define HDSPM_madiSync (1<<18) /* MADI is in sync */
454
455 #define HDSPM_tcoLockMadi 0x00000020 /* Optional TCO locked status for HDSPe MADI*/
456 #define HDSPM_tcoSync 0x10000000 /* Optional TCO sync status for HDSPe MADI and AES32!*/
457
458 #define HDSPM_syncInLock 0x00010000 /* Sync In lock status for HDSPe MADI! */
459 #define HDSPM_syncInSync 0x00020000 /* Sync In sync status for HDSPe MADI! */
460
461 #define HDSPM_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
462 /* since 64byte accurate, last 6 bits are not used */
463
464
465
466 #define HDSPM_DoubleSpeedStatus (1<<19) /* (input) card in double speed */
467
468 #define HDSPM_madiFreq0 (1<<22) /* system freq 0=error */
469 #define HDSPM_madiFreq1 (1<<23) /* 1=32, 2=44.1 3=48 */
470 #define HDSPM_madiFreq2 (1<<24) /* 4=64, 5=88.2 6=96 */
471 #define HDSPM_madiFreq3 (1<<25) /* 7=128, 8=176.4 9=192 */
472
473 #define HDSPM_BufferID (1<<26) /* (Double)Buffer ID toggles with
474 * Interrupt
475 */
476 #define HDSPM_tco_detect 0x08000000
477 #define HDSPM_tcoLockAes 0x20000000 /* Optional TCO locked status for HDSPe AES */
478
479 #define HDSPM_s2_tco_detect 0x00000040
480 #define HDSPM_s2_AEBO_D 0x00000080
481 #define HDSPM_s2_AEBI_D 0x00000100
482
483
484 #define HDSPM_midi0IRQPending 0x40000000
485 #define HDSPM_midi1IRQPending 0x80000000
486 #define HDSPM_midi2IRQPending 0x20000000
487 #define HDSPM_midi2IRQPendingAES 0x00000020
488 #define HDSPM_midi3IRQPending 0x00200000
489
490 /* --- status bit helpers */
491 #define HDSPM_madiFreqMask (HDSPM_madiFreq0|HDSPM_madiFreq1|\
492 HDSPM_madiFreq2|HDSPM_madiFreq3)
493 #define HDSPM_madiFreq32 (HDSPM_madiFreq0)
494 #define HDSPM_madiFreq44_1 (HDSPM_madiFreq1)
495 #define HDSPM_madiFreq48 (HDSPM_madiFreq0|HDSPM_madiFreq1)
496 #define HDSPM_madiFreq64 (HDSPM_madiFreq2)
497 #define HDSPM_madiFreq88_2 (HDSPM_madiFreq0|HDSPM_madiFreq2)
498 #define HDSPM_madiFreq96 (HDSPM_madiFreq1|HDSPM_madiFreq2)
499 #define HDSPM_madiFreq128 (HDSPM_madiFreq0|HDSPM_madiFreq1|HDSPM_madiFreq2)
500 #define HDSPM_madiFreq176_4 (HDSPM_madiFreq3)
501 #define HDSPM_madiFreq192 (HDSPM_madiFreq3|HDSPM_madiFreq0)
502
503 /* Status2 Register bits */ /* MADI ONLY */
504
505 #define HDSPM_version0 (1<<0) /* not really defined but I guess */
506 #define HDSPM_version1 (1<<1) /* in former cards it was ??? */
507 #define HDSPM_version2 (1<<2)
508
509 #define HDSPM_wcLock (1<<3) /* Wordclock is detected and locked */
510 #define HDSPM_wcSync (1<<4) /* Wordclock is in sync with systemclock */
511
512 #define HDSPM_wc_freq0 (1<<5) /* input freq detected via autosync */
513 #define HDSPM_wc_freq1 (1<<6) /* 001=32, 010==44.1, 011=48, */
514 #define HDSPM_wc_freq2 (1<<7) /* 100=64, 101=88.2, 110=96, 111=128 */
515 #define HDSPM_wc_freq3 0x800 /* 1000=176.4, 1001=192 */
516
517 #define HDSPM_SyncRef0 0x10000 /* Sync Reference */
518 #define HDSPM_SyncRef1 0x20000
519
520 #define HDSPM_SelSyncRef0 (1<<8) /* AutoSync Source */
521 #define HDSPM_SelSyncRef1 (1<<9) /* 000=word, 001=MADI, */
522 #define HDSPM_SelSyncRef2 (1<<10) /* 111=no valid signal */
523
524 #define HDSPM_wc_valid (HDSPM_wcLock|HDSPM_wcSync)
525
526 #define HDSPM_wcFreqMask (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2|\
527 HDSPM_wc_freq3)
528 #define HDSPM_wcFreq32 (HDSPM_wc_freq0)
529 #define HDSPM_wcFreq44_1 (HDSPM_wc_freq1)
530 #define HDSPM_wcFreq48 (HDSPM_wc_freq0|HDSPM_wc_freq1)
531 #define HDSPM_wcFreq64 (HDSPM_wc_freq2)
532 #define HDSPM_wcFreq88_2 (HDSPM_wc_freq0|HDSPM_wc_freq2)
533 #define HDSPM_wcFreq96 (HDSPM_wc_freq1|HDSPM_wc_freq2)
534 #define HDSPM_wcFreq128 (HDSPM_wc_freq0|HDSPM_wc_freq1|HDSPM_wc_freq2)
535 #define HDSPM_wcFreq176_4 (HDSPM_wc_freq3)
536 #define HDSPM_wcFreq192 (HDSPM_wc_freq0|HDSPM_wc_freq3)
537
538 #define HDSPM_status1_F_0 0x0400000
539 #define HDSPM_status1_F_1 0x0800000
540 #define HDSPM_status1_F_2 0x1000000
541 #define HDSPM_status1_F_3 0x2000000
542 #define HDSPM_status1_freqMask (HDSPM_status1_F_0|HDSPM_status1_F_1|HDSPM_status1_F_2|HDSPM_status1_F_3)
543
544
545 #define HDSPM_SelSyncRefMask (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
546 HDSPM_SelSyncRef2)
547 #define HDSPM_SelSyncRef_WORD 0
548 #define HDSPM_SelSyncRef_MADI (HDSPM_SelSyncRef0)
549 #define HDSPM_SelSyncRef_TCO (HDSPM_SelSyncRef1)
550 #define HDSPM_SelSyncRef_SyncIn (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1)
551 #define HDSPM_SelSyncRef_NVALID (HDSPM_SelSyncRef0|HDSPM_SelSyncRef1|\
552 HDSPM_SelSyncRef2)
553
554 /*
555 For AES32, bits for status, status2 and timecode are different
556 */
557 /* status */
558 #define HDSPM_AES32_wcLock 0x0200000
559 #define HDSPM_AES32_wcSync 0x0100000
560 #define HDSPM_AES32_wcFreq_bit 22
561 /* (status >> HDSPM_AES32_wcFreq_bit) & 0xF gives WC frequency (cf function
562 HDSPM_bit2freq */
563 #define HDSPM_AES32_syncref_bit 16
564 /* (status >> HDSPM_AES32_syncref_bit) & 0xF gives sync source */
565
566 #define HDSPM_AES32_AUTOSYNC_FROM_WORD 0
567 #define HDSPM_AES32_AUTOSYNC_FROM_AES1 1
568 #define HDSPM_AES32_AUTOSYNC_FROM_AES2 2
569 #define HDSPM_AES32_AUTOSYNC_FROM_AES3 3
570 #define HDSPM_AES32_AUTOSYNC_FROM_AES4 4
571 #define HDSPM_AES32_AUTOSYNC_FROM_AES5 5
572 #define HDSPM_AES32_AUTOSYNC_FROM_AES6 6
573 #define HDSPM_AES32_AUTOSYNC_FROM_AES7 7
574 #define HDSPM_AES32_AUTOSYNC_FROM_AES8 8
575 #define HDSPM_AES32_AUTOSYNC_FROM_TCO 9
576 #define HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN 10
577 #define HDSPM_AES32_AUTOSYNC_FROM_NONE 11
578
579 /* status2 */
580 /* HDSPM_LockAES_bit is given by HDSPM_LockAES >> (AES# - 1) */
581 #define HDSPM_LockAES 0x80
582 #define HDSPM_LockAES1 0x80
583 #define HDSPM_LockAES2 0x40
584 #define HDSPM_LockAES3 0x20
585 #define HDSPM_LockAES4 0x10
586 #define HDSPM_LockAES5 0x8
587 #define HDSPM_LockAES6 0x4
588 #define HDSPM_LockAES7 0x2
589 #define HDSPM_LockAES8 0x1
590 /*
591 Timecode
592 After windows driver sources, bits 4*i to 4*i+3 give the input frequency on
593 AES i+1
594 bits 3210
595 0001 32kHz
596 0010 44.1kHz
597 0011 48kHz
598 0100 64kHz
599 0101 88.2kHz
600 0110 96kHz
601 0111 128kHz
602 1000 176.4kHz
603 1001 192kHz
604 NB: Timecode register doesn't seem to work on AES32 card revision 230
605 */
606
607 /* Mixer Values */
608 #define UNITY_GAIN 32768 /* = 65536/2 */
609 #define MINUS_INFINITY_GAIN 0
610
611 /* Number of channels for different Speed Modes */
612 #define MADI_SS_CHANNELS 64
613 #define MADI_DS_CHANNELS 32
614 #define MADI_QS_CHANNELS 16
615
616 #define RAYDAT_SS_CHANNELS 36
617 #define RAYDAT_DS_CHANNELS 20
618 #define RAYDAT_QS_CHANNELS 12
619
620 #define AIO_IN_SS_CHANNELS 14
621 #define AIO_IN_DS_CHANNELS 10
622 #define AIO_IN_QS_CHANNELS 8
623 #define AIO_OUT_SS_CHANNELS 16
624 #define AIO_OUT_DS_CHANNELS 12
625 #define AIO_OUT_QS_CHANNELS 10
626
627 #define AES32_CHANNELS 16
628
629 /* the size of a substream (1 mono data stream) */
630 #define HDSPM_CHANNEL_BUFFER_SAMPLES (16*1024)
631 #define HDSPM_CHANNEL_BUFFER_BYTES (4*HDSPM_CHANNEL_BUFFER_SAMPLES)
632
633 /* the size of the area we need to allocate for DMA transfers. the
634 size is the same regardless of the number of channels, and
635 also the latency to use.
636 for one direction !!!
637 */
638 #define HDSPM_DMA_AREA_BYTES (HDSPM_MAX_CHANNELS * HDSPM_CHANNEL_BUFFER_BYTES)
639 #define HDSPM_DMA_AREA_KILOBYTES (HDSPM_DMA_AREA_BYTES/1024)
640
641 #define HDSPM_RAYDAT_REV 211
642 #define HDSPM_AIO_REV 212
643 #define HDSPM_MADIFACE_REV 213
644
645 /* speed factor modes */
646 #define HDSPM_SPEED_SINGLE 0
647 #define HDSPM_SPEED_DOUBLE 1
648 #define HDSPM_SPEED_QUAD 2
649
650 /* names for speed modes */
651 static char *hdspm_speed_names[] = { "single", "double", "quad" };
652
653 static const char *const texts_autosync_aes_tco[] = { "Word Clock",
654 "AES1", "AES2", "AES3", "AES4",
655 "AES5", "AES6", "AES7", "AES8",
656 "TCO", "Sync In"
657 };
658 static const char *const texts_autosync_aes[] = { "Word Clock",
659 "AES1", "AES2", "AES3", "AES4",
660 "AES5", "AES6", "AES7", "AES8",
661 "Sync In"
662 };
663 static const char *const texts_autosync_madi_tco[] = { "Word Clock",
664 "MADI", "TCO", "Sync In" };
665 static const char *const texts_autosync_madi[] = { "Word Clock",
666 "MADI", "Sync In" };
667
668 static const char *const texts_autosync_raydat_tco[] = {
669 "Word Clock",
670 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
671 "AES", "SPDIF", "TCO", "Sync In"
672 };
673 static const char *const texts_autosync_raydat[] = {
674 "Word Clock",
675 "ADAT 1", "ADAT 2", "ADAT 3", "ADAT 4",
676 "AES", "SPDIF", "Sync In"
677 };
678 static const char *const texts_autosync_aio_tco[] = {
679 "Word Clock",
680 "ADAT", "AES", "SPDIF", "TCO", "Sync In"
681 };
682 static const char *const texts_autosync_aio[] = { "Word Clock",
683 "ADAT", "AES", "SPDIF", "Sync In" };
684
685 static const char *const texts_freq[] = {
686 "No Lock",
687 "32 kHz",
688 "44.1 kHz",
689 "48 kHz",
690 "64 kHz",
691 "88.2 kHz",
692 "96 kHz",
693 "128 kHz",
694 "176.4 kHz",
695 "192 kHz"
696 };
697
698 static char *texts_ports_madi[] = {
699 "MADI.1", "MADI.2", "MADI.3", "MADI.4", "MADI.5", "MADI.6",
700 "MADI.7", "MADI.8", "MADI.9", "MADI.10", "MADI.11", "MADI.12",
701 "MADI.13", "MADI.14", "MADI.15", "MADI.16", "MADI.17", "MADI.18",
702 "MADI.19", "MADI.20", "MADI.21", "MADI.22", "MADI.23", "MADI.24",
703 "MADI.25", "MADI.26", "MADI.27", "MADI.28", "MADI.29", "MADI.30",
704 "MADI.31", "MADI.32", "MADI.33", "MADI.34", "MADI.35", "MADI.36",
705 "MADI.37", "MADI.38", "MADI.39", "MADI.40", "MADI.41", "MADI.42",
706 "MADI.43", "MADI.44", "MADI.45", "MADI.46", "MADI.47", "MADI.48",
707 "MADI.49", "MADI.50", "MADI.51", "MADI.52", "MADI.53", "MADI.54",
708 "MADI.55", "MADI.56", "MADI.57", "MADI.58", "MADI.59", "MADI.60",
709 "MADI.61", "MADI.62", "MADI.63", "MADI.64",
710 };
711
712
713 static char *texts_ports_raydat_ss[] = {
714 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4", "ADAT1.5", "ADAT1.6",
715 "ADAT1.7", "ADAT1.8", "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
716 "ADAT2.5", "ADAT2.6", "ADAT2.7", "ADAT2.8", "ADAT3.1", "ADAT3.2",
717 "ADAT3.3", "ADAT3.4", "ADAT3.5", "ADAT3.6", "ADAT3.7", "ADAT3.8",
718 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4", "ADAT4.5", "ADAT4.6",
719 "ADAT4.7", "ADAT4.8",
720 "AES.L", "AES.R",
721 "SPDIF.L", "SPDIF.R"
722 };
723
724 static char *texts_ports_raydat_ds[] = {
725 "ADAT1.1", "ADAT1.2", "ADAT1.3", "ADAT1.4",
726 "ADAT2.1", "ADAT2.2", "ADAT2.3", "ADAT2.4",
727 "ADAT3.1", "ADAT3.2", "ADAT3.3", "ADAT3.4",
728 "ADAT4.1", "ADAT4.2", "ADAT4.3", "ADAT4.4",
729 "AES.L", "AES.R",
730 "SPDIF.L", "SPDIF.R"
731 };
732
733 static char *texts_ports_raydat_qs[] = {
734 "ADAT1.1", "ADAT1.2",
735 "ADAT2.1", "ADAT2.2",
736 "ADAT3.1", "ADAT3.2",
737 "ADAT4.1", "ADAT4.2",
738 "AES.L", "AES.R",
739 "SPDIF.L", "SPDIF.R"
740 };
741
742
743 static char *texts_ports_aio_in_ss[] = {
744 "Analogue.L", "Analogue.R",
745 "AES.L", "AES.R",
746 "SPDIF.L", "SPDIF.R",
747 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
748 "ADAT.7", "ADAT.8",
749 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
750 };
751
752 static char *texts_ports_aio_out_ss[] = {
753 "Analogue.L", "Analogue.R",
754 "AES.L", "AES.R",
755 "SPDIF.L", "SPDIF.R",
756 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4", "ADAT.5", "ADAT.6",
757 "ADAT.7", "ADAT.8",
758 "Phone.L", "Phone.R",
759 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
760 };
761
762 static char *texts_ports_aio_in_ds[] = {
763 "Analogue.L", "Analogue.R",
764 "AES.L", "AES.R",
765 "SPDIF.L", "SPDIF.R",
766 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
767 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
768 };
769
770 static char *texts_ports_aio_out_ds[] = {
771 "Analogue.L", "Analogue.R",
772 "AES.L", "AES.R",
773 "SPDIF.L", "SPDIF.R",
774 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
775 "Phone.L", "Phone.R",
776 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
777 };
778
779 static char *texts_ports_aio_in_qs[] = {
780 "Analogue.L", "Analogue.R",
781 "AES.L", "AES.R",
782 "SPDIF.L", "SPDIF.R",
783 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
784 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
785 };
786
787 static char *texts_ports_aio_out_qs[] = {
788 "Analogue.L", "Analogue.R",
789 "AES.L", "AES.R",
790 "SPDIF.L", "SPDIF.R",
791 "ADAT.1", "ADAT.2", "ADAT.3", "ADAT.4",
792 "Phone.L", "Phone.R",
793 "AEB.1", "AEB.2", "AEB.3", "AEB.4"
794 };
795
796 static char *texts_ports_aes32[] = {
797 "AES.1", "AES.2", "AES.3", "AES.4", "AES.5", "AES.6", "AES.7",
798 "AES.8", "AES.9.", "AES.10", "AES.11", "AES.12", "AES.13", "AES.14",
799 "AES.15", "AES.16"
800 };
801
802 /* These tables map the ALSA channels 1..N to the channels that we
803 need to use in order to find the relevant channel buffer. RME
804 refers to this kind of mapping as between "the ADAT channel and
805 the DMA channel." We index it using the logical audio channel,
806 and the value is the DMA channel (i.e. channel buffer number)
807 where the data for that channel can be read/written from/to.
808 */
809
810 static char channel_map_unity_ss[HDSPM_MAX_CHANNELS] = {
811 0, 1, 2, 3, 4, 5, 6, 7,
812 8, 9, 10, 11, 12, 13, 14, 15,
813 16, 17, 18, 19, 20, 21, 22, 23,
814 24, 25, 26, 27, 28, 29, 30, 31,
815 32, 33, 34, 35, 36, 37, 38, 39,
816 40, 41, 42, 43, 44, 45, 46, 47,
817 48, 49, 50, 51, 52, 53, 54, 55,
818 56, 57, 58, 59, 60, 61, 62, 63
819 };
820
821 static char channel_map_raydat_ss[HDSPM_MAX_CHANNELS] = {
822 4, 5, 6, 7, 8, 9, 10, 11, /* ADAT 1 */
823 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT 2 */
824 20, 21, 22, 23, 24, 25, 26, 27, /* ADAT 3 */
825 28, 29, 30, 31, 32, 33, 34, 35, /* ADAT 4 */
826 0, 1, /* AES */
827 2, 3, /* SPDIF */
828 -1, -1, -1, -1,
829 -1, -1, -1, -1, -1, -1, -1, -1,
830 -1, -1, -1, -1, -1, -1, -1, -1,
831 -1, -1, -1, -1, -1, -1, -1, -1,
832 };
833
834 static char channel_map_raydat_ds[HDSPM_MAX_CHANNELS] = {
835 4, 5, 6, 7, /* ADAT 1 */
836 8, 9, 10, 11, /* ADAT 2 */
837 12, 13, 14, 15, /* ADAT 3 */
838 16, 17, 18, 19, /* ADAT 4 */
839 0, 1, /* AES */
840 2, 3, /* SPDIF */
841 -1, -1, -1, -1,
842 -1, -1, -1, -1, -1, -1, -1, -1,
843 -1, -1, -1, -1, -1, -1, -1, -1,
844 -1, -1, -1, -1, -1, -1, -1, -1,
845 -1, -1, -1, -1, -1, -1, -1, -1,
846 -1, -1, -1, -1, -1, -1, -1, -1,
847 };
848
849 static char channel_map_raydat_qs[HDSPM_MAX_CHANNELS] = {
850 4, 5, /* ADAT 1 */
851 6, 7, /* ADAT 2 */
852 8, 9, /* ADAT 3 */
853 10, 11, /* ADAT 4 */
854 0, 1, /* AES */
855 2, 3, /* SPDIF */
856 -1, -1, -1, -1,
857 -1, -1, -1, -1, -1, -1, -1, -1,
858 -1, -1, -1, -1, -1, -1, -1, -1,
859 -1, -1, -1, -1, -1, -1, -1, -1,
860 -1, -1, -1, -1, -1, -1, -1, -1,
861 -1, -1, -1, -1, -1, -1, -1, -1,
862 -1, -1, -1, -1, -1, -1, -1, -1,
863 };
864
865 static char channel_map_aio_in_ss[HDSPM_MAX_CHANNELS] = {
866 0, 1, /* line in */
867 8, 9, /* aes in, */
868 10, 11, /* spdif in */
869 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT in */
870 2, 3, 4, 5, /* AEB */
871 -1, -1, -1, -1, -1, -1,
872 -1, -1, -1, -1, -1, -1, -1, -1,
873 -1, -1, -1, -1, -1, -1, -1, -1,
874 -1, -1, -1, -1, -1, -1, -1, -1,
875 -1, -1, -1, -1, -1, -1, -1, -1,
876 -1, -1, -1, -1, -1, -1, -1, -1,
877 };
878
879 static char channel_map_aio_out_ss[HDSPM_MAX_CHANNELS] = {
880 0, 1, /* line out */
881 8, 9, /* aes out */
882 10, 11, /* spdif out */
883 12, 13, 14, 15, 16, 17, 18, 19, /* ADAT out */
884 6, 7, /* phone out */
885 2, 3, 4, 5, /* AEB */
886 -1, -1, -1, -1,
887 -1, -1, -1, -1, -1, -1, -1, -1,
888 -1, -1, -1, -1, -1, -1, -1, -1,
889 -1, -1, -1, -1, -1, -1, -1, -1,
890 -1, -1, -1, -1, -1, -1, -1, -1,
891 -1, -1, -1, -1, -1, -1, -1, -1,
892 };
893
894 static char channel_map_aio_in_ds[HDSPM_MAX_CHANNELS] = {
895 0, 1, /* line in */
896 8, 9, /* aes in */
897 10, 11, /* spdif in */
898 12, 14, 16, 18, /* adat in */
899 2, 3, 4, 5, /* AEB */
900 -1, -1,
901 -1, -1, -1, -1, -1, -1, -1, -1,
902 -1, -1, -1, -1, -1, -1, -1, -1,
903 -1, -1, -1, -1, -1, -1, -1, -1,
904 -1, -1, -1, -1, -1, -1, -1, -1,
905 -1, -1, -1, -1, -1, -1, -1, -1,
906 -1, -1, -1, -1, -1, -1, -1, -1
907 };
908
909 static char channel_map_aio_out_ds[HDSPM_MAX_CHANNELS] = {
910 0, 1, /* line out */
911 8, 9, /* aes out */
912 10, 11, /* spdif out */
913 12, 14, 16, 18, /* adat out */
914 6, 7, /* phone out */
915 2, 3, 4, 5, /* AEB */
916 -1, -1, -1, -1, -1, -1, -1, -1,
917 -1, -1, -1, -1, -1, -1, -1, -1,
918 -1, -1, -1, -1, -1, -1, -1, -1,
919 -1, -1, -1, -1, -1, -1, -1, -1,
920 -1, -1, -1, -1, -1, -1, -1, -1,
921 -1, -1, -1, -1, -1, -1, -1, -1
922 };
923
924 static char channel_map_aio_in_qs[HDSPM_MAX_CHANNELS] = {
925 0, 1, /* line in */
926 8, 9, /* aes in */
927 10, 11, /* spdif in */
928 12, 16, /* adat in */
929 2, 3, 4, 5, /* AEB */
930 -1, -1, -1, -1,
931 -1, -1, -1, -1, -1, -1, -1, -1,
932 -1, -1, -1, -1, -1, -1, -1, -1,
933 -1, -1, -1, -1, -1, -1, -1, -1,
934 -1, -1, -1, -1, -1, -1, -1, -1,
935 -1, -1, -1, -1, -1, -1, -1, -1,
936 -1, -1, -1, -1, -1, -1, -1, -1
937 };
938
939 static char channel_map_aio_out_qs[HDSPM_MAX_CHANNELS] = {
940 0, 1, /* line out */
941 8, 9, /* aes out */
942 10, 11, /* spdif out */
943 12, 16, /* adat out */
944 6, 7, /* phone out */
945 2, 3, 4, 5, /* AEB */
946 -1, -1,
947 -1, -1, -1, -1, -1, -1, -1, -1,
948 -1, -1, -1, -1, -1, -1, -1, -1,
949 -1, -1, -1, -1, -1, -1, -1, -1,
950 -1, -1, -1, -1, -1, -1, -1, -1,
951 -1, -1, -1, -1, -1, -1, -1, -1,
952 -1, -1, -1, -1, -1, -1, -1, -1
953 };
954
955 static char channel_map_aes32[HDSPM_MAX_CHANNELS] = {
956 0, 1, 2, 3, 4, 5, 6, 7,
957 8, 9, 10, 11, 12, 13, 14, 15,
958 -1, -1, -1, -1, -1, -1, -1, -1,
959 -1, -1, -1, -1, -1, -1, -1, -1,
960 -1, -1, -1, -1, -1, -1, -1, -1,
961 -1, -1, -1, -1, -1, -1, -1, -1,
962 -1, -1, -1, -1, -1, -1, -1, -1,
963 -1, -1, -1, -1, -1, -1, -1, -1
964 };
965
966 struct hdspm_midi {
967 struct hdspm *hdspm;
968 int id;
969 struct snd_rawmidi *rmidi;
970 struct snd_rawmidi_substream *input;
971 struct snd_rawmidi_substream *output;
972 char istimer; /* timer in use */
973 struct timer_list timer;
974 spinlock_t lock;
975 int pending;
976 int dataIn;
977 int statusIn;
978 int dataOut;
979 int statusOut;
980 int ie;
981 int irq;
982 };
983
984 struct hdspm_tco {
985 int input; /* 0: LTC, 1:Video, 2: WC*/
986 int framerate; /* 0=24, 1=25, 2=29.97, 3=29.97d, 4=30, 5=30d */
987 int wordclock; /* 0=1:1, 1=44.1->48, 2=48->44.1 */
988 int samplerate; /* 0=44.1, 1=48, 2= freq from app */
989 int pull; /* 0=0, 1=+0.1%, 2=-0.1%, 3=+4%, 4=-4%*/
990 int term; /* 0 = off, 1 = on */
991 };
992
993 struct hdspm {
994 spinlock_t lock;
995 /* only one playback and/or capture stream */
996 struct snd_pcm_substream *capture_substream;
997 struct snd_pcm_substream *playback_substream;
998
999 char *card_name; /* for procinfo */
1000 unsigned short firmware_rev; /* dont know if relevant (yes if AES32)*/
1001
1002 uint8_t io_type;
1003
1004 int monitor_outs; /* set up monitoring outs init flag */
1005
1006 u32 control_register; /* cached value */
1007 u32 control2_register; /* cached value */
1008 u32 settings_register; /* cached value for AIO / RayDat (sync reference, master/slave) */
1009
1010 struct hdspm_midi midi[4];
1011 struct tasklet_struct midi_tasklet;
1012
1013 size_t period_bytes;
1014 unsigned char ss_in_channels;
1015 unsigned char ds_in_channels;
1016 unsigned char qs_in_channels;
1017 unsigned char ss_out_channels;
1018 unsigned char ds_out_channels;
1019 unsigned char qs_out_channels;
1020
1021 unsigned char max_channels_in;
1022 unsigned char max_channels_out;
1023
1024 signed char *channel_map_in;
1025 signed char *channel_map_out;
1026
1027 signed char *channel_map_in_ss, *channel_map_in_ds, *channel_map_in_qs;
1028 signed char *channel_map_out_ss, *channel_map_out_ds, *channel_map_out_qs;
1029
1030 char **port_names_in;
1031 char **port_names_out;
1032
1033 char **port_names_in_ss, **port_names_in_ds, **port_names_in_qs;
1034 char **port_names_out_ss, **port_names_out_ds, **port_names_out_qs;
1035
1036 unsigned char *playback_buffer; /* suitably aligned address */
1037 unsigned char *capture_buffer; /* suitably aligned address */
1038
1039 pid_t capture_pid; /* process id which uses capture */
1040 pid_t playback_pid; /* process id which uses capture */
1041 int running; /* running status */
1042
1043 int last_external_sample_rate; /* samplerate mystic ... */
1044 int last_internal_sample_rate;
1045 int system_sample_rate;
1046
1047 int dev; /* Hardware vars... */
1048 int irq;
1049 unsigned long port;
1050 void __iomem *iobase;
1051
1052 int irq_count; /* for debug */
1053 int midiPorts;
1054
1055 struct snd_card *card; /* one card */
1056 struct snd_pcm *pcm; /* has one pcm */
1057 struct snd_hwdep *hwdep; /* and a hwdep for additional ioctl */
1058 struct pci_dev *pci; /* and an pci info */
1059
1060 /* Mixer vars */
1061 /* fast alsa mixer */
1062 struct snd_kcontrol *playback_mixer_ctls[HDSPM_MAX_CHANNELS];
1063 /* but input to much, so not used */
1064 struct snd_kcontrol *input_mixer_ctls[HDSPM_MAX_CHANNELS];
1065 /* full mixer accessible over mixer ioctl or hwdep-device */
1066 struct hdspm_mixer *mixer;
1067
1068 struct hdspm_tco *tco; /* NULL if no TCO detected */
1069
1070 const char *const *texts_autosync;
1071 int texts_autosync_items;
1072
1073 cycles_t last_interrupt;
1074
1075 unsigned int serial;
1076
1077 struct hdspm_peak_rms peak_rms;
1078 };
1079
1080
1081 static const struct pci_device_id snd_hdspm_ids[] = {
1082 {
1083 .vendor = PCI_VENDOR_ID_XILINX,
1084 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP_MADI,
1085 .subvendor = PCI_ANY_ID,
1086 .subdevice = PCI_ANY_ID,
1087 .class = 0,
1088 .class_mask = 0,
1089 .driver_data = 0},
1090 {0,}
1091 };
1092
1093 MODULE_DEVICE_TABLE(pci, snd_hdspm_ids);
1094
1095 /* prototypes */
1096 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
1097 struct hdspm *hdspm);
1098 static int snd_hdspm_create_pcm(struct snd_card *card,
1099 struct hdspm *hdspm);
1100
1101 static inline void snd_hdspm_initialize_midi_flush(struct hdspm *hdspm);
1102 static inline int hdspm_get_pll_freq(struct hdspm *hdspm);
1103 static int hdspm_update_simple_mixer_controls(struct hdspm *hdspm);
1104 static int hdspm_autosync_ref(struct hdspm *hdspm);
1105 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out);
1106 static int snd_hdspm_set_defaults(struct hdspm *hdspm);
1107 static int hdspm_system_clock_mode(struct hdspm *hdspm);
1108 static void hdspm_set_sgbuf(struct hdspm *hdspm,
1109 struct snd_pcm_substream *substream,
1110 unsigned int reg, int channels);
1111
1112 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx);
1113 static int hdspm_wc_sync_check(struct hdspm *hdspm);
1114 static int hdspm_tco_sync_check(struct hdspm *hdspm);
1115 static int hdspm_sync_in_sync_check(struct hdspm *hdspm);
1116
1117 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index);
1118 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm);
1119 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm);
1120
1121
1122
1123 static inline int HDSPM_bit2freq(int n)
1124 {
1125 static const int bit2freq_tab[] = {
1126 0, 32000, 44100, 48000, 64000, 88200,
1127 96000, 128000, 176400, 192000 };
1128 if (n < 1 || n > 9)
1129 return 0;
1130 return bit2freq_tab[n];
1131 }
1132
1133 static bool hdspm_is_raydat_or_aio(struct hdspm *hdspm)
1134 {
1135 return ((AIO == hdspm->io_type) || (RayDAT == hdspm->io_type));
1136 }
1137
1138
1139 /* Write/read to/from HDSPM with Adresses in Bytes
1140 not words but only 32Bit writes are allowed */
1141
1142 static inline void hdspm_write(struct hdspm * hdspm, unsigned int reg,
1143 unsigned int val)
1144 {
1145 writel(val, hdspm->iobase + reg);
1146 }
1147
1148 static inline unsigned int hdspm_read(struct hdspm * hdspm, unsigned int reg)
1149 {
1150 return readl(hdspm->iobase + reg);
1151 }
1152
1153 /* for each output channel (chan) I have an Input (in) and Playback (pb) Fader
1154 mixer is write only on hardware so we have to cache him for read
1155 each fader is a u32, but uses only the first 16 bit */
1156
1157 static inline int hdspm_read_in_gain(struct hdspm * hdspm, unsigned int chan,
1158 unsigned int in)
1159 {
1160 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1161 return 0;
1162
1163 return hdspm->mixer->ch[chan].in[in];
1164 }
1165
1166 static inline int hdspm_read_pb_gain(struct hdspm * hdspm, unsigned int chan,
1167 unsigned int pb)
1168 {
1169 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1170 return 0;
1171 return hdspm->mixer->ch[chan].pb[pb];
1172 }
1173
1174 static int hdspm_write_in_gain(struct hdspm *hdspm, unsigned int chan,
1175 unsigned int in, unsigned short data)
1176 {
1177 if (chan >= HDSPM_MIXER_CHANNELS || in >= HDSPM_MIXER_CHANNELS)
1178 return -1;
1179
1180 hdspm_write(hdspm,
1181 HDSPM_MADI_mixerBase +
1182 ((in + 128 * chan) * sizeof(u32)),
1183 (hdspm->mixer->ch[chan].in[in] = data & 0xFFFF));
1184 return 0;
1185 }
1186
1187 static int hdspm_write_pb_gain(struct hdspm *hdspm, unsigned int chan,
1188 unsigned int pb, unsigned short data)
1189 {
1190 if (chan >= HDSPM_MIXER_CHANNELS || pb >= HDSPM_MIXER_CHANNELS)
1191 return -1;
1192
1193 hdspm_write(hdspm,
1194 HDSPM_MADI_mixerBase +
1195 ((64 + pb + 128 * chan) * sizeof(u32)),
1196 (hdspm->mixer->ch[chan].pb[pb] = data & 0xFFFF));
1197 return 0;
1198 }
1199
1200
1201 /* enable DMA for specific channels, now available for DSP-MADI */
1202 static inline void snd_hdspm_enable_in(struct hdspm * hdspm, int i, int v)
1203 {
1204 hdspm_write(hdspm, HDSPM_inputEnableBase + (4 * i), v);
1205 }
1206
1207 static inline void snd_hdspm_enable_out(struct hdspm * hdspm, int i, int v)
1208 {
1209 hdspm_write(hdspm, HDSPM_outputEnableBase + (4 * i), v);
1210 }
1211
1212 /* check if same process is writing and reading */
1213 static int snd_hdspm_use_is_exclusive(struct hdspm *hdspm)
1214 {
1215 unsigned long flags;
1216 int ret = 1;
1217
1218 spin_lock_irqsave(&hdspm->lock, flags);
1219 if ((hdspm->playback_pid != hdspm->capture_pid) &&
1220 (hdspm->playback_pid >= 0) && (hdspm->capture_pid >= 0)) {
1221 ret = 0;
1222 }
1223 spin_unlock_irqrestore(&hdspm->lock, flags);
1224 return ret;
1225 }
1226
1227 /* round arbitary sample rates to commonly known rates */
1228 static int hdspm_round_frequency(int rate)
1229 {
1230 if (rate < 38050)
1231 return 32000;
1232 if (rate < 46008)
1233 return 44100;
1234 else
1235 return 48000;
1236 }
1237
1238 /* QS and DS rates normally can not be detected
1239 * automatically by the card. Only exception is MADI
1240 * in 96k frame mode.
1241 *
1242 * So if we read SS values (32 .. 48k), check for
1243 * user-provided DS/QS bits in the control register
1244 * and multiply the base frequency accordingly.
1245 */
1246 static int hdspm_rate_multiplier(struct hdspm *hdspm, int rate)
1247 {
1248 if (rate <= 48000) {
1249 if (hdspm->control_register & HDSPM_QuadSpeed)
1250 return rate * 4;
1251 else if (hdspm->control_register &
1252 HDSPM_DoubleSpeed)
1253 return rate * 2;
1254 }
1255 return rate;
1256 }
1257
1258 /* check for external sample rate, returns the sample rate in Hz*/
1259 static int hdspm_external_sample_rate(struct hdspm *hdspm)
1260 {
1261 unsigned int status, status2;
1262 int syncref, rate = 0, rate_bits;
1263
1264 switch (hdspm->io_type) {
1265 case AES32:
1266 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1267 status = hdspm_read(hdspm, HDSPM_statusRegister);
1268
1269 syncref = hdspm_autosync_ref(hdspm);
1270 switch (syncref) {
1271 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
1272 /* Check WC sync and get sample rate */
1273 if (hdspm_wc_sync_check(hdspm))
1274 return HDSPM_bit2freq(hdspm_get_wc_sample_rate(hdspm));
1275 break;
1276
1277 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
1278 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
1279 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
1280 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
1281 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
1282 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
1283 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
1284 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
1285 /* Check AES sync and get sample rate */
1286 if (hdspm_aes_sync_check(hdspm, syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1))
1287 return HDSPM_bit2freq(hdspm_get_aes_sample_rate(hdspm,
1288 syncref - HDSPM_AES32_AUTOSYNC_FROM_AES1));
1289 break;
1290
1291
1292 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
1293 /* Check TCO sync and get sample rate */
1294 if (hdspm_tco_sync_check(hdspm))
1295 return HDSPM_bit2freq(hdspm_get_tco_sample_rate(hdspm));
1296 break;
1297 default:
1298 return 0;
1299 } /* end switch(syncref) */
1300 break;
1301
1302 case MADIface:
1303 status = hdspm_read(hdspm, HDSPM_statusRegister);
1304
1305 if (!(status & HDSPM_madiLock)) {
1306 rate = 0; /* no lock */
1307 } else {
1308 switch (status & (HDSPM_status1_freqMask)) {
1309 case HDSPM_status1_F_0*1:
1310 rate = 32000; break;
1311 case HDSPM_status1_F_0*2:
1312 rate = 44100; break;
1313 case HDSPM_status1_F_0*3:
1314 rate = 48000; break;
1315 case HDSPM_status1_F_0*4:
1316 rate = 64000; break;
1317 case HDSPM_status1_F_0*5:
1318 rate = 88200; break;
1319 case HDSPM_status1_F_0*6:
1320 rate = 96000; break;
1321 case HDSPM_status1_F_0*7:
1322 rate = 128000; break;
1323 case HDSPM_status1_F_0*8:
1324 rate = 176400; break;
1325 case HDSPM_status1_F_0*9:
1326 rate = 192000; break;
1327 default:
1328 rate = 0; break;
1329 }
1330 }
1331
1332 break;
1333
1334 case MADI:
1335 case AIO:
1336 case RayDAT:
1337 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
1338 status = hdspm_read(hdspm, HDSPM_statusRegister);
1339 rate = 0;
1340
1341 /* if wordclock has synced freq and wordclock is valid */
1342 if ((status2 & HDSPM_wcLock) != 0 &&
1343 (status2 & HDSPM_SelSyncRef0) == 0) {
1344
1345 rate_bits = status2 & HDSPM_wcFreqMask;
1346
1347
1348 switch (rate_bits) {
1349 case HDSPM_wcFreq32:
1350 rate = 32000;
1351 break;
1352 case HDSPM_wcFreq44_1:
1353 rate = 44100;
1354 break;
1355 case HDSPM_wcFreq48:
1356 rate = 48000;
1357 break;
1358 case HDSPM_wcFreq64:
1359 rate = 64000;
1360 break;
1361 case HDSPM_wcFreq88_2:
1362 rate = 88200;
1363 break;
1364 case HDSPM_wcFreq96:
1365 rate = 96000;
1366 break;
1367 case HDSPM_wcFreq128:
1368 rate = 128000;
1369 break;
1370 case HDSPM_wcFreq176_4:
1371 rate = 176400;
1372 break;
1373 case HDSPM_wcFreq192:
1374 rate = 192000;
1375 break;
1376 default:
1377 rate = 0;
1378 break;
1379 }
1380 }
1381
1382 /* if rate detected and Syncref is Word than have it,
1383 * word has priority to MADI
1384 */
1385 if (rate != 0 &&
1386 (status2 & HDSPM_SelSyncRefMask) == HDSPM_SelSyncRef_WORD)
1387 return hdspm_rate_multiplier(hdspm, rate);
1388
1389 /* maybe a madi input (which is taken if sel sync is madi) */
1390 if (status & HDSPM_madiLock) {
1391 rate_bits = status & HDSPM_madiFreqMask;
1392
1393 switch (rate_bits) {
1394 case HDSPM_madiFreq32:
1395 rate = 32000;
1396 break;
1397 case HDSPM_madiFreq44_1:
1398 rate = 44100;
1399 break;
1400 case HDSPM_madiFreq48:
1401 rate = 48000;
1402 break;
1403 case HDSPM_madiFreq64:
1404 rate = 64000;
1405 break;
1406 case HDSPM_madiFreq88_2:
1407 rate = 88200;
1408 break;
1409 case HDSPM_madiFreq96:
1410 rate = 96000;
1411 break;
1412 case HDSPM_madiFreq128:
1413 rate = 128000;
1414 break;
1415 case HDSPM_madiFreq176_4:
1416 rate = 176400;
1417 break;
1418 case HDSPM_madiFreq192:
1419 rate = 192000;
1420 break;
1421 default:
1422 rate = 0;
1423 break;
1424 }
1425
1426 } /* endif HDSPM_madiLock */
1427
1428 /* check sample rate from TCO or SYNC_IN */
1429 {
1430 bool is_valid_input = 0;
1431 bool has_sync = 0;
1432
1433 syncref = hdspm_autosync_ref(hdspm);
1434 if (HDSPM_AUTOSYNC_FROM_TCO == syncref) {
1435 is_valid_input = 1;
1436 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1437 hdspm_tco_sync_check(hdspm));
1438 } else if (HDSPM_AUTOSYNC_FROM_SYNC_IN == syncref) {
1439 is_valid_input = 1;
1440 has_sync = (HDSPM_SYNC_CHECK_SYNC ==
1441 hdspm_sync_in_sync_check(hdspm));
1442 }
1443
1444 if (is_valid_input && has_sync) {
1445 rate = hdspm_round_frequency(
1446 hdspm_get_pll_freq(hdspm));
1447 }
1448 }
1449
1450 rate = hdspm_rate_multiplier(hdspm, rate);
1451
1452 break;
1453 }
1454
1455 return rate;
1456 }
1457
1458 /* return latency in samples per period */
1459 static int hdspm_get_latency(struct hdspm *hdspm)
1460 {
1461 int n;
1462
1463 n = hdspm_decode_latency(hdspm->control_register);
1464
1465 /* Special case for new RME cards with 32 samples period size.
1466 * The three latency bits in the control register
1467 * (HDSP_LatencyMask) encode latency values of 64 samples as
1468 * 0, 128 samples as 1 ... 4096 samples as 6. For old cards, 7
1469 * denotes 8192 samples, but on new cards like RayDAT or AIO,
1470 * it corresponds to 32 samples.
1471 */
1472 if ((7 == n) && (RayDAT == hdspm->io_type || AIO == hdspm->io_type))
1473 n = -1;
1474
1475 return 1 << (n + 6);
1476 }
1477
1478 /* Latency function */
1479 static inline void hdspm_compute_period_size(struct hdspm *hdspm)
1480 {
1481 hdspm->period_bytes = 4 * hdspm_get_latency(hdspm);
1482 }
1483
1484
1485 static snd_pcm_uframes_t hdspm_hw_pointer(struct hdspm *hdspm)
1486 {
1487 int position;
1488
1489 position = hdspm_read(hdspm, HDSPM_statusRegister);
1490
1491 switch (hdspm->io_type) {
1492 case RayDAT:
1493 case AIO:
1494 position &= HDSPM_BufferPositionMask;
1495 position /= 4; /* Bytes per sample */
1496 break;
1497 default:
1498 position = (position & HDSPM_BufferID) ?
1499 (hdspm->period_bytes / 4) : 0;
1500 }
1501
1502 return position;
1503 }
1504
1505
1506 static inline void hdspm_start_audio(struct hdspm * s)
1507 {
1508 s->control_register |= (HDSPM_AudioInterruptEnable | HDSPM_Start);
1509 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1510 }
1511
1512 static inline void hdspm_stop_audio(struct hdspm * s)
1513 {
1514 s->control_register &= ~(HDSPM_Start | HDSPM_AudioInterruptEnable);
1515 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1516 }
1517
1518 /* should I silence all or only opened ones ? doit all for first even is 4MB*/
1519 static void hdspm_silence_playback(struct hdspm *hdspm)
1520 {
1521 int i;
1522 int n = hdspm->period_bytes;
1523 void *buf = hdspm->playback_buffer;
1524
1525 if (!buf)
1526 return;
1527
1528 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
1529 memset(buf, 0, n);
1530 buf += HDSPM_CHANNEL_BUFFER_BYTES;
1531 }
1532 }
1533
1534 static int hdspm_set_interrupt_interval(struct hdspm *s, unsigned int frames)
1535 {
1536 int n;
1537
1538 spin_lock_irq(&s->lock);
1539
1540 if (32 == frames) {
1541 /* Special case for new RME cards like RayDAT/AIO which
1542 * support period sizes of 32 samples. Since latency is
1543 * encoded in the three bits of HDSP_LatencyMask, we can only
1544 * have values from 0 .. 7. While 0 still means 64 samples and
1545 * 6 represents 4096 samples on all cards, 7 represents 8192
1546 * on older cards and 32 samples on new cards.
1547 *
1548 * In other words, period size in samples is calculated by
1549 * 2^(n+6) with n ranging from 0 .. 7.
1550 */
1551 n = 7;
1552 } else {
1553 frames >>= 7;
1554 n = 0;
1555 while (frames) {
1556 n++;
1557 frames >>= 1;
1558 }
1559 }
1560
1561 s->control_register &= ~HDSPM_LatencyMask;
1562 s->control_register |= hdspm_encode_latency(n);
1563
1564 hdspm_write(s, HDSPM_controlRegister, s->control_register);
1565
1566 hdspm_compute_period_size(s);
1567
1568 spin_unlock_irq(&s->lock);
1569
1570 return 0;
1571 }
1572
1573 static u64 hdspm_calc_dds_value(struct hdspm *hdspm, u64 period)
1574 {
1575 u64 freq_const;
1576
1577 if (period == 0)
1578 return 0;
1579
1580 switch (hdspm->io_type) {
1581 case MADI:
1582 case AES32:
1583 freq_const = 110069313433624ULL;
1584 break;
1585 case RayDAT:
1586 case AIO:
1587 freq_const = 104857600000000ULL;
1588 break;
1589 case MADIface:
1590 freq_const = 131072000000000ULL;
1591 break;
1592 default:
1593 snd_BUG();
1594 return 0;
1595 }
1596
1597 return div_u64(freq_const, period);
1598 }
1599
1600
1601 static void hdspm_set_dds_value(struct hdspm *hdspm, int rate)
1602 {
1603 u64 n;
1604
1605 if (snd_BUG_ON(rate <= 0))
1606 return;
1607
1608 if (rate >= 112000)
1609 rate /= 4;
1610 else if (rate >= 56000)
1611 rate /= 2;
1612
1613 switch (hdspm->io_type) {
1614 case MADIface:
1615 n = 131072000000000ULL; /* 125 MHz */
1616 break;
1617 case MADI:
1618 case AES32:
1619 n = 110069313433624ULL; /* 105 MHz */
1620 break;
1621 case RayDAT:
1622 case AIO:
1623 n = 104857600000000ULL; /* 100 MHz */
1624 break;
1625 default:
1626 snd_BUG();
1627 return;
1628 }
1629
1630 n = div_u64(n, rate);
1631 /* n should be less than 2^32 for being written to FREQ register */
1632 snd_BUG_ON(n >> 32);
1633 hdspm_write(hdspm, HDSPM_freqReg, (u32)n);
1634 }
1635
1636 /* dummy set rate lets see what happens */
1637 static int hdspm_set_rate(struct hdspm * hdspm, int rate, int called_internally)
1638 {
1639 int current_rate;
1640 int rate_bits;
1641 int not_set = 0;
1642 int current_speed, target_speed;
1643
1644 /* ASSUMPTION: hdspm->lock is either set, or there is no need for
1645 it (e.g. during module initialization).
1646 */
1647
1648 if (!(hdspm->control_register & HDSPM_ClockModeMaster)) {
1649
1650 /* SLAVE --- */
1651 if (called_internally) {
1652
1653 /* request from ctl or card initialization
1654 just make a warning an remember setting
1655 for future master mode switching */
1656
1657 dev_warn(hdspm->card->dev,
1658 "Warning: device is not running as a clock master.\n");
1659 not_set = 1;
1660 } else {
1661
1662 /* hw_param request while in AutoSync mode */
1663 int external_freq =
1664 hdspm_external_sample_rate(hdspm);
1665
1666 if (hdspm_autosync_ref(hdspm) ==
1667 HDSPM_AUTOSYNC_FROM_NONE) {
1668
1669 dev_warn(hdspm->card->dev,
1670 "Detected no External Sync\n");
1671 not_set = 1;
1672
1673 } else if (rate != external_freq) {
1674
1675 dev_warn(hdspm->card->dev,
1676 "Warning: No AutoSync source for requested rate\n");
1677 not_set = 1;
1678 }
1679 }
1680 }
1681
1682 current_rate = hdspm->system_sample_rate;
1683
1684 /* Changing between Singe, Double and Quad speed is not
1685 allowed if any substreams are open. This is because such a change
1686 causes a shift in the location of the DMA buffers and a reduction
1687 in the number of available buffers.
1688
1689 Note that a similar but essentially insoluble problem exists for
1690 externally-driven rate changes. All we can do is to flag rate
1691 changes in the read/write routines.
1692 */
1693
1694 if (current_rate <= 48000)
1695 current_speed = HDSPM_SPEED_SINGLE;
1696 else if (current_rate <= 96000)
1697 current_speed = HDSPM_SPEED_DOUBLE;
1698 else
1699 current_speed = HDSPM_SPEED_QUAD;
1700
1701 if (rate <= 48000)
1702 target_speed = HDSPM_SPEED_SINGLE;
1703 else if (rate <= 96000)
1704 target_speed = HDSPM_SPEED_DOUBLE;
1705 else
1706 target_speed = HDSPM_SPEED_QUAD;
1707
1708 switch (rate) {
1709 case 32000:
1710 rate_bits = HDSPM_Frequency32KHz;
1711 break;
1712 case 44100:
1713 rate_bits = HDSPM_Frequency44_1KHz;
1714 break;
1715 case 48000:
1716 rate_bits = HDSPM_Frequency48KHz;
1717 break;
1718 case 64000:
1719 rate_bits = HDSPM_Frequency64KHz;
1720 break;
1721 case 88200:
1722 rate_bits = HDSPM_Frequency88_2KHz;
1723 break;
1724 case 96000:
1725 rate_bits = HDSPM_Frequency96KHz;
1726 break;
1727 case 128000:
1728 rate_bits = HDSPM_Frequency128KHz;
1729 break;
1730 case 176400:
1731 rate_bits = HDSPM_Frequency176_4KHz;
1732 break;
1733 case 192000:
1734 rate_bits = HDSPM_Frequency192KHz;
1735 break;
1736 default:
1737 return -EINVAL;
1738 }
1739
1740 if (current_speed != target_speed
1741 && (hdspm->capture_pid >= 0 || hdspm->playback_pid >= 0)) {
1742 dev_err(hdspm->card->dev,
1743 "cannot change from %s speed to %s speed mode (capture PID = %d, playback PID = %d)\n",
1744 hdspm_speed_names[current_speed],
1745 hdspm_speed_names[target_speed],
1746 hdspm->capture_pid, hdspm->playback_pid);
1747 return -EBUSY;
1748 }
1749
1750 hdspm->control_register &= ~HDSPM_FrequencyMask;
1751 hdspm->control_register |= rate_bits;
1752 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1753
1754 /* For AES32, need to set DDS value in FREQ register
1755 For MADI, also apparently */
1756 hdspm_set_dds_value(hdspm, rate);
1757
1758 if (AES32 == hdspm->io_type && rate != current_rate)
1759 hdspm_write(hdspm, HDSPM_eeprom_wr, 0);
1760
1761 hdspm->system_sample_rate = rate;
1762
1763 if (rate <= 48000) {
1764 hdspm->channel_map_in = hdspm->channel_map_in_ss;
1765 hdspm->channel_map_out = hdspm->channel_map_out_ss;
1766 hdspm->max_channels_in = hdspm->ss_in_channels;
1767 hdspm->max_channels_out = hdspm->ss_out_channels;
1768 hdspm->port_names_in = hdspm->port_names_in_ss;
1769 hdspm->port_names_out = hdspm->port_names_out_ss;
1770 } else if (rate <= 96000) {
1771 hdspm->channel_map_in = hdspm->channel_map_in_ds;
1772 hdspm->channel_map_out = hdspm->channel_map_out_ds;
1773 hdspm->max_channels_in = hdspm->ds_in_channels;
1774 hdspm->max_channels_out = hdspm->ds_out_channels;
1775 hdspm->port_names_in = hdspm->port_names_in_ds;
1776 hdspm->port_names_out = hdspm->port_names_out_ds;
1777 } else {
1778 hdspm->channel_map_in = hdspm->channel_map_in_qs;
1779 hdspm->channel_map_out = hdspm->channel_map_out_qs;
1780 hdspm->max_channels_in = hdspm->qs_in_channels;
1781 hdspm->max_channels_out = hdspm->qs_out_channels;
1782 hdspm->port_names_in = hdspm->port_names_in_qs;
1783 hdspm->port_names_out = hdspm->port_names_out_qs;
1784 }
1785
1786 if (not_set != 0)
1787 return -1;
1788
1789 return 0;
1790 }
1791
1792 /* mainly for init to 0 on load */
1793 static void all_in_all_mixer(struct hdspm * hdspm, int sgain)
1794 {
1795 int i, j;
1796 unsigned int gain;
1797
1798 if (sgain > UNITY_GAIN)
1799 gain = UNITY_GAIN;
1800 else if (sgain < 0)
1801 gain = 0;
1802 else
1803 gain = sgain;
1804
1805 for (i = 0; i < HDSPM_MIXER_CHANNELS; i++)
1806 for (j = 0; j < HDSPM_MIXER_CHANNELS; j++) {
1807 hdspm_write_in_gain(hdspm, i, j, gain);
1808 hdspm_write_pb_gain(hdspm, i, j, gain);
1809 }
1810 }
1811
1812 /*----------------------------------------------------------------------------
1813 MIDI
1814 ----------------------------------------------------------------------------*/
1815
1816 static inline unsigned char snd_hdspm_midi_read_byte (struct hdspm *hdspm,
1817 int id)
1818 {
1819 /* the hardware already does the relevant bit-mask with 0xff */
1820 return hdspm_read(hdspm, hdspm->midi[id].dataIn);
1821 }
1822
1823 static inline void snd_hdspm_midi_write_byte (struct hdspm *hdspm, int id,
1824 int val)
1825 {
1826 /* the hardware already does the relevant bit-mask with 0xff */
1827 return hdspm_write(hdspm, hdspm->midi[id].dataOut, val);
1828 }
1829
1830 static inline int snd_hdspm_midi_input_available (struct hdspm *hdspm, int id)
1831 {
1832 return hdspm_read(hdspm, hdspm->midi[id].statusIn) & 0xFF;
1833 }
1834
1835 static inline int snd_hdspm_midi_output_possible (struct hdspm *hdspm, int id)
1836 {
1837 int fifo_bytes_used;
1838
1839 fifo_bytes_used = hdspm_read(hdspm, hdspm->midi[id].statusOut) & 0xFF;
1840
1841 if (fifo_bytes_used < 128)
1842 return 128 - fifo_bytes_used;
1843 else
1844 return 0;
1845 }
1846
1847 static void snd_hdspm_flush_midi_input(struct hdspm *hdspm, int id)
1848 {
1849 while (snd_hdspm_midi_input_available (hdspm, id))
1850 snd_hdspm_midi_read_byte (hdspm, id);
1851 }
1852
1853 static int snd_hdspm_midi_output_write (struct hdspm_midi *hmidi)
1854 {
1855 unsigned long flags;
1856 int n_pending;
1857 int to_write;
1858 int i;
1859 unsigned char buf[128];
1860
1861 /* Output is not interrupt driven */
1862
1863 spin_lock_irqsave (&hmidi->lock, flags);
1864 if (hmidi->output &&
1865 !snd_rawmidi_transmit_empty (hmidi->output)) {
1866 n_pending = snd_hdspm_midi_output_possible (hmidi->hdspm,
1867 hmidi->id);
1868 if (n_pending > 0) {
1869 if (n_pending > (int)sizeof (buf))
1870 n_pending = sizeof (buf);
1871
1872 to_write = snd_rawmidi_transmit (hmidi->output, buf,
1873 n_pending);
1874 if (to_write > 0) {
1875 for (i = 0; i < to_write; ++i)
1876 snd_hdspm_midi_write_byte (hmidi->hdspm,
1877 hmidi->id,
1878 buf[i]);
1879 }
1880 }
1881 }
1882 spin_unlock_irqrestore (&hmidi->lock, flags);
1883 return 0;
1884 }
1885
1886 static int snd_hdspm_midi_input_read (struct hdspm_midi *hmidi)
1887 {
1888 unsigned char buf[128]; /* this buffer is designed to match the MIDI
1889 * input FIFO size
1890 */
1891 unsigned long flags;
1892 int n_pending;
1893 int i;
1894
1895 spin_lock_irqsave (&hmidi->lock, flags);
1896 n_pending = snd_hdspm_midi_input_available (hmidi->hdspm, hmidi->id);
1897 if (n_pending > 0) {
1898 if (hmidi->input) {
1899 if (n_pending > (int)sizeof (buf))
1900 n_pending = sizeof (buf);
1901 for (i = 0; i < n_pending; ++i)
1902 buf[i] = snd_hdspm_midi_read_byte (hmidi->hdspm,
1903 hmidi->id);
1904 if (n_pending)
1905 snd_rawmidi_receive (hmidi->input, buf,
1906 n_pending);
1907 } else {
1908 /* flush the MIDI input FIFO */
1909 while (n_pending--)
1910 snd_hdspm_midi_read_byte (hmidi->hdspm,
1911 hmidi->id);
1912 }
1913 }
1914 hmidi->pending = 0;
1915 spin_unlock_irqrestore(&hmidi->lock, flags);
1916
1917 spin_lock_irqsave(&hmidi->hdspm->lock, flags);
1918 hmidi->hdspm->control_register |= hmidi->ie;
1919 hdspm_write(hmidi->hdspm, HDSPM_controlRegister,
1920 hmidi->hdspm->control_register);
1921 spin_unlock_irqrestore(&hmidi->hdspm->lock, flags);
1922
1923 return snd_hdspm_midi_output_write (hmidi);
1924 }
1925
1926 static void
1927 snd_hdspm_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1928 {
1929 struct hdspm *hdspm;
1930 struct hdspm_midi *hmidi;
1931 unsigned long flags;
1932
1933 hmidi = substream->rmidi->private_data;
1934 hdspm = hmidi->hdspm;
1935
1936 spin_lock_irqsave (&hdspm->lock, flags);
1937 if (up) {
1938 if (!(hdspm->control_register & hmidi->ie)) {
1939 snd_hdspm_flush_midi_input (hdspm, hmidi->id);
1940 hdspm->control_register |= hmidi->ie;
1941 }
1942 } else {
1943 hdspm->control_register &= ~hmidi->ie;
1944 }
1945
1946 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
1947 spin_unlock_irqrestore (&hdspm->lock, flags);
1948 }
1949
1950 static void snd_hdspm_midi_output_timer(struct timer_list *t)
1951 {
1952 struct hdspm_midi *hmidi = from_timer(hmidi, t, timer);
1953 unsigned long flags;
1954
1955 snd_hdspm_midi_output_write(hmidi);
1956 spin_lock_irqsave (&hmidi->lock, flags);
1957
1958 /* this does not bump hmidi->istimer, because the
1959 kernel automatically removed the timer when it
1960 expired, and we are now adding it back, thus
1961 leaving istimer wherever it was set before.
1962 */
1963
1964 if (hmidi->istimer)
1965 mod_timer(&hmidi->timer, 1 + jiffies);
1966
1967 spin_unlock_irqrestore (&hmidi->lock, flags);
1968 }
1969
1970 static void
1971 snd_hdspm_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1972 {
1973 struct hdspm_midi *hmidi;
1974 unsigned long flags;
1975
1976 hmidi = substream->rmidi->private_data;
1977 spin_lock_irqsave (&hmidi->lock, flags);
1978 if (up) {
1979 if (!hmidi->istimer) {
1980 timer_setup(&hmidi->timer,
1981 snd_hdspm_midi_output_timer, 0);
1982 mod_timer(&hmidi->timer, 1 + jiffies);
1983 hmidi->istimer++;
1984 }
1985 } else {
1986 if (hmidi->istimer && --hmidi->istimer <= 0)
1987 del_timer (&hmidi->timer);
1988 }
1989 spin_unlock_irqrestore (&hmidi->lock, flags);
1990 if (up)
1991 snd_hdspm_midi_output_write(hmidi);
1992 }
1993
1994 static int snd_hdspm_midi_input_open(struct snd_rawmidi_substream *substream)
1995 {
1996 struct hdspm_midi *hmidi;
1997
1998 hmidi = substream->rmidi->private_data;
1999 spin_lock_irq (&hmidi->lock);
2000 snd_hdspm_flush_midi_input (hmidi->hdspm, hmidi->id);
2001 hmidi->input = substream;
2002 spin_unlock_irq (&hmidi->lock);
2003
2004 return 0;
2005 }
2006
2007 static int snd_hdspm_midi_output_open(struct snd_rawmidi_substream *substream)
2008 {
2009 struct hdspm_midi *hmidi;
2010
2011 hmidi = substream->rmidi->private_data;
2012 spin_lock_irq (&hmidi->lock);
2013 hmidi->output = substream;
2014 spin_unlock_irq (&hmidi->lock);
2015
2016 return 0;
2017 }
2018
2019 static int snd_hdspm_midi_input_close(struct snd_rawmidi_substream *substream)
2020 {
2021 struct hdspm_midi *hmidi;
2022
2023 snd_hdspm_midi_input_trigger (substream, 0);
2024
2025 hmidi = substream->rmidi->private_data;
2026 spin_lock_irq (&hmidi->lock);
2027 hmidi->input = NULL;
2028 spin_unlock_irq (&hmidi->lock);
2029
2030 return 0;
2031 }
2032
2033 static int snd_hdspm_midi_output_close(struct snd_rawmidi_substream *substream)
2034 {
2035 struct hdspm_midi *hmidi;
2036
2037 snd_hdspm_midi_output_trigger (substream, 0);
2038
2039 hmidi = substream->rmidi->private_data;
2040 spin_lock_irq (&hmidi->lock);
2041 hmidi->output = NULL;
2042 spin_unlock_irq (&hmidi->lock);
2043
2044 return 0;
2045 }
2046
2047 static const struct snd_rawmidi_ops snd_hdspm_midi_output =
2048 {
2049 .open = snd_hdspm_midi_output_open,
2050 .close = snd_hdspm_midi_output_close,
2051 .trigger = snd_hdspm_midi_output_trigger,
2052 };
2053
2054 static const struct snd_rawmidi_ops snd_hdspm_midi_input =
2055 {
2056 .open = snd_hdspm_midi_input_open,
2057 .close = snd_hdspm_midi_input_close,
2058 .trigger = snd_hdspm_midi_input_trigger,
2059 };
2060
2061 static int snd_hdspm_create_midi(struct snd_card *card,
2062 struct hdspm *hdspm, int id)
2063 {
2064 int err;
2065 char buf[64];
2066
2067 hdspm->midi[id].id = id;
2068 hdspm->midi[id].hdspm = hdspm;
2069 spin_lock_init (&hdspm->midi[id].lock);
2070
2071 if (0 == id) {
2072 if (MADIface == hdspm->io_type) {
2073 /* MIDI-over-MADI on HDSPe MADIface */
2074 hdspm->midi[0].dataIn = HDSPM_midiDataIn2;
2075 hdspm->midi[0].statusIn = HDSPM_midiStatusIn2;
2076 hdspm->midi[0].dataOut = HDSPM_midiDataOut2;
2077 hdspm->midi[0].statusOut = HDSPM_midiStatusOut2;
2078 hdspm->midi[0].ie = HDSPM_Midi2InterruptEnable;
2079 hdspm->midi[0].irq = HDSPM_midi2IRQPending;
2080 } else {
2081 hdspm->midi[0].dataIn = HDSPM_midiDataIn0;
2082 hdspm->midi[0].statusIn = HDSPM_midiStatusIn0;
2083 hdspm->midi[0].dataOut = HDSPM_midiDataOut0;
2084 hdspm->midi[0].statusOut = HDSPM_midiStatusOut0;
2085 hdspm->midi[0].ie = HDSPM_Midi0InterruptEnable;
2086 hdspm->midi[0].irq = HDSPM_midi0IRQPending;
2087 }
2088 } else if (1 == id) {
2089 hdspm->midi[1].dataIn = HDSPM_midiDataIn1;
2090 hdspm->midi[1].statusIn = HDSPM_midiStatusIn1;
2091 hdspm->midi[1].dataOut = HDSPM_midiDataOut1;
2092 hdspm->midi[1].statusOut = HDSPM_midiStatusOut1;
2093 hdspm->midi[1].ie = HDSPM_Midi1InterruptEnable;
2094 hdspm->midi[1].irq = HDSPM_midi1IRQPending;
2095 } else if ((2 == id) && (MADI == hdspm->io_type)) {
2096 /* MIDI-over-MADI on HDSPe MADI */
2097 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2098 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2099 hdspm->midi[2].dataOut = HDSPM_midiDataOut2;
2100 hdspm->midi[2].statusOut = HDSPM_midiStatusOut2;
2101 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2102 hdspm->midi[2].irq = HDSPM_midi2IRQPending;
2103 } else if (2 == id) {
2104 /* TCO MTC, read only */
2105 hdspm->midi[2].dataIn = HDSPM_midiDataIn2;
2106 hdspm->midi[2].statusIn = HDSPM_midiStatusIn2;
2107 hdspm->midi[2].dataOut = -1;
2108 hdspm->midi[2].statusOut = -1;
2109 hdspm->midi[2].ie = HDSPM_Midi2InterruptEnable;
2110 hdspm->midi[2].irq = HDSPM_midi2IRQPendingAES;
2111 } else if (3 == id) {
2112 /* TCO MTC on HDSPe MADI */
2113 hdspm->midi[3].dataIn = HDSPM_midiDataIn3;
2114 hdspm->midi[3].statusIn = HDSPM_midiStatusIn3;
2115 hdspm->midi[3].dataOut = -1;
2116 hdspm->midi[3].statusOut = -1;
2117 hdspm->midi[3].ie = HDSPM_Midi3InterruptEnable;
2118 hdspm->midi[3].irq = HDSPM_midi3IRQPending;
2119 }
2120
2121 if ((id < 2) || ((2 == id) && ((MADI == hdspm->io_type) ||
2122 (MADIface == hdspm->io_type)))) {
2123 if ((id == 0) && (MADIface == hdspm->io_type)) {
2124 snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2125 card->shortname);
2126 } else if ((id == 2) && (MADI == hdspm->io_type)) {
2127 snprintf(buf, sizeof(buf), "%s MIDIoverMADI",
2128 card->shortname);
2129 } else {
2130 snprintf(buf, sizeof(buf), "%s MIDI %d",
2131 card->shortname, id+1);
2132 }
2133 err = snd_rawmidi_new(card, buf, id, 1, 1,
2134 &hdspm->midi[id].rmidi);
2135 if (err < 0)
2136 return err;
2137
2138 snprintf(hdspm->midi[id].rmidi->name,
2139 sizeof(hdspm->midi[id].rmidi->name),
2140 "%s MIDI %d", card->id, id+1);
2141 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2142
2143 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2144 SNDRV_RAWMIDI_STREAM_OUTPUT,
2145 &snd_hdspm_midi_output);
2146 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2147 SNDRV_RAWMIDI_STREAM_INPUT,
2148 &snd_hdspm_midi_input);
2149
2150 hdspm->midi[id].rmidi->info_flags |=
2151 SNDRV_RAWMIDI_INFO_OUTPUT |
2152 SNDRV_RAWMIDI_INFO_INPUT |
2153 SNDRV_RAWMIDI_INFO_DUPLEX;
2154 } else {
2155 /* TCO MTC, read only */
2156 snprintf(buf, sizeof(buf), "%s MTC %d",
2157 card->shortname, id+1);
2158 err = snd_rawmidi_new(card, buf, id, 1, 1,
2159 &hdspm->midi[id].rmidi);
2160 if (err < 0)
2161 return err;
2162
2163 snprintf(hdspm->midi[id].rmidi->name,
2164 sizeof(hdspm->midi[id].rmidi->name),
2165 "%s MTC %d", card->id, id+1);
2166 hdspm->midi[id].rmidi->private_data = &hdspm->midi[id];
2167
2168 snd_rawmidi_set_ops(hdspm->midi[id].rmidi,
2169 SNDRV_RAWMIDI_STREAM_INPUT,
2170 &snd_hdspm_midi_input);
2171
2172 hdspm->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_INPUT;
2173 }
2174
2175 return 0;
2176 }
2177
2178
2179 static void hdspm_midi_tasklet(unsigned long arg)
2180 {
2181 struct hdspm *hdspm = (struct hdspm *)arg;
2182 int i = 0;
2183
2184 while (i < hdspm->midiPorts) {
2185 if (hdspm->midi[i].pending)
2186 snd_hdspm_midi_input_read(&hdspm->midi[i]);
2187
2188 i++;
2189 }
2190 }
2191
2192
2193 /*-----------------------------------------------------------------------------
2194 Status Interface
2195 ----------------------------------------------------------------------------*/
2196
2197 /* get the system sample rate which is set */
2198
2199
2200 static inline int hdspm_get_pll_freq(struct hdspm *hdspm)
2201 {
2202 unsigned int period, rate;
2203
2204 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
2205 rate = hdspm_calc_dds_value(hdspm, period);
2206
2207 return rate;
2208 }
2209
2210 /*
2211 * Calculate the real sample rate from the
2212 * current DDS value.
2213 */
2214 static int hdspm_get_system_sample_rate(struct hdspm *hdspm)
2215 {
2216 unsigned int rate;
2217
2218 rate = hdspm_get_pll_freq(hdspm);
2219
2220 if (rate > 207000) {
2221 /* Unreasonable high sample rate as seen on PCI MADI cards. */
2222 if (0 == hdspm_system_clock_mode(hdspm)) {
2223 /* master mode, return internal sample rate */
2224 rate = hdspm->system_sample_rate;
2225 } else {
2226 /* slave mode, return external sample rate */
2227 rate = hdspm_external_sample_rate(hdspm);
2228 if (!rate)
2229 rate = hdspm->system_sample_rate;
2230 }
2231 }
2232
2233 return rate;
2234 }
2235
2236
2237 #define HDSPM_SYSTEM_SAMPLE_RATE(xname, xindex) \
2238 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2239 .name = xname, \
2240 .index = xindex, \
2241 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2242 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2243 .info = snd_hdspm_info_system_sample_rate, \
2244 .put = snd_hdspm_put_system_sample_rate, \
2245 .get = snd_hdspm_get_system_sample_rate \
2246 }
2247
2248 static int snd_hdspm_info_system_sample_rate(struct snd_kcontrol *kcontrol,
2249 struct snd_ctl_elem_info *uinfo)
2250 {
2251 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2252 uinfo->count = 1;
2253 uinfo->value.integer.min = 27000;
2254 uinfo->value.integer.max = 207000;
2255 uinfo->value.integer.step = 1;
2256 return 0;
2257 }
2258
2259
2260 static int snd_hdspm_get_system_sample_rate(struct snd_kcontrol *kcontrol,
2261 struct snd_ctl_elem_value *
2262 ucontrol)
2263 {
2264 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2265
2266 ucontrol->value.integer.value[0] = hdspm_get_system_sample_rate(hdspm);
2267 return 0;
2268 }
2269
2270 static int snd_hdspm_put_system_sample_rate(struct snd_kcontrol *kcontrol,
2271 struct snd_ctl_elem_value *
2272 ucontrol)
2273 {
2274 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2275 int rate = ucontrol->value.integer.value[0];
2276
2277 if (rate < 27000 || rate > 207000)
2278 return -EINVAL;
2279 hdspm_set_dds_value(hdspm, ucontrol->value.integer.value[0]);
2280 return 0;
2281 }
2282
2283
2284 /*
2285 * Returns the WordClock sample rate class for the given card.
2286 */
2287 static int hdspm_get_wc_sample_rate(struct hdspm *hdspm)
2288 {
2289 int status;
2290
2291 switch (hdspm->io_type) {
2292 case RayDAT:
2293 case AIO:
2294 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2295 return (status >> 16) & 0xF;
2296 break;
2297 case AES32:
2298 status = hdspm_read(hdspm, HDSPM_statusRegister);
2299 return (status >> HDSPM_AES32_wcFreq_bit) & 0xF;
2300 default:
2301 break;
2302 }
2303
2304
2305 return 0;
2306 }
2307
2308
2309 /*
2310 * Returns the TCO sample rate class for the given card.
2311 */
2312 static int hdspm_get_tco_sample_rate(struct hdspm *hdspm)
2313 {
2314 int status;
2315
2316 if (hdspm->tco) {
2317 switch (hdspm->io_type) {
2318 case RayDAT:
2319 case AIO:
2320 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
2321 return (status >> 20) & 0xF;
2322 break;
2323 case AES32:
2324 status = hdspm_read(hdspm, HDSPM_statusRegister);
2325 return (status >> 1) & 0xF;
2326 default:
2327 break;
2328 }
2329 }
2330
2331 return 0;
2332 }
2333
2334
2335 /*
2336 * Returns the SYNC_IN sample rate class for the given card.
2337 */
2338 static int hdspm_get_sync_in_sample_rate(struct hdspm *hdspm)
2339 {
2340 int status;
2341
2342 if (hdspm->tco) {
2343 switch (hdspm->io_type) {
2344 case RayDAT:
2345 case AIO:
2346 status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2347 return (status >> 12) & 0xF;
2348 break;
2349 default:
2350 break;
2351 }
2352 }
2353
2354 return 0;
2355 }
2356
2357 /*
2358 * Returns the AES sample rate class for the given card.
2359 */
2360 static int hdspm_get_aes_sample_rate(struct hdspm *hdspm, int index)
2361 {
2362 int timecode;
2363
2364 switch (hdspm->io_type) {
2365 case AES32:
2366 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
2367 return (timecode >> (4*index)) & 0xF;
2368 break;
2369 default:
2370 break;
2371 }
2372 return 0;
2373 }
2374
2375 /*
2376 * Returns the sample rate class for input source <idx> for
2377 * 'new style' cards like the AIO and RayDAT.
2378 */
2379 static int hdspm_get_s1_sample_rate(struct hdspm *hdspm, unsigned int idx)
2380 {
2381 int status = hdspm_read(hdspm, HDSPM_RD_STATUS_2);
2382
2383 return (status >> (idx*4)) & 0xF;
2384 }
2385
2386 #define ENUMERATED_CTL_INFO(info, texts) \
2387 snd_ctl_enum_info(info, 1, ARRAY_SIZE(texts), texts)
2388
2389
2390 /* Helper function to query the external sample rate and return the
2391 * corresponding enum to be returned to userspace.
2392 */
2393 static int hdspm_external_rate_to_enum(struct hdspm *hdspm)
2394 {
2395 int rate = hdspm_external_sample_rate(hdspm);
2396 int i, selected_rate = 0;
2397 for (i = 1; i < 10; i++)
2398 if (HDSPM_bit2freq(i) == rate) {
2399 selected_rate = i;
2400 break;
2401 }
2402 return selected_rate;
2403 }
2404
2405
2406 #define HDSPM_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
2407 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2408 .name = xname, \
2409 .private_value = xindex, \
2410 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2411 .info = snd_hdspm_info_autosync_sample_rate, \
2412 .get = snd_hdspm_get_autosync_sample_rate \
2413 }
2414
2415
2416 static int snd_hdspm_info_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2417 struct snd_ctl_elem_info *uinfo)
2418 {
2419 ENUMERATED_CTL_INFO(uinfo, texts_freq);
2420 return 0;
2421 }
2422
2423
2424 static int snd_hdspm_get_autosync_sample_rate(struct snd_kcontrol *kcontrol,
2425 struct snd_ctl_elem_value *
2426 ucontrol)
2427 {
2428 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2429
2430 switch (hdspm->io_type) {
2431 case RayDAT:
2432 switch (kcontrol->private_value) {
2433 case 0:
2434 ucontrol->value.enumerated.item[0] =
2435 hdspm_get_wc_sample_rate(hdspm);
2436 break;
2437 case 7:
2438 ucontrol->value.enumerated.item[0] =
2439 hdspm_get_tco_sample_rate(hdspm);
2440 break;
2441 case 8:
2442 ucontrol->value.enumerated.item[0] =
2443 hdspm_get_sync_in_sample_rate(hdspm);
2444 break;
2445 default:
2446 ucontrol->value.enumerated.item[0] =
2447 hdspm_get_s1_sample_rate(hdspm,
2448 kcontrol->private_value-1);
2449 }
2450 break;
2451
2452 case AIO:
2453 switch (kcontrol->private_value) {
2454 case 0: /* WC */
2455 ucontrol->value.enumerated.item[0] =
2456 hdspm_get_wc_sample_rate(hdspm);
2457 break;
2458 case 4: /* TCO */
2459 ucontrol->value.enumerated.item[0] =
2460 hdspm_get_tco_sample_rate(hdspm);
2461 break;
2462 case 5: /* SYNC_IN */
2463 ucontrol->value.enumerated.item[0] =
2464 hdspm_get_sync_in_sample_rate(hdspm);
2465 break;
2466 default:
2467 ucontrol->value.enumerated.item[0] =
2468 hdspm_get_s1_sample_rate(hdspm,
2469 kcontrol->private_value-1);
2470 }
2471 break;
2472
2473 case AES32:
2474
2475 switch (kcontrol->private_value) {
2476 case 0: /* WC */
2477 ucontrol->value.enumerated.item[0] =
2478 hdspm_get_wc_sample_rate(hdspm);
2479 break;
2480 case 9: /* TCO */
2481 ucontrol->value.enumerated.item[0] =
2482 hdspm_get_tco_sample_rate(hdspm);
2483 break;
2484 case 10: /* SYNC_IN */
2485 ucontrol->value.enumerated.item[0] =
2486 hdspm_get_sync_in_sample_rate(hdspm);
2487 break;
2488 case 11: /* External Rate */
2489 ucontrol->value.enumerated.item[0] =
2490 hdspm_external_rate_to_enum(hdspm);
2491 break;
2492 default: /* AES1 to AES8 */
2493 ucontrol->value.enumerated.item[0] =
2494 hdspm_get_aes_sample_rate(hdspm,
2495 kcontrol->private_value -
2496 HDSPM_AES32_AUTOSYNC_FROM_AES1);
2497 break;
2498 }
2499 break;
2500
2501 case MADI:
2502 case MADIface:
2503 ucontrol->value.enumerated.item[0] =
2504 hdspm_external_rate_to_enum(hdspm);
2505 break;
2506 default:
2507 break;
2508 }
2509
2510 return 0;
2511 }
2512
2513
2514 #define HDSPM_SYSTEM_CLOCK_MODE(xname, xindex) \
2515 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2516 .name = xname, \
2517 .index = xindex, \
2518 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2519 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2520 .info = snd_hdspm_info_system_clock_mode, \
2521 .get = snd_hdspm_get_system_clock_mode, \
2522 .put = snd_hdspm_put_system_clock_mode, \
2523 }
2524
2525
2526 /*
2527 * Returns the system clock mode for the given card.
2528 * @returns 0 - master, 1 - slave
2529 */
2530 static int hdspm_system_clock_mode(struct hdspm *hdspm)
2531 {
2532 switch (hdspm->io_type) {
2533 case AIO:
2534 case RayDAT:
2535 if (hdspm->settings_register & HDSPM_c0Master)
2536 return 0;
2537 break;
2538
2539 default:
2540 if (hdspm->control_register & HDSPM_ClockModeMaster)
2541 return 0;
2542 }
2543
2544 return 1;
2545 }
2546
2547
2548 /*
2549 * Sets the system clock mode.
2550 * @param mode 0 - master, 1 - slave
2551 */
2552 static void hdspm_set_system_clock_mode(struct hdspm *hdspm, int mode)
2553 {
2554 hdspm_set_toggle_setting(hdspm,
2555 (hdspm_is_raydat_or_aio(hdspm)) ?
2556 HDSPM_c0Master : HDSPM_ClockModeMaster,
2557 (0 == mode));
2558 }
2559
2560
2561 static int snd_hdspm_info_system_clock_mode(struct snd_kcontrol *kcontrol,
2562 struct snd_ctl_elem_info *uinfo)
2563 {
2564 static const char *const texts[] = { "Master", "AutoSync" };
2565 ENUMERATED_CTL_INFO(uinfo, texts);
2566 return 0;
2567 }
2568
2569 static int snd_hdspm_get_system_clock_mode(struct snd_kcontrol *kcontrol,
2570 struct snd_ctl_elem_value *ucontrol)
2571 {
2572 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2573
2574 ucontrol->value.enumerated.item[0] = hdspm_system_clock_mode(hdspm);
2575 return 0;
2576 }
2577
2578 static int snd_hdspm_put_system_clock_mode(struct snd_kcontrol *kcontrol,
2579 struct snd_ctl_elem_value *ucontrol)
2580 {
2581 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2582 int val;
2583
2584 if (!snd_hdspm_use_is_exclusive(hdspm))
2585 return -EBUSY;
2586
2587 val = ucontrol->value.enumerated.item[0];
2588 if (val < 0)
2589 val = 0;
2590 else if (val > 1)
2591 val = 1;
2592
2593 hdspm_set_system_clock_mode(hdspm, val);
2594
2595 return 0;
2596 }
2597
2598
2599 #define HDSPM_INTERNAL_CLOCK(xname, xindex) \
2600 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2601 .name = xname, \
2602 .index = xindex, \
2603 .info = snd_hdspm_info_clock_source, \
2604 .get = snd_hdspm_get_clock_source, \
2605 .put = snd_hdspm_put_clock_source \
2606 }
2607
2608
2609 static int hdspm_clock_source(struct hdspm * hdspm)
2610 {
2611 switch (hdspm->system_sample_rate) {
2612 case 32000: return 0;
2613 case 44100: return 1;
2614 case 48000: return 2;
2615 case 64000: return 3;
2616 case 88200: return 4;
2617 case 96000: return 5;
2618 case 128000: return 6;
2619 case 176400: return 7;
2620 case 192000: return 8;
2621 }
2622
2623 return -1;
2624 }
2625
2626 static int hdspm_set_clock_source(struct hdspm * hdspm, int mode)
2627 {
2628 int rate;
2629 switch (mode) {
2630 case 0:
2631 rate = 32000; break;
2632 case 1:
2633 rate = 44100; break;
2634 case 2:
2635 rate = 48000; break;
2636 case 3:
2637 rate = 64000; break;
2638 case 4:
2639 rate = 88200; break;
2640 case 5:
2641 rate = 96000; break;
2642 case 6:
2643 rate = 128000; break;
2644 case 7:
2645 rate = 176400; break;
2646 case 8:
2647 rate = 192000; break;
2648 default:
2649 rate = 48000;
2650 }
2651 hdspm_set_rate(hdspm, rate, 1);
2652 return 0;
2653 }
2654
2655 static int snd_hdspm_info_clock_source(struct snd_kcontrol *kcontrol,
2656 struct snd_ctl_elem_info *uinfo)
2657 {
2658 return snd_ctl_enum_info(uinfo, 1, 9, texts_freq + 1);
2659 }
2660
2661 static int snd_hdspm_get_clock_source(struct snd_kcontrol *kcontrol,
2662 struct snd_ctl_elem_value *ucontrol)
2663 {
2664 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2665
2666 ucontrol->value.enumerated.item[0] = hdspm_clock_source(hdspm);
2667 return 0;
2668 }
2669
2670 static int snd_hdspm_put_clock_source(struct snd_kcontrol *kcontrol,
2671 struct snd_ctl_elem_value *ucontrol)
2672 {
2673 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2674 int change;
2675 int val;
2676
2677 if (!snd_hdspm_use_is_exclusive(hdspm))
2678 return -EBUSY;
2679 val = ucontrol->value.enumerated.item[0];
2680 if (val < 0)
2681 val = 0;
2682 if (val > 9)
2683 val = 9;
2684 spin_lock_irq(&hdspm->lock);
2685 if (val != hdspm_clock_source(hdspm))
2686 change = (hdspm_set_clock_source(hdspm, val) == 0) ? 1 : 0;
2687 else
2688 change = 0;
2689 spin_unlock_irq(&hdspm->lock);
2690 return change;
2691 }
2692
2693
2694 #define HDSPM_PREF_SYNC_REF(xname, xindex) \
2695 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2696 .name = xname, \
2697 .index = xindex, \
2698 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
2699 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2700 .info = snd_hdspm_info_pref_sync_ref, \
2701 .get = snd_hdspm_get_pref_sync_ref, \
2702 .put = snd_hdspm_put_pref_sync_ref \
2703 }
2704
2705
2706 /*
2707 * Returns the current preferred sync reference setting.
2708 * The semantics of the return value are depending on the
2709 * card, please see the comments for clarification.
2710 */
2711 static int hdspm_pref_sync_ref(struct hdspm * hdspm)
2712 {
2713 switch (hdspm->io_type) {
2714 case AES32:
2715 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2716 case 0: return 0; /* WC */
2717 case HDSPM_SyncRef0: return 1; /* AES 1 */
2718 case HDSPM_SyncRef1: return 2; /* AES 2 */
2719 case HDSPM_SyncRef1+HDSPM_SyncRef0: return 3; /* AES 3 */
2720 case HDSPM_SyncRef2: return 4; /* AES 4 */
2721 case HDSPM_SyncRef2+HDSPM_SyncRef0: return 5; /* AES 5 */
2722 case HDSPM_SyncRef2+HDSPM_SyncRef1: return 6; /* AES 6 */
2723 case HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0:
2724 return 7; /* AES 7 */
2725 case HDSPM_SyncRef3: return 8; /* AES 8 */
2726 case HDSPM_SyncRef3+HDSPM_SyncRef0: return 9; /* TCO */
2727 }
2728 break;
2729
2730 case MADI:
2731 case MADIface:
2732 if (hdspm->tco) {
2733 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2734 case 0: return 0; /* WC */
2735 case HDSPM_SyncRef0: return 1; /* MADI */
2736 case HDSPM_SyncRef1: return 2; /* TCO */
2737 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2738 return 3; /* SYNC_IN */
2739 }
2740 } else {
2741 switch (hdspm->control_register & HDSPM_SyncRefMask) {
2742 case 0: return 0; /* WC */
2743 case HDSPM_SyncRef0: return 1; /* MADI */
2744 case HDSPM_SyncRef1+HDSPM_SyncRef0:
2745 return 2; /* SYNC_IN */
2746 }
2747 }
2748 break;
2749
2750 case RayDAT:
2751 if (hdspm->tco) {
2752 switch ((hdspm->settings_register &
2753 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2754 case 0: return 0; /* WC */
2755 case 3: return 1; /* ADAT 1 */
2756 case 4: return 2; /* ADAT 2 */
2757 case 5: return 3; /* ADAT 3 */
2758 case 6: return 4; /* ADAT 4 */
2759 case 1: return 5; /* AES */
2760 case 2: return 6; /* SPDIF */
2761 case 9: return 7; /* TCO */
2762 case 10: return 8; /* SYNC_IN */
2763 }
2764 } else {
2765 switch ((hdspm->settings_register &
2766 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2767 case 0: return 0; /* WC */
2768 case 3: return 1; /* ADAT 1 */
2769 case 4: return 2; /* ADAT 2 */
2770 case 5: return 3; /* ADAT 3 */
2771 case 6: return 4; /* ADAT 4 */
2772 case 1: return 5; /* AES */
2773 case 2: return 6; /* SPDIF */
2774 case 10: return 7; /* SYNC_IN */
2775 }
2776 }
2777
2778 break;
2779
2780 case AIO:
2781 if (hdspm->tco) {
2782 switch ((hdspm->settings_register &
2783 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2784 case 0: return 0; /* WC */
2785 case 3: return 1; /* ADAT */
2786 case 1: return 2; /* AES */
2787 case 2: return 3; /* SPDIF */
2788 case 9: return 4; /* TCO */
2789 case 10: return 5; /* SYNC_IN */
2790 }
2791 } else {
2792 switch ((hdspm->settings_register &
2793 HDSPM_c0_SyncRefMask) / HDSPM_c0_SyncRef0) {
2794 case 0: return 0; /* WC */
2795 case 3: return 1; /* ADAT */
2796 case 1: return 2; /* AES */
2797 case 2: return 3; /* SPDIF */
2798 case 10: return 4; /* SYNC_IN */
2799 }
2800 }
2801
2802 break;
2803 }
2804
2805 return -1;
2806 }
2807
2808
2809 /*
2810 * Set the preferred sync reference to <pref>. The semantics
2811 * of <pref> are depending on the card type, see the comments
2812 * for clarification.
2813 */
2814 static int hdspm_set_pref_sync_ref(struct hdspm * hdspm, int pref)
2815 {
2816 int p = 0;
2817
2818 switch (hdspm->io_type) {
2819 case AES32:
2820 hdspm->control_register &= ~HDSPM_SyncRefMask;
2821 switch (pref) {
2822 case 0: /* WC */
2823 break;
2824 case 1: /* AES 1 */
2825 hdspm->control_register |= HDSPM_SyncRef0;
2826 break;
2827 case 2: /* AES 2 */
2828 hdspm->control_register |= HDSPM_SyncRef1;
2829 break;
2830 case 3: /* AES 3 */
2831 hdspm->control_register |=
2832 HDSPM_SyncRef1+HDSPM_SyncRef0;
2833 break;
2834 case 4: /* AES 4 */
2835 hdspm->control_register |= HDSPM_SyncRef2;
2836 break;
2837 case 5: /* AES 5 */
2838 hdspm->control_register |=
2839 HDSPM_SyncRef2+HDSPM_SyncRef0;
2840 break;
2841 case 6: /* AES 6 */
2842 hdspm->control_register |=
2843 HDSPM_SyncRef2+HDSPM_SyncRef1;
2844 break;
2845 case 7: /* AES 7 */
2846 hdspm->control_register |=
2847 HDSPM_SyncRef2+HDSPM_SyncRef1+HDSPM_SyncRef0;
2848 break;
2849 case 8: /* AES 8 */
2850 hdspm->control_register |= HDSPM_SyncRef3;
2851 break;
2852 case 9: /* TCO */
2853 hdspm->control_register |=
2854 HDSPM_SyncRef3+HDSPM_SyncRef0;
2855 break;
2856 default:
2857 return -1;
2858 }
2859
2860 break;
2861
2862 case MADI:
2863 case MADIface:
2864 hdspm->control_register &= ~HDSPM_SyncRefMask;
2865 if (hdspm->tco) {
2866 switch (pref) {
2867 case 0: /* WC */
2868 break;
2869 case 1: /* MADI */
2870 hdspm->control_register |= HDSPM_SyncRef0;
2871 break;
2872 case 2: /* TCO */
2873 hdspm->control_register |= HDSPM_SyncRef1;
2874 break;
2875 case 3: /* SYNC_IN */
2876 hdspm->control_register |=
2877 HDSPM_SyncRef0+HDSPM_SyncRef1;
2878 break;
2879 default:
2880 return -1;
2881 }
2882 } else {
2883 switch (pref) {
2884 case 0: /* WC */
2885 break;
2886 case 1: /* MADI */
2887 hdspm->control_register |= HDSPM_SyncRef0;
2888 break;
2889 case 2: /* SYNC_IN */
2890 hdspm->control_register |=
2891 HDSPM_SyncRef0+HDSPM_SyncRef1;
2892 break;
2893 default:
2894 return -1;
2895 }
2896 }
2897
2898 break;
2899
2900 case RayDAT:
2901 if (hdspm->tco) {
2902 switch (pref) {
2903 case 0: p = 0; break; /* WC */
2904 case 1: p = 3; break; /* ADAT 1 */
2905 case 2: p = 4; break; /* ADAT 2 */
2906 case 3: p = 5; break; /* ADAT 3 */
2907 case 4: p = 6; break; /* ADAT 4 */
2908 case 5: p = 1; break; /* AES */
2909 case 6: p = 2; break; /* SPDIF */
2910 case 7: p = 9; break; /* TCO */
2911 case 8: p = 10; break; /* SYNC_IN */
2912 default: return -1;
2913 }
2914 } else {
2915 switch (pref) {
2916 case 0: p = 0; break; /* WC */
2917 case 1: p = 3; break; /* ADAT 1 */
2918 case 2: p = 4; break; /* ADAT 2 */
2919 case 3: p = 5; break; /* ADAT 3 */
2920 case 4: p = 6; break; /* ADAT 4 */
2921 case 5: p = 1; break; /* AES */
2922 case 6: p = 2; break; /* SPDIF */
2923 case 7: p = 10; break; /* SYNC_IN */
2924 default: return -1;
2925 }
2926 }
2927 break;
2928
2929 case AIO:
2930 if (hdspm->tco) {
2931 switch (pref) {
2932 case 0: p = 0; break; /* WC */
2933 case 1: p = 3; break; /* ADAT */
2934 case 2: p = 1; break; /* AES */
2935 case 3: p = 2; break; /* SPDIF */
2936 case 4: p = 9; break; /* TCO */
2937 case 5: p = 10; break; /* SYNC_IN */
2938 default: return -1;
2939 }
2940 } else {
2941 switch (pref) {
2942 case 0: p = 0; break; /* WC */
2943 case 1: p = 3; break; /* ADAT */
2944 case 2: p = 1; break; /* AES */
2945 case 3: p = 2; break; /* SPDIF */
2946 case 4: p = 10; break; /* SYNC_IN */
2947 default: return -1;
2948 }
2949 }
2950 break;
2951 }
2952
2953 switch (hdspm->io_type) {
2954 case RayDAT:
2955 case AIO:
2956 hdspm->settings_register &= ~HDSPM_c0_SyncRefMask;
2957 hdspm->settings_register |= HDSPM_c0_SyncRef0 * p;
2958 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
2959 break;
2960
2961 case MADI:
2962 case MADIface:
2963 case AES32:
2964 hdspm_write(hdspm, HDSPM_controlRegister,
2965 hdspm->control_register);
2966 }
2967
2968 return 0;
2969 }
2970
2971
2972 static int snd_hdspm_info_pref_sync_ref(struct snd_kcontrol *kcontrol,
2973 struct snd_ctl_elem_info *uinfo)
2974 {
2975 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2976
2977 snd_ctl_enum_info(uinfo, 1, hdspm->texts_autosync_items, hdspm->texts_autosync);
2978
2979 return 0;
2980 }
2981
2982 static int snd_hdspm_get_pref_sync_ref(struct snd_kcontrol *kcontrol,
2983 struct snd_ctl_elem_value *ucontrol)
2984 {
2985 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
2986 int psf = hdspm_pref_sync_ref(hdspm);
2987
2988 if (psf >= 0) {
2989 ucontrol->value.enumerated.item[0] = psf;
2990 return 0;
2991 }
2992
2993 return -1;
2994 }
2995
2996 static int snd_hdspm_put_pref_sync_ref(struct snd_kcontrol *kcontrol,
2997 struct snd_ctl_elem_value *ucontrol)
2998 {
2999 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3000 int val, change = 0;
3001
3002 if (!snd_hdspm_use_is_exclusive(hdspm))
3003 return -EBUSY;
3004
3005 val = ucontrol->value.enumerated.item[0];
3006
3007 if (val < 0)
3008 val = 0;
3009 else if (val >= hdspm->texts_autosync_items)
3010 val = hdspm->texts_autosync_items-1;
3011
3012 spin_lock_irq(&hdspm->lock);
3013 if (val != hdspm_pref_sync_ref(hdspm))
3014 change = (0 == hdspm_set_pref_sync_ref(hdspm, val)) ? 1 : 0;
3015
3016 spin_unlock_irq(&hdspm->lock);
3017 return change;
3018 }
3019
3020
3021 #define HDSPM_AUTOSYNC_REF(xname, xindex) \
3022 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3023 .name = xname, \
3024 .index = xindex, \
3025 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
3026 .info = snd_hdspm_info_autosync_ref, \
3027 .get = snd_hdspm_get_autosync_ref, \
3028 }
3029
3030 static int hdspm_autosync_ref(struct hdspm *hdspm)
3031 {
3032 /* This looks at the autosync selected sync reference */
3033 if (AES32 == hdspm->io_type) {
3034
3035 unsigned int status = hdspm_read(hdspm, HDSPM_statusRegister);
3036 unsigned int syncref = (status >> HDSPM_AES32_syncref_bit) & 0xF;
3037 if ((syncref >= HDSPM_AES32_AUTOSYNC_FROM_WORD) &&
3038 (syncref <= HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN)) {
3039 return syncref;
3040 }
3041 return HDSPM_AES32_AUTOSYNC_FROM_NONE;
3042
3043 } else if (MADI == hdspm->io_type) {
3044
3045 unsigned int status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3046 switch (status2 & HDSPM_SelSyncRefMask) {
3047 case HDSPM_SelSyncRef_WORD:
3048 return HDSPM_AUTOSYNC_FROM_WORD;
3049 case HDSPM_SelSyncRef_MADI:
3050 return HDSPM_AUTOSYNC_FROM_MADI;
3051 case HDSPM_SelSyncRef_TCO:
3052 return HDSPM_AUTOSYNC_FROM_TCO;
3053 case HDSPM_SelSyncRef_SyncIn:
3054 return HDSPM_AUTOSYNC_FROM_SYNC_IN;
3055 case HDSPM_SelSyncRef_NVALID:
3056 return HDSPM_AUTOSYNC_FROM_NONE;
3057 default:
3058 return HDSPM_AUTOSYNC_FROM_NONE;
3059 }
3060
3061 }
3062 return 0;
3063 }
3064
3065
3066 static int snd_hdspm_info_autosync_ref(struct snd_kcontrol *kcontrol,
3067 struct snd_ctl_elem_info *uinfo)
3068 {
3069 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3070
3071 if (AES32 == hdspm->io_type) {
3072 static const char *const texts[] = { "WordClock", "AES1", "AES2", "AES3",
3073 "AES4", "AES5", "AES6", "AES7", "AES8", "TCO", "Sync In", "None"};
3074
3075 ENUMERATED_CTL_INFO(uinfo, texts);
3076 } else if (MADI == hdspm->io_type) {
3077 static const char *const texts[] = {"Word Clock", "MADI", "TCO",
3078 "Sync In", "None" };
3079
3080 ENUMERATED_CTL_INFO(uinfo, texts);
3081 }
3082 return 0;
3083 }
3084
3085 static int snd_hdspm_get_autosync_ref(struct snd_kcontrol *kcontrol,
3086 struct snd_ctl_elem_value *ucontrol)
3087 {
3088 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3089
3090 ucontrol->value.enumerated.item[0] = hdspm_autosync_ref(hdspm);
3091 return 0;
3092 }
3093
3094
3095
3096 #define HDSPM_TCO_VIDEO_INPUT_FORMAT(xname, xindex) \
3097 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3098 .name = xname, \
3099 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3100 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3101 .info = snd_hdspm_info_tco_video_input_format, \
3102 .get = snd_hdspm_get_tco_video_input_format, \
3103 }
3104
3105 static int snd_hdspm_info_tco_video_input_format(struct snd_kcontrol *kcontrol,
3106 struct snd_ctl_elem_info *uinfo)
3107 {
3108 static const char *const texts[] = {"No video", "NTSC", "PAL"};
3109 ENUMERATED_CTL_INFO(uinfo, texts);
3110 return 0;
3111 }
3112
3113 static int snd_hdspm_get_tco_video_input_format(struct snd_kcontrol *kcontrol,
3114 struct snd_ctl_elem_value *ucontrol)
3115 {
3116 u32 status;
3117 int ret = 0;
3118
3119 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3120 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3121 switch (status & (HDSPM_TCO1_Video_Input_Format_NTSC |
3122 HDSPM_TCO1_Video_Input_Format_PAL)) {
3123 case HDSPM_TCO1_Video_Input_Format_NTSC:
3124 /* ntsc */
3125 ret = 1;
3126 break;
3127 case HDSPM_TCO1_Video_Input_Format_PAL:
3128 /* pal */
3129 ret = 2;
3130 break;
3131 default:
3132 /* no video */
3133 ret = 0;
3134 break;
3135 }
3136 ucontrol->value.enumerated.item[0] = ret;
3137 return 0;
3138 }
3139
3140
3141
3142 #define HDSPM_TCO_LTC_FRAMES(xname, xindex) \
3143 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3144 .name = xname, \
3145 .access = SNDRV_CTL_ELEM_ACCESS_READ |\
3146 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3147 .info = snd_hdspm_info_tco_ltc_frames, \
3148 .get = snd_hdspm_get_tco_ltc_frames, \
3149 }
3150
3151 static int snd_hdspm_info_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3152 struct snd_ctl_elem_info *uinfo)
3153 {
3154 static const char *const texts[] = {"No lock", "24 fps", "25 fps", "29.97 fps",
3155 "30 fps"};
3156 ENUMERATED_CTL_INFO(uinfo, texts);
3157 return 0;
3158 }
3159
3160 static int hdspm_tco_ltc_frames(struct hdspm *hdspm)
3161 {
3162 u32 status;
3163 int ret = 0;
3164
3165 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3166 if (status & HDSPM_TCO1_LTC_Input_valid) {
3167 switch (status & (HDSPM_TCO1_LTC_Format_LSB |
3168 HDSPM_TCO1_LTC_Format_MSB)) {
3169 case 0:
3170 /* 24 fps */
3171 ret = fps_24;
3172 break;
3173 case HDSPM_TCO1_LTC_Format_LSB:
3174 /* 25 fps */
3175 ret = fps_25;
3176 break;
3177 case HDSPM_TCO1_LTC_Format_MSB:
3178 /* 29.97 fps */
3179 ret = fps_2997;
3180 break;
3181 default:
3182 /* 30 fps */
3183 ret = fps_30;
3184 break;
3185 }
3186 }
3187
3188 return ret;
3189 }
3190
3191 static int snd_hdspm_get_tco_ltc_frames(struct snd_kcontrol *kcontrol,
3192 struct snd_ctl_elem_value *ucontrol)
3193 {
3194 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3195
3196 ucontrol->value.enumerated.item[0] = hdspm_tco_ltc_frames(hdspm);
3197 return 0;
3198 }
3199
3200 #define HDSPM_TOGGLE_SETTING(xname, xindex) \
3201 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3202 .name = xname, \
3203 .private_value = xindex, \
3204 .info = snd_hdspm_info_toggle_setting, \
3205 .get = snd_hdspm_get_toggle_setting, \
3206 .put = snd_hdspm_put_toggle_setting \
3207 }
3208
3209 static int hdspm_toggle_setting(struct hdspm *hdspm, u32 regmask)
3210 {
3211 u32 reg;
3212
3213 if (hdspm_is_raydat_or_aio(hdspm))
3214 reg = hdspm->settings_register;
3215 else
3216 reg = hdspm->control_register;
3217
3218 return (reg & regmask) ? 1 : 0;
3219 }
3220
3221 static int hdspm_set_toggle_setting(struct hdspm *hdspm, u32 regmask, int out)
3222 {
3223 u32 *reg;
3224 u32 target_reg;
3225
3226 if (hdspm_is_raydat_or_aio(hdspm)) {
3227 reg = &(hdspm->settings_register);
3228 target_reg = HDSPM_WR_SETTINGS;
3229 } else {
3230 reg = &(hdspm->control_register);
3231 target_reg = HDSPM_controlRegister;
3232 }
3233
3234 if (out)
3235 *reg |= regmask;
3236 else
3237 *reg &= ~regmask;
3238
3239 hdspm_write(hdspm, target_reg, *reg);
3240
3241 return 0;
3242 }
3243
3244 #define snd_hdspm_info_toggle_setting snd_ctl_boolean_mono_info
3245
3246 static int snd_hdspm_get_toggle_setting(struct snd_kcontrol *kcontrol,
3247 struct snd_ctl_elem_value *ucontrol)
3248 {
3249 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3250 u32 regmask = kcontrol->private_value;
3251
3252 spin_lock_irq(&hdspm->lock);
3253 ucontrol->value.integer.value[0] = hdspm_toggle_setting(hdspm, regmask);
3254 spin_unlock_irq(&hdspm->lock);
3255 return 0;
3256 }
3257
3258 static int snd_hdspm_put_toggle_setting(struct snd_kcontrol *kcontrol,
3259 struct snd_ctl_elem_value *ucontrol)
3260 {
3261 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3262 u32 regmask = kcontrol->private_value;
3263 int change;
3264 unsigned int val;
3265
3266 if (!snd_hdspm_use_is_exclusive(hdspm))
3267 return -EBUSY;
3268 val = ucontrol->value.integer.value[0] & 1;
3269 spin_lock_irq(&hdspm->lock);
3270 change = (int) val != hdspm_toggle_setting(hdspm, regmask);
3271 hdspm_set_toggle_setting(hdspm, regmask, val);
3272 spin_unlock_irq(&hdspm->lock);
3273 return change;
3274 }
3275
3276 #define HDSPM_INPUT_SELECT(xname, xindex) \
3277 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3278 .name = xname, \
3279 .index = xindex, \
3280 .info = snd_hdspm_info_input_select, \
3281 .get = snd_hdspm_get_input_select, \
3282 .put = snd_hdspm_put_input_select \
3283 }
3284
3285 static int hdspm_input_select(struct hdspm * hdspm)
3286 {
3287 return (hdspm->control_register & HDSPM_InputSelect0) ? 1 : 0;
3288 }
3289
3290 static int hdspm_set_input_select(struct hdspm * hdspm, int out)
3291 {
3292 if (out)
3293 hdspm->control_register |= HDSPM_InputSelect0;
3294 else
3295 hdspm->control_register &= ~HDSPM_InputSelect0;
3296 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3297
3298 return 0;
3299 }
3300
3301 static int snd_hdspm_info_input_select(struct snd_kcontrol *kcontrol,
3302 struct snd_ctl_elem_info *uinfo)
3303 {
3304 static const char *const texts[] = { "optical", "coaxial" };
3305 ENUMERATED_CTL_INFO(uinfo, texts);
3306 return 0;
3307 }
3308
3309 static int snd_hdspm_get_input_select(struct snd_kcontrol *kcontrol,
3310 struct snd_ctl_elem_value *ucontrol)
3311 {
3312 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3313
3314 spin_lock_irq(&hdspm->lock);
3315 ucontrol->value.enumerated.item[0] = hdspm_input_select(hdspm);
3316 spin_unlock_irq(&hdspm->lock);
3317 return 0;
3318 }
3319
3320 static int snd_hdspm_put_input_select(struct snd_kcontrol *kcontrol,
3321 struct snd_ctl_elem_value *ucontrol)
3322 {
3323 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3324 int change;
3325 unsigned int val;
3326
3327 if (!snd_hdspm_use_is_exclusive(hdspm))
3328 return -EBUSY;
3329 val = ucontrol->value.integer.value[0] & 1;
3330 spin_lock_irq(&hdspm->lock);
3331 change = (int) val != hdspm_input_select(hdspm);
3332 hdspm_set_input_select(hdspm, val);
3333 spin_unlock_irq(&hdspm->lock);
3334 return change;
3335 }
3336
3337
3338 #define HDSPM_DS_WIRE(xname, xindex) \
3339 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3340 .name = xname, \
3341 .index = xindex, \
3342 .info = snd_hdspm_info_ds_wire, \
3343 .get = snd_hdspm_get_ds_wire, \
3344 .put = snd_hdspm_put_ds_wire \
3345 }
3346
3347 static int hdspm_ds_wire(struct hdspm * hdspm)
3348 {
3349 return (hdspm->control_register & HDSPM_DS_DoubleWire) ? 1 : 0;
3350 }
3351
3352 static int hdspm_set_ds_wire(struct hdspm * hdspm, int ds)
3353 {
3354 if (ds)
3355 hdspm->control_register |= HDSPM_DS_DoubleWire;
3356 else
3357 hdspm->control_register &= ~HDSPM_DS_DoubleWire;
3358 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3359
3360 return 0;
3361 }
3362
3363 static int snd_hdspm_info_ds_wire(struct snd_kcontrol *kcontrol,
3364 struct snd_ctl_elem_info *uinfo)
3365 {
3366 static const char *const texts[] = { "Single", "Double" };
3367 ENUMERATED_CTL_INFO(uinfo, texts);
3368 return 0;
3369 }
3370
3371 static int snd_hdspm_get_ds_wire(struct snd_kcontrol *kcontrol,
3372 struct snd_ctl_elem_value *ucontrol)
3373 {
3374 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3375
3376 spin_lock_irq(&hdspm->lock);
3377 ucontrol->value.enumerated.item[0] = hdspm_ds_wire(hdspm);
3378 spin_unlock_irq(&hdspm->lock);
3379 return 0;
3380 }
3381
3382 static int snd_hdspm_put_ds_wire(struct snd_kcontrol *kcontrol,
3383 struct snd_ctl_elem_value *ucontrol)
3384 {
3385 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3386 int change;
3387 unsigned int val;
3388
3389 if (!snd_hdspm_use_is_exclusive(hdspm))
3390 return -EBUSY;
3391 val = ucontrol->value.integer.value[0] & 1;
3392 spin_lock_irq(&hdspm->lock);
3393 change = (int) val != hdspm_ds_wire(hdspm);
3394 hdspm_set_ds_wire(hdspm, val);
3395 spin_unlock_irq(&hdspm->lock);
3396 return change;
3397 }
3398
3399
3400 #define HDSPM_QS_WIRE(xname, xindex) \
3401 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3402 .name = xname, \
3403 .index = xindex, \
3404 .info = snd_hdspm_info_qs_wire, \
3405 .get = snd_hdspm_get_qs_wire, \
3406 .put = snd_hdspm_put_qs_wire \
3407 }
3408
3409 static int hdspm_qs_wire(struct hdspm * hdspm)
3410 {
3411 if (hdspm->control_register & HDSPM_QS_DoubleWire)
3412 return 1;
3413 if (hdspm->control_register & HDSPM_QS_QuadWire)
3414 return 2;
3415 return 0;
3416 }
3417
3418 static int hdspm_set_qs_wire(struct hdspm * hdspm, int mode)
3419 {
3420 hdspm->control_register &= ~(HDSPM_QS_DoubleWire | HDSPM_QS_QuadWire);
3421 switch (mode) {
3422 case 0:
3423 break;
3424 case 1:
3425 hdspm->control_register |= HDSPM_QS_DoubleWire;
3426 break;
3427 case 2:
3428 hdspm->control_register |= HDSPM_QS_QuadWire;
3429 break;
3430 }
3431 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3432
3433 return 0;
3434 }
3435
3436 static int snd_hdspm_info_qs_wire(struct snd_kcontrol *kcontrol,
3437 struct snd_ctl_elem_info *uinfo)
3438 {
3439 static const char *const texts[] = { "Single", "Double", "Quad" };
3440 ENUMERATED_CTL_INFO(uinfo, texts);
3441 return 0;
3442 }
3443
3444 static int snd_hdspm_get_qs_wire(struct snd_kcontrol *kcontrol,
3445 struct snd_ctl_elem_value *ucontrol)
3446 {
3447 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3448
3449 spin_lock_irq(&hdspm->lock);
3450 ucontrol->value.enumerated.item[0] = hdspm_qs_wire(hdspm);
3451 spin_unlock_irq(&hdspm->lock);
3452 return 0;
3453 }
3454
3455 static int snd_hdspm_put_qs_wire(struct snd_kcontrol *kcontrol,
3456 struct snd_ctl_elem_value *ucontrol)
3457 {
3458 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3459 int change;
3460 int val;
3461
3462 if (!snd_hdspm_use_is_exclusive(hdspm))
3463 return -EBUSY;
3464 val = ucontrol->value.integer.value[0];
3465 if (val < 0)
3466 val = 0;
3467 if (val > 2)
3468 val = 2;
3469 spin_lock_irq(&hdspm->lock);
3470 change = val != hdspm_qs_wire(hdspm);
3471 hdspm_set_qs_wire(hdspm, val);
3472 spin_unlock_irq(&hdspm->lock);
3473 return change;
3474 }
3475
3476 #define HDSPM_CONTROL_TRISTATE(xname, xindex) \
3477 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3478 .name = xname, \
3479 .private_value = xindex, \
3480 .info = snd_hdspm_info_tristate, \
3481 .get = snd_hdspm_get_tristate, \
3482 .put = snd_hdspm_put_tristate \
3483 }
3484
3485 static int hdspm_tristate(struct hdspm *hdspm, u32 regmask)
3486 {
3487 u32 reg = hdspm->settings_register & (regmask * 3);
3488 return reg / regmask;
3489 }
3490
3491 static int hdspm_set_tristate(struct hdspm *hdspm, int mode, u32 regmask)
3492 {
3493 hdspm->settings_register &= ~(regmask * 3);
3494 hdspm->settings_register |= (regmask * mode);
3495 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
3496
3497 return 0;
3498 }
3499
3500 static int snd_hdspm_info_tristate(struct snd_kcontrol *kcontrol,
3501 struct snd_ctl_elem_info *uinfo)
3502 {
3503 u32 regmask = kcontrol->private_value;
3504
3505 static const char *const texts_spdif[] = { "Optical", "Coaxial", "Internal" };
3506 static const char *const texts_levels[] = { "Hi Gain", "+4 dBu", "-10 dBV" };
3507
3508 switch (regmask) {
3509 case HDSPM_c0_Input0:
3510 ENUMERATED_CTL_INFO(uinfo, texts_spdif);
3511 break;
3512 default:
3513 ENUMERATED_CTL_INFO(uinfo, texts_levels);
3514 break;
3515 }
3516 return 0;
3517 }
3518
3519 static int snd_hdspm_get_tristate(struct snd_kcontrol *kcontrol,
3520 struct snd_ctl_elem_value *ucontrol)
3521 {
3522 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3523 u32 regmask = kcontrol->private_value;
3524
3525 spin_lock_irq(&hdspm->lock);
3526 ucontrol->value.enumerated.item[0] = hdspm_tristate(hdspm, regmask);
3527 spin_unlock_irq(&hdspm->lock);
3528 return 0;
3529 }
3530
3531 static int snd_hdspm_put_tristate(struct snd_kcontrol *kcontrol,
3532 struct snd_ctl_elem_value *ucontrol)
3533 {
3534 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3535 u32 regmask = kcontrol->private_value;
3536 int change;
3537 int val;
3538
3539 if (!snd_hdspm_use_is_exclusive(hdspm))
3540 return -EBUSY;
3541 val = ucontrol->value.integer.value[0];
3542 if (val < 0)
3543 val = 0;
3544 if (val > 2)
3545 val = 2;
3546
3547 spin_lock_irq(&hdspm->lock);
3548 change = val != hdspm_tristate(hdspm, regmask);
3549 hdspm_set_tristate(hdspm, val, regmask);
3550 spin_unlock_irq(&hdspm->lock);
3551 return change;
3552 }
3553
3554 #define HDSPM_MADI_SPEEDMODE(xname, xindex) \
3555 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3556 .name = xname, \
3557 .index = xindex, \
3558 .info = snd_hdspm_info_madi_speedmode, \
3559 .get = snd_hdspm_get_madi_speedmode, \
3560 .put = snd_hdspm_put_madi_speedmode \
3561 }
3562
3563 static int hdspm_madi_speedmode(struct hdspm *hdspm)
3564 {
3565 if (hdspm->control_register & HDSPM_QuadSpeed)
3566 return 2;
3567 if (hdspm->control_register & HDSPM_DoubleSpeed)
3568 return 1;
3569 return 0;
3570 }
3571
3572 static int hdspm_set_madi_speedmode(struct hdspm *hdspm, int mode)
3573 {
3574 hdspm->control_register &= ~(HDSPM_DoubleSpeed | HDSPM_QuadSpeed);
3575 switch (mode) {
3576 case 0:
3577 break;
3578 case 1:
3579 hdspm->control_register |= HDSPM_DoubleSpeed;
3580 break;
3581 case 2:
3582 hdspm->control_register |= HDSPM_QuadSpeed;
3583 break;
3584 }
3585 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
3586
3587 return 0;
3588 }
3589
3590 static int snd_hdspm_info_madi_speedmode(struct snd_kcontrol *kcontrol,
3591 struct snd_ctl_elem_info *uinfo)
3592 {
3593 static const char *const texts[] = { "Single", "Double", "Quad" };
3594 ENUMERATED_CTL_INFO(uinfo, texts);
3595 return 0;
3596 }
3597
3598 static int snd_hdspm_get_madi_speedmode(struct snd_kcontrol *kcontrol,
3599 struct snd_ctl_elem_value *ucontrol)
3600 {
3601 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3602
3603 spin_lock_irq(&hdspm->lock);
3604 ucontrol->value.enumerated.item[0] = hdspm_madi_speedmode(hdspm);
3605 spin_unlock_irq(&hdspm->lock);
3606 return 0;
3607 }
3608
3609 static int snd_hdspm_put_madi_speedmode(struct snd_kcontrol *kcontrol,
3610 struct snd_ctl_elem_value *ucontrol)
3611 {
3612 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3613 int change;
3614 int val;
3615
3616 if (!snd_hdspm_use_is_exclusive(hdspm))
3617 return -EBUSY;
3618 val = ucontrol->value.integer.value[0];
3619 if (val < 0)
3620 val = 0;
3621 if (val > 2)
3622 val = 2;
3623 spin_lock_irq(&hdspm->lock);
3624 change = val != hdspm_madi_speedmode(hdspm);
3625 hdspm_set_madi_speedmode(hdspm, val);
3626 spin_unlock_irq(&hdspm->lock);
3627 return change;
3628 }
3629
3630 #define HDSPM_MIXER(xname, xindex) \
3631 { .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
3632 .name = xname, \
3633 .index = xindex, \
3634 .device = 0, \
3635 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
3636 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3637 .info = snd_hdspm_info_mixer, \
3638 .get = snd_hdspm_get_mixer, \
3639 .put = snd_hdspm_put_mixer \
3640 }
3641
3642 static int snd_hdspm_info_mixer(struct snd_kcontrol *kcontrol,
3643 struct snd_ctl_elem_info *uinfo)
3644 {
3645 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3646 uinfo->count = 3;
3647 uinfo->value.integer.min = 0;
3648 uinfo->value.integer.max = 65535;
3649 uinfo->value.integer.step = 1;
3650 return 0;
3651 }
3652
3653 static int snd_hdspm_get_mixer(struct snd_kcontrol *kcontrol,
3654 struct snd_ctl_elem_value *ucontrol)
3655 {
3656 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3657 int source;
3658 int destination;
3659
3660 source = ucontrol->value.integer.value[0];
3661 if (source < 0)
3662 source = 0;
3663 else if (source >= 2 * HDSPM_MAX_CHANNELS)
3664 source = 2 * HDSPM_MAX_CHANNELS - 1;
3665
3666 destination = ucontrol->value.integer.value[1];
3667 if (destination < 0)
3668 destination = 0;
3669 else if (destination >= HDSPM_MAX_CHANNELS)
3670 destination = HDSPM_MAX_CHANNELS - 1;
3671
3672 spin_lock_irq(&hdspm->lock);
3673 if (source >= HDSPM_MAX_CHANNELS)
3674 ucontrol->value.integer.value[2] =
3675 hdspm_read_pb_gain(hdspm, destination,
3676 source - HDSPM_MAX_CHANNELS);
3677 else
3678 ucontrol->value.integer.value[2] =
3679 hdspm_read_in_gain(hdspm, destination, source);
3680
3681 spin_unlock_irq(&hdspm->lock);
3682
3683 return 0;
3684 }
3685
3686 static int snd_hdspm_put_mixer(struct snd_kcontrol *kcontrol,
3687 struct snd_ctl_elem_value *ucontrol)
3688 {
3689 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3690 int change;
3691 int source;
3692 int destination;
3693 int gain;
3694
3695 if (!snd_hdspm_use_is_exclusive(hdspm))
3696 return -EBUSY;
3697
3698 source = ucontrol->value.integer.value[0];
3699 destination = ucontrol->value.integer.value[1];
3700
3701 if (source < 0 || source >= 2 * HDSPM_MAX_CHANNELS)
3702 return -1;
3703 if (destination < 0 || destination >= HDSPM_MAX_CHANNELS)
3704 return -1;
3705
3706 gain = ucontrol->value.integer.value[2];
3707
3708 spin_lock_irq(&hdspm->lock);
3709
3710 if (source >= HDSPM_MAX_CHANNELS)
3711 change = gain != hdspm_read_pb_gain(hdspm, destination,
3712 source -
3713 HDSPM_MAX_CHANNELS);
3714 else
3715 change = gain != hdspm_read_in_gain(hdspm, destination,
3716 source);
3717
3718 if (change) {
3719 if (source >= HDSPM_MAX_CHANNELS)
3720 hdspm_write_pb_gain(hdspm, destination,
3721 source - HDSPM_MAX_CHANNELS,
3722 gain);
3723 else
3724 hdspm_write_in_gain(hdspm, destination, source,
3725 gain);
3726 }
3727 spin_unlock_irq(&hdspm->lock);
3728
3729 return change;
3730 }
3731
3732 /* The simple mixer control(s) provide gain control for the
3733 basic 1:1 mappings of playback streams to output
3734 streams.
3735 */
3736
3737 #define HDSPM_PLAYBACK_MIXER \
3738 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3739 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_WRITE | \
3740 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3741 .info = snd_hdspm_info_playback_mixer, \
3742 .get = snd_hdspm_get_playback_mixer, \
3743 .put = snd_hdspm_put_playback_mixer \
3744 }
3745
3746 static int snd_hdspm_info_playback_mixer(struct snd_kcontrol *kcontrol,
3747 struct snd_ctl_elem_info *uinfo)
3748 {
3749 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
3750 uinfo->count = 1;
3751 uinfo->value.integer.min = 0;
3752 uinfo->value.integer.max = 64;
3753 uinfo->value.integer.step = 1;
3754 return 0;
3755 }
3756
3757 static int snd_hdspm_get_playback_mixer(struct snd_kcontrol *kcontrol,
3758 struct snd_ctl_elem_value *ucontrol)
3759 {
3760 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3761 int channel;
3762
3763 channel = ucontrol->id.index - 1;
3764
3765 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3766 return -EINVAL;
3767
3768 spin_lock_irq(&hdspm->lock);
3769 ucontrol->value.integer.value[0] =
3770 (hdspm_read_pb_gain(hdspm, channel, channel)*64)/UNITY_GAIN;
3771 spin_unlock_irq(&hdspm->lock);
3772
3773 return 0;
3774 }
3775
3776 static int snd_hdspm_put_playback_mixer(struct snd_kcontrol *kcontrol,
3777 struct snd_ctl_elem_value *ucontrol)
3778 {
3779 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
3780 int change;
3781 int channel;
3782 int gain;
3783
3784 if (!snd_hdspm_use_is_exclusive(hdspm))
3785 return -EBUSY;
3786
3787 channel = ucontrol->id.index - 1;
3788
3789 if (snd_BUG_ON(channel < 0 || channel >= HDSPM_MAX_CHANNELS))
3790 return -EINVAL;
3791
3792 gain = ucontrol->value.integer.value[0]*UNITY_GAIN/64;
3793
3794 spin_lock_irq(&hdspm->lock);
3795 change =
3796 gain != hdspm_read_pb_gain(hdspm, channel,
3797 channel);
3798 if (change)
3799 hdspm_write_pb_gain(hdspm, channel, channel,
3800 gain);
3801 spin_unlock_irq(&hdspm->lock);
3802 return change;
3803 }
3804
3805 #define HDSPM_SYNC_CHECK(xname, xindex) \
3806 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3807 .name = xname, \
3808 .private_value = xindex, \
3809 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3810 .info = snd_hdspm_info_sync_check, \
3811 .get = snd_hdspm_get_sync_check \
3812 }
3813
3814 #define HDSPM_TCO_LOCK_CHECK(xname, xindex) \
3815 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
3816 .name = xname, \
3817 .private_value = xindex, \
3818 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
3819 .info = snd_hdspm_tco_info_lock_check, \
3820 .get = snd_hdspm_get_sync_check \
3821 }
3822
3823
3824
3825 static int snd_hdspm_info_sync_check(struct snd_kcontrol *kcontrol,
3826 struct snd_ctl_elem_info *uinfo)
3827 {
3828 static const char *const texts[] = { "No Lock", "Lock", "Sync", "N/A" };
3829 ENUMERATED_CTL_INFO(uinfo, texts);
3830 return 0;
3831 }
3832
3833 static int snd_hdspm_tco_info_lock_check(struct snd_kcontrol *kcontrol,
3834 struct snd_ctl_elem_info *uinfo)
3835 {
3836 static const char *const texts[] = { "No Lock", "Lock" };
3837 ENUMERATED_CTL_INFO(uinfo, texts);
3838 return 0;
3839 }
3840
3841 static int hdspm_wc_sync_check(struct hdspm *hdspm)
3842 {
3843 int status, status2;
3844
3845 switch (hdspm->io_type) {
3846 case AES32:
3847 status = hdspm_read(hdspm, HDSPM_statusRegister);
3848 if (status & HDSPM_AES32_wcLock) {
3849 if (status & HDSPM_AES32_wcSync)
3850 return 2;
3851 else
3852 return 1;
3853 }
3854 return 0;
3855 break;
3856
3857 case MADI:
3858 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3859 if (status2 & HDSPM_wcLock) {
3860 if (status2 & HDSPM_wcSync)
3861 return 2;
3862 else
3863 return 1;
3864 }
3865 return 0;
3866 break;
3867
3868 case RayDAT:
3869 case AIO:
3870 status = hdspm_read(hdspm, HDSPM_statusRegister);
3871
3872 if (status & 0x2000000)
3873 return 2;
3874 else if (status & 0x1000000)
3875 return 1;
3876 return 0;
3877
3878 break;
3879
3880 case MADIface:
3881 break;
3882 }
3883
3884
3885 return 3;
3886 }
3887
3888
3889 static int hdspm_madi_sync_check(struct hdspm *hdspm)
3890 {
3891 int status = hdspm_read(hdspm, HDSPM_statusRegister);
3892 if (status & HDSPM_madiLock) {
3893 if (status & HDSPM_madiSync)
3894 return 2;
3895 else
3896 return 1;
3897 }
3898 return 0;
3899 }
3900
3901
3902 static int hdspm_s1_sync_check(struct hdspm *hdspm, int idx)
3903 {
3904 int status, lock, sync;
3905
3906 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
3907
3908 lock = (status & (0x1<<idx)) ? 1 : 0;
3909 sync = (status & (0x100<<idx)) ? 1 : 0;
3910
3911 if (lock && sync)
3912 return 2;
3913 else if (lock)
3914 return 1;
3915 return 0;
3916 }
3917
3918
3919 static int hdspm_sync_in_sync_check(struct hdspm *hdspm)
3920 {
3921 int status, lock = 0, sync = 0;
3922
3923 switch (hdspm->io_type) {
3924 case RayDAT:
3925 case AIO:
3926 status = hdspm_read(hdspm, HDSPM_RD_STATUS_3);
3927 lock = (status & 0x400) ? 1 : 0;
3928 sync = (status & 0x800) ? 1 : 0;
3929 break;
3930
3931 case MADI:
3932 status = hdspm_read(hdspm, HDSPM_statusRegister);
3933 lock = (status & HDSPM_syncInLock) ? 1 : 0;
3934 sync = (status & HDSPM_syncInSync) ? 1 : 0;
3935 break;
3936
3937 case AES32:
3938 status = hdspm_read(hdspm, HDSPM_statusRegister2);
3939 lock = (status & 0x100000) ? 1 : 0;
3940 sync = (status & 0x200000) ? 1 : 0;
3941 break;
3942
3943 case MADIface:
3944 break;
3945 }
3946
3947 if (lock && sync)
3948 return 2;
3949 else if (lock)
3950 return 1;
3951
3952 return 0;
3953 }
3954
3955 static int hdspm_aes_sync_check(struct hdspm *hdspm, int idx)
3956 {
3957 int status2, lock, sync;
3958 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
3959
3960 lock = (status2 & (0x0080 >> idx)) ? 1 : 0;
3961 sync = (status2 & (0x8000 >> idx)) ? 1 : 0;
3962
3963 if (sync)
3964 return 2;
3965 else if (lock)
3966 return 1;
3967 return 0;
3968 }
3969
3970 static int hdspm_tco_input_check(struct hdspm *hdspm, u32 mask)
3971 {
3972 u32 status;
3973 status = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
3974
3975 return (status & mask) ? 1 : 0;
3976 }
3977
3978
3979 static int hdspm_tco_sync_check(struct hdspm *hdspm)
3980 {
3981 int status;
3982
3983 if (hdspm->tco) {
3984 switch (hdspm->io_type) {
3985 case MADI:
3986 status = hdspm_read(hdspm, HDSPM_statusRegister);
3987 if (status & HDSPM_tcoLockMadi) {
3988 if (status & HDSPM_tcoSync)
3989 return 2;
3990 else
3991 return 1;
3992 }
3993 return 0;
3994 case AES32:
3995 status = hdspm_read(hdspm, HDSPM_statusRegister);
3996 if (status & HDSPM_tcoLockAes) {
3997 if (status & HDSPM_tcoSync)
3998 return 2;
3999 else
4000 return 1;
4001 }
4002 return 0;
4003 case RayDAT:
4004 case AIO:
4005 status = hdspm_read(hdspm, HDSPM_RD_STATUS_1);
4006
4007 if (status & 0x8000000)
4008 return 2; /* Sync */
4009 if (status & 0x4000000)
4010 return 1; /* Lock */
4011 return 0; /* No signal */
4012
4013 default:
4014 break;
4015 }
4016 }
4017
4018 return 3; /* N/A */
4019 }
4020
4021
4022 static int snd_hdspm_get_sync_check(struct snd_kcontrol *kcontrol,
4023 struct snd_ctl_elem_value *ucontrol)
4024 {
4025 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4026 int val = -1;
4027
4028 switch (hdspm->io_type) {
4029 case RayDAT:
4030 switch (kcontrol->private_value) {
4031 case 0: /* WC */
4032 val = hdspm_wc_sync_check(hdspm); break;
4033 case 7: /* TCO */
4034 val = hdspm_tco_sync_check(hdspm); break;
4035 case 8: /* SYNC IN */
4036 val = hdspm_sync_in_sync_check(hdspm); break;
4037 default:
4038 val = hdspm_s1_sync_check(hdspm,
4039 kcontrol->private_value-1);
4040 }
4041 break;
4042
4043 case AIO:
4044 switch (kcontrol->private_value) {
4045 case 0: /* WC */
4046 val = hdspm_wc_sync_check(hdspm); break;
4047 case 4: /* TCO */
4048 val = hdspm_tco_sync_check(hdspm); break;
4049 case 5: /* SYNC IN */
4050 val = hdspm_sync_in_sync_check(hdspm); break;
4051 default:
4052 val = hdspm_s1_sync_check(hdspm,
4053 kcontrol->private_value-1);
4054 }
4055 break;
4056
4057 case MADI:
4058 switch (kcontrol->private_value) {
4059 case 0: /* WC */
4060 val = hdspm_wc_sync_check(hdspm); break;
4061 case 1: /* MADI */
4062 val = hdspm_madi_sync_check(hdspm); break;
4063 case 2: /* TCO */
4064 val = hdspm_tco_sync_check(hdspm); break;
4065 case 3: /* SYNC_IN */
4066 val = hdspm_sync_in_sync_check(hdspm); break;
4067 }
4068 break;
4069
4070 case MADIface:
4071 val = hdspm_madi_sync_check(hdspm); /* MADI */
4072 break;
4073
4074 case AES32:
4075 switch (kcontrol->private_value) {
4076 case 0: /* WC */
4077 val = hdspm_wc_sync_check(hdspm); break;
4078 case 9: /* TCO */
4079 val = hdspm_tco_sync_check(hdspm); break;
4080 case 10 /* SYNC IN */:
4081 val = hdspm_sync_in_sync_check(hdspm); break;
4082 default: /* AES1 to AES8 */
4083 val = hdspm_aes_sync_check(hdspm,
4084 kcontrol->private_value-1);
4085 }
4086 break;
4087
4088 }
4089
4090 if (hdspm->tco) {
4091 switch (kcontrol->private_value) {
4092 case 11:
4093 /* Check TCO for lock state of its current input */
4094 val = hdspm_tco_input_check(hdspm, HDSPM_TCO1_TCO_lock);
4095 break;
4096 case 12:
4097 /* Check TCO for valid time code on LTC input. */
4098 val = hdspm_tco_input_check(hdspm,
4099 HDSPM_TCO1_LTC_Input_valid);
4100 break;
4101 default:
4102 break;
4103 }
4104 }
4105
4106 if (-1 == val)
4107 val = 3;
4108
4109 ucontrol->value.enumerated.item[0] = val;
4110 return 0;
4111 }
4112
4113
4114
4115 /*
4116 * TCO controls
4117 */
4118 static void hdspm_tco_write(struct hdspm *hdspm)
4119 {
4120 unsigned int tc[4] = { 0, 0, 0, 0};
4121
4122 switch (hdspm->tco->input) {
4123 case 0:
4124 tc[2] |= HDSPM_TCO2_set_input_MSB;
4125 break;
4126 case 1:
4127 tc[2] |= HDSPM_TCO2_set_input_LSB;
4128 break;
4129 default:
4130 break;
4131 }
4132
4133 switch (hdspm->tco->framerate) {
4134 case 1:
4135 tc[1] |= HDSPM_TCO1_LTC_Format_LSB;
4136 break;
4137 case 2:
4138 tc[1] |= HDSPM_TCO1_LTC_Format_MSB;
4139 break;
4140 case 3:
4141 tc[1] |= HDSPM_TCO1_LTC_Format_MSB +
4142 HDSPM_TCO1_set_drop_frame_flag;
4143 break;
4144 case 4:
4145 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4146 HDSPM_TCO1_LTC_Format_MSB;
4147 break;
4148 case 5:
4149 tc[1] |= HDSPM_TCO1_LTC_Format_LSB +
4150 HDSPM_TCO1_LTC_Format_MSB +
4151 HDSPM_TCO1_set_drop_frame_flag;
4152 break;
4153 default:
4154 break;
4155 }
4156
4157 switch (hdspm->tco->wordclock) {
4158 case 1:
4159 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_LSB;
4160 break;
4161 case 2:
4162 tc[2] |= HDSPM_TCO2_WCK_IO_ratio_MSB;
4163 break;
4164 default:
4165 break;
4166 }
4167
4168 switch (hdspm->tco->samplerate) {
4169 case 1:
4170 tc[2] |= HDSPM_TCO2_set_freq;
4171 break;
4172 case 2:
4173 tc[2] |= HDSPM_TCO2_set_freq_from_app;
4174 break;
4175 default:
4176 break;
4177 }
4178
4179 switch (hdspm->tco->pull) {
4180 case 1:
4181 tc[2] |= HDSPM_TCO2_set_pull_up;
4182 break;
4183 case 2:
4184 tc[2] |= HDSPM_TCO2_set_pull_down;
4185 break;
4186 case 3:
4187 tc[2] |= HDSPM_TCO2_set_pull_up + HDSPM_TCO2_set_01_4;
4188 break;
4189 case 4:
4190 tc[2] |= HDSPM_TCO2_set_pull_down + HDSPM_TCO2_set_01_4;
4191 break;
4192 default:
4193 break;
4194 }
4195
4196 if (1 == hdspm->tco->term) {
4197 tc[2] |= HDSPM_TCO2_set_term_75R;
4198 }
4199
4200 hdspm_write(hdspm, HDSPM_WR_TCO, tc[0]);
4201 hdspm_write(hdspm, HDSPM_WR_TCO+4, tc[1]);
4202 hdspm_write(hdspm, HDSPM_WR_TCO+8, tc[2]);
4203 hdspm_write(hdspm, HDSPM_WR_TCO+12, tc[3]);
4204 }
4205
4206
4207 #define HDSPM_TCO_SAMPLE_RATE(xname, xindex) \
4208 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4209 .name = xname, \
4210 .index = xindex, \
4211 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4212 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4213 .info = snd_hdspm_info_tco_sample_rate, \
4214 .get = snd_hdspm_get_tco_sample_rate, \
4215 .put = snd_hdspm_put_tco_sample_rate \
4216 }
4217
4218 static int snd_hdspm_info_tco_sample_rate(struct snd_kcontrol *kcontrol,
4219 struct snd_ctl_elem_info *uinfo)
4220 {
4221 /* TODO freq from app could be supported here, see tco->samplerate */
4222 static const char *const texts[] = { "44.1 kHz", "48 kHz" };
4223 ENUMERATED_CTL_INFO(uinfo, texts);
4224 return 0;
4225 }
4226
4227 static int snd_hdspm_get_tco_sample_rate(struct snd_kcontrol *kcontrol,
4228 struct snd_ctl_elem_value *ucontrol)
4229 {
4230 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4231
4232 ucontrol->value.enumerated.item[0] = hdspm->tco->samplerate;
4233
4234 return 0;
4235 }
4236
4237 static int snd_hdspm_put_tco_sample_rate(struct snd_kcontrol *kcontrol,
4238 struct snd_ctl_elem_value *ucontrol)
4239 {
4240 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4241
4242 if (hdspm->tco->samplerate != ucontrol->value.enumerated.item[0]) {
4243 hdspm->tco->samplerate = ucontrol->value.enumerated.item[0];
4244
4245 hdspm_tco_write(hdspm);
4246
4247 return 1;
4248 }
4249
4250 return 0;
4251 }
4252
4253
4254 #define HDSPM_TCO_PULL(xname, xindex) \
4255 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4256 .name = xname, \
4257 .index = xindex, \
4258 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4259 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4260 .info = snd_hdspm_info_tco_pull, \
4261 .get = snd_hdspm_get_tco_pull, \
4262 .put = snd_hdspm_put_tco_pull \
4263 }
4264
4265 static int snd_hdspm_info_tco_pull(struct snd_kcontrol *kcontrol,
4266 struct snd_ctl_elem_info *uinfo)
4267 {
4268 static const char *const texts[] = { "0", "+ 0.1 %", "- 0.1 %",
4269 "+ 4 %", "- 4 %" };
4270 ENUMERATED_CTL_INFO(uinfo, texts);
4271 return 0;
4272 }
4273
4274 static int snd_hdspm_get_tco_pull(struct snd_kcontrol *kcontrol,
4275 struct snd_ctl_elem_value *ucontrol)
4276 {
4277 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4278
4279 ucontrol->value.enumerated.item[0] = hdspm->tco->pull;
4280
4281 return 0;
4282 }
4283
4284 static int snd_hdspm_put_tco_pull(struct snd_kcontrol *kcontrol,
4285 struct snd_ctl_elem_value *ucontrol)
4286 {
4287 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4288
4289 if (hdspm->tco->pull != ucontrol->value.enumerated.item[0]) {
4290 hdspm->tco->pull = ucontrol->value.enumerated.item[0];
4291
4292 hdspm_tco_write(hdspm);
4293
4294 return 1;
4295 }
4296
4297 return 0;
4298 }
4299
4300 #define HDSPM_TCO_WCK_CONVERSION(xname, xindex) \
4301 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4302 .name = xname, \
4303 .index = xindex, \
4304 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4305 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4306 .info = snd_hdspm_info_tco_wck_conversion, \
4307 .get = snd_hdspm_get_tco_wck_conversion, \
4308 .put = snd_hdspm_put_tco_wck_conversion \
4309 }
4310
4311 static int snd_hdspm_info_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4312 struct snd_ctl_elem_info *uinfo)
4313 {
4314 static const char *const texts[] = { "1:1", "44.1 -> 48", "48 -> 44.1" };
4315 ENUMERATED_CTL_INFO(uinfo, texts);
4316 return 0;
4317 }
4318
4319 static int snd_hdspm_get_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4320 struct snd_ctl_elem_value *ucontrol)
4321 {
4322 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4323
4324 ucontrol->value.enumerated.item[0] = hdspm->tco->wordclock;
4325
4326 return 0;
4327 }
4328
4329 static int snd_hdspm_put_tco_wck_conversion(struct snd_kcontrol *kcontrol,
4330 struct snd_ctl_elem_value *ucontrol)
4331 {
4332 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4333
4334 if (hdspm->tco->wordclock != ucontrol->value.enumerated.item[0]) {
4335 hdspm->tco->wordclock = ucontrol->value.enumerated.item[0];
4336
4337 hdspm_tco_write(hdspm);
4338
4339 return 1;
4340 }
4341
4342 return 0;
4343 }
4344
4345
4346 #define HDSPM_TCO_FRAME_RATE(xname, xindex) \
4347 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4348 .name = xname, \
4349 .index = xindex, \
4350 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4351 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4352 .info = snd_hdspm_info_tco_frame_rate, \
4353 .get = snd_hdspm_get_tco_frame_rate, \
4354 .put = snd_hdspm_put_tco_frame_rate \
4355 }
4356
4357 static int snd_hdspm_info_tco_frame_rate(struct snd_kcontrol *kcontrol,
4358 struct snd_ctl_elem_info *uinfo)
4359 {
4360 static const char *const texts[] = { "24 fps", "25 fps", "29.97fps",
4361 "29.97 dfps", "30 fps", "30 dfps" };
4362 ENUMERATED_CTL_INFO(uinfo, texts);
4363 return 0;
4364 }
4365
4366 static int snd_hdspm_get_tco_frame_rate(struct snd_kcontrol *kcontrol,
4367 struct snd_ctl_elem_value *ucontrol)
4368 {
4369 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4370
4371 ucontrol->value.enumerated.item[0] = hdspm->tco->framerate;
4372
4373 return 0;
4374 }
4375
4376 static int snd_hdspm_put_tco_frame_rate(struct snd_kcontrol *kcontrol,
4377 struct snd_ctl_elem_value *ucontrol)
4378 {
4379 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4380
4381 if (hdspm->tco->framerate != ucontrol->value.enumerated.item[0]) {
4382 hdspm->tco->framerate = ucontrol->value.enumerated.item[0];
4383
4384 hdspm_tco_write(hdspm);
4385
4386 return 1;
4387 }
4388
4389 return 0;
4390 }
4391
4392
4393 #define HDSPM_TCO_SYNC_SOURCE(xname, xindex) \
4394 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4395 .name = xname, \
4396 .index = xindex, \
4397 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4398 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4399 .info = snd_hdspm_info_tco_sync_source, \
4400 .get = snd_hdspm_get_tco_sync_source, \
4401 .put = snd_hdspm_put_tco_sync_source \
4402 }
4403
4404 static int snd_hdspm_info_tco_sync_source(struct snd_kcontrol *kcontrol,
4405 struct snd_ctl_elem_info *uinfo)
4406 {
4407 static const char *const texts[] = { "LTC", "Video", "WCK" };
4408 ENUMERATED_CTL_INFO(uinfo, texts);
4409 return 0;
4410 }
4411
4412 static int snd_hdspm_get_tco_sync_source(struct snd_kcontrol *kcontrol,
4413 struct snd_ctl_elem_value *ucontrol)
4414 {
4415 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4416
4417 ucontrol->value.enumerated.item[0] = hdspm->tco->input;
4418
4419 return 0;
4420 }
4421
4422 static int snd_hdspm_put_tco_sync_source(struct snd_kcontrol *kcontrol,
4423 struct snd_ctl_elem_value *ucontrol)
4424 {
4425 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4426
4427 if (hdspm->tco->input != ucontrol->value.enumerated.item[0]) {
4428 hdspm->tco->input = ucontrol->value.enumerated.item[0];
4429
4430 hdspm_tco_write(hdspm);
4431
4432 return 1;
4433 }
4434
4435 return 0;
4436 }
4437
4438
4439 #define HDSPM_TCO_WORD_TERM(xname, xindex) \
4440 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
4441 .name = xname, \
4442 .index = xindex, \
4443 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |\
4444 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
4445 .info = snd_hdspm_info_tco_word_term, \
4446 .get = snd_hdspm_get_tco_word_term, \
4447 .put = snd_hdspm_put_tco_word_term \
4448 }
4449
4450 static int snd_hdspm_info_tco_word_term(struct snd_kcontrol *kcontrol,
4451 struct snd_ctl_elem_info *uinfo)
4452 {
4453 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
4454 uinfo->count = 1;
4455 uinfo->value.integer.min = 0;
4456 uinfo->value.integer.max = 1;
4457
4458 return 0;
4459 }
4460
4461
4462 static int snd_hdspm_get_tco_word_term(struct snd_kcontrol *kcontrol,
4463 struct snd_ctl_elem_value *ucontrol)
4464 {
4465 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4466
4467 ucontrol->value.integer.value[0] = hdspm->tco->term;
4468
4469 return 0;
4470 }
4471
4472
4473 static int snd_hdspm_put_tco_word_term(struct snd_kcontrol *kcontrol,
4474 struct snd_ctl_elem_value *ucontrol)
4475 {
4476 struct hdspm *hdspm = snd_kcontrol_chip(kcontrol);
4477
4478 if (hdspm->tco->term != ucontrol->value.integer.value[0]) {
4479 hdspm->tco->term = ucontrol->value.integer.value[0];
4480
4481 hdspm_tco_write(hdspm);
4482
4483 return 1;
4484 }
4485
4486 return 0;
4487 }
4488
4489
4490
4491
4492 static struct snd_kcontrol_new snd_hdspm_controls_madi[] = {
4493 HDSPM_MIXER("Mixer", 0),
4494 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4495 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4496 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4497 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4498 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4499 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4500 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4501 HDSPM_SYNC_CHECK("MADI SyncCheck", 1),
4502 HDSPM_SYNC_CHECK("TCO SyncCheck", 2),
4503 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 3),
4504 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4505 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4506 HDSPM_TOGGLE_SETTING("Disable 96K frames", HDSPM_SMUX),
4507 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4508 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4509 HDSPM_INPUT_SELECT("Input Select", 0),
4510 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4511 };
4512
4513
4514 static struct snd_kcontrol_new snd_hdspm_controls_madiface[] = {
4515 HDSPM_MIXER("Mixer", 0),
4516 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4517 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4518 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4519 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4520 HDSPM_SYNC_CHECK("MADI SyncCheck", 0),
4521 HDSPM_TOGGLE_SETTING("TX 64 channels mode", HDSPM_TX_64ch),
4522 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4523 HDSPM_TOGGLE_SETTING("Safe Mode", HDSPM_AutoInp),
4524 HDSPM_MADI_SPEEDMODE("MADI Speed Mode", 0)
4525 };
4526
4527 static struct snd_kcontrol_new snd_hdspm_controls_aio[] = {
4528 HDSPM_MIXER("Mixer", 0),
4529 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4530 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4531 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4532 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4533 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
4534 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4535 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4536 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4537 HDSPM_SYNC_CHECK("ADAT SyncCheck", 3),
4538 HDSPM_SYNC_CHECK("TCO SyncCheck", 4),
4539 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 5),
4540 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4541 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4542 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4543 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT Frequency", 3),
4544 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 4),
4545 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 5),
4546 HDSPM_CONTROL_TRISTATE("S/PDIF Input", HDSPM_c0_Input0),
4547 HDSPM_TOGGLE_SETTING("S/PDIF Out Optical", HDSPM_c0_Spdif_Opt),
4548 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4549 HDSPM_TOGGLE_SETTING("ADAT internal (AEB/TEB)", HDSPM_c0_AEB1),
4550 HDSPM_TOGGLE_SETTING("XLR Breakout Cable", HDSPM_c0_Sym6db),
4551 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48),
4552 HDSPM_CONTROL_TRISTATE("Input Level", HDSPM_c0_AD_GAIN0),
4553 HDSPM_CONTROL_TRISTATE("Output Level", HDSPM_c0_DA_GAIN0),
4554 HDSPM_CONTROL_TRISTATE("Phones Level", HDSPM_c0_PH_GAIN0)
4555
4556 /*
4557 HDSPM_INPUT_SELECT("Input Select", 0),
4558 HDSPM_SPDIF_OPTICAL("SPDIF Out Optical", 0),
4559 HDSPM_PROFESSIONAL("SPDIF Out Professional", 0);
4560 HDSPM_SPDIF_IN("SPDIF In", 0);
4561 HDSPM_BREAKOUT_CABLE("Breakout Cable", 0);
4562 HDSPM_INPUT_LEVEL("Input Level", 0);
4563 HDSPM_OUTPUT_LEVEL("Output Level", 0);
4564 HDSPM_PHONES("Phones", 0);
4565 */
4566 };
4567
4568 static struct snd_kcontrol_new snd_hdspm_controls_raydat[] = {
4569 HDSPM_MIXER("Mixer", 0),
4570 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4571 HDSPM_SYSTEM_CLOCK_MODE("Clock Mode", 0),
4572 HDSPM_PREF_SYNC_REF("Pref Sync Ref", 0),
4573 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4574 HDSPM_SYNC_CHECK("WC SyncCheck", 0),
4575 HDSPM_SYNC_CHECK("AES SyncCheck", 1),
4576 HDSPM_SYNC_CHECK("SPDIF SyncCheck", 2),
4577 HDSPM_SYNC_CHECK("ADAT1 SyncCheck", 3),
4578 HDSPM_SYNC_CHECK("ADAT2 SyncCheck", 4),
4579 HDSPM_SYNC_CHECK("ADAT3 SyncCheck", 5),
4580 HDSPM_SYNC_CHECK("ADAT4 SyncCheck", 6),
4581 HDSPM_SYNC_CHECK("TCO SyncCheck", 7),
4582 HDSPM_SYNC_CHECK("SYNC IN SyncCheck", 8),
4583 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4584 HDSPM_AUTOSYNC_SAMPLE_RATE("AES Frequency", 1),
4585 HDSPM_AUTOSYNC_SAMPLE_RATE("SPDIF Frequency", 2),
4586 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT1 Frequency", 3),
4587 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT2 Frequency", 4),
4588 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT3 Frequency", 5),
4589 HDSPM_AUTOSYNC_SAMPLE_RATE("ADAT4 Frequency", 6),
4590 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 7),
4591 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 8),
4592 HDSPM_TOGGLE_SETTING("S/PDIF Out Professional", HDSPM_c0_Pro),
4593 HDSPM_TOGGLE_SETTING("Single Speed WordClock Out", HDSPM_c0_Wck48)
4594 };
4595
4596 static struct snd_kcontrol_new snd_hdspm_controls_aes32[] = {
4597 HDSPM_MIXER("Mixer", 0),
4598 HDSPM_INTERNAL_CLOCK("Internal Clock", 0),
4599 HDSPM_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
4600 HDSPM_PREF_SYNC_REF("Preferred Sync Reference", 0),
4601 HDSPM_AUTOSYNC_REF("AutoSync Reference", 0),
4602 HDSPM_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
4603 HDSPM_AUTOSYNC_SAMPLE_RATE("External Rate", 11),
4604 HDSPM_SYNC_CHECK("WC Sync Check", 0),
4605 HDSPM_SYNC_CHECK("AES1 Sync Check", 1),
4606 HDSPM_SYNC_CHECK("AES2 Sync Check", 2),
4607 HDSPM_SYNC_CHECK("AES3 Sync Check", 3),
4608 HDSPM_SYNC_CHECK("AES4 Sync Check", 4),
4609 HDSPM_SYNC_CHECK("AES5 Sync Check", 5),
4610 HDSPM_SYNC_CHECK("AES6 Sync Check", 6),
4611 HDSPM_SYNC_CHECK("AES7 Sync Check", 7),
4612 HDSPM_SYNC_CHECK("AES8 Sync Check", 8),
4613 HDSPM_SYNC_CHECK("TCO Sync Check", 9),
4614 HDSPM_SYNC_CHECK("SYNC IN Sync Check", 10),
4615 HDSPM_AUTOSYNC_SAMPLE_RATE("WC Frequency", 0),
4616 HDSPM_AUTOSYNC_SAMPLE_RATE("AES1 Frequency", 1),
4617 HDSPM_AUTOSYNC_SAMPLE_RATE("AES2 Frequency", 2),
4618 HDSPM_AUTOSYNC_SAMPLE_RATE("AES3 Frequency", 3),
4619 HDSPM_AUTOSYNC_SAMPLE_RATE("AES4 Frequency", 4),
4620 HDSPM_AUTOSYNC_SAMPLE_RATE("AES5 Frequency", 5),
4621 HDSPM_AUTOSYNC_SAMPLE_RATE("AES6 Frequency", 6),
4622 HDSPM_AUTOSYNC_SAMPLE_RATE("AES7 Frequency", 7),
4623 HDSPM_AUTOSYNC_SAMPLE_RATE("AES8 Frequency", 8),
4624 HDSPM_AUTOSYNC_SAMPLE_RATE("TCO Frequency", 9),
4625 HDSPM_AUTOSYNC_SAMPLE_RATE("SYNC IN Frequency", 10),
4626 HDSPM_TOGGLE_SETTING("Line Out", HDSPM_LineOut),
4627 HDSPM_TOGGLE_SETTING("Emphasis", HDSPM_Emphasis),
4628 HDSPM_TOGGLE_SETTING("Non Audio", HDSPM_Dolby),
4629 HDSPM_TOGGLE_SETTING("Professional", HDSPM_Professional),
4630 HDSPM_TOGGLE_SETTING("Clear Track Marker", HDSPM_clr_tms),
4631 HDSPM_DS_WIRE("Double Speed Wire Mode", 0),
4632 HDSPM_QS_WIRE("Quad Speed Wire Mode", 0),
4633 };
4634
4635
4636
4637 /* Control elements for the optional TCO module */
4638 static struct snd_kcontrol_new snd_hdspm_controls_tco[] = {
4639 HDSPM_TCO_SAMPLE_RATE("TCO Sample Rate", 0),
4640 HDSPM_TCO_PULL("TCO Pull", 0),
4641 HDSPM_TCO_WCK_CONVERSION("TCO WCK Conversion", 0),
4642 HDSPM_TCO_FRAME_RATE("TCO Frame Rate", 0),
4643 HDSPM_TCO_SYNC_SOURCE("TCO Sync Source", 0),
4644 HDSPM_TCO_WORD_TERM("TCO Word Term", 0),
4645 HDSPM_TCO_LOCK_CHECK("TCO Input Check", 11),
4646 HDSPM_TCO_LOCK_CHECK("TCO LTC Valid", 12),
4647 HDSPM_TCO_LTC_FRAMES("TCO Detected Frame Rate", 0),
4648 HDSPM_TCO_VIDEO_INPUT_FORMAT("Video Input Format", 0)
4649 };
4650
4651
4652 static struct snd_kcontrol_new snd_hdspm_playback_mixer = HDSPM_PLAYBACK_MIXER;
4653
4654
4655 static int hdspm_update_simple_mixer_controls(struct hdspm * hdspm)
4656 {
4657 int i;
4658
4659 for (i = hdspm->ds_out_channels; i < hdspm->ss_out_channels; ++i) {
4660 if (hdspm->system_sample_rate > 48000) {
4661 hdspm->playback_mixer_ctls[i]->vd[0].access =
4662 SNDRV_CTL_ELEM_ACCESS_INACTIVE |
4663 SNDRV_CTL_ELEM_ACCESS_READ |
4664 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4665 } else {
4666 hdspm->playback_mixer_ctls[i]->vd[0].access =
4667 SNDRV_CTL_ELEM_ACCESS_READWRITE |
4668 SNDRV_CTL_ELEM_ACCESS_VOLATILE;
4669 }
4670 snd_ctl_notify(hdspm->card, SNDRV_CTL_EVENT_MASK_VALUE |
4671 SNDRV_CTL_EVENT_MASK_INFO,
4672 &hdspm->playback_mixer_ctls[i]->id);
4673 }
4674
4675 return 0;
4676 }
4677
4678
4679 static int snd_hdspm_create_controls(struct snd_card *card,
4680 struct hdspm *hdspm)
4681 {
4682 unsigned int idx, limit;
4683 int err;
4684 struct snd_kcontrol *kctl;
4685 struct snd_kcontrol_new *list = NULL;
4686
4687 switch (hdspm->io_type) {
4688 case MADI:
4689 list = snd_hdspm_controls_madi;
4690 limit = ARRAY_SIZE(snd_hdspm_controls_madi);
4691 break;
4692 case MADIface:
4693 list = snd_hdspm_controls_madiface;
4694 limit = ARRAY_SIZE(snd_hdspm_controls_madiface);
4695 break;
4696 case AIO:
4697 list = snd_hdspm_controls_aio;
4698 limit = ARRAY_SIZE(snd_hdspm_controls_aio);
4699 break;
4700 case RayDAT:
4701 list = snd_hdspm_controls_raydat;
4702 limit = ARRAY_SIZE(snd_hdspm_controls_raydat);
4703 break;
4704 case AES32:
4705 list = snd_hdspm_controls_aes32;
4706 limit = ARRAY_SIZE(snd_hdspm_controls_aes32);
4707 break;
4708 }
4709
4710 if (list) {
4711 for (idx = 0; idx < limit; idx++) {
4712 err = snd_ctl_add(card,
4713 snd_ctl_new1(&list[idx], hdspm));
4714 if (err < 0)
4715 return err;
4716 }
4717 }
4718
4719
4720 /* create simple 1:1 playback mixer controls */
4721 snd_hdspm_playback_mixer.name = "Chn";
4722 if (hdspm->system_sample_rate >= 128000) {
4723 limit = hdspm->qs_out_channels;
4724 } else if (hdspm->system_sample_rate >= 64000) {
4725 limit = hdspm->ds_out_channels;
4726 } else {
4727 limit = hdspm->ss_out_channels;
4728 }
4729 for (idx = 0; idx < limit; ++idx) {
4730 snd_hdspm_playback_mixer.index = idx + 1;
4731 kctl = snd_ctl_new1(&snd_hdspm_playback_mixer, hdspm);
4732 err = snd_ctl_add(card, kctl);
4733 if (err < 0)
4734 return err;
4735 hdspm->playback_mixer_ctls[idx] = kctl;
4736 }
4737
4738
4739 if (hdspm->tco) {
4740 /* add tco control elements */
4741 list = snd_hdspm_controls_tco;
4742 limit = ARRAY_SIZE(snd_hdspm_controls_tco);
4743 for (idx = 0; idx < limit; idx++) {
4744 err = snd_ctl_add(card,
4745 snd_ctl_new1(&list[idx], hdspm));
4746 if (err < 0)
4747 return err;
4748 }
4749 }
4750
4751 return 0;
4752 }
4753
4754 /*------------------------------------------------------------
4755 /proc interface
4756 ------------------------------------------------------------*/
4757
4758 static void
4759 snd_hdspm_proc_read_tco(struct snd_info_entry *entry,
4760 struct snd_info_buffer *buffer)
4761 {
4762 struct hdspm *hdspm = entry->private_data;
4763 unsigned int status, control;
4764 int a, ltc, frames, seconds, minutes, hours;
4765 unsigned int period;
4766 u64 freq_const = 0;
4767 u32 rate;
4768
4769 snd_iprintf(buffer, "--- TCO ---\n");
4770
4771 status = hdspm_read(hdspm, HDSPM_statusRegister);
4772 control = hdspm->control_register;
4773
4774
4775 if (status & HDSPM_tco_detect) {
4776 snd_iprintf(buffer, "TCO module detected.\n");
4777 a = hdspm_read(hdspm, HDSPM_RD_TCO+4);
4778 if (a & HDSPM_TCO1_LTC_Input_valid) {
4779 snd_iprintf(buffer, " LTC valid, ");
4780 switch (a & (HDSPM_TCO1_LTC_Format_LSB |
4781 HDSPM_TCO1_LTC_Format_MSB)) {
4782 case 0:
4783 snd_iprintf(buffer, "24 fps, ");
4784 break;
4785 case HDSPM_TCO1_LTC_Format_LSB:
4786 snd_iprintf(buffer, "25 fps, ");
4787 break;
4788 case HDSPM_TCO1_LTC_Format_MSB:
4789 snd_iprintf(buffer, "29.97 fps, ");
4790 break;
4791 default:
4792 snd_iprintf(buffer, "30 fps, ");
4793 break;
4794 }
4795 if (a & HDSPM_TCO1_set_drop_frame_flag) {
4796 snd_iprintf(buffer, "drop frame\n");
4797 } else {
4798 snd_iprintf(buffer, "full frame\n");
4799 }
4800 } else {
4801 snd_iprintf(buffer, " no LTC\n");
4802 }
4803 if (a & HDSPM_TCO1_Video_Input_Format_NTSC) {
4804 snd_iprintf(buffer, " Video: NTSC\n");
4805 } else if (a & HDSPM_TCO1_Video_Input_Format_PAL) {
4806 snd_iprintf(buffer, " Video: PAL\n");
4807 } else {
4808 snd_iprintf(buffer, " No video\n");
4809 }
4810 if (a & HDSPM_TCO1_TCO_lock) {
4811 snd_iprintf(buffer, " Sync: lock\n");
4812 } else {
4813 snd_iprintf(buffer, " Sync: no lock\n");
4814 }
4815
4816 switch (hdspm->io_type) {
4817 case MADI:
4818 case AES32:
4819 freq_const = 110069313433624ULL;
4820 break;
4821 case RayDAT:
4822 case AIO:
4823 freq_const = 104857600000000ULL;
4824 break;
4825 case MADIface:
4826 break; /* no TCO possible */
4827 }
4828
4829 period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
4830 snd_iprintf(buffer, " period: %u\n", period);
4831
4832
4833 /* rate = freq_const/period; */
4834 rate = div_u64(freq_const, period);
4835
4836 if (control & HDSPM_QuadSpeed) {
4837 rate *= 4;
4838 } else if (control & HDSPM_DoubleSpeed) {
4839 rate *= 2;
4840 }
4841
4842 snd_iprintf(buffer, " Frequency: %u Hz\n",
4843 (unsigned int) rate);
4844
4845 ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
4846 frames = ltc & 0xF;
4847 ltc >>= 4;
4848 frames += (ltc & 0x3) * 10;
4849 ltc >>= 4;
4850 seconds = ltc & 0xF;
4851 ltc >>= 4;
4852 seconds += (ltc & 0x7) * 10;
4853 ltc >>= 4;
4854 minutes = ltc & 0xF;
4855 ltc >>= 4;
4856 minutes += (ltc & 0x7) * 10;
4857 ltc >>= 4;
4858 hours = ltc & 0xF;
4859 ltc >>= 4;
4860 hours += (ltc & 0x3) * 10;
4861 snd_iprintf(buffer,
4862 " LTC In: %02d:%02d:%02d:%02d\n",
4863 hours, minutes, seconds, frames);
4864
4865 } else {
4866 snd_iprintf(buffer, "No TCO module detected.\n");
4867 }
4868 }
4869
4870 static void
4871 snd_hdspm_proc_read_madi(struct snd_info_entry *entry,
4872 struct snd_info_buffer *buffer)
4873 {
4874 struct hdspm *hdspm = entry->private_data;
4875 unsigned int status, status2;
4876
4877 char *pref_sync_ref;
4878 char *autosync_ref;
4879 char *system_clock_mode;
4880 int x, x2;
4881
4882 status = hdspm_read(hdspm, HDSPM_statusRegister);
4883 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
4884
4885 snd_iprintf(buffer, "%s (Card #%d) Rev.%x Status2first3bits: %x\n",
4886 hdspm->card_name, hdspm->card->number + 1,
4887 hdspm->firmware_rev,
4888 (status2 & HDSPM_version0) |
4889 (status2 & HDSPM_version1) | (status2 &
4890 HDSPM_version2));
4891
4892 snd_iprintf(buffer, "HW Serial: 0x%06x%06x\n",
4893 (hdspm_read(hdspm, HDSPM_midiStatusIn1)>>8) & 0xFFFFFF,
4894 hdspm->serial);
4895
4896 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
4897 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
4898
4899 snd_iprintf(buffer, "--- System ---\n");
4900
4901 snd_iprintf(buffer,
4902 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
4903 status & HDSPM_audioIRQPending,
4904 (status & HDSPM_midi0IRQPending) ? 1 : 0,
4905 (status & HDSPM_midi1IRQPending) ? 1 : 0,
4906 hdspm->irq_count);
4907 snd_iprintf(buffer,
4908 "HW pointer: id = %d, rawptr = %d (%d->%d) "
4909 "estimated= %ld (bytes)\n",
4910 ((status & HDSPM_BufferID) ? 1 : 0),
4911 (status & HDSPM_BufferPositionMask),
4912 (status & HDSPM_BufferPositionMask) %
4913 (2 * (int)hdspm->period_bytes),
4914 ((status & HDSPM_BufferPositionMask) - 64) %
4915 (2 * (int)hdspm->period_bytes),
4916 (long) hdspm_hw_pointer(hdspm) * 4);
4917
4918 snd_iprintf(buffer,
4919 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
4920 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
4921 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
4922 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
4923 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
4924 snd_iprintf(buffer,
4925 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
4926 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
4927 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
4928 snd_iprintf(buffer,
4929 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
4930 "status2=0x%x\n",
4931 hdspm->control_register, hdspm->control2_register,
4932 status, status2);
4933
4934
4935 snd_iprintf(buffer, "--- Settings ---\n");
4936
4937 x = hdspm_get_latency(hdspm);
4938
4939 snd_iprintf(buffer,
4940 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
4941 x, (unsigned long) hdspm->period_bytes);
4942
4943 snd_iprintf(buffer, "Line out: %s\n",
4944 (hdspm->control_register & HDSPM_LineOut) ? "on " : "off");
4945
4946 snd_iprintf(buffer,
4947 "ClearTrackMarker = %s, Transmit in %s Channel Mode, "
4948 "Auto Input %s\n",
4949 (hdspm->control_register & HDSPM_clr_tms) ? "on" : "off",
4950 (hdspm->control_register & HDSPM_TX_64ch) ? "64" : "56",
4951 (hdspm->control_register & HDSPM_AutoInp) ? "on" : "off");
4952
4953
4954 if (!(hdspm->control_register & HDSPM_ClockModeMaster))
4955 system_clock_mode = "AutoSync";
4956 else
4957 system_clock_mode = "Master";
4958 snd_iprintf(buffer, "AutoSync Reference: %s\n", system_clock_mode);
4959
4960 switch (hdspm_pref_sync_ref(hdspm)) {
4961 case HDSPM_SYNC_FROM_WORD:
4962 pref_sync_ref = "Word Clock";
4963 break;
4964 case HDSPM_SYNC_FROM_MADI:
4965 pref_sync_ref = "MADI Sync";
4966 break;
4967 case HDSPM_SYNC_FROM_TCO:
4968 pref_sync_ref = "TCO";
4969 break;
4970 case HDSPM_SYNC_FROM_SYNC_IN:
4971 pref_sync_ref = "Sync In";
4972 break;
4973 default:
4974 pref_sync_ref = "XXXX Clock";
4975 break;
4976 }
4977 snd_iprintf(buffer, "Preferred Sync Reference: %s\n",
4978 pref_sync_ref);
4979
4980 snd_iprintf(buffer, "System Clock Frequency: %d\n",
4981 hdspm->system_sample_rate);
4982
4983
4984 snd_iprintf(buffer, "--- Status:\n");
4985
4986 x = status & HDSPM_madiSync;
4987 x2 = status2 & HDSPM_wcSync;
4988
4989 snd_iprintf(buffer, "Inputs MADI=%s, WordClock=%s\n",
4990 (status & HDSPM_madiLock) ? (x ? "Sync" : "Lock") :
4991 "NoLock",
4992 (status2 & HDSPM_wcLock) ? (x2 ? "Sync" : "Lock") :
4993 "NoLock");
4994
4995 switch (hdspm_autosync_ref(hdspm)) {
4996 case HDSPM_AUTOSYNC_FROM_SYNC_IN:
4997 autosync_ref = "Sync In";
4998 break;
4999 case HDSPM_AUTOSYNC_FROM_TCO:
5000 autosync_ref = "TCO";
5001 break;
5002 case HDSPM_AUTOSYNC_FROM_WORD:
5003 autosync_ref = "Word Clock";
5004 break;
5005 case HDSPM_AUTOSYNC_FROM_MADI:
5006 autosync_ref = "MADI Sync";
5007 break;
5008 case HDSPM_AUTOSYNC_FROM_NONE:
5009 autosync_ref = "Input not valid";
5010 break;
5011 default:
5012 autosync_ref = "---";
5013 break;
5014 }
5015 snd_iprintf(buffer,
5016 "AutoSync: Reference= %s, Freq=%d (MADI = %d, Word = %d)\n",
5017 autosync_ref, hdspm_external_sample_rate(hdspm),
5018 (status & HDSPM_madiFreqMask) >> 22,
5019 (status2 & HDSPM_wcFreqMask) >> 5);
5020
5021 snd_iprintf(buffer, "Input: %s, Mode=%s\n",
5022 (status & HDSPM_AB_int) ? "Coax" : "Optical",
5023 (status & HDSPM_RX_64ch) ? "64 channels" :
5024 "56 channels");
5025
5026 /* call readout function for TCO specific status */
5027 snd_hdspm_proc_read_tco(entry, buffer);
5028
5029 snd_iprintf(buffer, "\n");
5030 }
5031
5032 static void
5033 snd_hdspm_proc_read_aes32(struct snd_info_entry * entry,
5034 struct snd_info_buffer *buffer)
5035 {
5036 struct hdspm *hdspm = entry->private_data;
5037 unsigned int status;
5038 unsigned int status2;
5039 unsigned int timecode;
5040 unsigned int wcLock, wcSync;
5041 int pref_syncref;
5042 char *autosync_ref;
5043 int x;
5044
5045 status = hdspm_read(hdspm, HDSPM_statusRegister);
5046 status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
5047 timecode = hdspm_read(hdspm, HDSPM_timecodeRegister);
5048
5049 snd_iprintf(buffer, "%s (Card #%d) Rev.%x\n",
5050 hdspm->card_name, hdspm->card->number + 1,
5051 hdspm->firmware_rev);
5052
5053 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
5054 hdspm->irq, hdspm->port, (unsigned long)hdspm->iobase);
5055
5056 snd_iprintf(buffer, "--- System ---\n");
5057
5058 snd_iprintf(buffer,
5059 "IRQ Pending: Audio=%d, MIDI0=%d, MIDI1=%d, IRQcount=%d\n",
5060 status & HDSPM_audioIRQPending,
5061 (status & HDSPM_midi0IRQPending) ? 1 : 0,
5062 (status & HDSPM_midi1IRQPending) ? 1 : 0,
5063 hdspm->irq_count);
5064 snd_iprintf(buffer,
5065 "HW pointer: id = %d, rawptr = %d (%d->%d) "
5066 "estimated= %ld (bytes)\n",
5067 ((status & HDSPM_BufferID) ? 1 : 0),
5068 (status & HDSPM_BufferPositionMask),
5069 (status & HDSPM_BufferPositionMask) %
5070 (2 * (int)hdspm->period_bytes),
5071 ((status & HDSPM_BufferPositionMask) - 64) %
5072 (2 * (int)hdspm->period_bytes),
5073 (long) hdspm_hw_pointer(hdspm) * 4);
5074
5075 snd_iprintf(buffer,
5076 "MIDI FIFO: Out1=0x%x, Out2=0x%x, In1=0x%x, In2=0x%x \n",
5077 hdspm_read(hdspm, HDSPM_midiStatusOut0) & 0xFF,
5078 hdspm_read(hdspm, HDSPM_midiStatusOut1) & 0xFF,
5079 hdspm_read(hdspm, HDSPM_midiStatusIn0) & 0xFF,
5080 hdspm_read(hdspm, HDSPM_midiStatusIn1) & 0xFF);
5081 snd_iprintf(buffer,
5082 "MIDIoverMADI FIFO: In=0x%x, Out=0x%x \n",
5083 hdspm_read(hdspm, HDSPM_midiStatusIn2) & 0xFF,
5084 hdspm_read(hdspm, HDSPM_midiStatusOut2) & 0xFF);
5085 snd_iprintf(buffer,
5086 "Register: ctrl1=0x%x, ctrl2=0x%x, status1=0x%x, "
5087 "status2=0x%x\n",
5088 hdspm->control_register, hdspm->control2_register,
5089 status, status2);
5090
5091 snd_iprintf(buffer, "--- Settings ---\n");
5092
5093 x = hdspm_get_latency(hdspm);
5094
5095 snd_iprintf(buffer,
5096 "Size (Latency): %d samples (2 periods of %lu bytes)\n",
5097 x, (unsigned long) hdspm->period_bytes);
5098
5099 snd_iprintf(buffer, "Line out: %s\n",
5100 (hdspm->
5101 control_register & HDSPM_LineOut) ? "on " : "off");
5102
5103 snd_iprintf(buffer,
5104 "ClearTrackMarker %s, Emphasis %s, Dolby %s\n",
5105 (hdspm->
5106 control_register & HDSPM_clr_tms) ? "on" : "off",
5107 (hdspm->
5108 control_register & HDSPM_Emphasis) ? "on" : "off",
5109 (hdspm->
5110 control_register & HDSPM_Dolby) ? "on" : "off");
5111
5112
5113 pref_syncref = hdspm_pref_sync_ref(hdspm);
5114 if (pref_syncref == 0)
5115 snd_iprintf(buffer, "Preferred Sync Reference: Word Clock\n");
5116 else
5117 snd_iprintf(buffer, "Preferred Sync Reference: AES%d\n",
5118 pref_syncref);
5119
5120 snd_iprintf(buffer, "System Clock Frequency: %d\n",
5121 hdspm->system_sample_rate);
5122
5123 snd_iprintf(buffer, "Double speed: %s\n",
5124 hdspm->control_register & HDSPM_DS_DoubleWire?
5125 "Double wire" : "Single wire");
5126 snd_iprintf(buffer, "Quad speed: %s\n",
5127 hdspm->control_register & HDSPM_QS_DoubleWire?
5128 "Double wire" :
5129 hdspm->control_register & HDSPM_QS_QuadWire?
5130 "Quad wire" : "Single wire");
5131
5132 snd_iprintf(buffer, "--- Status:\n");
5133
5134 wcLock = status & HDSPM_AES32_wcLock;
5135 wcSync = wcLock && (status & HDSPM_AES32_wcSync);
5136
5137 snd_iprintf(buffer, "Word: %s Frequency: %d\n",
5138 (wcLock) ? (wcSync ? "Sync " : "Lock ") : "No Lock",
5139 HDSPM_bit2freq((status >> HDSPM_AES32_wcFreq_bit) & 0xF));
5140
5141 for (x = 0; x < 8; x++) {
5142 snd_iprintf(buffer, "AES%d: %s Frequency: %d\n",
5143 x+1,
5144 (status2 & (HDSPM_LockAES >> x)) ?
5145 "Sync " : "No Lock",
5146 HDSPM_bit2freq((timecode >> (4*x)) & 0xF));
5147 }
5148
5149 switch (hdspm_autosync_ref(hdspm)) {
5150 case HDSPM_AES32_AUTOSYNC_FROM_NONE:
5151 autosync_ref = "None"; break;
5152 case HDSPM_AES32_AUTOSYNC_FROM_WORD:
5153 autosync_ref = "Word Clock"; break;
5154 case HDSPM_AES32_AUTOSYNC_FROM_AES1:
5155 autosync_ref = "AES1"; break;
5156 case HDSPM_AES32_AUTOSYNC_FROM_AES2:
5157 autosync_ref = "AES2"; break;
5158 case HDSPM_AES32_AUTOSYNC_FROM_AES3:
5159 autosync_ref = "AES3"; break;
5160 case HDSPM_AES32_AUTOSYNC_FROM_AES4:
5161 autosync_ref = "AES4"; break;
5162 case HDSPM_AES32_AUTOSYNC_FROM_AES5:
5163 autosync_ref = "AES5"; break;
5164 case HDSPM_AES32_AUTOSYNC_FROM_AES6:
5165 autosync_ref = "AES6"; break;
5166 case HDSPM_AES32_AUTOSYNC_FROM_AES7:
5167 autosync_ref = "AES7"; break;
5168 case HDSPM_AES32_AUTOSYNC_FROM_AES8:
5169 autosync_ref = "AES8"; break;
5170 case HDSPM_AES32_AUTOSYNC_FROM_TCO:
5171 autosync_ref = "TCO"; break;
5172 case HDSPM_AES32_AUTOSYNC_FROM_SYNC_IN:
5173 autosync_ref = "Sync In"; break;
5174 default:
5175 autosync_ref = "---"; break;
5176 }
5177 snd_iprintf(buffer, "AutoSync ref = %s\n", autosync_ref);
5178
5179 /* call readout function for TCO specific status */
5180 snd_hdspm_proc_read_tco(entry, buffer);
5181
5182 snd_iprintf(buffer, "\n");
5183 }
5184
5185 static void
5186 snd_hdspm_proc_read_raydat(struct snd_info_entry *entry,
5187 struct snd_info_buffer *buffer)
5188 {
5189 struct hdspm *hdspm = entry->private_data;
5190 unsigned int status1, status2, status3, i;
5191 unsigned int lock, sync;
5192
5193 status1 = hdspm_read(hdspm, HDSPM_RD_STATUS_1); /* s1 */
5194 status2 = hdspm_read(hdspm, HDSPM_RD_STATUS_2); /* freq */
5195 status3 = hdspm_read(hdspm, HDSPM_RD_STATUS_3); /* s2 */
5196
5197 snd_iprintf(buffer, "STATUS1: 0x%08x\n", status1);
5198 snd_iprintf(buffer, "STATUS2: 0x%08x\n", status2);
5199 snd_iprintf(buffer, "STATUS3: 0x%08x\n", status3);
5200
5201
5202 snd_iprintf(buffer, "\n*** CLOCK MODE\n\n");
5203
5204 snd_iprintf(buffer, "Clock mode : %s\n",
5205 (hdspm_system_clock_mode(hdspm) == 0) ? "master" : "slave");
5206 snd_iprintf(buffer, "System frequency: %d Hz\n",
5207 hdspm_get_system_sample_rate(hdspm));
5208
5209 snd_iprintf(buffer, "\n*** INPUT STATUS\n\n");
5210
5211 lock = 0x1;
5212 sync = 0x100;
5213
5214 for (i = 0; i < 8; i++) {
5215 snd_iprintf(buffer, "s1_input %d: Lock %d, Sync %d, Freq %s\n",
5216 i,
5217 (status1 & lock) ? 1 : 0,
5218 (status1 & sync) ? 1 : 0,
5219 texts_freq[(status2 >> (i * 4)) & 0xF]);
5220
5221 lock = lock<<1;
5222 sync = sync<<1;
5223 }
5224
5225 snd_iprintf(buffer, "WC input: Lock %d, Sync %d, Freq %s\n",
5226 (status1 & 0x1000000) ? 1 : 0,
5227 (status1 & 0x2000000) ? 1 : 0,
5228 texts_freq[(status1 >> 16) & 0xF]);
5229
5230 snd_iprintf(buffer, "TCO input: Lock %d, Sync %d, Freq %s\n",
5231 (status1 & 0x4000000) ? 1 : 0,
5232 (status1 & 0x8000000) ? 1 : 0,
5233 texts_freq[(status1 >> 20) & 0xF]);
5234
5235 snd_iprintf(buffer, "SYNC IN: Lock %d, Sync %d, Freq %s\n",
5236 (status3 & 0x400) ? 1 : 0,
5237 (status3 & 0x800) ? 1 : 0,
5238 texts_freq[(status2 >> 12) & 0xF]);
5239
5240 }
5241
5242 #ifdef CONFIG_SND_DEBUG
5243 static void
5244 snd_hdspm_proc_read_debug(struct snd_info_entry *entry,
5245 struct snd_info_buffer *buffer)
5246 {
5247 struct hdspm *hdspm = entry->private_data;
5248
5249 int j,i;
5250
5251 for (i = 0; i < 256 /* 1024*64 */; i += j) {
5252 snd_iprintf(buffer, "0x%08X: ", i);
5253 for (j = 0; j < 16; j += 4)
5254 snd_iprintf(buffer, "%08X ", hdspm_read(hdspm, i + j));
5255 snd_iprintf(buffer, "\n");
5256 }
5257 }
5258 #endif
5259
5260
5261 static void snd_hdspm_proc_ports_in(struct snd_info_entry *entry,
5262 struct snd_info_buffer *buffer)
5263 {
5264 struct hdspm *hdspm = entry->private_data;
5265 int i;
5266
5267 snd_iprintf(buffer, "# generated by hdspm\n");
5268
5269 for (i = 0; i < hdspm->max_channels_in; i++) {
5270 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_in[i]);
5271 }
5272 }
5273
5274 static void snd_hdspm_proc_ports_out(struct snd_info_entry *entry,
5275 struct snd_info_buffer *buffer)
5276 {
5277 struct hdspm *hdspm = entry->private_data;
5278 int i;
5279
5280 snd_iprintf(buffer, "# generated by hdspm\n");
5281
5282 for (i = 0; i < hdspm->max_channels_out; i++) {
5283 snd_iprintf(buffer, "%d=%s\n", i+1, hdspm->port_names_out[i]);
5284 }
5285 }
5286
5287
5288 static void snd_hdspm_proc_init(struct hdspm *hdspm)
5289 {
5290 struct snd_info_entry *entry;
5291
5292 if (!snd_card_proc_new(hdspm->card, "hdspm", &entry)) {
5293 switch (hdspm->io_type) {
5294 case AES32:
5295 snd_info_set_text_ops(entry, hdspm,
5296 snd_hdspm_proc_read_aes32);
5297 break;
5298 case MADI:
5299 snd_info_set_text_ops(entry, hdspm,
5300 snd_hdspm_proc_read_madi);
5301 break;
5302 case MADIface:
5303 /* snd_info_set_text_ops(entry, hdspm,
5304 snd_hdspm_proc_read_madiface); */
5305 break;
5306 case RayDAT:
5307 snd_info_set_text_ops(entry, hdspm,
5308 snd_hdspm_proc_read_raydat);
5309 break;
5310 case AIO:
5311 break;
5312 }
5313 }
5314
5315 if (!snd_card_proc_new(hdspm->card, "ports.in", &entry)) {
5316 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_in);
5317 }
5318
5319 if (!snd_card_proc_new(hdspm->card, "ports.out", &entry)) {
5320 snd_info_set_text_ops(entry, hdspm, snd_hdspm_proc_ports_out);
5321 }
5322
5323 #ifdef CONFIG_SND_DEBUG
5324 /* debug file to read all hdspm registers */
5325 if (!snd_card_proc_new(hdspm->card, "debug", &entry))
5326 snd_info_set_text_ops(entry, hdspm,
5327 snd_hdspm_proc_read_debug);
5328 #endif
5329 }
5330
5331 /*------------------------------------------------------------
5332 hdspm intitialize
5333 ------------------------------------------------------------*/
5334
5335 static int snd_hdspm_set_defaults(struct hdspm * hdspm)
5336 {
5337 /* ASSUMPTION: hdspm->lock is either held, or there is no need to
5338 hold it (e.g. during module initialization).
5339 */
5340
5341 /* set defaults: */
5342
5343 hdspm->settings_register = 0;
5344
5345 switch (hdspm->io_type) {
5346 case MADI:
5347 case MADIface:
5348 hdspm->control_register =
5349 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5350 break;
5351
5352 case RayDAT:
5353 case AIO:
5354 hdspm->settings_register = 0x1 + 0x1000;
5355 /* Magic values are: LAT_0, LAT_2, Master, freq1, tx64ch, inp_0,
5356 * line_out */
5357 hdspm->control_register =
5358 0x2 + 0x8 + 0x10 + 0x80 + 0x400 + 0x4000 + 0x1000000;
5359 break;
5360
5361 case AES32:
5362 hdspm->control_register =
5363 HDSPM_ClockModeMaster | /* Master Clock Mode on */
5364 hdspm_encode_latency(7) | /* latency max=8192samples */
5365 HDSPM_SyncRef0 | /* AES1 is syncclock */
5366 HDSPM_LineOut | /* Analog output in */
5367 HDSPM_Professional; /* Professional mode */
5368 break;
5369 }
5370
5371 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5372
5373 if (AES32 == hdspm->io_type) {
5374 /* No control2 register for AES32 */
5375 #ifdef SNDRV_BIG_ENDIAN
5376 hdspm->control2_register = HDSPM_BIGENDIAN_MODE;
5377 #else
5378 hdspm->control2_register = 0;
5379 #endif
5380
5381 hdspm_write(hdspm, HDSPM_control2Reg, hdspm->control2_register);
5382 }
5383 hdspm_compute_period_size(hdspm);
5384
5385 /* silence everything */
5386
5387 all_in_all_mixer(hdspm, 0 * UNITY_GAIN);
5388
5389 if (hdspm_is_raydat_or_aio(hdspm))
5390 hdspm_write(hdspm, HDSPM_WR_SETTINGS, hdspm->settings_register);
5391
5392 /* set a default rate so that the channel map is set up. */
5393 hdspm_set_rate(hdspm, 48000, 1);
5394
5395 return 0;
5396 }
5397
5398
5399 /*------------------------------------------------------------
5400 interrupt
5401 ------------------------------------------------------------*/
5402
5403 static irqreturn_t snd_hdspm_interrupt(int irq, void *dev_id)
5404 {
5405 struct hdspm *hdspm = (struct hdspm *) dev_id;
5406 unsigned int status;
5407 int i, audio, midi, schedule = 0;
5408 /* cycles_t now; */
5409
5410 status = hdspm_read(hdspm, HDSPM_statusRegister);
5411
5412 audio = status & HDSPM_audioIRQPending;
5413 midi = status & (HDSPM_midi0IRQPending | HDSPM_midi1IRQPending |
5414 HDSPM_midi2IRQPending | HDSPM_midi3IRQPending);
5415
5416 /* now = get_cycles(); */
5417 /*
5418 * LAT_2..LAT_0 period counter (win) counter (mac)
5419 * 6 4096 ~256053425 ~514672358
5420 * 5 2048 ~128024983 ~257373821
5421 * 4 1024 ~64023706 ~128718089
5422 * 3 512 ~32005945 ~64385999
5423 * 2 256 ~16003039 ~32260176
5424 * 1 128 ~7998738 ~16194507
5425 * 0 64 ~3998231 ~8191558
5426 */
5427 /*
5428 dev_info(hdspm->card->dev, "snd_hdspm_interrupt %llu @ %llx\n",
5429 now-hdspm->last_interrupt, status & 0xFFC0);
5430 hdspm->last_interrupt = now;
5431 */
5432
5433 if (!audio && !midi)
5434 return IRQ_NONE;
5435
5436 hdspm_write(hdspm, HDSPM_interruptConfirmation, 0);
5437 hdspm->irq_count++;
5438
5439
5440 if (audio) {
5441 if (hdspm->capture_substream)
5442 snd_pcm_period_elapsed(hdspm->capture_substream);
5443
5444 if (hdspm->playback_substream)
5445 snd_pcm_period_elapsed(hdspm->playback_substream);
5446 }
5447
5448 if (midi) {
5449 i = 0;
5450 while (i < hdspm->midiPorts) {
5451 if ((hdspm_read(hdspm,
5452 hdspm->midi[i].statusIn) & 0xff) &&
5453 (status & hdspm->midi[i].irq)) {
5454 /* we disable interrupts for this input until
5455 * processing is done
5456 */
5457 hdspm->control_register &= ~hdspm->midi[i].ie;
5458 hdspm_write(hdspm, HDSPM_controlRegister,
5459 hdspm->control_register);
5460 hdspm->midi[i].pending = 1;
5461 schedule = 1;
5462 }
5463
5464 i++;
5465 }
5466
5467 if (schedule)
5468 tasklet_hi_schedule(&hdspm->midi_tasklet);
5469 }
5470
5471 return IRQ_HANDLED;
5472 }
5473
5474 /*------------------------------------------------------------
5475 pcm interface
5476 ------------------------------------------------------------*/
5477
5478
5479 static snd_pcm_uframes_t snd_hdspm_hw_pointer(struct snd_pcm_substream
5480 *substream)
5481 {
5482 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5483 return hdspm_hw_pointer(hdspm);
5484 }
5485
5486
5487 static int snd_hdspm_reset(struct snd_pcm_substream *substream)
5488 {
5489 struct snd_pcm_runtime *runtime = substream->runtime;
5490 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5491 struct snd_pcm_substream *other;
5492
5493 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5494 other = hdspm->capture_substream;
5495 else
5496 other = hdspm->playback_substream;
5497
5498 if (hdspm->running)
5499 runtime->status->hw_ptr = hdspm_hw_pointer(hdspm);
5500 else
5501 runtime->status->hw_ptr = 0;
5502 if (other) {
5503 struct snd_pcm_substream *s;
5504 struct snd_pcm_runtime *oruntime = other->runtime;
5505 snd_pcm_group_for_each_entry(s, substream) {
5506 if (s == other) {
5507 oruntime->status->hw_ptr =
5508 runtime->status->hw_ptr;
5509 break;
5510 }
5511 }
5512 }
5513 return 0;
5514 }
5515
5516 static int snd_hdspm_hw_params(struct snd_pcm_substream *substream,
5517 struct snd_pcm_hw_params *params)
5518 {
5519 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5520 int err;
5521 int i;
5522 pid_t this_pid;
5523 pid_t other_pid;
5524
5525 spin_lock_irq(&hdspm->lock);
5526
5527 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5528 this_pid = hdspm->playback_pid;
5529 other_pid = hdspm->capture_pid;
5530 } else {
5531 this_pid = hdspm->capture_pid;
5532 other_pid = hdspm->playback_pid;
5533 }
5534
5535 if (other_pid > 0 && this_pid != other_pid) {
5536
5537 /* The other stream is open, and not by the same
5538 task as this one. Make sure that the parameters
5539 that matter are the same.
5540 */
5541
5542 if (params_rate(params) != hdspm->system_sample_rate) {
5543 spin_unlock_irq(&hdspm->lock);
5544 _snd_pcm_hw_param_setempty(params,
5545 SNDRV_PCM_HW_PARAM_RATE);
5546 return -EBUSY;
5547 }
5548
5549 if (params_period_size(params) != hdspm->period_bytes / 4) {
5550 spin_unlock_irq(&hdspm->lock);
5551 _snd_pcm_hw_param_setempty(params,
5552 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5553 return -EBUSY;
5554 }
5555
5556 }
5557 /* We're fine. */
5558 spin_unlock_irq(&hdspm->lock);
5559
5560 /* how to make sure that the rate matches an externally-set one ? */
5561
5562 spin_lock_irq(&hdspm->lock);
5563 err = hdspm_set_rate(hdspm, params_rate(params), 0);
5564 if (err < 0) {
5565 dev_info(hdspm->card->dev, "err on hdspm_set_rate: %d\n", err);
5566 spin_unlock_irq(&hdspm->lock);
5567 _snd_pcm_hw_param_setempty(params,
5568 SNDRV_PCM_HW_PARAM_RATE);
5569 return err;
5570 }
5571 spin_unlock_irq(&hdspm->lock);
5572
5573 err = hdspm_set_interrupt_interval(hdspm,
5574 params_period_size(params));
5575 if (err < 0) {
5576 dev_info(hdspm->card->dev,
5577 "err on hdspm_set_interrupt_interval: %d\n", err);
5578 _snd_pcm_hw_param_setempty(params,
5579 SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
5580 return err;
5581 }
5582
5583 /* Memory allocation, takashi's method, dont know if we should
5584 * spinlock
5585 */
5586 /* malloc all buffer even if not enabled to get sure */
5587 /* Update for MADI rev 204: we need to allocate for all channels,
5588 * otherwise it doesn't work at 96kHz */
5589
5590 err =
5591 snd_pcm_lib_malloc_pages(substream, HDSPM_DMA_AREA_BYTES);
5592 if (err < 0) {
5593 dev_info(hdspm->card->dev,
5594 "err on snd_pcm_lib_malloc_pages: %d\n", err);
5595 return err;
5596 }
5597
5598 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5599
5600 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferOut,
5601 params_channels(params));
5602
5603 for (i = 0; i < params_channels(params); ++i)
5604 snd_hdspm_enable_out(hdspm, i, 1);
5605
5606 hdspm->playback_buffer =
5607 (unsigned char *) substream->runtime->dma_area;
5608 dev_dbg(hdspm->card->dev,
5609 "Allocated sample buffer for playback at %p\n",
5610 hdspm->playback_buffer);
5611 } else {
5612 hdspm_set_sgbuf(hdspm, substream, HDSPM_pageAddressBufferIn,
5613 params_channels(params));
5614
5615 for (i = 0; i < params_channels(params); ++i)
5616 snd_hdspm_enable_in(hdspm, i, 1);
5617
5618 hdspm->capture_buffer =
5619 (unsigned char *) substream->runtime->dma_area;
5620 dev_dbg(hdspm->card->dev,
5621 "Allocated sample buffer for capture at %p\n",
5622 hdspm->capture_buffer);
5623 }
5624
5625 /*
5626 dev_dbg(hdspm->card->dev,
5627 "Allocated sample buffer for %s at 0x%08X\n",
5628 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5629 "playback" : "capture",
5630 snd_pcm_sgbuf_get_addr(substream, 0));
5631 */
5632 /*
5633 dev_dbg(hdspm->card->dev,
5634 "set_hwparams: %s %d Hz, %d channels, bs = %d\n",
5635 substream->stream == SNDRV_PCM_STREAM_PLAYBACK ?
5636 "playback" : "capture",
5637 params_rate(params), params_channels(params),
5638 params_buffer_size(params));
5639 */
5640
5641
5642 /* For AES cards, the float format bit is the same as the
5643 * preferred sync reference. Since we don't want to break
5644 * sync settings, we have to skip the remaining part of this
5645 * function.
5646 */
5647 if (hdspm->io_type == AES32) {
5648 return 0;
5649 }
5650
5651
5652 /* Switch to native float format if requested */
5653 if (SNDRV_PCM_FORMAT_FLOAT_LE == params_format(params)) {
5654 if (!(hdspm->control_register & HDSPe_FLOAT_FORMAT))
5655 dev_info(hdspm->card->dev,
5656 "Switching to native 32bit LE float format.\n");
5657
5658 hdspm->control_register |= HDSPe_FLOAT_FORMAT;
5659 } else if (SNDRV_PCM_FORMAT_S32_LE == params_format(params)) {
5660 if (hdspm->control_register & HDSPe_FLOAT_FORMAT)
5661 dev_info(hdspm->card->dev,
5662 "Switching to native 32bit LE integer format.\n");
5663
5664 hdspm->control_register &= ~HDSPe_FLOAT_FORMAT;
5665 }
5666 hdspm_write(hdspm, HDSPM_controlRegister, hdspm->control_register);
5667
5668 return 0;
5669 }
5670
5671 static int snd_hdspm_hw_free(struct snd_pcm_substream *substream)
5672 {
5673 int i;
5674 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5675
5676 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5677
5678 /* params_channels(params) should be enough,
5679 but to get sure in case of error */
5680 for (i = 0; i < hdspm->max_channels_out; ++i)
5681 snd_hdspm_enable_out(hdspm, i, 0);
5682
5683 hdspm->playback_buffer = NULL;
5684 } else {
5685 for (i = 0; i < hdspm->max_channels_in; ++i)
5686 snd_hdspm_enable_in(hdspm, i, 0);
5687
5688 hdspm->capture_buffer = NULL;
5689
5690 }
5691
5692 snd_pcm_lib_free_pages(substream);
5693
5694 return 0;
5695 }
5696
5697
5698 static int snd_hdspm_channel_info(struct snd_pcm_substream *substream,
5699 struct snd_pcm_channel_info *info)
5700 {
5701 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5702 unsigned int channel = info->channel;
5703
5704 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5705 if (snd_BUG_ON(channel >= hdspm->max_channels_out)) {
5706 dev_info(hdspm->card->dev,
5707 "snd_hdspm_channel_info: output channel out of range (%d)\n",
5708 channel);
5709 return -EINVAL;
5710 }
5711
5712 channel = array_index_nospec(channel, hdspm->max_channels_out);
5713 if (hdspm->channel_map_out[channel] < 0) {
5714 dev_info(hdspm->card->dev,
5715 "snd_hdspm_channel_info: output channel %d mapped out\n",
5716 channel);
5717 return -EINVAL;
5718 }
5719
5720 info->offset = hdspm->channel_map_out[channel] *
5721 HDSPM_CHANNEL_BUFFER_BYTES;
5722 } else {
5723 if (snd_BUG_ON(channel >= hdspm->max_channels_in)) {
5724 dev_info(hdspm->card->dev,
5725 "snd_hdspm_channel_info: input channel out of range (%d)\n",
5726 channel);
5727 return -EINVAL;
5728 }
5729
5730 channel = array_index_nospec(channel, hdspm->max_channels_in);
5731 if (hdspm->channel_map_in[channel] < 0) {
5732 dev_info(hdspm->card->dev,
5733 "snd_hdspm_channel_info: input channel %d mapped out\n",
5734 channel);
5735 return -EINVAL;
5736 }
5737
5738 info->offset = hdspm->channel_map_in[channel] *
5739 HDSPM_CHANNEL_BUFFER_BYTES;
5740 }
5741
5742 info->first = 0;
5743 info->step = 32;
5744 return 0;
5745 }
5746
5747
5748 static int snd_hdspm_ioctl(struct snd_pcm_substream *substream,
5749 unsigned int cmd, void *arg)
5750 {
5751 switch (cmd) {
5752 case SNDRV_PCM_IOCTL1_RESET:
5753 return snd_hdspm_reset(substream);
5754
5755 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
5756 {
5757 struct snd_pcm_channel_info *info = arg;
5758 return snd_hdspm_channel_info(substream, info);
5759 }
5760 default:
5761 break;
5762 }
5763
5764 return snd_pcm_lib_ioctl(substream, cmd, arg);
5765 }
5766
5767 static int snd_hdspm_trigger(struct snd_pcm_substream *substream, int cmd)
5768 {
5769 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
5770 struct snd_pcm_substream *other;
5771 int running;
5772
5773 spin_lock(&hdspm->lock);
5774 running = hdspm->running;
5775 switch (cmd) {
5776 case SNDRV_PCM_TRIGGER_START:
5777 running |= 1 << substream->stream;
5778 break;
5779 case SNDRV_PCM_TRIGGER_STOP:
5780 running &= ~(1 << substream->stream);
5781 break;
5782 default:
5783 snd_BUG();
5784 spin_unlock(&hdspm->lock);
5785 return -EINVAL;
5786 }
5787 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5788 other = hdspm->capture_substream;
5789 else
5790 other = hdspm->playback_substream;
5791
5792 if (other) {
5793 struct snd_pcm_substream *s;
5794 snd_pcm_group_for_each_entry(s, substream) {
5795 if (s == other) {
5796 snd_pcm_trigger_done(s, substream);
5797 if (cmd == SNDRV_PCM_TRIGGER_START)
5798 running |= 1 << s->stream;
5799 else
5800 running &= ~(1 << s->stream);
5801 goto _ok;
5802 }
5803 }
5804 if (cmd == SNDRV_PCM_TRIGGER_START) {
5805 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK))
5806 && substream->stream ==
5807 SNDRV_PCM_STREAM_CAPTURE)
5808 hdspm_silence_playback(hdspm);
5809 } else {
5810 if (running &&
5811 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
5812 hdspm_silence_playback(hdspm);
5813 }
5814 } else {
5815 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
5816 hdspm_silence_playback(hdspm);
5817 }
5818 _ok:
5819 snd_pcm_trigger_done(substream, substream);
5820 if (!hdspm->running && running)
5821 hdspm_start_audio(hdspm);
5822 else if (hdspm->running && !running)
5823 hdspm_stop_audio(hdspm);
5824 hdspm->running = running;
5825 spin_unlock(&hdspm->lock);
5826
5827 return 0;
5828 }
5829
5830 static int snd_hdspm_prepare(struct snd_pcm_substream *substream)
5831 {
5832 return 0;
5833 }
5834
5835 static struct snd_pcm_hardware snd_hdspm_playback_subinfo = {
5836 .info = (SNDRV_PCM_INFO_MMAP |
5837 SNDRV_PCM_INFO_MMAP_VALID |
5838 SNDRV_PCM_INFO_NONINTERLEAVED |
5839 SNDRV_PCM_INFO_SYNC_START | SNDRV_PCM_INFO_DOUBLE),
5840 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5841 .rates = (SNDRV_PCM_RATE_32000 |
5842 SNDRV_PCM_RATE_44100 |
5843 SNDRV_PCM_RATE_48000 |
5844 SNDRV_PCM_RATE_64000 |
5845 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5846 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000 ),
5847 .rate_min = 32000,
5848 .rate_max = 192000,
5849 .channels_min = 1,
5850 .channels_max = HDSPM_MAX_CHANNELS,
5851 .buffer_bytes_max =
5852 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5853 .period_bytes_min = (32 * 4),
5854 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5855 .periods_min = 2,
5856 .periods_max = 512,
5857 .fifo_size = 0
5858 };
5859
5860 static struct snd_pcm_hardware snd_hdspm_capture_subinfo = {
5861 .info = (SNDRV_PCM_INFO_MMAP |
5862 SNDRV_PCM_INFO_MMAP_VALID |
5863 SNDRV_PCM_INFO_NONINTERLEAVED |
5864 SNDRV_PCM_INFO_SYNC_START),
5865 .formats = SNDRV_PCM_FMTBIT_S32_LE,
5866 .rates = (SNDRV_PCM_RATE_32000 |
5867 SNDRV_PCM_RATE_44100 |
5868 SNDRV_PCM_RATE_48000 |
5869 SNDRV_PCM_RATE_64000 |
5870 SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000 |
5871 SNDRV_PCM_RATE_176400 | SNDRV_PCM_RATE_192000),
5872 .rate_min = 32000,
5873 .rate_max = 192000,
5874 .channels_min = 1,
5875 .channels_max = HDSPM_MAX_CHANNELS,
5876 .buffer_bytes_max =
5877 HDSPM_CHANNEL_BUFFER_BYTES * HDSPM_MAX_CHANNELS,
5878 .period_bytes_min = (32 * 4),
5879 .period_bytes_max = (8192 * 4) * HDSPM_MAX_CHANNELS,
5880 .periods_min = 2,
5881 .periods_max = 512,
5882 .fifo_size = 0
5883 };
5884
5885 static int snd_hdspm_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
5886 struct snd_pcm_hw_rule *rule)
5887 {
5888 struct hdspm *hdspm = rule->private;
5889 struct snd_interval *c =
5890 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5891 struct snd_interval *r =
5892 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5893
5894 if (r->min > 96000 && r->max <= 192000) {
5895 struct snd_interval t = {
5896 .min = hdspm->qs_in_channels,
5897 .max = hdspm->qs_in_channels,
5898 .integer = 1,
5899 };
5900 return snd_interval_refine(c, &t);
5901 } else if (r->min > 48000 && r->max <= 96000) {
5902 struct snd_interval t = {
5903 .min = hdspm->ds_in_channels,
5904 .max = hdspm->ds_in_channels,
5905 .integer = 1,
5906 };
5907 return snd_interval_refine(c, &t);
5908 } else if (r->max < 64000) {
5909 struct snd_interval t = {
5910 .min = hdspm->ss_in_channels,
5911 .max = hdspm->ss_in_channels,
5912 .integer = 1,
5913 };
5914 return snd_interval_refine(c, &t);
5915 }
5916
5917 return 0;
5918 }
5919
5920 static int snd_hdspm_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
5921 struct snd_pcm_hw_rule * rule)
5922 {
5923 struct hdspm *hdspm = rule->private;
5924 struct snd_interval *c =
5925 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5926 struct snd_interval *r =
5927 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5928
5929 if (r->min > 96000 && r->max <= 192000) {
5930 struct snd_interval t = {
5931 .min = hdspm->qs_out_channels,
5932 .max = hdspm->qs_out_channels,
5933 .integer = 1,
5934 };
5935 return snd_interval_refine(c, &t);
5936 } else if (r->min > 48000 && r->max <= 96000) {
5937 struct snd_interval t = {
5938 .min = hdspm->ds_out_channels,
5939 .max = hdspm->ds_out_channels,
5940 .integer = 1,
5941 };
5942 return snd_interval_refine(c, &t);
5943 } else if (r->max < 64000) {
5944 struct snd_interval t = {
5945 .min = hdspm->ss_out_channels,
5946 .max = hdspm->ss_out_channels,
5947 .integer = 1,
5948 };
5949 return snd_interval_refine(c, &t);
5950 } else {
5951 }
5952 return 0;
5953 }
5954
5955 static int snd_hdspm_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
5956 struct snd_pcm_hw_rule * rule)
5957 {
5958 struct hdspm *hdspm = rule->private;
5959 struct snd_interval *c =
5960 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5961 struct snd_interval *r =
5962 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5963
5964 if (c->min >= hdspm->ss_in_channels) {
5965 struct snd_interval t = {
5966 .min = 32000,
5967 .max = 48000,
5968 .integer = 1,
5969 };
5970 return snd_interval_refine(r, &t);
5971 } else if (c->max <= hdspm->qs_in_channels) {
5972 struct snd_interval t = {
5973 .min = 128000,
5974 .max = 192000,
5975 .integer = 1,
5976 };
5977 return snd_interval_refine(r, &t);
5978 } else if (c->max <= hdspm->ds_in_channels) {
5979 struct snd_interval t = {
5980 .min = 64000,
5981 .max = 96000,
5982 .integer = 1,
5983 };
5984 return snd_interval_refine(r, &t);
5985 }
5986
5987 return 0;
5988 }
5989 static int snd_hdspm_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
5990 struct snd_pcm_hw_rule *rule)
5991 {
5992 struct hdspm *hdspm = rule->private;
5993 struct snd_interval *c =
5994 hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
5995 struct snd_interval *r =
5996 hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
5997
5998 if (c->min >= hdspm->ss_out_channels) {
5999 struct snd_interval t = {
6000 .min = 32000,
6001 .max = 48000,
6002 .integer = 1,
6003 };
6004 return snd_interval_refine(r, &t);
6005 } else if (c->max <= hdspm->qs_out_channels) {
6006 struct snd_interval t = {
6007 .min = 128000,
6008 .max = 192000,
6009 .integer = 1,
6010 };
6011 return snd_interval_refine(r, &t);
6012 } else if (c->max <= hdspm->ds_out_channels) {
6013 struct snd_interval t = {
6014 .min = 64000,
6015 .max = 96000,
6016 .integer = 1,
6017 };
6018 return snd_interval_refine(r, &t);
6019 }
6020
6021 return 0;
6022 }
6023
6024 static int snd_hdspm_hw_rule_in_channels(struct snd_pcm_hw_params *params,
6025 struct snd_pcm_hw_rule *rule)
6026 {
6027 unsigned int list[3];
6028 struct hdspm *hdspm = rule->private;
6029 struct snd_interval *c = hw_param_interval(params,
6030 SNDRV_PCM_HW_PARAM_CHANNELS);
6031
6032 list[0] = hdspm->qs_in_channels;
6033 list[1] = hdspm->ds_in_channels;
6034 list[2] = hdspm->ss_in_channels;
6035 return snd_interval_list(c, 3, list, 0);
6036 }
6037
6038 static int snd_hdspm_hw_rule_out_channels(struct snd_pcm_hw_params *params,
6039 struct snd_pcm_hw_rule *rule)
6040 {
6041 unsigned int list[3];
6042 struct hdspm *hdspm = rule->private;
6043 struct snd_interval *c = hw_param_interval(params,
6044 SNDRV_PCM_HW_PARAM_CHANNELS);
6045
6046 list[0] = hdspm->qs_out_channels;
6047 list[1] = hdspm->ds_out_channels;
6048 list[2] = hdspm->ss_out_channels;
6049 return snd_interval_list(c, 3, list, 0);
6050 }
6051
6052
6053 static const unsigned int hdspm_aes32_sample_rates[] = {
6054 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000
6055 };
6056
6057 static const struct snd_pcm_hw_constraint_list
6058 hdspm_hw_constraints_aes32_sample_rates = {
6059 .count = ARRAY_SIZE(hdspm_aes32_sample_rates),
6060 .list = hdspm_aes32_sample_rates,
6061 .mask = 0
6062 };
6063
6064 static int snd_hdspm_open(struct snd_pcm_substream *substream)
6065 {
6066 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6067 struct snd_pcm_runtime *runtime = substream->runtime;
6068 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6069
6070 spin_lock_irq(&hdspm->lock);
6071 snd_pcm_set_sync(substream);
6072 runtime->hw = (playback) ? snd_hdspm_playback_subinfo :
6073 snd_hdspm_capture_subinfo;
6074
6075 if (playback) {
6076 if (!hdspm->capture_substream)
6077 hdspm_stop_audio(hdspm);
6078
6079 hdspm->playback_pid = current->pid;
6080 hdspm->playback_substream = substream;
6081 } else {
6082 if (!hdspm->playback_substream)
6083 hdspm_stop_audio(hdspm);
6084
6085 hdspm->capture_pid = current->pid;
6086 hdspm->capture_substream = substream;
6087 }
6088
6089 spin_unlock_irq(&hdspm->lock);
6090
6091 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
6092 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
6093
6094 switch (hdspm->io_type) {
6095 case AIO:
6096 case RayDAT:
6097 snd_pcm_hw_constraint_minmax(runtime,
6098 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6099 32, 4096);
6100 /* RayDAT & AIO have a fixed buffer of 16384 samples per channel */
6101 snd_pcm_hw_constraint_single(runtime,
6102 SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
6103 16384);
6104 break;
6105
6106 default:
6107 snd_pcm_hw_constraint_minmax(runtime,
6108 SNDRV_PCM_HW_PARAM_PERIOD_SIZE,
6109 64, 8192);
6110 snd_pcm_hw_constraint_single(runtime,
6111 SNDRV_PCM_HW_PARAM_PERIODS, 2);
6112 break;
6113 }
6114
6115 if (AES32 == hdspm->io_type) {
6116 runtime->hw.rates |= SNDRV_PCM_RATE_KNOT;
6117 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6118 &hdspm_hw_constraints_aes32_sample_rates);
6119 } else {
6120 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
6121 (playback ?
6122 snd_hdspm_hw_rule_rate_out_channels :
6123 snd_hdspm_hw_rule_rate_in_channels), hdspm,
6124 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6125 }
6126
6127 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6128 (playback ? snd_hdspm_hw_rule_out_channels :
6129 snd_hdspm_hw_rule_in_channels), hdspm,
6130 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
6131
6132 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
6133 (playback ? snd_hdspm_hw_rule_out_channels_rate :
6134 snd_hdspm_hw_rule_in_channels_rate), hdspm,
6135 SNDRV_PCM_HW_PARAM_RATE, -1);
6136
6137 return 0;
6138 }
6139
6140 static int snd_hdspm_release(struct snd_pcm_substream *substream)
6141 {
6142 struct hdspm *hdspm = snd_pcm_substream_chip(substream);
6143 bool playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
6144
6145 spin_lock_irq(&hdspm->lock);
6146
6147 if (playback) {
6148 hdspm->playback_pid = -1;
6149 hdspm->playback_substream = NULL;
6150 } else {
6151 hdspm->capture_pid = -1;
6152 hdspm->capture_substream = NULL;
6153 }
6154
6155 spin_unlock_irq(&hdspm->lock);
6156
6157 return 0;
6158 }
6159
6160 static int snd_hdspm_hwdep_dummy_op(struct snd_hwdep *hw, struct file *file)
6161 {
6162 /* we have nothing to initialize but the call is required */
6163 return 0;
6164 }
6165
6166 static inline int copy_u32_le(void __user *dest, void __iomem *src)
6167 {
6168 u32 val = readl(src);
6169 return copy_to_user(dest, &val, 4);
6170 }
6171
6172 static int snd_hdspm_hwdep_ioctl(struct snd_hwdep *hw, struct file *file,
6173 unsigned int cmd, unsigned long arg)
6174 {
6175 void __user *argp = (void __user *)arg;
6176 struct hdspm *hdspm = hw->private_data;
6177 struct hdspm_mixer_ioctl mixer;
6178 struct hdspm_config info;
6179 struct hdspm_status status;
6180 struct hdspm_version hdspm_version;
6181 struct hdspm_peak_rms *levels;
6182 struct hdspm_ltc ltc;
6183 unsigned int statusregister;
6184 long unsigned int s;
6185 int i = 0;
6186
6187 switch (cmd) {
6188
6189 case SNDRV_HDSPM_IOCTL_GET_PEAK_RMS:
6190 levels = &hdspm->peak_rms;
6191 for (i = 0; i < HDSPM_MAX_CHANNELS; i++) {
6192 levels->input_peaks[i] =
6193 readl(hdspm->iobase +
6194 HDSPM_MADI_INPUT_PEAK + i*4);
6195 levels->playback_peaks[i] =
6196 readl(hdspm->iobase +
6197 HDSPM_MADI_PLAYBACK_PEAK + i*4);
6198 levels->output_peaks[i] =
6199 readl(hdspm->iobase +
6200 HDSPM_MADI_OUTPUT_PEAK + i*4);
6201
6202 levels->input_rms[i] =
6203 ((uint64_t) readl(hdspm->iobase +
6204 HDSPM_MADI_INPUT_RMS_H + i*4) << 32) |
6205 (uint64_t) readl(hdspm->iobase +
6206 HDSPM_MADI_INPUT_RMS_L + i*4);
6207 levels->playback_rms[i] =
6208 ((uint64_t)readl(hdspm->iobase +
6209 HDSPM_MADI_PLAYBACK_RMS_H+i*4) << 32) |
6210 (uint64_t)readl(hdspm->iobase +
6211 HDSPM_MADI_PLAYBACK_RMS_L + i*4);
6212 levels->output_rms[i] =
6213 ((uint64_t)readl(hdspm->iobase +
6214 HDSPM_MADI_OUTPUT_RMS_H + i*4) << 32) |
6215 (uint64_t)readl(hdspm->iobase +
6216 HDSPM_MADI_OUTPUT_RMS_L + i*4);
6217 }
6218
6219 if (hdspm->system_sample_rate > 96000) {
6220 levels->speed = qs;
6221 } else if (hdspm->system_sample_rate > 48000) {
6222 levels->speed = ds;
6223 } else {
6224 levels->speed = ss;
6225 }
6226 levels->status2 = hdspm_read(hdspm, HDSPM_statusRegister2);
6227
6228 s = copy_to_user(argp, levels, sizeof(*levels));
6229 if (0 != s) {
6230 /* dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu
6231 [Levels]\n", sizeof(struct hdspm_peak_rms), s);
6232 */
6233 return -EFAULT;
6234 }
6235 break;
6236
6237 case SNDRV_HDSPM_IOCTL_GET_LTC:
6238 ltc.ltc = hdspm_read(hdspm, HDSPM_RD_TCO);
6239 i = hdspm_read(hdspm, HDSPM_RD_TCO + 4);
6240 if (i & HDSPM_TCO1_LTC_Input_valid) {
6241 switch (i & (HDSPM_TCO1_LTC_Format_LSB |
6242 HDSPM_TCO1_LTC_Format_MSB)) {
6243 case 0:
6244 ltc.format = fps_24;
6245 break;
6246 case HDSPM_TCO1_LTC_Format_LSB:
6247 ltc.format = fps_25;
6248 break;
6249 case HDSPM_TCO1_LTC_Format_MSB:
6250 ltc.format = fps_2997;
6251 break;
6252 default:
6253 ltc.format = fps_30;
6254 break;
6255 }
6256 if (i & HDSPM_TCO1_set_drop_frame_flag) {
6257 ltc.frame = drop_frame;
6258 } else {
6259 ltc.frame = full_frame;
6260 }
6261 } else {
6262 ltc.format = format_invalid;
6263 ltc.frame = frame_invalid;
6264 }
6265 if (i & HDSPM_TCO1_Video_Input_Format_NTSC) {
6266 ltc.input_format = ntsc;
6267 } else if (i & HDSPM_TCO1_Video_Input_Format_PAL) {
6268 ltc.input_format = pal;
6269 } else {
6270 ltc.input_format = no_video;
6271 }
6272
6273 s = copy_to_user(argp, &ltc, sizeof(ltc));
6274 if (0 != s) {
6275 /*
6276 dev_err(hdspm->card->dev, "copy_to_user(.., .., %lu): %lu [LTC]\n", sizeof(struct hdspm_ltc), s); */
6277 return -EFAULT;
6278 }
6279
6280 break;
6281
6282 case SNDRV_HDSPM_IOCTL_GET_CONFIG:
6283
6284 memset(&info, 0, sizeof(info));
6285 spin_lock_irq(&hdspm->lock);
6286 info.pref_sync_ref = hdspm_pref_sync_ref(hdspm);
6287 info.wordclock_sync_check = hdspm_wc_sync_check(hdspm);
6288
6289 info.system_sample_rate = hdspm->system_sample_rate;
6290 info.autosync_sample_rate =
6291 hdspm_external_sample_rate(hdspm);
6292 info.system_clock_mode = hdspm_system_clock_mode(hdspm);
6293 info.clock_source = hdspm_clock_source(hdspm);
6294 info.autosync_ref = hdspm_autosync_ref(hdspm);
6295 info.line_out = hdspm_toggle_setting(hdspm, HDSPM_LineOut);
6296 info.passthru = 0;
6297 spin_unlock_irq(&hdspm->lock);
6298 if (copy_to_user(argp, &info, sizeof(info)))
6299 return -EFAULT;
6300 break;
6301
6302 case SNDRV_HDSPM_IOCTL_GET_STATUS:
6303 memset(&status, 0, sizeof(status));
6304
6305 status.card_type = hdspm->io_type;
6306
6307 status.autosync_source = hdspm_autosync_ref(hdspm);
6308
6309 status.card_clock = 110069313433624ULL;
6310 status.master_period = hdspm_read(hdspm, HDSPM_RD_PLL_FREQ);
6311
6312 switch (hdspm->io_type) {
6313 case MADI:
6314 case MADIface:
6315 status.card_specific.madi.sync_wc =
6316 hdspm_wc_sync_check(hdspm);
6317 status.card_specific.madi.sync_madi =
6318 hdspm_madi_sync_check(hdspm);
6319 status.card_specific.madi.sync_tco =
6320 hdspm_tco_sync_check(hdspm);
6321 status.card_specific.madi.sync_in =
6322 hdspm_sync_in_sync_check(hdspm);
6323
6324 statusregister =
6325 hdspm_read(hdspm, HDSPM_statusRegister);
6326 status.card_specific.madi.madi_input =
6327 (statusregister & HDSPM_AB_int) ? 1 : 0;
6328 status.card_specific.madi.channel_format =
6329 (statusregister & HDSPM_RX_64ch) ? 1 : 0;
6330 /* TODO: Mac driver sets it when f_s>48kHz */
6331 status.card_specific.madi.frame_format = 0;
6332
6333 default:
6334 break;
6335 }
6336
6337 if (copy_to_user(argp, &status, sizeof(status)))
6338 return -EFAULT;
6339
6340
6341 break;
6342
6343 case SNDRV_HDSPM_IOCTL_GET_VERSION:
6344 memset(&hdspm_version, 0, sizeof(hdspm_version));
6345
6346 hdspm_version.card_type = hdspm->io_type;
6347 strlcpy(hdspm_version.cardname, hdspm->card_name,
6348 sizeof(hdspm_version.cardname));
6349 hdspm_version.serial = hdspm->serial;
6350 hdspm_version.firmware_rev = hdspm->firmware_rev;
6351 hdspm_version.addons = 0;
6352 if (hdspm->tco)
6353 hdspm_version.addons |= HDSPM_ADDON_TCO;
6354
6355 if (copy_to_user(argp, &hdspm_version,
6356 sizeof(hdspm_version)))
6357 return -EFAULT;
6358 break;
6359
6360 case SNDRV_HDSPM_IOCTL_GET_MIXER:
6361 if (copy_from_user(&mixer, argp, sizeof(mixer)))
6362 return -EFAULT;
6363 if (copy_to_user((void __user *)mixer.mixer, hdspm->mixer,
6364 sizeof(*mixer.mixer)))
6365 return -EFAULT;
6366 break;
6367
6368 default:
6369 return -EINVAL;
6370 }
6371 return 0;
6372 }
6373
6374 static const struct snd_pcm_ops snd_hdspm_ops = {
6375 .open = snd_hdspm_open,
6376 .close = snd_hdspm_release,
6377 .ioctl = snd_hdspm_ioctl,
6378 .hw_params = snd_hdspm_hw_params,
6379 .hw_free = snd_hdspm_hw_free,
6380 .prepare = snd_hdspm_prepare,
6381 .trigger = snd_hdspm_trigger,
6382 .pointer = snd_hdspm_hw_pointer,
6383 .page = snd_pcm_sgbuf_ops_page,
6384 };
6385
6386 static int snd_hdspm_create_hwdep(struct snd_card *card,
6387 struct hdspm *hdspm)
6388 {
6389 struct snd_hwdep *hw;
6390 int err;
6391
6392 err = snd_hwdep_new(card, "HDSPM hwdep", 0, &hw);
6393 if (err < 0)
6394 return err;
6395
6396 hdspm->hwdep = hw;
6397 hw->private_data = hdspm;
6398 strcpy(hw->name, "HDSPM hwdep interface");
6399
6400 hw->ops.open = snd_hdspm_hwdep_dummy_op;
6401 hw->ops.ioctl = snd_hdspm_hwdep_ioctl;
6402 hw->ops.ioctl_compat = snd_hdspm_hwdep_ioctl;
6403 hw->ops.release = snd_hdspm_hwdep_dummy_op;
6404
6405 return 0;
6406 }
6407
6408
6409 /*------------------------------------------------------------
6410 memory interface
6411 ------------------------------------------------------------*/
6412 static int snd_hdspm_preallocate_memory(struct hdspm *hdspm)
6413 {
6414 int err;
6415 struct snd_pcm *pcm;
6416 size_t wanted;
6417
6418 pcm = hdspm->pcm;
6419
6420 wanted = HDSPM_DMA_AREA_BYTES;
6421
6422 err =
6423 snd_pcm_lib_preallocate_pages_for_all(pcm,
6424 SNDRV_DMA_TYPE_DEV_SG,
6425 snd_dma_pci_data(hdspm->pci),
6426 wanted,
6427 wanted);
6428 if (err < 0) {
6429 dev_dbg(hdspm->card->dev,
6430 "Could not preallocate %zd Bytes\n", wanted);
6431
6432 return err;
6433 } else
6434 dev_dbg(hdspm->card->dev,
6435 " Preallocated %zd Bytes\n", wanted);
6436
6437 return 0;
6438 }
6439
6440
6441 static void hdspm_set_sgbuf(struct hdspm *hdspm,
6442 struct snd_pcm_substream *substream,
6443 unsigned int reg, int channels)
6444 {
6445 int i;
6446
6447 /* continuous memory segment */
6448 for (i = 0; i < (channels * 16); i++)
6449 hdspm_write(hdspm, reg + 4 * i,
6450 snd_pcm_sgbuf_get_addr(substream, 4096 * i));
6451 }
6452
6453
6454 /* ------------- ALSA Devices ---------------------------- */
6455 static int snd_hdspm_create_pcm(struct snd_card *card,
6456 struct hdspm *hdspm)
6457 {
6458 struct snd_pcm *pcm;
6459 int err;
6460
6461 err = snd_pcm_new(card, hdspm->card_name, 0, 1, 1, &pcm);
6462 if (err < 0)
6463 return err;
6464
6465 hdspm->pcm = pcm;
6466 pcm->private_data = hdspm;
6467 strcpy(pcm->name, hdspm->card_name);
6468
6469 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK,
6470 &snd_hdspm_ops);
6471 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE,
6472 &snd_hdspm_ops);
6473
6474 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
6475
6476 err = snd_hdspm_preallocate_memory(hdspm);
6477 if (err < 0)
6478 return err;
6479
6480 return 0;
6481 }
6482
6483 static inline void snd_hdspm_initialize_midi_flush(struct hdspm * hdspm)
6484 {
6485 int i;
6486
6487 for (i = 0; i < hdspm->midiPorts; i++)
6488 snd_hdspm_flush_midi_input(hdspm, i);
6489 }
6490
6491 static int snd_hdspm_create_alsa_devices(struct snd_card *card,
6492 struct hdspm *hdspm)
6493 {
6494 int err, i;
6495
6496 dev_dbg(card->dev, "Create card...\n");
6497 err = snd_hdspm_create_pcm(card, hdspm);
6498 if (err < 0)
6499 return err;
6500
6501 i = 0;
6502 while (i < hdspm->midiPorts) {
6503 err = snd_hdspm_create_midi(card, hdspm, i);
6504 if (err < 0) {
6505 return err;
6506 }
6507 i++;
6508 }
6509
6510 err = snd_hdspm_create_controls(card, hdspm);
6511 if (err < 0)
6512 return err;
6513
6514 err = snd_hdspm_create_hwdep(card, hdspm);
6515 if (err < 0)
6516 return err;
6517
6518 dev_dbg(card->dev, "proc init...\n");
6519 snd_hdspm_proc_init(hdspm);
6520
6521 hdspm->system_sample_rate = -1;
6522 hdspm->last_external_sample_rate = -1;
6523 hdspm->last_internal_sample_rate = -1;
6524 hdspm->playback_pid = -1;
6525 hdspm->capture_pid = -1;
6526 hdspm->capture_substream = NULL;
6527 hdspm->playback_substream = NULL;
6528
6529 dev_dbg(card->dev, "Set defaults...\n");
6530 err = snd_hdspm_set_defaults(hdspm);
6531 if (err < 0)
6532 return err;
6533
6534 dev_dbg(card->dev, "Update mixer controls...\n");
6535 hdspm_update_simple_mixer_controls(hdspm);
6536
6537 dev_dbg(card->dev, "Initializeing complete ???\n");
6538
6539 err = snd_card_register(card);
6540 if (err < 0) {
6541 dev_err(card->dev, "error registering card\n");
6542 return err;
6543 }
6544
6545 dev_dbg(card->dev, "... yes now\n");
6546
6547 return 0;
6548 }
6549
6550 static int snd_hdspm_create(struct snd_card *card,
6551 struct hdspm *hdspm)
6552 {
6553
6554 struct pci_dev *pci = hdspm->pci;
6555 int err;
6556 unsigned long io_extent;
6557
6558 hdspm->irq = -1;
6559 hdspm->card = card;
6560
6561 spin_lock_init(&hdspm->lock);
6562
6563 pci_read_config_word(hdspm->pci,
6564 PCI_CLASS_REVISION, &hdspm->firmware_rev);
6565
6566 strcpy(card->mixername, "Xilinx FPGA");
6567 strcpy(card->driver, "HDSPM");
6568
6569 switch (hdspm->firmware_rev) {
6570 case HDSPM_RAYDAT_REV:
6571 hdspm->io_type = RayDAT;
6572 hdspm->card_name = "RME RayDAT";
6573 hdspm->midiPorts = 2;
6574 break;
6575 case HDSPM_AIO_REV:
6576 hdspm->io_type = AIO;
6577 hdspm->card_name = "RME AIO";
6578 hdspm->midiPorts = 1;
6579 break;
6580 case HDSPM_MADIFACE_REV:
6581 hdspm->io_type = MADIface;
6582 hdspm->card_name = "RME MADIface";
6583 hdspm->midiPorts = 1;
6584 break;
6585 default:
6586 if ((hdspm->firmware_rev == 0xf0) ||
6587 ((hdspm->firmware_rev >= 0xe6) &&
6588 (hdspm->firmware_rev <= 0xea))) {
6589 hdspm->io_type = AES32;
6590 hdspm->card_name = "RME AES32";
6591 hdspm->midiPorts = 2;
6592 } else if ((hdspm->firmware_rev == 0xd2) ||
6593 ((hdspm->firmware_rev >= 0xc8) &&
6594 (hdspm->firmware_rev <= 0xcf))) {
6595 hdspm->io_type = MADI;
6596 hdspm->card_name = "RME MADI";
6597 hdspm->midiPorts = 3;
6598 } else {
6599 dev_err(card->dev,
6600 "unknown firmware revision %x\n",
6601 hdspm->firmware_rev);
6602 return -ENODEV;
6603 }
6604 }
6605
6606 err = pci_enable_device(pci);
6607 if (err < 0)
6608 return err;
6609
6610 pci_set_master(hdspm->pci);
6611
6612 err = pci_request_regions(pci, "hdspm");
6613 if (err < 0)
6614 return err;
6615
6616 hdspm->port = pci_resource_start(pci, 0);
6617 io_extent = pci_resource_len(pci, 0);
6618
6619 dev_dbg(card->dev, "grabbed memory region 0x%lx-0x%lx\n",
6620 hdspm->port, hdspm->port + io_extent - 1);
6621
6622 hdspm->iobase = ioremap_nocache(hdspm->port, io_extent);
6623 if (!hdspm->iobase) {
6624 dev_err(card->dev, "unable to remap region 0x%lx-0x%lx\n",
6625 hdspm->port, hdspm->port + io_extent - 1);
6626 return -EBUSY;
6627 }
6628 dev_dbg(card->dev, "remapped region (0x%lx) 0x%lx-0x%lx\n",
6629 (unsigned long)hdspm->iobase, hdspm->port,
6630 hdspm->port + io_extent - 1);
6631
6632 if (request_irq(pci->irq, snd_hdspm_interrupt,
6633 IRQF_SHARED, KBUILD_MODNAME, hdspm)) {
6634 dev_err(card->dev, "unable to use IRQ %d\n", pci->irq);
6635 return -EBUSY;
6636 }
6637
6638 dev_dbg(card->dev, "use IRQ %d\n", pci->irq);
6639
6640 hdspm->irq = pci->irq;
6641
6642 dev_dbg(card->dev, "kmalloc Mixer memory of %zd Bytes\n",
6643 sizeof(*hdspm->mixer));
6644 hdspm->mixer = kzalloc(sizeof(*hdspm->mixer), GFP_KERNEL);
6645 if (!hdspm->mixer)
6646 return -ENOMEM;
6647
6648 hdspm->port_names_in = NULL;
6649 hdspm->port_names_out = NULL;
6650
6651 switch (hdspm->io_type) {
6652 case AES32:
6653 hdspm->ss_in_channels = hdspm->ss_out_channels = AES32_CHANNELS;
6654 hdspm->ds_in_channels = hdspm->ds_out_channels = AES32_CHANNELS;
6655 hdspm->qs_in_channels = hdspm->qs_out_channels = AES32_CHANNELS;
6656
6657 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6658 channel_map_aes32;
6659 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6660 channel_map_aes32;
6661 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6662 channel_map_aes32;
6663 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6664 texts_ports_aes32;
6665 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6666 texts_ports_aes32;
6667 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6668 texts_ports_aes32;
6669
6670 hdspm->max_channels_out = hdspm->max_channels_in =
6671 AES32_CHANNELS;
6672 hdspm->port_names_in = hdspm->port_names_out =
6673 texts_ports_aes32;
6674 hdspm->channel_map_in = hdspm->channel_map_out =
6675 channel_map_aes32;
6676
6677 break;
6678
6679 case MADI:
6680 case MADIface:
6681 hdspm->ss_in_channels = hdspm->ss_out_channels =
6682 MADI_SS_CHANNELS;
6683 hdspm->ds_in_channels = hdspm->ds_out_channels =
6684 MADI_DS_CHANNELS;
6685 hdspm->qs_in_channels = hdspm->qs_out_channels =
6686 MADI_QS_CHANNELS;
6687
6688 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6689 channel_map_unity_ss;
6690 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6691 channel_map_unity_ss;
6692 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6693 channel_map_unity_ss;
6694
6695 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6696 texts_ports_madi;
6697 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6698 texts_ports_madi;
6699 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6700 texts_ports_madi;
6701 break;
6702
6703 case AIO:
6704 hdspm->ss_in_channels = AIO_IN_SS_CHANNELS;
6705 hdspm->ds_in_channels = AIO_IN_DS_CHANNELS;
6706 hdspm->qs_in_channels = AIO_IN_QS_CHANNELS;
6707 hdspm->ss_out_channels = AIO_OUT_SS_CHANNELS;
6708 hdspm->ds_out_channels = AIO_OUT_DS_CHANNELS;
6709 hdspm->qs_out_channels = AIO_OUT_QS_CHANNELS;
6710
6711 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBI_D)) {
6712 dev_info(card->dev, "AEB input board found\n");
6713 hdspm->ss_in_channels += 4;
6714 hdspm->ds_in_channels += 4;
6715 hdspm->qs_in_channels += 4;
6716 }
6717
6718 if (0 == (hdspm_read(hdspm, HDSPM_statusRegister2) & HDSPM_s2_AEBO_D)) {
6719 dev_info(card->dev, "AEB output board found\n");
6720 hdspm->ss_out_channels += 4;
6721 hdspm->ds_out_channels += 4;
6722 hdspm->qs_out_channels += 4;
6723 }
6724
6725 hdspm->channel_map_out_ss = channel_map_aio_out_ss;
6726 hdspm->channel_map_out_ds = channel_map_aio_out_ds;
6727 hdspm->channel_map_out_qs = channel_map_aio_out_qs;
6728
6729 hdspm->channel_map_in_ss = channel_map_aio_in_ss;
6730 hdspm->channel_map_in_ds = channel_map_aio_in_ds;
6731 hdspm->channel_map_in_qs = channel_map_aio_in_qs;
6732
6733 hdspm->port_names_in_ss = texts_ports_aio_in_ss;
6734 hdspm->port_names_out_ss = texts_ports_aio_out_ss;
6735 hdspm->port_names_in_ds = texts_ports_aio_in_ds;
6736 hdspm->port_names_out_ds = texts_ports_aio_out_ds;
6737 hdspm->port_names_in_qs = texts_ports_aio_in_qs;
6738 hdspm->port_names_out_qs = texts_ports_aio_out_qs;
6739
6740 break;
6741
6742 case RayDAT:
6743 hdspm->ss_in_channels = hdspm->ss_out_channels =
6744 RAYDAT_SS_CHANNELS;
6745 hdspm->ds_in_channels = hdspm->ds_out_channels =
6746 RAYDAT_DS_CHANNELS;
6747 hdspm->qs_in_channels = hdspm->qs_out_channels =
6748 RAYDAT_QS_CHANNELS;
6749
6750 hdspm->max_channels_in = RAYDAT_SS_CHANNELS;
6751 hdspm->max_channels_out = RAYDAT_SS_CHANNELS;
6752
6753 hdspm->channel_map_in_ss = hdspm->channel_map_out_ss =
6754 channel_map_raydat_ss;
6755 hdspm->channel_map_in_ds = hdspm->channel_map_out_ds =
6756 channel_map_raydat_ds;
6757 hdspm->channel_map_in_qs = hdspm->channel_map_out_qs =
6758 channel_map_raydat_qs;
6759 hdspm->channel_map_in = hdspm->channel_map_out =
6760 channel_map_raydat_ss;
6761
6762 hdspm->port_names_in_ss = hdspm->port_names_out_ss =
6763 texts_ports_raydat_ss;
6764 hdspm->port_names_in_ds = hdspm->port_names_out_ds =
6765 texts_ports_raydat_ds;
6766 hdspm->port_names_in_qs = hdspm->port_names_out_qs =
6767 texts_ports_raydat_qs;
6768
6769
6770 break;
6771
6772 }
6773
6774 /* TCO detection */
6775 switch (hdspm->io_type) {
6776 case AIO:
6777 case RayDAT:
6778 if (hdspm_read(hdspm, HDSPM_statusRegister2) &
6779 HDSPM_s2_tco_detect) {
6780 hdspm->midiPorts++;
6781 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6782 if (hdspm->tco)
6783 hdspm_tco_write(hdspm);
6784
6785 dev_info(card->dev, "AIO/RayDAT TCO module found\n");
6786 } else {
6787 hdspm->tco = NULL;
6788 }
6789 break;
6790
6791 case MADI:
6792 case AES32:
6793 if (hdspm_read(hdspm, HDSPM_statusRegister) & HDSPM_tco_detect) {
6794 hdspm->midiPorts++;
6795 hdspm->tco = kzalloc(sizeof(*hdspm->tco), GFP_KERNEL);
6796 if (hdspm->tco)
6797 hdspm_tco_write(hdspm);
6798
6799 dev_info(card->dev, "MADI/AES TCO module found\n");
6800 } else {
6801 hdspm->tco = NULL;
6802 }
6803 break;
6804
6805 default:
6806 hdspm->tco = NULL;
6807 }
6808
6809 /* texts */
6810 switch (hdspm->io_type) {
6811 case AES32:
6812 if (hdspm->tco) {
6813 hdspm->texts_autosync = texts_autosync_aes_tco;
6814 hdspm->texts_autosync_items =
6815 ARRAY_SIZE(texts_autosync_aes_tco);
6816 } else {
6817 hdspm->texts_autosync = texts_autosync_aes;
6818 hdspm->texts_autosync_items =
6819 ARRAY_SIZE(texts_autosync_aes);
6820 }
6821 break;
6822
6823 case MADI:
6824 if (hdspm->tco) {
6825 hdspm->texts_autosync = texts_autosync_madi_tco;
6826 hdspm->texts_autosync_items = 4;
6827 } else {
6828 hdspm->texts_autosync = texts_autosync_madi;
6829 hdspm->texts_autosync_items = 3;
6830 }
6831 break;
6832
6833 case MADIface:
6834
6835 break;
6836
6837 case RayDAT:
6838 if (hdspm->tco) {
6839 hdspm->texts_autosync = texts_autosync_raydat_tco;
6840 hdspm->texts_autosync_items = 9;
6841 } else {
6842 hdspm->texts_autosync = texts_autosync_raydat;
6843 hdspm->texts_autosync_items = 8;
6844 }
6845 break;
6846
6847 case AIO:
6848 if (hdspm->tco) {
6849 hdspm->texts_autosync = texts_autosync_aio_tco;
6850 hdspm->texts_autosync_items = 6;
6851 } else {
6852 hdspm->texts_autosync = texts_autosync_aio;
6853 hdspm->texts_autosync_items = 5;
6854 }
6855 break;
6856
6857 }
6858
6859 tasklet_init(&hdspm->midi_tasklet,
6860 hdspm_midi_tasklet, (unsigned long) hdspm);
6861
6862
6863 if (hdspm->io_type != MADIface) {
6864 hdspm->serial = (hdspm_read(hdspm,
6865 HDSPM_midiStatusIn0)>>8) & 0xFFFFFF;
6866 /* id contains either a user-provided value or the default
6867 * NULL. If it's the default, we're safe to
6868 * fill card->id with the serial number.
6869 *
6870 * If the serial number is 0xFFFFFF, then we're dealing with
6871 * an old PCI revision that comes without a sane number. In
6872 * this case, we don't set card->id to avoid collisions
6873 * when running with multiple cards.
6874 */
6875 if (!id[hdspm->dev] && hdspm->serial != 0xFFFFFF) {
6876 snprintf(card->id, sizeof(card->id),
6877 "HDSPMx%06x", hdspm->serial);
6878 snd_card_set_id(card, card->id);
6879 }
6880 }
6881
6882 dev_dbg(card->dev, "create alsa devices.\n");
6883 err = snd_hdspm_create_alsa_devices(card, hdspm);
6884 if (err < 0)
6885 return err;
6886
6887 snd_hdspm_initialize_midi_flush(hdspm);
6888
6889 return 0;
6890 }
6891
6892
6893 static int snd_hdspm_free(struct hdspm * hdspm)
6894 {
6895
6896 if (hdspm->port) {
6897
6898 /* stop th audio, and cancel all interrupts */
6899 hdspm->control_register &=
6900 ~(HDSPM_Start | HDSPM_AudioInterruptEnable |
6901 HDSPM_Midi0InterruptEnable | HDSPM_Midi1InterruptEnable |
6902 HDSPM_Midi2InterruptEnable | HDSPM_Midi3InterruptEnable);
6903 hdspm_write(hdspm, HDSPM_controlRegister,
6904 hdspm->control_register);
6905 }
6906
6907 if (hdspm->irq >= 0)
6908 free_irq(hdspm->irq, (void *) hdspm);
6909
6910 kfree(hdspm->mixer);
6911 iounmap(hdspm->iobase);
6912
6913 if (hdspm->port)
6914 pci_release_regions(hdspm->pci);
6915
6916 pci_disable_device(hdspm->pci);
6917 return 0;
6918 }
6919
6920
6921 static void snd_hdspm_card_free(struct snd_card *card)
6922 {
6923 struct hdspm *hdspm = card->private_data;
6924
6925 if (hdspm)
6926 snd_hdspm_free(hdspm);
6927 }
6928
6929
6930 static int snd_hdspm_probe(struct pci_dev *pci,
6931 const struct pci_device_id *pci_id)
6932 {
6933 static int dev;
6934 struct hdspm *hdspm;
6935 struct snd_card *card;
6936 int err;
6937
6938 if (dev >= SNDRV_CARDS)
6939 return -ENODEV;
6940 if (!enable[dev]) {
6941 dev++;
6942 return -ENOENT;
6943 }
6944
6945 err = snd_card_new(&pci->dev, index[dev], id[dev],
6946 THIS_MODULE, sizeof(*hdspm), &card);
6947 if (err < 0)
6948 return err;
6949
6950 hdspm = card->private_data;
6951 card->private_free = snd_hdspm_card_free;
6952 hdspm->dev = dev;
6953 hdspm->pci = pci;
6954
6955 err = snd_hdspm_create(card, hdspm);
6956 if (err < 0)
6957 goto free_card;
6958
6959 if (hdspm->io_type != MADIface) {
6960 snprintf(card->shortname, sizeof(card->shortname), "%s_%x",
6961 hdspm->card_name, hdspm->serial);
6962 snprintf(card->longname, sizeof(card->longname),
6963 "%s S/N 0x%x at 0x%lx, irq %d",
6964 hdspm->card_name, hdspm->serial,
6965 hdspm->port, hdspm->irq);
6966 } else {
6967 snprintf(card->shortname, sizeof(card->shortname), "%s",
6968 hdspm->card_name);
6969 snprintf(card->longname, sizeof(card->longname),
6970 "%s at 0x%lx, irq %d",
6971 hdspm->card_name, hdspm->port, hdspm->irq);
6972 }
6973
6974 err = snd_card_register(card);
6975 if (err < 0)
6976 goto free_card;
6977
6978 pci_set_drvdata(pci, card);
6979
6980 dev++;
6981 return 0;
6982
6983 free_card:
6984 snd_card_free(card);
6985 return err;
6986 }
6987
6988 static void snd_hdspm_remove(struct pci_dev *pci)
6989 {
6990 snd_card_free(pci_get_drvdata(pci));
6991 }
6992
6993 static struct pci_driver hdspm_driver = {
6994 .name = KBUILD_MODNAME,
6995 .id_table = snd_hdspm_ids,
6996 .probe = snd_hdspm_probe,
6997 .remove = snd_hdspm_remove,
6998 };
6999
7000 module_pci_driver(hdspm_driver);
Linux with added FPC-III support