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Driver Core: devtmpfs - kernel-maintained tmpfs-based /dev
[linux/fpc-iii.git] / drivers / char / agp / intel-agp.c
blobc58557790585dfe6a0d56dba70fabb3764a3e2c6
1 /*
2 * Intel AGPGART routines.
3 */
4
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/init.h>
8 #include <linux/kernel.h>
9 #include <linux/pagemap.h>
10 #include <linux/agp_backend.h>
11 #include "agp.h"
12
13 #define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
14 #define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
15 #define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
16 #define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
17 #define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
18 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
19 #define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
20 #define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
21 #define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
22 #define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
23 #define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
24 #define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
25 #define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
26 #define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
27 #define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
28 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
29 #define PCI_DEVICE_ID_INTEL_IGDGM_HB 0xA010
30 #define PCI_DEVICE_ID_INTEL_IGDGM_IG 0xA011
31 #define PCI_DEVICE_ID_INTEL_IGDG_HB 0xA000
32 #define PCI_DEVICE_ID_INTEL_IGDG_IG 0xA001
33 #define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
34 #define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
35 #define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
36 #define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
37 #define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
38 #define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
39 #define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
40 #define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
41 #define PCI_DEVICE_ID_INTEL_IGD_E_HB 0x2E00
42 #define PCI_DEVICE_ID_INTEL_IGD_E_IG 0x2E02
43 #define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
44 #define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
45 #define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
46 #define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
47 #define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
48 #define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
49 #define PCI_DEVICE_ID_INTEL_IGDNG_D_HB 0x0040
50 #define PCI_DEVICE_ID_INTEL_IGDNG_D_IG 0x0042
51 #define PCI_DEVICE_ID_INTEL_IGDNG_M_HB 0x0044
52 #define PCI_DEVICE_ID_INTEL_IGDNG_MA_HB 0x0062
53 #define PCI_DEVICE_ID_INTEL_IGDNG_M_IG 0x0046
54
55 /* cover 915 and 945 variants */
56 #define IS_I915 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_E7221_HB || \
57 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915G_HB || \
58 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB || \
59 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945G_HB || \
60 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GM_HB || \
61 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82945GME_HB)
62
63 #define IS_I965 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82946GZ_HB || \
64 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82G35_HB || \
65 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965Q_HB || \
66 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965G_HB || \
67 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GM_HB || \
68 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82965GME_HB)
69
70 #define IS_G33 (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G33_HB || \
71 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q35_HB || \
72 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q33_HB || \
73 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
74 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
75
76 #define IS_IGD (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDGM_HB || \
77 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDG_HB)
78
79 #define IS_G4X (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGD_E_HB || \
80 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_Q45_HB || \
81 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G45_HB || \
82 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_GM45_HB || \
83 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_G41_HB || \
84 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_D_HB || \
85 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_M_HB || \
86 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_IGDNG_MA_HB)
87
88 extern int agp_memory_reserved;
89
90
91 /* Intel 815 register */
92 #define INTEL_815_APCONT 0x51
93 #define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
94
95 /* Intel i820 registers */
96 #define INTEL_I820_RDCR 0x51
97 #define INTEL_I820_ERRSTS 0xc8
98
99 /* Intel i840 registers */
100 #define INTEL_I840_MCHCFG 0x50
101 #define INTEL_I840_ERRSTS 0xc8
102
103 /* Intel i850 registers */
104 #define INTEL_I850_MCHCFG 0x50
105 #define INTEL_I850_ERRSTS 0xc8
106
107 /* intel 915G registers */
108 #define I915_GMADDR 0x18
109 #define I915_MMADDR 0x10
110 #define I915_PTEADDR 0x1C
111 #define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
112 #define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
113 #define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
114 #define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
115 #define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
116 #define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
117 #define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
118 #define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
119
120 #define I915_IFPADDR 0x60
121
122 /* Intel 965G registers */
123 #define I965_MSAC 0x62
124 #define I965_IFPADDR 0x70
125
126 /* Intel 7505 registers */
127 #define INTEL_I7505_APSIZE 0x74
128 #define INTEL_I7505_NCAPID 0x60
129 #define INTEL_I7505_NISTAT 0x6c
130 #define INTEL_I7505_ATTBASE 0x78
131 #define INTEL_I7505_ERRSTS 0x42
132 #define INTEL_I7505_AGPCTRL 0x70
133 #define INTEL_I7505_MCHCFG 0x50
134
135 static const struct aper_size_info_fixed intel_i810_sizes[] =
136 {
137 {64, 16384, 4},
138 /* The 32M mode still requires a 64k gatt */
139 {32, 8192, 4}
140 };
141
142 #define AGP_DCACHE_MEMORY 1
143 #define AGP_PHYS_MEMORY 2
144 #define INTEL_AGP_CACHED_MEMORY 3
145
146 static struct gatt_mask intel_i810_masks[] =
147 {
148 {.mask = I810_PTE_VALID, .type = 0},
149 {.mask = (I810_PTE_VALID | I810_PTE_LOCAL), .type = AGP_DCACHE_MEMORY},
150 {.mask = I810_PTE_VALID, .type = 0},
151 {.mask = I810_PTE_VALID | I830_PTE_SYSTEM_CACHED,
152 .type = INTEL_AGP_CACHED_MEMORY}
153 };
154
155 static struct _intel_private {
156 struct pci_dev *pcidev; /* device one */
157 u8 __iomem *registers;
158 u32 __iomem *gtt; /* I915G */
159 int num_dcache_entries;
160 /* gtt_entries is the number of gtt entries that are already mapped
161 * to stolen memory. Stolen memory is larger than the memory mapped
162 * through gtt_entries, as it includes some reserved space for the BIOS
163 * popup and for the GTT.
164 */
165 int gtt_entries; /* i830+ */
166 union {
167 void __iomem *i9xx_flush_page;
168 void *i8xx_flush_page;
169 };
170 struct page *i8xx_page;
171 struct resource ifp_resource;
172 int resource_valid;
173 } intel_private;
174
175 static int intel_i810_fetch_size(void)
176 {
177 u32 smram_miscc;
178 struct aper_size_info_fixed *values;
179
180 pci_read_config_dword(agp_bridge->dev, I810_SMRAM_MISCC, &smram_miscc);
181 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
182
183 if ((smram_miscc & I810_GMS) == I810_GMS_DISABLE) {
184 dev_warn(&agp_bridge->dev->dev, "i810 is disabled\n");
185 return 0;
186 }
187 if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) == I810_GFX_MEM_WIN_32M) {
188 agp_bridge->previous_size =
189 agp_bridge->current_size = (void *) (values + 1);
190 agp_bridge->aperture_size_idx = 1;
191 return values[1].size;
192 } else {
193 agp_bridge->previous_size =
194 agp_bridge->current_size = (void *) (values);
195 agp_bridge->aperture_size_idx = 0;
196 return values[0].size;
197 }
198
199 return 0;
200 }
201
202 static int intel_i810_configure(void)
203 {
204 struct aper_size_info_fixed *current_size;
205 u32 temp;
206 int i;
207
208 current_size = A_SIZE_FIX(agp_bridge->current_size);
209
210 if (!intel_private.registers) {
211 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
212 temp &= 0xfff80000;
213
214 intel_private.registers = ioremap(temp, 128 * 4096);
215 if (!intel_private.registers) {
216 dev_err(&intel_private.pcidev->dev,
217 "can't remap memory\n");
218 return -ENOMEM;
219 }
220 }
221
222 if ((readl(intel_private.registers+I810_DRAM_CTL)
223 & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) {
224 /* This will need to be dynamically assigned */
225 dev_info(&intel_private.pcidev->dev,
226 "detected 4MB dedicated video ram\n");
227 intel_private.num_dcache_entries = 1024;
228 }
229 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
230 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
231 writel(agp_bridge->gatt_bus_addr | I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
232 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
233
234 if (agp_bridge->driver->needs_scratch_page) {
235 for (i = 0; i < current_size->num_entries; i++) {
236 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
237 }
238 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI posting. */
239 }
240 global_cache_flush();
241 return 0;
242 }
243
244 static void intel_i810_cleanup(void)
245 {
246 writel(0, intel_private.registers+I810_PGETBL_CTL);
247 readl(intel_private.registers); /* PCI Posting. */
248 iounmap(intel_private.registers);
249 }
250
251 static void intel_i810_tlbflush(struct agp_memory *mem)
252 {
253 return;
254 }
255
256 static void intel_i810_agp_enable(struct agp_bridge_data *bridge, u32 mode)
257 {
258 return;
259 }
260
261 /* Exists to support ARGB cursors */
262 static struct page *i8xx_alloc_pages(void)
263 {
264 struct page *page;
265
266 page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2);
267 if (page == NULL)
268 return NULL;
269
270 if (set_pages_uc(page, 4) < 0) {
271 set_pages_wb(page, 4);
272 __free_pages(page, 2);
273 return NULL;
274 }
275 get_page(page);
276 atomic_inc(&agp_bridge->current_memory_agp);
277 return page;
278 }
279
280 static void i8xx_destroy_pages(struct page *page)
281 {
282 if (page == NULL)
283 return;
284
285 set_pages_wb(page, 4);
286 put_page(page);
287 __free_pages(page, 2);
288 atomic_dec(&agp_bridge->current_memory_agp);
289 }
290
291 static int intel_i830_type_to_mask_type(struct agp_bridge_data *bridge,
292 int type)
293 {
294 if (type < AGP_USER_TYPES)
295 return type;
296 else if (type == AGP_USER_CACHED_MEMORY)
297 return INTEL_AGP_CACHED_MEMORY;
298 else
299 return 0;
300 }
301
302 static int intel_i810_insert_entries(struct agp_memory *mem, off_t pg_start,
303 int type)
304 {
305 int i, j, num_entries;
306 void *temp;
307 int ret = -EINVAL;
308 int mask_type;
309
310 if (mem->page_count == 0)
311 goto out;
312
313 temp = agp_bridge->current_size;
314 num_entries = A_SIZE_FIX(temp)->num_entries;
315
316 if ((pg_start + mem->page_count) > num_entries)
317 goto out_err;
318
319
320 for (j = pg_start; j < (pg_start + mem->page_count); j++) {
321 if (!PGE_EMPTY(agp_bridge, readl(agp_bridge->gatt_table+j))) {
322 ret = -EBUSY;
323 goto out_err;
324 }
325 }
326
327 if (type != mem->type)
328 goto out_err;
329
330 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
331
332 switch (mask_type) {
333 case AGP_DCACHE_MEMORY:
334 if (!mem->is_flushed)
335 global_cache_flush();
336 for (i = pg_start; i < (pg_start + mem->page_count); i++) {
337 writel((i*4096)|I810_PTE_LOCAL|I810_PTE_VALID,
338 intel_private.registers+I810_PTE_BASE+(i*4));
339 }
340 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
341 break;
342 case AGP_PHYS_MEMORY:
343 case AGP_NORMAL_MEMORY:
344 if (!mem->is_flushed)
345 global_cache_flush();
346 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
347 writel(agp_bridge->driver->mask_memory(agp_bridge,
348 mem->pages[i],
349 mask_type),
350 intel_private.registers+I810_PTE_BASE+(j*4));
351 }
352 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
353 break;
354 default:
355 goto out_err;
356 }
357
358 agp_bridge->driver->tlb_flush(mem);
359 out:
360 ret = 0;
361 out_err:
362 mem->is_flushed = true;
363 return ret;
364 }
365
366 static int intel_i810_remove_entries(struct agp_memory *mem, off_t pg_start,
367 int type)
368 {
369 int i;
370
371 if (mem->page_count == 0)
372 return 0;
373
374 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
375 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
376 }
377 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
378
379 agp_bridge->driver->tlb_flush(mem);
380 return 0;
381 }
382
383 /*
384 * The i810/i830 requires a physical address to program its mouse
385 * pointer into hardware.
386 * However the Xserver still writes to it through the agp aperture.
387 */
388 static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type)
389 {
390 struct agp_memory *new;
391 struct page *page;
392
393 switch (pg_count) {
394 case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge);
395 break;
396 case 4:
397 /* kludge to get 4 physical pages for ARGB cursor */
398 page = i8xx_alloc_pages();
399 break;
400 default:
401 return NULL;
402 }
403
404 if (page == NULL)
405 return NULL;
406
407 new = agp_create_memory(pg_count);
408 if (new == NULL)
409 return NULL;
410
411 new->pages[0] = page;
412 if (pg_count == 4) {
413 /* kludge to get 4 physical pages for ARGB cursor */
414 new->pages[1] = new->pages[0] + 1;
415 new->pages[2] = new->pages[1] + 1;
416 new->pages[3] = new->pages[2] + 1;
417 }
418 new->page_count = pg_count;
419 new->num_scratch_pages = pg_count;
420 new->type = AGP_PHYS_MEMORY;
421 new->physical = page_to_phys(new->pages[0]);
422 return new;
423 }
424
425 static struct agp_memory *intel_i810_alloc_by_type(size_t pg_count, int type)
426 {
427 struct agp_memory *new;
428
429 if (type == AGP_DCACHE_MEMORY) {
430 if (pg_count != intel_private.num_dcache_entries)
431 return NULL;
432
433 new = agp_create_memory(1);
434 if (new == NULL)
435 return NULL;
436
437 new->type = AGP_DCACHE_MEMORY;
438 new->page_count = pg_count;
439 new->num_scratch_pages = 0;
440 agp_free_page_array(new);
441 return new;
442 }
443 if (type == AGP_PHYS_MEMORY)
444 return alloc_agpphysmem_i8xx(pg_count, type);
445 return NULL;
446 }
447
448 static void intel_i810_free_by_type(struct agp_memory *curr)
449 {
450 agp_free_key(curr->key);
451 if (curr->type == AGP_PHYS_MEMORY) {
452 if (curr->page_count == 4)
453 i8xx_destroy_pages(curr->pages[0]);
454 else {
455 agp_bridge->driver->agp_destroy_page(curr->pages[0],
456 AGP_PAGE_DESTROY_UNMAP);
457 agp_bridge->driver->agp_destroy_page(curr->pages[0],
458 AGP_PAGE_DESTROY_FREE);
459 }
460 agp_free_page_array(curr);
461 }
462 kfree(curr);
463 }
464
465 static unsigned long intel_i810_mask_memory(struct agp_bridge_data *bridge,
466 struct page *page, int type)
467 {
468 unsigned long addr = phys_to_gart(page_to_phys(page));
469 /* Type checking must be done elsewhere */
470 return addr | bridge->driver->masks[type].mask;
471 }
472
473 static struct aper_size_info_fixed intel_i830_sizes[] =
474 {
475 {128, 32768, 5},
476 /* The 64M mode still requires a 128k gatt */
477 {64, 16384, 5},
478 {256, 65536, 6},
479 {512, 131072, 7},
480 };
481
482 static void intel_i830_init_gtt_entries(void)
483 {
484 u16 gmch_ctrl;
485 int gtt_entries;
486 u8 rdct;
487 int local = 0;
488 static const int ddt[4] = { 0, 16, 32, 64 };
489 int size; /* reserved space (in kb) at the top of stolen memory */
490
491 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
492
493 if (IS_I965) {
494 u32 pgetbl_ctl;
495 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL);
496
497 /* The 965 has a field telling us the size of the GTT,
498 * which may be larger than what is necessary to map the
499 * aperture.
500 */
501 switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) {
502 case I965_PGETBL_SIZE_128KB:
503 size = 128;
504 break;
505 case I965_PGETBL_SIZE_256KB:
506 size = 256;
507 break;
508 case I965_PGETBL_SIZE_512KB:
509 size = 512;
510 break;
511 case I965_PGETBL_SIZE_1MB:
512 size = 1024;
513 break;
514 case I965_PGETBL_SIZE_2MB:
515 size = 2048;
516 break;
517 case I965_PGETBL_SIZE_1_5MB:
518 size = 1024 + 512;
519 break;
520 default:
521 dev_info(&intel_private.pcidev->dev,
522 "unknown page table size, assuming 512KB\n");
523 size = 512;
524 }
525 size += 4; /* add in BIOS popup space */
526 } else if (IS_G33 && !IS_IGD) {
527 /* G33's GTT size defined in gmch_ctrl */
528 switch (gmch_ctrl & G33_PGETBL_SIZE_MASK) {
529 case G33_PGETBL_SIZE_1M:
530 size = 1024;
531 break;
532 case G33_PGETBL_SIZE_2M:
533 size = 2048;
534 break;
535 default:
536 dev_info(&agp_bridge->dev->dev,
537 "unknown page table size 0x%x, assuming 512KB\n",
538 (gmch_ctrl & G33_PGETBL_SIZE_MASK));
539 size = 512;
540 }
541 size += 4;
542 } else if (IS_G4X || IS_IGD) {
543 /* On 4 series hardware, GTT stolen is separate from graphics
544 * stolen, ignore it in stolen gtt entries counting. However,
545 * 4KB of the stolen memory doesn't get mapped to the GTT.
546 */
547 size = 4;
548 } else {
549 /* On previous hardware, the GTT size was just what was
550 * required to map the aperture.
551 */
552 size = agp_bridge->driver->fetch_size() + 4;
553 }
554
555 if (agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82830_HB ||
556 agp_bridge->dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) {
557 switch (gmch_ctrl & I830_GMCH_GMS_MASK) {
558 case I830_GMCH_GMS_STOLEN_512:
559 gtt_entries = KB(512) - KB(size);
560 break;
561 case I830_GMCH_GMS_STOLEN_1024:
562 gtt_entries = MB(1) - KB(size);
563 break;
564 case I830_GMCH_GMS_STOLEN_8192:
565 gtt_entries = MB(8) - KB(size);
566 break;
567 case I830_GMCH_GMS_LOCAL:
568 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE);
569 gtt_entries = (I830_RDRAM_ND(rdct) + 1) *
570 MB(ddt[I830_RDRAM_DDT(rdct)]);
571 local = 1;
572 break;
573 default:
574 gtt_entries = 0;
575 break;
576 }
577 } else {
578 switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
579 case I855_GMCH_GMS_STOLEN_1M:
580 gtt_entries = MB(1) - KB(size);
581 break;
582 case I855_GMCH_GMS_STOLEN_4M:
583 gtt_entries = MB(4) - KB(size);
584 break;
585 case I855_GMCH_GMS_STOLEN_8M:
586 gtt_entries = MB(8) - KB(size);
587 break;
588 case I855_GMCH_GMS_STOLEN_16M:
589 gtt_entries = MB(16) - KB(size);
590 break;
591 case I855_GMCH_GMS_STOLEN_32M:
592 gtt_entries = MB(32) - KB(size);
593 break;
594 case I915_GMCH_GMS_STOLEN_48M:
595 /* Check it's really I915G */
596 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
597 gtt_entries = MB(48) - KB(size);
598 else
599 gtt_entries = 0;
600 break;
601 case I915_GMCH_GMS_STOLEN_64M:
602 /* Check it's really I915G */
603 if (IS_I915 || IS_I965 || IS_G33 || IS_G4X)
604 gtt_entries = MB(64) - KB(size);
605 else
606 gtt_entries = 0;
607 break;
608 case G33_GMCH_GMS_STOLEN_128M:
609 if (IS_G33 || IS_I965 || IS_G4X)
610 gtt_entries = MB(128) - KB(size);
611 else
612 gtt_entries = 0;
613 break;
614 case G33_GMCH_GMS_STOLEN_256M:
615 if (IS_G33 || IS_I965 || IS_G4X)
616 gtt_entries = MB(256) - KB(size);
617 else
618 gtt_entries = 0;
619 break;
620 case INTEL_GMCH_GMS_STOLEN_96M:
621 if (IS_I965 || IS_G4X)
622 gtt_entries = MB(96) - KB(size);
623 else
624 gtt_entries = 0;
625 break;
626 case INTEL_GMCH_GMS_STOLEN_160M:
627 if (IS_I965 || IS_G4X)
628 gtt_entries = MB(160) - KB(size);
629 else
630 gtt_entries = 0;
631 break;
632 case INTEL_GMCH_GMS_STOLEN_224M:
633 if (IS_I965 || IS_G4X)
634 gtt_entries = MB(224) - KB(size);
635 else
636 gtt_entries = 0;
637 break;
638 case INTEL_GMCH_GMS_STOLEN_352M:
639 if (IS_I965 || IS_G4X)
640 gtt_entries = MB(352) - KB(size);
641 else
642 gtt_entries = 0;
643 break;
644 default:
645 gtt_entries = 0;
646 break;
647 }
648 }
649 if (gtt_entries > 0) {
650 dev_info(&agp_bridge->dev->dev, "detected %dK %s memory\n",
651 gtt_entries / KB(1), local ? "local" : "stolen");
652 gtt_entries /= KB(4);
653 } else {
654 dev_info(&agp_bridge->dev->dev,
655 "no pre-allocated video memory detected\n");
656 gtt_entries = 0;
657 }
658
659 intel_private.gtt_entries = gtt_entries;
660 }
661
662 static void intel_i830_fini_flush(void)
663 {
664 kunmap(intel_private.i8xx_page);
665 intel_private.i8xx_flush_page = NULL;
666 unmap_page_from_agp(intel_private.i8xx_page);
667
668 __free_page(intel_private.i8xx_page);
669 intel_private.i8xx_page = NULL;
670 }
671
672 static void intel_i830_setup_flush(void)
673 {
674 /* return if we've already set the flush mechanism up */
675 if (intel_private.i8xx_page)
676 return;
677
678 intel_private.i8xx_page = alloc_page(GFP_KERNEL | __GFP_ZERO | GFP_DMA32);
679 if (!intel_private.i8xx_page)
680 return;
681
682 /* make page uncached */
683 map_page_into_agp(intel_private.i8xx_page);
684
685 intel_private.i8xx_flush_page = kmap(intel_private.i8xx_page);
686 if (!intel_private.i8xx_flush_page)
687 intel_i830_fini_flush();
688 }
689
690 static void intel_i830_chipset_flush(struct agp_bridge_data *bridge)
691 {
692 unsigned int *pg = intel_private.i8xx_flush_page;
693 int i;
694
695 for (i = 0; i < 256; i += 2)
696 *(pg + i) = i;
697
698 wmb();
699 }
700
701 /* The intel i830 automatically initializes the agp aperture during POST.
702 * Use the memory already set aside for in the GTT.
703 */
704 static int intel_i830_create_gatt_table(struct agp_bridge_data *bridge)
705 {
706 int page_order;
707 struct aper_size_info_fixed *size;
708 int num_entries;
709 u32 temp;
710
711 size = agp_bridge->current_size;
712 page_order = size->page_order;
713 num_entries = size->num_entries;
714 agp_bridge->gatt_table_real = NULL;
715
716 pci_read_config_dword(intel_private.pcidev, I810_MMADDR, &temp);
717 temp &= 0xfff80000;
718
719 intel_private.registers = ioremap(temp, 128 * 4096);
720 if (!intel_private.registers)
721 return -ENOMEM;
722
723 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
724 global_cache_flush(); /* FIXME: ?? */
725
726 /* we have to call this as early as possible after the MMIO base address is known */
727 intel_i830_init_gtt_entries();
728
729 agp_bridge->gatt_table = NULL;
730
731 agp_bridge->gatt_bus_addr = temp;
732
733 return 0;
734 }
735
736 /* Return the gatt table to a sane state. Use the top of stolen
737 * memory for the GTT.
738 */
739 static int intel_i830_free_gatt_table(struct agp_bridge_data *bridge)
740 {
741 return 0;
742 }
743
744 static int intel_i830_fetch_size(void)
745 {
746 u16 gmch_ctrl;
747 struct aper_size_info_fixed *values;
748
749 values = A_SIZE_FIX(agp_bridge->driver->aperture_sizes);
750
751 if (agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82830_HB &&
752 agp_bridge->dev->device != PCI_DEVICE_ID_INTEL_82845G_HB) {
753 /* 855GM/852GM/865G has 128MB aperture size */
754 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
755 agp_bridge->aperture_size_idx = 0;
756 return values[0].size;
757 }
758
759 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
760
761 if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
762 agp_bridge->previous_size = agp_bridge->current_size = (void *) values;
763 agp_bridge->aperture_size_idx = 0;
764 return values[0].size;
765 } else {
766 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + 1);
767 agp_bridge->aperture_size_idx = 1;
768 return values[1].size;
769 }
770
771 return 0;
772 }
773
774 static int intel_i830_configure(void)
775 {
776 struct aper_size_info_fixed *current_size;
777 u32 temp;
778 u16 gmch_ctrl;
779 int i;
780
781 current_size = A_SIZE_FIX(agp_bridge->current_size);
782
783 pci_read_config_dword(intel_private.pcidev, I810_GMADDR, &temp);
784 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
785
786 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
787 gmch_ctrl |= I830_GMCH_ENABLED;
788 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
789
790 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
791 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
792
793 if (agp_bridge->driver->needs_scratch_page) {
794 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
795 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
796 }
797 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4)); /* PCI Posting. */
798 }
799
800 global_cache_flush();
801
802 intel_i830_setup_flush();
803 return 0;
804 }
805
806 static void intel_i830_cleanup(void)
807 {
808 iounmap(intel_private.registers);
809 }
810
811 static int intel_i830_insert_entries(struct agp_memory *mem, off_t pg_start,
812 int type)
813 {
814 int i, j, num_entries;
815 void *temp;
816 int ret = -EINVAL;
817 int mask_type;
818
819 if (mem->page_count == 0)
820 goto out;
821
822 temp = agp_bridge->current_size;
823 num_entries = A_SIZE_FIX(temp)->num_entries;
824
825 if (pg_start < intel_private.gtt_entries) {
826 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
827 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
828 pg_start, intel_private.gtt_entries);
829
830 dev_info(&intel_private.pcidev->dev,
831 "trying to insert into local/stolen memory\n");
832 goto out_err;
833 }
834
835 if ((pg_start + mem->page_count) > num_entries)
836 goto out_err;
837
838 /* The i830 can't check the GTT for entries since its read only,
839 * depend on the caller to make the correct offset decisions.
840 */
841
842 if (type != mem->type)
843 goto out_err;
844
845 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
846
847 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
848 mask_type != INTEL_AGP_CACHED_MEMORY)
849 goto out_err;
850
851 if (!mem->is_flushed)
852 global_cache_flush();
853
854 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
855 writel(agp_bridge->driver->mask_memory(agp_bridge,
856 mem->pages[i], mask_type),
857 intel_private.registers+I810_PTE_BASE+(j*4));
858 }
859 readl(intel_private.registers+I810_PTE_BASE+((j-1)*4));
860 agp_bridge->driver->tlb_flush(mem);
861
862 out:
863 ret = 0;
864 out_err:
865 mem->is_flushed = true;
866 return ret;
867 }
868
869 static int intel_i830_remove_entries(struct agp_memory *mem, off_t pg_start,
870 int type)
871 {
872 int i;
873
874 if (mem->page_count == 0)
875 return 0;
876
877 if (pg_start < intel_private.gtt_entries) {
878 dev_info(&intel_private.pcidev->dev,
879 "trying to disable local/stolen memory\n");
880 return -EINVAL;
881 }
882
883 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
884 writel(agp_bridge->scratch_page, intel_private.registers+I810_PTE_BASE+(i*4));
885 }
886 readl(intel_private.registers+I810_PTE_BASE+((i-1)*4));
887
888 agp_bridge->driver->tlb_flush(mem);
889 return 0;
890 }
891
892 static struct agp_memory *intel_i830_alloc_by_type(size_t pg_count, int type)
893 {
894 if (type == AGP_PHYS_MEMORY)
895 return alloc_agpphysmem_i8xx(pg_count, type);
896 /* always return NULL for other allocation types for now */
897 return NULL;
898 }
899
900 static int intel_alloc_chipset_flush_resource(void)
901 {
902 int ret;
903 ret = pci_bus_alloc_resource(agp_bridge->dev->bus, &intel_private.ifp_resource, PAGE_SIZE,
904 PAGE_SIZE, PCIBIOS_MIN_MEM, 0,
905 pcibios_align_resource, agp_bridge->dev);
906
907 return ret;
908 }
909
910 static void intel_i915_setup_chipset_flush(void)
911 {
912 int ret;
913 u32 temp;
914
915 pci_read_config_dword(agp_bridge->dev, I915_IFPADDR, &temp);
916 if (!(temp & 0x1)) {
917 intel_alloc_chipset_flush_resource();
918 intel_private.resource_valid = 1;
919 pci_write_config_dword(agp_bridge->dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
920 } else {
921 temp &= ~1;
922
923 intel_private.resource_valid = 1;
924 intel_private.ifp_resource.start = temp;
925 intel_private.ifp_resource.end = temp + PAGE_SIZE;
926 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
927 /* some BIOSes reserve this area in a pnp some don't */
928 if (ret)
929 intel_private.resource_valid = 0;
930 }
931 }
932
933 static void intel_i965_g33_setup_chipset_flush(void)
934 {
935 u32 temp_hi, temp_lo;
936 int ret;
937
938 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR + 4, &temp_hi);
939 pci_read_config_dword(agp_bridge->dev, I965_IFPADDR, &temp_lo);
940
941 if (!(temp_lo & 0x1)) {
942
943 intel_alloc_chipset_flush_resource();
944
945 intel_private.resource_valid = 1;
946 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR + 4,
947 upper_32_bits(intel_private.ifp_resource.start));
948 pci_write_config_dword(agp_bridge->dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1);
949 } else {
950 u64 l64;
951
952 temp_lo &= ~0x1;
953 l64 = ((u64)temp_hi << 32) | temp_lo;
954
955 intel_private.resource_valid = 1;
956 intel_private.ifp_resource.start = l64;
957 intel_private.ifp_resource.end = l64 + PAGE_SIZE;
958 ret = request_resource(&iomem_resource, &intel_private.ifp_resource);
959 /* some BIOSes reserve this area in a pnp some don't */
960 if (ret)
961 intel_private.resource_valid = 0;
962 }
963 }
964
965 static void intel_i9xx_setup_flush(void)
966 {
967 /* return if already configured */
968 if (intel_private.ifp_resource.start)
969 return;
970
971 /* setup a resource for this object */
972 intel_private.ifp_resource.name = "Intel Flush Page";
973 intel_private.ifp_resource.flags = IORESOURCE_MEM;
974
975 /* Setup chipset flush for 915 */
976 if (IS_I965 || IS_G33 || IS_G4X) {
977 intel_i965_g33_setup_chipset_flush();
978 } else {
979 intel_i915_setup_chipset_flush();
980 }
981
982 if (intel_private.ifp_resource.start) {
983 intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE);
984 if (!intel_private.i9xx_flush_page)
985 dev_info(&intel_private.pcidev->dev, "can't ioremap flush page - no chipset flushing");
986 }
987 }
988
989 static int intel_i915_configure(void)
990 {
991 struct aper_size_info_fixed *current_size;
992 u32 temp;
993 u16 gmch_ctrl;
994 int i;
995
996 current_size = A_SIZE_FIX(agp_bridge->current_size);
997
998 pci_read_config_dword(intel_private.pcidev, I915_GMADDR, &temp);
999
1000 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1001
1002 pci_read_config_word(agp_bridge->dev, I830_GMCH_CTRL, &gmch_ctrl);
1003 gmch_ctrl |= I830_GMCH_ENABLED;
1004 pci_write_config_word(agp_bridge->dev, I830_GMCH_CTRL, gmch_ctrl);
1005
1006 writel(agp_bridge->gatt_bus_addr|I810_PGETBL_ENABLED, intel_private.registers+I810_PGETBL_CTL);
1007 readl(intel_private.registers+I810_PGETBL_CTL); /* PCI Posting. */
1008
1009 if (agp_bridge->driver->needs_scratch_page) {
1010 for (i = intel_private.gtt_entries; i < current_size->num_entries; i++) {
1011 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1012 }
1013 readl(intel_private.gtt+i-1); /* PCI Posting. */
1014 }
1015
1016 global_cache_flush();
1017
1018 intel_i9xx_setup_flush();
1019
1020 return 0;
1021 }
1022
1023 static void intel_i915_cleanup(void)
1024 {
1025 if (intel_private.i9xx_flush_page)
1026 iounmap(intel_private.i9xx_flush_page);
1027 if (intel_private.resource_valid)
1028 release_resource(&intel_private.ifp_resource);
1029 intel_private.ifp_resource.start = 0;
1030 intel_private.resource_valid = 0;
1031 iounmap(intel_private.gtt);
1032 iounmap(intel_private.registers);
1033 }
1034
1035 static void intel_i915_chipset_flush(struct agp_bridge_data *bridge)
1036 {
1037 if (intel_private.i9xx_flush_page)
1038 writel(1, intel_private.i9xx_flush_page);
1039 }
1040
1041 static int intel_i915_insert_entries(struct agp_memory *mem, off_t pg_start,
1042 int type)
1043 {
1044 int i, j, num_entries;
1045 void *temp;
1046 int ret = -EINVAL;
1047 int mask_type;
1048
1049 if (mem->page_count == 0)
1050 goto out;
1051
1052 temp = agp_bridge->current_size;
1053 num_entries = A_SIZE_FIX(temp)->num_entries;
1054
1055 if (pg_start < intel_private.gtt_entries) {
1056 dev_printk(KERN_DEBUG, &intel_private.pcidev->dev,
1057 "pg_start == 0x%.8lx, intel_private.gtt_entries == 0x%.8x\n",
1058 pg_start, intel_private.gtt_entries);
1059
1060 dev_info(&intel_private.pcidev->dev,
1061 "trying to insert into local/stolen memory\n");
1062 goto out_err;
1063 }
1064
1065 if ((pg_start + mem->page_count) > num_entries)
1066 goto out_err;
1067
1068 /* The i915 can't check the GTT for entries since its read only,
1069 * depend on the caller to make the correct offset decisions.
1070 */
1071
1072 if (type != mem->type)
1073 goto out_err;
1074
1075 mask_type = agp_bridge->driver->agp_type_to_mask_type(agp_bridge, type);
1076
1077 if (mask_type != 0 && mask_type != AGP_PHYS_MEMORY &&
1078 mask_type != INTEL_AGP_CACHED_MEMORY)
1079 goto out_err;
1080
1081 if (!mem->is_flushed)
1082 global_cache_flush();
1083
1084 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
1085 writel(agp_bridge->driver->mask_memory(agp_bridge,
1086 mem->pages[i], mask_type), intel_private.gtt+j);
1087 }
1088
1089 readl(intel_private.gtt+j-1);
1090 agp_bridge->driver->tlb_flush(mem);
1091
1092 out:
1093 ret = 0;
1094 out_err:
1095 mem->is_flushed = true;
1096 return ret;
1097 }
1098
1099 static int intel_i915_remove_entries(struct agp_memory *mem, off_t pg_start,
1100 int type)
1101 {
1102 int i;
1103
1104 if (mem->page_count == 0)
1105 return 0;
1106
1107 if (pg_start < intel_private.gtt_entries) {
1108 dev_info(&intel_private.pcidev->dev,
1109 "trying to disable local/stolen memory\n");
1110 return -EINVAL;
1111 }
1112
1113 for (i = pg_start; i < (mem->page_count + pg_start); i++)
1114 writel(agp_bridge->scratch_page, intel_private.gtt+i);
1115
1116 readl(intel_private.gtt+i-1);
1117
1118 agp_bridge->driver->tlb_flush(mem);
1119 return 0;
1120 }
1121
1122 /* Return the aperture size by just checking the resource length. The effect
1123 * described in the spec of the MSAC registers is just changing of the
1124 * resource size.
1125 */
1126 static int intel_i9xx_fetch_size(void)
1127 {
1128 int num_sizes = ARRAY_SIZE(intel_i830_sizes);
1129 int aper_size; /* size in megabytes */
1130 int i;
1131
1132 aper_size = pci_resource_len(intel_private.pcidev, 2) / MB(1);
1133
1134 for (i = 0; i < num_sizes; i++) {
1135 if (aper_size == intel_i830_sizes[i].size) {
1136 agp_bridge->current_size = intel_i830_sizes + i;
1137 agp_bridge->previous_size = agp_bridge->current_size;
1138 return aper_size;
1139 }
1140 }
1141
1142 return 0;
1143 }
1144
1145 /* The intel i915 automatically initializes the agp aperture during POST.
1146 * Use the memory already set aside for in the GTT.
1147 */
1148 static int intel_i915_create_gatt_table(struct agp_bridge_data *bridge)
1149 {
1150 int page_order;
1151 struct aper_size_info_fixed *size;
1152 int num_entries;
1153 u32 temp, temp2;
1154 int gtt_map_size = 256 * 1024;
1155
1156 size = agp_bridge->current_size;
1157 page_order = size->page_order;
1158 num_entries = size->num_entries;
1159 agp_bridge->gatt_table_real = NULL;
1160
1161 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1162 pci_read_config_dword(intel_private.pcidev, I915_PTEADDR, &temp2);
1163
1164 if (IS_G33)
1165 gtt_map_size = 1024 * 1024; /* 1M on G33 */
1166 intel_private.gtt = ioremap(temp2, gtt_map_size);
1167 if (!intel_private.gtt)
1168 return -ENOMEM;
1169
1170 temp &= 0xfff80000;
1171
1172 intel_private.registers = ioremap(temp, 128 * 4096);
1173 if (!intel_private.registers) {
1174 iounmap(intel_private.gtt);
1175 return -ENOMEM;
1176 }
1177
1178 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1179 global_cache_flush(); /* FIXME: ? */
1180
1181 /* we have to call this as early as possible after the MMIO base address is known */
1182 intel_i830_init_gtt_entries();
1183
1184 agp_bridge->gatt_table = NULL;
1185
1186 agp_bridge->gatt_bus_addr = temp;
1187
1188 return 0;
1189 }
1190
1191 /*
1192 * The i965 supports 36-bit physical addresses, but to keep
1193 * the format of the GTT the same, the bits that don't fit
1194 * in a 32-bit word are shifted down to bits 4..7.
1195 *
1196 * Gcc is smart enough to notice that "(addr >> 28) & 0xf0"
1197 * is always zero on 32-bit architectures, so no need to make
1198 * this conditional.
1199 */
1200 static unsigned long intel_i965_mask_memory(struct agp_bridge_data *bridge,
1201 struct page *page, int type)
1202 {
1203 dma_addr_t addr = phys_to_gart(page_to_phys(page));
1204 /* Shift high bits down */
1205 addr |= (addr >> 28) & 0xf0;
1206
1207 /* Type checking must be done elsewhere */
1208 return addr | bridge->driver->masks[type].mask;
1209 }
1210
1211 static void intel_i965_get_gtt_range(int *gtt_offset, int *gtt_size)
1212 {
1213 switch (agp_bridge->dev->device) {
1214 case PCI_DEVICE_ID_INTEL_GM45_HB:
1215 case PCI_DEVICE_ID_INTEL_IGD_E_HB:
1216 case PCI_DEVICE_ID_INTEL_Q45_HB:
1217 case PCI_DEVICE_ID_INTEL_G45_HB:
1218 case PCI_DEVICE_ID_INTEL_G41_HB:
1219 case PCI_DEVICE_ID_INTEL_IGDNG_D_HB:
1220 case PCI_DEVICE_ID_INTEL_IGDNG_M_HB:
1221 case PCI_DEVICE_ID_INTEL_IGDNG_MA_HB:
1222 *gtt_offset = *gtt_size = MB(2);
1223 break;
1224 default:
1225 *gtt_offset = *gtt_size = KB(512);
1226 }
1227 }
1228
1229 /* The intel i965 automatically initializes the agp aperture during POST.
1230 * Use the memory already set aside for in the GTT.
1231 */
1232 static int intel_i965_create_gatt_table(struct agp_bridge_data *bridge)
1233 {
1234 int page_order;
1235 struct aper_size_info_fixed *size;
1236 int num_entries;
1237 u32 temp;
1238 int gtt_offset, gtt_size;
1239
1240 size = agp_bridge->current_size;
1241 page_order = size->page_order;
1242 num_entries = size->num_entries;
1243 agp_bridge->gatt_table_real = NULL;
1244
1245 pci_read_config_dword(intel_private.pcidev, I915_MMADDR, &temp);
1246
1247 temp &= 0xfff00000;
1248
1249 intel_i965_get_gtt_range(&gtt_offset, &gtt_size);
1250
1251 intel_private.gtt = ioremap((temp + gtt_offset) , gtt_size);
1252
1253 if (!intel_private.gtt)
1254 return -ENOMEM;
1255
1256 intel_private.registers = ioremap(temp, 128 * 4096);
1257 if (!intel_private.registers) {
1258 iounmap(intel_private.gtt);
1259 return -ENOMEM;
1260 }
1261
1262 temp = readl(intel_private.registers+I810_PGETBL_CTL) & 0xfffff000;
1263 global_cache_flush(); /* FIXME: ? */
1264
1265 /* we have to call this as early as possible after the MMIO base address is known */
1266 intel_i830_init_gtt_entries();
1267
1268 agp_bridge->gatt_table = NULL;
1269
1270 agp_bridge->gatt_bus_addr = temp;
1271
1272 return 0;
1273 }
1274
1275
1276 static int intel_fetch_size(void)
1277 {
1278 int i;
1279 u16 temp;
1280 struct aper_size_info_16 *values;
1281
1282 pci_read_config_word(agp_bridge->dev, INTEL_APSIZE, &temp);
1283 values = A_SIZE_16(agp_bridge->driver->aperture_sizes);
1284
1285 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1286 if (temp == values[i].size_value) {
1287 agp_bridge->previous_size = agp_bridge->current_size = (void *) (values + i);
1288 agp_bridge->aperture_size_idx = i;
1289 return values[i].size;
1290 }
1291 }
1292
1293 return 0;
1294 }
1295
1296 static int __intel_8xx_fetch_size(u8 temp)
1297 {
1298 int i;
1299 struct aper_size_info_8 *values;
1300
1301 values = A_SIZE_8(agp_bridge->driver->aperture_sizes);
1302
1303 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
1304 if (temp == values[i].size_value) {
1305 agp_bridge->previous_size =
1306 agp_bridge->current_size = (void *) (values + i);
1307 agp_bridge->aperture_size_idx = i;
1308 return values[i].size;
1309 }
1310 }
1311 return 0;
1312 }
1313
1314 static int intel_8xx_fetch_size(void)
1315 {
1316 u8 temp;
1317
1318 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1319 return __intel_8xx_fetch_size(temp);
1320 }
1321
1322 static int intel_815_fetch_size(void)
1323 {
1324 u8 temp;
1325
1326 /* Intel 815 chipsets have a _weird_ APSIZE register with only
1327 * one non-reserved bit, so mask the others out ... */
1328 pci_read_config_byte(agp_bridge->dev, INTEL_APSIZE, &temp);
1329 temp &= (1 << 3);
1330
1331 return __intel_8xx_fetch_size(temp);
1332 }
1333
1334 static void intel_tlbflush(struct agp_memory *mem)
1335 {
1336 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2200);
1337 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1338 }
1339
1340
1341 static void intel_8xx_tlbflush(struct agp_memory *mem)
1342 {
1343 u32 temp;
1344 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1345 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp & ~(1 << 7));
1346 pci_read_config_dword(agp_bridge->dev, INTEL_AGPCTRL, &temp);
1347 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, temp | (1 << 7));
1348 }
1349
1350
1351 static void intel_cleanup(void)
1352 {
1353 u16 temp;
1354 struct aper_size_info_16 *previous_size;
1355
1356 previous_size = A_SIZE_16(agp_bridge->previous_size);
1357 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1358 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1359 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1360 }
1361
1362
1363 static void intel_8xx_cleanup(void)
1364 {
1365 u16 temp;
1366 struct aper_size_info_8 *previous_size;
1367
1368 previous_size = A_SIZE_8(agp_bridge->previous_size);
1369 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp);
1370 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp & ~(1 << 9));
1371 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, previous_size->size_value);
1372 }
1373
1374
1375 static int intel_configure(void)
1376 {
1377 u32 temp;
1378 u16 temp2;
1379 struct aper_size_info_16 *current_size;
1380
1381 current_size = A_SIZE_16(agp_bridge->current_size);
1382
1383 /* aperture size */
1384 pci_write_config_word(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1385
1386 /* address to map to */
1387 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1388 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1389
1390 /* attbase - aperture base */
1391 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1392
1393 /* agpctrl */
1394 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x2280);
1395
1396 /* paccfg/nbxcfg */
1397 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1398 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG,
1399 (temp2 & ~(1 << 10)) | (1 << 9));
1400 /* clear any possible error conditions */
1401 pci_write_config_byte(agp_bridge->dev, INTEL_ERRSTS + 1, 7);
1402 return 0;
1403 }
1404
1405 static int intel_815_configure(void)
1406 {
1407 u32 temp, addr;
1408 u8 temp2;
1409 struct aper_size_info_8 *current_size;
1410
1411 /* attbase - aperture base */
1412 /* the Intel 815 chipset spec. says that bits 29-31 in the
1413 * ATTBASE register are reserved -> try not to write them */
1414 if (agp_bridge->gatt_bus_addr & INTEL_815_ATTBASE_MASK) {
1415 dev_emerg(&agp_bridge->dev->dev, "gatt bus addr too high");
1416 return -EINVAL;
1417 }
1418
1419 current_size = A_SIZE_8(agp_bridge->current_size);
1420
1421 /* aperture size */
1422 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1423 current_size->size_value);
1424
1425 /* address to map to */
1426 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1427 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1428
1429 pci_read_config_dword(agp_bridge->dev, INTEL_ATTBASE, &addr);
1430 addr &= INTEL_815_ATTBASE_MASK;
1431 addr |= agp_bridge->gatt_bus_addr;
1432 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, addr);
1433
1434 /* agpctrl */
1435 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1436
1437 /* apcont */
1438 pci_read_config_byte(agp_bridge->dev, INTEL_815_APCONT, &temp2);
1439 pci_write_config_byte(agp_bridge->dev, INTEL_815_APCONT, temp2 | (1 << 1));
1440
1441 /* clear any possible error conditions */
1442 /* Oddness : this chipset seems to have no ERRSTS register ! */
1443 return 0;
1444 }
1445
1446 static void intel_820_tlbflush(struct agp_memory *mem)
1447 {
1448 return;
1449 }
1450
1451 static void intel_820_cleanup(void)
1452 {
1453 u8 temp;
1454 struct aper_size_info_8 *previous_size;
1455
1456 previous_size = A_SIZE_8(agp_bridge->previous_size);
1457 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp);
1458 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR,
1459 temp & ~(1 << 1));
1460 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE,
1461 previous_size->size_value);
1462 }
1463
1464
1465 static int intel_820_configure(void)
1466 {
1467 u32 temp;
1468 u8 temp2;
1469 struct aper_size_info_8 *current_size;
1470
1471 current_size = A_SIZE_8(agp_bridge->current_size);
1472
1473 /* aperture size */
1474 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1475
1476 /* address to map to */
1477 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1478 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1479
1480 /* attbase - aperture base */
1481 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1482
1483 /* agpctrl */
1484 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1485
1486 /* global enable aperture access */
1487 /* This flag is not accessed through MCHCFG register as in */
1488 /* i850 chipset. */
1489 pci_read_config_byte(agp_bridge->dev, INTEL_I820_RDCR, &temp2);
1490 pci_write_config_byte(agp_bridge->dev, INTEL_I820_RDCR, temp2 | (1 << 1));
1491 /* clear any possible AGP-related error conditions */
1492 pci_write_config_word(agp_bridge->dev, INTEL_I820_ERRSTS, 0x001c);
1493 return 0;
1494 }
1495
1496 static int intel_840_configure(void)
1497 {
1498 u32 temp;
1499 u16 temp2;
1500 struct aper_size_info_8 *current_size;
1501
1502 current_size = A_SIZE_8(agp_bridge->current_size);
1503
1504 /* aperture size */
1505 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1506
1507 /* address to map to */
1508 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1509 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1510
1511 /* attbase - aperture base */
1512 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1513
1514 /* agpctrl */
1515 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1516
1517 /* mcgcfg */
1518 pci_read_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, &temp2);
1519 pci_write_config_word(agp_bridge->dev, INTEL_I840_MCHCFG, temp2 | (1 << 9));
1520 /* clear any possible error conditions */
1521 pci_write_config_word(agp_bridge->dev, INTEL_I840_ERRSTS, 0xc000);
1522 return 0;
1523 }
1524
1525 static int intel_845_configure(void)
1526 {
1527 u32 temp;
1528 u8 temp2;
1529 struct aper_size_info_8 *current_size;
1530
1531 current_size = A_SIZE_8(agp_bridge->current_size);
1532
1533 /* aperture size */
1534 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1535
1536 if (agp_bridge->apbase_config != 0) {
1537 pci_write_config_dword(agp_bridge->dev, AGP_APBASE,
1538 agp_bridge->apbase_config);
1539 } else {
1540 /* address to map to */
1541 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1542 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1543 agp_bridge->apbase_config = temp;
1544 }
1545
1546 /* attbase - aperture base */
1547 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1548
1549 /* agpctrl */
1550 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1551
1552 /* agpm */
1553 pci_read_config_byte(agp_bridge->dev, INTEL_I845_AGPM, &temp2);
1554 pci_write_config_byte(agp_bridge->dev, INTEL_I845_AGPM, temp2 | (1 << 1));
1555 /* clear any possible error conditions */
1556 pci_write_config_word(agp_bridge->dev, INTEL_I845_ERRSTS, 0x001c);
1557
1558 intel_i830_setup_flush();
1559 return 0;
1560 }
1561
1562 static int intel_850_configure(void)
1563 {
1564 u32 temp;
1565 u16 temp2;
1566 struct aper_size_info_8 *current_size;
1567
1568 current_size = A_SIZE_8(agp_bridge->current_size);
1569
1570 /* aperture size */
1571 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1572
1573 /* address to map to */
1574 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1575 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1576
1577 /* attbase - aperture base */
1578 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1579
1580 /* agpctrl */
1581 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1582
1583 /* mcgcfg */
1584 pci_read_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, &temp2);
1585 pci_write_config_word(agp_bridge->dev, INTEL_I850_MCHCFG, temp2 | (1 << 9));
1586 /* clear any possible AGP-related error conditions */
1587 pci_write_config_word(agp_bridge->dev, INTEL_I850_ERRSTS, 0x001c);
1588 return 0;
1589 }
1590
1591 static int intel_860_configure(void)
1592 {
1593 u32 temp;
1594 u16 temp2;
1595 struct aper_size_info_8 *current_size;
1596
1597 current_size = A_SIZE_8(agp_bridge->current_size);
1598
1599 /* aperture size */
1600 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1601
1602 /* address to map to */
1603 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1604 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1605
1606 /* attbase - aperture base */
1607 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1608
1609 /* agpctrl */
1610 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1611
1612 /* mcgcfg */
1613 pci_read_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, &temp2);
1614 pci_write_config_word(agp_bridge->dev, INTEL_I860_MCHCFG, temp2 | (1 << 9));
1615 /* clear any possible AGP-related error conditions */
1616 pci_write_config_word(agp_bridge->dev, INTEL_I860_ERRSTS, 0xf700);
1617 return 0;
1618 }
1619
1620 static int intel_830mp_configure(void)
1621 {
1622 u32 temp;
1623 u16 temp2;
1624 struct aper_size_info_8 *current_size;
1625
1626 current_size = A_SIZE_8(agp_bridge->current_size);
1627
1628 /* aperture size */
1629 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1630
1631 /* address to map to */
1632 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1633 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1634
1635 /* attbase - aperture base */
1636 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1637
1638 /* agpctrl */
1639 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1640
1641 /* gmch */
1642 pci_read_config_word(agp_bridge->dev, INTEL_NBXCFG, &temp2);
1643 pci_write_config_word(agp_bridge->dev, INTEL_NBXCFG, temp2 | (1 << 9));
1644 /* clear any possible AGP-related error conditions */
1645 pci_write_config_word(agp_bridge->dev, INTEL_I830_ERRSTS, 0x1c);
1646 return 0;
1647 }
1648
1649 static int intel_7505_configure(void)
1650 {
1651 u32 temp;
1652 u16 temp2;
1653 struct aper_size_info_8 *current_size;
1654
1655 current_size = A_SIZE_8(agp_bridge->current_size);
1656
1657 /* aperture size */
1658 pci_write_config_byte(agp_bridge->dev, INTEL_APSIZE, current_size->size_value);
1659
1660 /* address to map to */
1661 pci_read_config_dword(agp_bridge->dev, AGP_APBASE, &temp);
1662 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
1663
1664 /* attbase - aperture base */
1665 pci_write_config_dword(agp_bridge->dev, INTEL_ATTBASE, agp_bridge->gatt_bus_addr);
1666
1667 /* agpctrl */
1668 pci_write_config_dword(agp_bridge->dev, INTEL_AGPCTRL, 0x0000);
1669
1670 /* mchcfg */
1671 pci_read_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, &temp2);
1672 pci_write_config_word(agp_bridge->dev, INTEL_I7505_MCHCFG, temp2 | (1 << 9));
1673
1674 return 0;
1675 }
1676
1677 /* Setup function */
1678 static const struct gatt_mask intel_generic_masks[] =
1679 {
1680 {.mask = 0x00000017, .type = 0}
1681 };
1682
1683 static const struct aper_size_info_8 intel_815_sizes[2] =
1684 {
1685 {64, 16384, 4, 0},
1686 {32, 8192, 3, 8},
1687 };
1688
1689 static const struct aper_size_info_8 intel_8xx_sizes[7] =
1690 {
1691 {256, 65536, 6, 0},
1692 {128, 32768, 5, 32},
1693 {64, 16384, 4, 48},
1694 {32, 8192, 3, 56},
1695 {16, 4096, 2, 60},
1696 {8, 2048, 1, 62},
1697 {4, 1024, 0, 63}
1698 };
1699
1700 static const struct aper_size_info_16 intel_generic_sizes[7] =
1701 {
1702 {256, 65536, 6, 0},
1703 {128, 32768, 5, 32},
1704 {64, 16384, 4, 48},
1705 {32, 8192, 3, 56},
1706 {16, 4096, 2, 60},
1707 {8, 2048, 1, 62},
1708 {4, 1024, 0, 63}
1709 };
1710
1711 static const struct aper_size_info_8 intel_830mp_sizes[4] =
1712 {
1713 {256, 65536, 6, 0},
1714 {128, 32768, 5, 32},
1715 {64, 16384, 4, 48},
1716 {32, 8192, 3, 56}
1717 };
1718
1719 static const struct agp_bridge_driver intel_generic_driver = {
1720 .owner = THIS_MODULE,
1721 .aperture_sizes = intel_generic_sizes,
1722 .size_type = U16_APER_SIZE,
1723 .num_aperture_sizes = 7,
1724 .configure = intel_configure,
1725 .fetch_size = intel_fetch_size,
1726 .cleanup = intel_cleanup,
1727 .tlb_flush = intel_tlbflush,
1728 .mask_memory = agp_generic_mask_memory,
1729 .masks = intel_generic_masks,
1730 .agp_enable = agp_generic_enable,
1731 .cache_flush = global_cache_flush,
1732 .create_gatt_table = agp_generic_create_gatt_table,
1733 .free_gatt_table = agp_generic_free_gatt_table,
1734 .insert_memory = agp_generic_insert_memory,
1735 .remove_memory = agp_generic_remove_memory,
1736 .alloc_by_type = agp_generic_alloc_by_type,
1737 .free_by_type = agp_generic_free_by_type,
1738 .agp_alloc_page = agp_generic_alloc_page,
1739 .agp_alloc_pages = agp_generic_alloc_pages,
1740 .agp_destroy_page = agp_generic_destroy_page,
1741 .agp_destroy_pages = agp_generic_destroy_pages,
1742 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1743 };
1744
1745 static const struct agp_bridge_driver intel_810_driver = {
1746 .owner = THIS_MODULE,
1747 .aperture_sizes = intel_i810_sizes,
1748 .size_type = FIXED_APER_SIZE,
1749 .num_aperture_sizes = 2,
1750 .needs_scratch_page = true,
1751 .configure = intel_i810_configure,
1752 .fetch_size = intel_i810_fetch_size,
1753 .cleanup = intel_i810_cleanup,
1754 .tlb_flush = intel_i810_tlbflush,
1755 .mask_memory = intel_i810_mask_memory,
1756 .masks = intel_i810_masks,
1757 .agp_enable = intel_i810_agp_enable,
1758 .cache_flush = global_cache_flush,
1759 .create_gatt_table = agp_generic_create_gatt_table,
1760 .free_gatt_table = agp_generic_free_gatt_table,
1761 .insert_memory = intel_i810_insert_entries,
1762 .remove_memory = intel_i810_remove_entries,
1763 .alloc_by_type = intel_i810_alloc_by_type,
1764 .free_by_type = intel_i810_free_by_type,
1765 .agp_alloc_page = agp_generic_alloc_page,
1766 .agp_alloc_pages = agp_generic_alloc_pages,
1767 .agp_destroy_page = agp_generic_destroy_page,
1768 .agp_destroy_pages = agp_generic_destroy_pages,
1769 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1770 };
1771
1772 static const struct agp_bridge_driver intel_815_driver = {
1773 .owner = THIS_MODULE,
1774 .aperture_sizes = intel_815_sizes,
1775 .size_type = U8_APER_SIZE,
1776 .num_aperture_sizes = 2,
1777 .configure = intel_815_configure,
1778 .fetch_size = intel_815_fetch_size,
1779 .cleanup = intel_8xx_cleanup,
1780 .tlb_flush = intel_8xx_tlbflush,
1781 .mask_memory = agp_generic_mask_memory,
1782 .masks = intel_generic_masks,
1783 .agp_enable = agp_generic_enable,
1784 .cache_flush = global_cache_flush,
1785 .create_gatt_table = agp_generic_create_gatt_table,
1786 .free_gatt_table = agp_generic_free_gatt_table,
1787 .insert_memory = agp_generic_insert_memory,
1788 .remove_memory = agp_generic_remove_memory,
1789 .alloc_by_type = agp_generic_alloc_by_type,
1790 .free_by_type = agp_generic_free_by_type,
1791 .agp_alloc_page = agp_generic_alloc_page,
1792 .agp_alloc_pages = agp_generic_alloc_pages,
1793 .agp_destroy_page = agp_generic_destroy_page,
1794 .agp_destroy_pages = agp_generic_destroy_pages,
1795 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1796 };
1797
1798 static const struct agp_bridge_driver intel_830_driver = {
1799 .owner = THIS_MODULE,
1800 .aperture_sizes = intel_i830_sizes,
1801 .size_type = FIXED_APER_SIZE,
1802 .num_aperture_sizes = 4,
1803 .needs_scratch_page = true,
1804 .configure = intel_i830_configure,
1805 .fetch_size = intel_i830_fetch_size,
1806 .cleanup = intel_i830_cleanup,
1807 .tlb_flush = intel_i810_tlbflush,
1808 .mask_memory = intel_i810_mask_memory,
1809 .masks = intel_i810_masks,
1810 .agp_enable = intel_i810_agp_enable,
1811 .cache_flush = global_cache_flush,
1812 .create_gatt_table = intel_i830_create_gatt_table,
1813 .free_gatt_table = intel_i830_free_gatt_table,
1814 .insert_memory = intel_i830_insert_entries,
1815 .remove_memory = intel_i830_remove_entries,
1816 .alloc_by_type = intel_i830_alloc_by_type,
1817 .free_by_type = intel_i810_free_by_type,
1818 .agp_alloc_page = agp_generic_alloc_page,
1819 .agp_alloc_pages = agp_generic_alloc_pages,
1820 .agp_destroy_page = agp_generic_destroy_page,
1821 .agp_destroy_pages = agp_generic_destroy_pages,
1822 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
1823 .chipset_flush = intel_i830_chipset_flush,
1824 };
1825
1826 static const struct agp_bridge_driver intel_820_driver = {
1827 .owner = THIS_MODULE,
1828 .aperture_sizes = intel_8xx_sizes,
1829 .size_type = U8_APER_SIZE,
1830 .num_aperture_sizes = 7,
1831 .configure = intel_820_configure,
1832 .fetch_size = intel_8xx_fetch_size,
1833 .cleanup = intel_820_cleanup,
1834 .tlb_flush = intel_820_tlbflush,
1835 .mask_memory = agp_generic_mask_memory,
1836 .masks = intel_generic_masks,
1837 .agp_enable = agp_generic_enable,
1838 .cache_flush = global_cache_flush,
1839 .create_gatt_table = agp_generic_create_gatt_table,
1840 .free_gatt_table = agp_generic_free_gatt_table,
1841 .insert_memory = agp_generic_insert_memory,
1842 .remove_memory = agp_generic_remove_memory,
1843 .alloc_by_type = agp_generic_alloc_by_type,
1844 .free_by_type = agp_generic_free_by_type,
1845 .agp_alloc_page = agp_generic_alloc_page,
1846 .agp_alloc_pages = agp_generic_alloc_pages,
1847 .agp_destroy_page = agp_generic_destroy_page,
1848 .agp_destroy_pages = agp_generic_destroy_pages,
1849 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1850 };
1851
1852 static const struct agp_bridge_driver intel_830mp_driver = {
1853 .owner = THIS_MODULE,
1854 .aperture_sizes = intel_830mp_sizes,
1855 .size_type = U8_APER_SIZE,
1856 .num_aperture_sizes = 4,
1857 .configure = intel_830mp_configure,
1858 .fetch_size = intel_8xx_fetch_size,
1859 .cleanup = intel_8xx_cleanup,
1860 .tlb_flush = intel_8xx_tlbflush,
1861 .mask_memory = agp_generic_mask_memory,
1862 .masks = intel_generic_masks,
1863 .agp_enable = agp_generic_enable,
1864 .cache_flush = global_cache_flush,
1865 .create_gatt_table = agp_generic_create_gatt_table,
1866 .free_gatt_table = agp_generic_free_gatt_table,
1867 .insert_memory = agp_generic_insert_memory,
1868 .remove_memory = agp_generic_remove_memory,
1869 .alloc_by_type = agp_generic_alloc_by_type,
1870 .free_by_type = agp_generic_free_by_type,
1871 .agp_alloc_page = agp_generic_alloc_page,
1872 .agp_alloc_pages = agp_generic_alloc_pages,
1873 .agp_destroy_page = agp_generic_destroy_page,
1874 .agp_destroy_pages = agp_generic_destroy_pages,
1875 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1876 };
1877
1878 static const struct agp_bridge_driver intel_840_driver = {
1879 .owner = THIS_MODULE,
1880 .aperture_sizes = intel_8xx_sizes,
1881 .size_type = U8_APER_SIZE,
1882 .num_aperture_sizes = 7,
1883 .configure = intel_840_configure,
1884 .fetch_size = intel_8xx_fetch_size,
1885 .cleanup = intel_8xx_cleanup,
1886 .tlb_flush = intel_8xx_tlbflush,
1887 .mask_memory = agp_generic_mask_memory,
1888 .masks = intel_generic_masks,
1889 .agp_enable = agp_generic_enable,
1890 .cache_flush = global_cache_flush,
1891 .create_gatt_table = agp_generic_create_gatt_table,
1892 .free_gatt_table = agp_generic_free_gatt_table,
1893 .insert_memory = agp_generic_insert_memory,
1894 .remove_memory = agp_generic_remove_memory,
1895 .alloc_by_type = agp_generic_alloc_by_type,
1896 .free_by_type = agp_generic_free_by_type,
1897 .agp_alloc_page = agp_generic_alloc_page,
1898 .agp_alloc_pages = agp_generic_alloc_pages,
1899 .agp_destroy_page = agp_generic_destroy_page,
1900 .agp_destroy_pages = agp_generic_destroy_pages,
1901 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1902 };
1903
1904 static const struct agp_bridge_driver intel_845_driver = {
1905 .owner = THIS_MODULE,
1906 .aperture_sizes = intel_8xx_sizes,
1907 .size_type = U8_APER_SIZE,
1908 .num_aperture_sizes = 7,
1909 .configure = intel_845_configure,
1910 .fetch_size = intel_8xx_fetch_size,
1911 .cleanup = intel_8xx_cleanup,
1912 .tlb_flush = intel_8xx_tlbflush,
1913 .mask_memory = agp_generic_mask_memory,
1914 .masks = intel_generic_masks,
1915 .agp_enable = agp_generic_enable,
1916 .cache_flush = global_cache_flush,
1917 .create_gatt_table = agp_generic_create_gatt_table,
1918 .free_gatt_table = agp_generic_free_gatt_table,
1919 .insert_memory = agp_generic_insert_memory,
1920 .remove_memory = agp_generic_remove_memory,
1921 .alloc_by_type = agp_generic_alloc_by_type,
1922 .free_by_type = agp_generic_free_by_type,
1923 .agp_alloc_page = agp_generic_alloc_page,
1924 .agp_alloc_pages = agp_generic_alloc_pages,
1925 .agp_destroy_page = agp_generic_destroy_page,
1926 .agp_destroy_pages = agp_generic_destroy_pages,
1927 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1928 .chipset_flush = intel_i830_chipset_flush,
1929 };
1930
1931 static const struct agp_bridge_driver intel_850_driver = {
1932 .owner = THIS_MODULE,
1933 .aperture_sizes = intel_8xx_sizes,
1934 .size_type = U8_APER_SIZE,
1935 .num_aperture_sizes = 7,
1936 .configure = intel_850_configure,
1937 .fetch_size = intel_8xx_fetch_size,
1938 .cleanup = intel_8xx_cleanup,
1939 .tlb_flush = intel_8xx_tlbflush,
1940 .mask_memory = agp_generic_mask_memory,
1941 .masks = intel_generic_masks,
1942 .agp_enable = agp_generic_enable,
1943 .cache_flush = global_cache_flush,
1944 .create_gatt_table = agp_generic_create_gatt_table,
1945 .free_gatt_table = agp_generic_free_gatt_table,
1946 .insert_memory = agp_generic_insert_memory,
1947 .remove_memory = agp_generic_remove_memory,
1948 .alloc_by_type = agp_generic_alloc_by_type,
1949 .free_by_type = agp_generic_free_by_type,
1950 .agp_alloc_page = agp_generic_alloc_page,
1951 .agp_alloc_pages = agp_generic_alloc_pages,
1952 .agp_destroy_page = agp_generic_destroy_page,
1953 .agp_destroy_pages = agp_generic_destroy_pages,
1954 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1955 };
1956
1957 static const struct agp_bridge_driver intel_860_driver = {
1958 .owner = THIS_MODULE,
1959 .aperture_sizes = intel_8xx_sizes,
1960 .size_type = U8_APER_SIZE,
1961 .num_aperture_sizes = 7,
1962 .configure = intel_860_configure,
1963 .fetch_size = intel_8xx_fetch_size,
1964 .cleanup = intel_8xx_cleanup,
1965 .tlb_flush = intel_8xx_tlbflush,
1966 .mask_memory = agp_generic_mask_memory,
1967 .masks = intel_generic_masks,
1968 .agp_enable = agp_generic_enable,
1969 .cache_flush = global_cache_flush,
1970 .create_gatt_table = agp_generic_create_gatt_table,
1971 .free_gatt_table = agp_generic_free_gatt_table,
1972 .insert_memory = agp_generic_insert_memory,
1973 .remove_memory = agp_generic_remove_memory,
1974 .alloc_by_type = agp_generic_alloc_by_type,
1975 .free_by_type = agp_generic_free_by_type,
1976 .agp_alloc_page = agp_generic_alloc_page,
1977 .agp_alloc_pages = agp_generic_alloc_pages,
1978 .agp_destroy_page = agp_generic_destroy_page,
1979 .agp_destroy_pages = agp_generic_destroy_pages,
1980 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
1981 };
1982
1983 static const struct agp_bridge_driver intel_915_driver = {
1984 .owner = THIS_MODULE,
1985 .aperture_sizes = intel_i830_sizes,
1986 .size_type = FIXED_APER_SIZE,
1987 .num_aperture_sizes = 4,
1988 .needs_scratch_page = true,
1989 .configure = intel_i915_configure,
1990 .fetch_size = intel_i9xx_fetch_size,
1991 .cleanup = intel_i915_cleanup,
1992 .tlb_flush = intel_i810_tlbflush,
1993 .mask_memory = intel_i810_mask_memory,
1994 .masks = intel_i810_masks,
1995 .agp_enable = intel_i810_agp_enable,
1996 .cache_flush = global_cache_flush,
1997 .create_gatt_table = intel_i915_create_gatt_table,
1998 .free_gatt_table = intel_i830_free_gatt_table,
1999 .insert_memory = intel_i915_insert_entries,
2000 .remove_memory = intel_i915_remove_entries,
2001 .alloc_by_type = intel_i830_alloc_by_type,
2002 .free_by_type = intel_i810_free_by_type,
2003 .agp_alloc_page = agp_generic_alloc_page,
2004 .agp_alloc_pages = agp_generic_alloc_pages,
2005 .agp_destroy_page = agp_generic_destroy_page,
2006 .agp_destroy_pages = agp_generic_destroy_pages,
2007 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2008 .chipset_flush = intel_i915_chipset_flush,
2009 };
2010
2011 static const struct agp_bridge_driver intel_i965_driver = {
2012 .owner = THIS_MODULE,
2013 .aperture_sizes = intel_i830_sizes,
2014 .size_type = FIXED_APER_SIZE,
2015 .num_aperture_sizes = 4,
2016 .needs_scratch_page = true,
2017 .configure = intel_i915_configure,
2018 .fetch_size = intel_i9xx_fetch_size,
2019 .cleanup = intel_i915_cleanup,
2020 .tlb_flush = intel_i810_tlbflush,
2021 .mask_memory = intel_i965_mask_memory,
2022 .masks = intel_i810_masks,
2023 .agp_enable = intel_i810_agp_enable,
2024 .cache_flush = global_cache_flush,
2025 .create_gatt_table = intel_i965_create_gatt_table,
2026 .free_gatt_table = intel_i830_free_gatt_table,
2027 .insert_memory = intel_i915_insert_entries,
2028 .remove_memory = intel_i915_remove_entries,
2029 .alloc_by_type = intel_i830_alloc_by_type,
2030 .free_by_type = intel_i810_free_by_type,
2031 .agp_alloc_page = agp_generic_alloc_page,
2032 .agp_alloc_pages = agp_generic_alloc_pages,
2033 .agp_destroy_page = agp_generic_destroy_page,
2034 .agp_destroy_pages = agp_generic_destroy_pages,
2035 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2036 .chipset_flush = intel_i915_chipset_flush,
2037 };
2038
2039 static const struct agp_bridge_driver intel_7505_driver = {
2040 .owner = THIS_MODULE,
2041 .aperture_sizes = intel_8xx_sizes,
2042 .size_type = U8_APER_SIZE,
2043 .num_aperture_sizes = 7,
2044 .configure = intel_7505_configure,
2045 .fetch_size = intel_8xx_fetch_size,
2046 .cleanup = intel_8xx_cleanup,
2047 .tlb_flush = intel_8xx_tlbflush,
2048 .mask_memory = agp_generic_mask_memory,
2049 .masks = intel_generic_masks,
2050 .agp_enable = agp_generic_enable,
2051 .cache_flush = global_cache_flush,
2052 .create_gatt_table = agp_generic_create_gatt_table,
2053 .free_gatt_table = agp_generic_free_gatt_table,
2054 .insert_memory = agp_generic_insert_memory,
2055 .remove_memory = agp_generic_remove_memory,
2056 .alloc_by_type = agp_generic_alloc_by_type,
2057 .free_by_type = agp_generic_free_by_type,
2058 .agp_alloc_page = agp_generic_alloc_page,
2059 .agp_alloc_pages = agp_generic_alloc_pages,
2060 .agp_destroy_page = agp_generic_destroy_page,
2061 .agp_destroy_pages = agp_generic_destroy_pages,
2062 .agp_type_to_mask_type = agp_generic_type_to_mask_type,
2063 };
2064
2065 static const struct agp_bridge_driver intel_g33_driver = {
2066 .owner = THIS_MODULE,
2067 .aperture_sizes = intel_i830_sizes,
2068 .size_type = FIXED_APER_SIZE,
2069 .num_aperture_sizes = 4,
2070 .needs_scratch_page = true,
2071 .configure = intel_i915_configure,
2072 .fetch_size = intel_i9xx_fetch_size,
2073 .cleanup = intel_i915_cleanup,
2074 .tlb_flush = intel_i810_tlbflush,
2075 .mask_memory = intel_i965_mask_memory,
2076 .masks = intel_i810_masks,
2077 .agp_enable = intel_i810_agp_enable,
2078 .cache_flush = global_cache_flush,
2079 .create_gatt_table = intel_i915_create_gatt_table,
2080 .free_gatt_table = intel_i830_free_gatt_table,
2081 .insert_memory = intel_i915_insert_entries,
2082 .remove_memory = intel_i915_remove_entries,
2083 .alloc_by_type = intel_i830_alloc_by_type,
2084 .free_by_type = intel_i810_free_by_type,
2085 .agp_alloc_page = agp_generic_alloc_page,
2086 .agp_alloc_pages = agp_generic_alloc_pages,
2087 .agp_destroy_page = agp_generic_destroy_page,
2088 .agp_destroy_pages = agp_generic_destroy_pages,
2089 .agp_type_to_mask_type = intel_i830_type_to_mask_type,
2090 .chipset_flush = intel_i915_chipset_flush,
2091 };
2092
2093 static int find_gmch(u16 device)
2094 {
2095 struct pci_dev *gmch_device;
2096
2097 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL);
2098 if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) {
2099 gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL,
2100 device, gmch_device);
2101 }
2102
2103 if (!gmch_device)
2104 return 0;
2105
2106 intel_private.pcidev = gmch_device;
2107 return 1;
2108 }
2109
2110 /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of
2111 * driver and gmch_driver must be non-null, and find_gmch will determine
2112 * which one should be used if a gmch_chip_id is present.
2113 */
2114 static const struct intel_driver_description {
2115 unsigned int chip_id;
2116 unsigned int gmch_chip_id;
2117 unsigned int multi_gmch_chip; /* if we have more gfx chip type on this HB. */
2118 char *name;
2119 const struct agp_bridge_driver *driver;
2120 const struct agp_bridge_driver *gmch_driver;
2121 } intel_agp_chipsets[] = {
2122 { PCI_DEVICE_ID_INTEL_82443LX_0, 0, 0, "440LX", &intel_generic_driver, NULL },
2123 { PCI_DEVICE_ID_INTEL_82443BX_0, 0, 0, "440BX", &intel_generic_driver, NULL },
2124 { PCI_DEVICE_ID_INTEL_82443GX_0, 0, 0, "440GX", &intel_generic_driver, NULL },
2125 { PCI_DEVICE_ID_INTEL_82810_MC1, PCI_DEVICE_ID_INTEL_82810_IG1, 0, "i810",
2126 NULL, &intel_810_driver },
2127 { PCI_DEVICE_ID_INTEL_82810_MC3, PCI_DEVICE_ID_INTEL_82810_IG3, 0, "i810",
2128 NULL, &intel_810_driver },
2129 { PCI_DEVICE_ID_INTEL_82810E_MC, PCI_DEVICE_ID_INTEL_82810E_IG, 0, "i810",
2130 NULL, &intel_810_driver },
2131 { PCI_DEVICE_ID_INTEL_82815_MC, PCI_DEVICE_ID_INTEL_82815_CGC, 0, "i815",
2132 &intel_815_driver, &intel_810_driver },
2133 { PCI_DEVICE_ID_INTEL_82820_HB, 0, 0, "i820", &intel_820_driver, NULL },
2134 { PCI_DEVICE_ID_INTEL_82820_UP_HB, 0, 0, "i820", &intel_820_driver, NULL },
2135 { PCI_DEVICE_ID_INTEL_82830_HB, PCI_DEVICE_ID_INTEL_82830_CGC, 0, "830M",
2136 &intel_830mp_driver, &intel_830_driver },
2137 { PCI_DEVICE_ID_INTEL_82840_HB, 0, 0, "i840", &intel_840_driver, NULL },
2138 { PCI_DEVICE_ID_INTEL_82845_HB, 0, 0, "845G", &intel_845_driver, NULL },
2139 { PCI_DEVICE_ID_INTEL_82845G_HB, PCI_DEVICE_ID_INTEL_82845G_IG, 0, "830M",
2140 &intel_845_driver, &intel_830_driver },
2141 { PCI_DEVICE_ID_INTEL_82850_HB, 0, 0, "i850", &intel_850_driver, NULL },
2142 { PCI_DEVICE_ID_INTEL_82854_HB, PCI_DEVICE_ID_INTEL_82854_IG, 0, "854",
2143 &intel_845_driver, &intel_830_driver },
2144 { PCI_DEVICE_ID_INTEL_82855PM_HB, 0, 0, "855PM", &intel_845_driver, NULL },
2145 { PCI_DEVICE_ID_INTEL_82855GM_HB, PCI_DEVICE_ID_INTEL_82855GM_IG, 0, "855GM",
2146 &intel_845_driver, &intel_830_driver },
2147 { PCI_DEVICE_ID_INTEL_82860_HB, 0, 0, "i860", &intel_860_driver, NULL },
2148 { PCI_DEVICE_ID_INTEL_82865_HB, PCI_DEVICE_ID_INTEL_82865_IG, 0, "865",
2149 &intel_845_driver, &intel_830_driver },
2150 { PCI_DEVICE_ID_INTEL_82875_HB, 0, 0, "i875", &intel_845_driver, NULL },
2151 { PCI_DEVICE_ID_INTEL_E7221_HB, PCI_DEVICE_ID_INTEL_E7221_IG, 0, "E7221 (i915)",
2152 NULL, &intel_915_driver },
2153 { PCI_DEVICE_ID_INTEL_82915G_HB, PCI_DEVICE_ID_INTEL_82915G_IG, 0, "915G",
2154 NULL, &intel_915_driver },
2155 { PCI_DEVICE_ID_INTEL_82915GM_HB, PCI_DEVICE_ID_INTEL_82915GM_IG, 0, "915GM",
2156 NULL, &intel_915_driver },
2157 { PCI_DEVICE_ID_INTEL_82945G_HB, PCI_DEVICE_ID_INTEL_82945G_IG, 0, "945G",
2158 NULL, &intel_915_driver },
2159 { PCI_DEVICE_ID_INTEL_82945GM_HB, PCI_DEVICE_ID_INTEL_82945GM_IG, 0, "945GM",
2160 NULL, &intel_915_driver },
2161 { PCI_DEVICE_ID_INTEL_82945GME_HB, PCI_DEVICE_ID_INTEL_82945GME_IG, 0, "945GME",
2162 NULL, &intel_915_driver },
2163 { PCI_DEVICE_ID_INTEL_82946GZ_HB, PCI_DEVICE_ID_INTEL_82946GZ_IG, 0, "946GZ",
2164 NULL, &intel_i965_driver },
2165 { PCI_DEVICE_ID_INTEL_82G35_HB, PCI_DEVICE_ID_INTEL_82G35_IG, 0, "G35",
2166 NULL, &intel_i965_driver },
2167 { PCI_DEVICE_ID_INTEL_82965Q_HB, PCI_DEVICE_ID_INTEL_82965Q_IG, 0, "965Q",
2168 NULL, &intel_i965_driver },
2169 { PCI_DEVICE_ID_INTEL_82965G_HB, PCI_DEVICE_ID_INTEL_82965G_IG, 0, "965G",
2170 NULL, &intel_i965_driver },
2171 { PCI_DEVICE_ID_INTEL_82965GM_HB, PCI_DEVICE_ID_INTEL_82965GM_IG, 0, "965GM",
2172 NULL, &intel_i965_driver },
2173 { PCI_DEVICE_ID_INTEL_82965GME_HB, PCI_DEVICE_ID_INTEL_82965GME_IG, 0, "965GME/GLE",
2174 NULL, &intel_i965_driver },
2175 { PCI_DEVICE_ID_INTEL_7505_0, 0, 0, "E7505", &intel_7505_driver, NULL },
2176 { PCI_DEVICE_ID_INTEL_7205_0, 0, 0, "E7205", &intel_7505_driver, NULL },
2177 { PCI_DEVICE_ID_INTEL_G33_HB, PCI_DEVICE_ID_INTEL_G33_IG, 0, "G33",
2178 NULL, &intel_g33_driver },
2179 { PCI_DEVICE_ID_INTEL_Q35_HB, PCI_DEVICE_ID_INTEL_Q35_IG, 0, "Q35",
2180 NULL, &intel_g33_driver },
2181 { PCI_DEVICE_ID_INTEL_Q33_HB, PCI_DEVICE_ID_INTEL_Q33_IG, 0, "Q33",
2182 NULL, &intel_g33_driver },
2183 { PCI_DEVICE_ID_INTEL_IGDGM_HB, PCI_DEVICE_ID_INTEL_IGDGM_IG, 0, "IGD",
2184 NULL, &intel_g33_driver },
2185 { PCI_DEVICE_ID_INTEL_IGDG_HB, PCI_DEVICE_ID_INTEL_IGDG_IG, 0, "IGD",
2186 NULL, &intel_g33_driver },
2187 { PCI_DEVICE_ID_INTEL_GM45_HB, PCI_DEVICE_ID_INTEL_GM45_IG, 0,
2188 "Mobile Intel® GM45 Express", NULL, &intel_i965_driver },
2189 { PCI_DEVICE_ID_INTEL_IGD_E_HB, PCI_DEVICE_ID_INTEL_IGD_E_IG, 0,
2190 "Intel Integrated Graphics Device", NULL, &intel_i965_driver },
2191 { PCI_DEVICE_ID_INTEL_Q45_HB, PCI_DEVICE_ID_INTEL_Q45_IG, 0,
2192 "Q45/Q43", NULL, &intel_i965_driver },
2193 { PCI_DEVICE_ID_INTEL_G45_HB, PCI_DEVICE_ID_INTEL_G45_IG, 0,
2194 "G45/G43", NULL, &intel_i965_driver },
2195 { PCI_DEVICE_ID_INTEL_G41_HB, PCI_DEVICE_ID_INTEL_G41_IG, 0,
2196 "G41", NULL, &intel_i965_driver },
2197 { PCI_DEVICE_ID_INTEL_IGDNG_D_HB, PCI_DEVICE_ID_INTEL_IGDNG_D_IG, 0,
2198 "IGDNG/D", NULL, &intel_i965_driver },
2199 { PCI_DEVICE_ID_INTEL_IGDNG_M_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2200 "IGDNG/M", NULL, &intel_i965_driver },
2201 { PCI_DEVICE_ID_INTEL_IGDNG_MA_HB, PCI_DEVICE_ID_INTEL_IGDNG_M_IG, 0,
2202 "IGDNG/MA", NULL, &intel_i965_driver },
2203 { 0, 0, 0, NULL, NULL, NULL }
2204 };
2205
2206 static int __devinit agp_intel_probe(struct pci_dev *pdev,
2207 const struct pci_device_id *ent)
2208 {
2209 struct agp_bridge_data *bridge;
2210 u8 cap_ptr = 0;
2211 struct resource *r;
2212 int i;
2213
2214 cap_ptr = pci_find_capability(pdev, PCI_CAP_ID_AGP);
2215
2216 bridge = agp_alloc_bridge();
2217 if (!bridge)
2218 return -ENOMEM;
2219
2220 for (i = 0; intel_agp_chipsets[i].name != NULL; i++) {
2221 /* In case that multiple models of gfx chip may
2222 stand on same host bridge type, this can be
2223 sure we detect the right IGD. */
2224 if (pdev->device == intel_agp_chipsets[i].chip_id) {
2225 if ((intel_agp_chipsets[i].gmch_chip_id != 0) &&
2226 find_gmch(intel_agp_chipsets[i].gmch_chip_id)) {
2227 bridge->driver =
2228 intel_agp_chipsets[i].gmch_driver;
2229 break;
2230 } else if (intel_agp_chipsets[i].multi_gmch_chip) {
2231 continue;
2232 } else {
2233 bridge->driver = intel_agp_chipsets[i].driver;
2234 break;
2235 }
2236 }
2237 }
2238
2239 if (intel_agp_chipsets[i].name == NULL) {
2240 if (cap_ptr)
2241 dev_warn(&pdev->dev, "unsupported Intel chipset [%04x/%04x]\n",
2242 pdev->vendor, pdev->device);
2243 agp_put_bridge(bridge);
2244 return -ENODEV;
2245 }
2246
2247 if (bridge->driver == NULL) {
2248 /* bridge has no AGP and no IGD detected */
2249 if (cap_ptr)
2250 dev_warn(&pdev->dev, "can't find bridge device (chip_id: %04x)\n",
2251 intel_agp_chipsets[i].gmch_chip_id);
2252 agp_put_bridge(bridge);
2253 return -ENODEV;
2254 }
2255
2256 bridge->dev = pdev;
2257 bridge->capndx = cap_ptr;
2258 bridge->dev_private_data = &intel_private;
2259
2260 dev_info(&pdev->dev, "Intel %s Chipset\n", intel_agp_chipsets[i].name);
2261
2262 /*
2263 * The following fixes the case where the BIOS has "forgotten" to
2264 * provide an address range for the GART.
2265 * 20030610 - hamish@zot.org
2266 */
2267 r = &pdev->resource[0];
2268 if (!r->start && r->end) {
2269 if (pci_assign_resource(pdev, 0)) {
2270 dev_err(&pdev->dev, "can't assign resource 0\n");
2271 agp_put_bridge(bridge);
2272 return -ENODEV;
2273 }
2274 }
2275
2276 /*
2277 * If the device has not been properly setup, the following will catch
2278 * the problem and should stop the system from crashing.
2279 * 20030610 - hamish@zot.org
2280 */
2281 if (pci_enable_device(pdev)) {
2282 dev_err(&pdev->dev, "can't enable PCI device\n");
2283 agp_put_bridge(bridge);
2284 return -ENODEV;
2285 }
2286
2287 /* Fill in the mode register */
2288 if (cap_ptr) {
2289 pci_read_config_dword(pdev,
2290 bridge->capndx+PCI_AGP_STATUS,
2291 &bridge->mode);
2292 }
2293
2294 pci_set_drvdata(pdev, bridge);
2295 return agp_add_bridge(bridge);
2296 }
2297
2298 static void __devexit agp_intel_remove(struct pci_dev *pdev)
2299 {
2300 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2301
2302 agp_remove_bridge(bridge);
2303
2304 if (intel_private.pcidev)
2305 pci_dev_put(intel_private.pcidev);
2306
2307 agp_put_bridge(bridge);
2308 }
2309
2310 #ifdef CONFIG_PM
2311 static int agp_intel_resume(struct pci_dev *pdev)
2312 {
2313 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
2314 int ret_val;
2315
2316 pci_restore_state(pdev);
2317
2318 /* We should restore our graphics device's config space,
2319 * as host bridge (00:00) resumes before graphics device (02:00),
2320 * then our access to its pci space can work right.
2321 */
2322 if (intel_private.pcidev)
2323 pci_restore_state(intel_private.pcidev);
2324
2325 if (bridge->driver == &intel_generic_driver)
2326 intel_configure();
2327 else if (bridge->driver == &intel_850_driver)
2328 intel_850_configure();
2329 else if (bridge->driver == &intel_845_driver)
2330 intel_845_configure();
2331 else if (bridge->driver == &intel_830mp_driver)
2332 intel_830mp_configure();
2333 else if (bridge->driver == &intel_915_driver)
2334 intel_i915_configure();
2335 else if (bridge->driver == &intel_830_driver)
2336 intel_i830_configure();
2337 else if (bridge->driver == &intel_810_driver)
2338 intel_i810_configure();
2339 else if (bridge->driver == &intel_i965_driver)
2340 intel_i915_configure();
2341
2342 ret_val = agp_rebind_memory();
2343 if (ret_val != 0)
2344 return ret_val;
2345
2346 return 0;
2347 }
2348 #endif
2349
2350 static struct pci_device_id agp_intel_pci_table[] = {
2351 #define ID(x) \
2352 { \
2353 .class = (PCI_CLASS_BRIDGE_HOST << 8), \
2354 .class_mask = ~0, \
2355 .vendor = PCI_VENDOR_ID_INTEL, \
2356 .device = x, \
2357 .subvendor = PCI_ANY_ID, \
2358 .subdevice = PCI_ANY_ID, \
2359 }
2360 ID(PCI_DEVICE_ID_INTEL_82443LX_0),
2361 ID(PCI_DEVICE_ID_INTEL_82443BX_0),
2362 ID(PCI_DEVICE_ID_INTEL_82443GX_0),
2363 ID(PCI_DEVICE_ID_INTEL_82810_MC1),
2364 ID(PCI_DEVICE_ID_INTEL_82810_MC3),
2365 ID(PCI_DEVICE_ID_INTEL_82810E_MC),
2366 ID(PCI_DEVICE_ID_INTEL_82815_MC),
2367 ID(PCI_DEVICE_ID_INTEL_82820_HB),
2368 ID(PCI_DEVICE_ID_INTEL_82820_UP_HB),
2369 ID(PCI_DEVICE_ID_INTEL_82830_HB),
2370 ID(PCI_DEVICE_ID_INTEL_82840_HB),
2371 ID(PCI_DEVICE_ID_INTEL_82845_HB),
2372 ID(PCI_DEVICE_ID_INTEL_82845G_HB),
2373 ID(PCI_DEVICE_ID_INTEL_82850_HB),
2374 ID(PCI_DEVICE_ID_INTEL_82854_HB),
2375 ID(PCI_DEVICE_ID_INTEL_82855PM_HB),
2376 ID(PCI_DEVICE_ID_INTEL_82855GM_HB),
2377 ID(PCI_DEVICE_ID_INTEL_82860_HB),
2378 ID(PCI_DEVICE_ID_INTEL_82865_HB),
2379 ID(PCI_DEVICE_ID_INTEL_82875_HB),
2380 ID(PCI_DEVICE_ID_INTEL_7505_0),
2381 ID(PCI_DEVICE_ID_INTEL_7205_0),
2382 ID(PCI_DEVICE_ID_INTEL_E7221_HB),
2383 ID(PCI_DEVICE_ID_INTEL_82915G_HB),
2384 ID(PCI_DEVICE_ID_INTEL_82915GM_HB),
2385 ID(PCI_DEVICE_ID_INTEL_82945G_HB),
2386 ID(PCI_DEVICE_ID_INTEL_82945GM_HB),
2387 ID(PCI_DEVICE_ID_INTEL_82945GME_HB),
2388 ID(PCI_DEVICE_ID_INTEL_IGDGM_HB),
2389 ID(PCI_DEVICE_ID_INTEL_IGDG_HB),
2390 ID(PCI_DEVICE_ID_INTEL_82946GZ_HB),
2391 ID(PCI_DEVICE_ID_INTEL_82G35_HB),
2392 ID(PCI_DEVICE_ID_INTEL_82965Q_HB),
2393 ID(PCI_DEVICE_ID_INTEL_82965G_HB),
2394 ID(PCI_DEVICE_ID_INTEL_82965GM_HB),
2395 ID(PCI_DEVICE_ID_INTEL_82965GME_HB),
2396 ID(PCI_DEVICE_ID_INTEL_G33_HB),
2397 ID(PCI_DEVICE_ID_INTEL_Q35_HB),
2398 ID(PCI_DEVICE_ID_INTEL_Q33_HB),
2399 ID(PCI_DEVICE_ID_INTEL_GM45_HB),
2400 ID(PCI_DEVICE_ID_INTEL_IGD_E_HB),
2401 ID(PCI_DEVICE_ID_INTEL_Q45_HB),
2402 ID(PCI_DEVICE_ID_INTEL_G45_HB),
2403 ID(PCI_DEVICE_ID_INTEL_G41_HB),
2404 ID(PCI_DEVICE_ID_INTEL_IGDNG_D_HB),
2405 ID(PCI_DEVICE_ID_INTEL_IGDNG_M_HB),
2406 ID(PCI_DEVICE_ID_INTEL_IGDNG_MA_HB),
2407 { }
2408 };
2409
2410 MODULE_DEVICE_TABLE(pci, agp_intel_pci_table);
2411
2412 static struct pci_driver agp_intel_pci_driver = {
2413 .name = "agpgart-intel",
2414 .id_table = agp_intel_pci_table,
2415 .probe = agp_intel_probe,
2416 .remove = __devexit_p(agp_intel_remove),
2417 #ifdef CONFIG_PM
2418 .resume = agp_intel_resume,
2419 #endif
2420 };
2421
2422 static int __init agp_intel_init(void)
2423 {
2424 if (agp_off)
2425 return -EINVAL;
2426 return pci_register_driver(&agp_intel_pci_driver);
2427 }
2428
2429 static void __exit agp_intel_cleanup(void)
2430 {
2431 pci_unregister_driver(&agp_intel_pci_driver);
2432 }
2433
2434 module_init(agp_intel_init);
2435 module_exit(agp_intel_cleanup);
2436
2437 MODULE_AUTHOR("Dave Jones <davej@redhat.com>");
2438 MODULE_LICENSE("GPL and additional rights");
Linux with added FPC-III support