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Driver Core: devtmpfs - kernel-maintained tmpfs-based /dev
[linux/fpc-iii.git] / drivers / media / video / cx23885 / cx23885-417.c
blob1a1048b18f7027c67eed1eac69b30fd1ad0b055d
1 /*
2 *
3 * Support for a cx23417 mpeg encoder via cx23885 host port.
4 *
5 * (c) 2004 Jelle Foks <jelle@foks.us>
6 * (c) 2004 Gerd Knorr <kraxel@bytesex.org>
7 * (c) 2008 Steven Toth <stoth@linuxtv.org>
8 * - CX23885/7/8 support
9 *
10 * Includes parts from the ivtv driver( http://ivtv.sourceforge.net/),
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/init.h>
30 #include <linux/fs.h>
31 #include <linux/delay.h>
32 #include <linux/device.h>
33 #include <linux/firmware.h>
34 #include <linux/smp_lock.h>
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-ioctl.h>
37 #include <media/cx2341x.h>
38
39 #include "cx23885.h"
40
41 #define CX23885_FIRM_IMAGE_SIZE 376836
42 #define CX23885_FIRM_IMAGE_NAME "v4l-cx23885-enc.fw"
43
44 static unsigned int mpegbufs = 32;
45 module_param(mpegbufs, int, 0644);
46 MODULE_PARM_DESC(mpegbufs, "number of mpeg buffers, range 2-32");
47 static unsigned int mpeglines = 32;
48 module_param(mpeglines, int, 0644);
49 MODULE_PARM_DESC(mpeglines, "number of lines in an MPEG buffer, range 2-32");
50 static unsigned int mpeglinesize = 512;
51 module_param(mpeglinesize, int, 0644);
52 MODULE_PARM_DESC(mpeglinesize,
53 "number of bytes in each line of an MPEG buffer, range 512-1024");
54
55 static unsigned int v4l_debug;
56 module_param(v4l_debug, int, 0644);
57 MODULE_PARM_DESC(v4l_debug, "enable V4L debug messages");
58
59 #define dprintk(level, fmt, arg...)\
60 do { if (v4l_debug >= level) \
61 printk(KERN_DEBUG "%s: " fmt, \
62 (dev) ? dev->name : "cx23885[?]", ## arg); \
63 } while (0)
64
65 static struct cx23885_tvnorm cx23885_tvnorms[] = {
66 {
67 .name = "NTSC-M",
68 .id = V4L2_STD_NTSC_M,
69 }, {
70 .name = "NTSC-JP",
71 .id = V4L2_STD_NTSC_M_JP,
72 }, {
73 .name = "PAL-BG",
74 .id = V4L2_STD_PAL_BG,
75 }, {
76 .name = "PAL-DK",
77 .id = V4L2_STD_PAL_DK,
78 }, {
79 .name = "PAL-I",
80 .id = V4L2_STD_PAL_I,
81 }, {
82 .name = "PAL-M",
83 .id = V4L2_STD_PAL_M,
84 }, {
85 .name = "PAL-N",
86 .id = V4L2_STD_PAL_N,
87 }, {
88 .name = "PAL-Nc",
89 .id = V4L2_STD_PAL_Nc,
90 }, {
91 .name = "PAL-60",
92 .id = V4L2_STD_PAL_60,
93 }, {
94 .name = "SECAM-L",
95 .id = V4L2_STD_SECAM_L,
96 }, {
97 .name = "SECAM-DK",
98 .id = V4L2_STD_SECAM_DK,
99 }
100 };
101
102 /* ------------------------------------------------------------------ */
103 enum cx23885_capture_type {
104 CX23885_MPEG_CAPTURE,
105 CX23885_RAW_CAPTURE,
106 CX23885_RAW_PASSTHRU_CAPTURE
107 };
108 enum cx23885_capture_bits {
109 CX23885_RAW_BITS_NONE = 0x00,
110 CX23885_RAW_BITS_YUV_CAPTURE = 0x01,
111 CX23885_RAW_BITS_PCM_CAPTURE = 0x02,
112 CX23885_RAW_BITS_VBI_CAPTURE = 0x04,
113 CX23885_RAW_BITS_PASSTHRU_CAPTURE = 0x08,
114 CX23885_RAW_BITS_TO_HOST_CAPTURE = 0x10
115 };
116 enum cx23885_capture_end {
117 CX23885_END_AT_GOP, /* stop at the end of gop, generate irq */
118 CX23885_END_NOW, /* stop immediately, no irq */
119 };
120 enum cx23885_framerate {
121 CX23885_FRAMERATE_NTSC_30, /* NTSC: 30fps */
122 CX23885_FRAMERATE_PAL_25 /* PAL: 25fps */
123 };
124 enum cx23885_stream_port {
125 CX23885_OUTPUT_PORT_MEMORY,
126 CX23885_OUTPUT_PORT_STREAMING,
127 CX23885_OUTPUT_PORT_SERIAL
128 };
129 enum cx23885_data_xfer_status {
130 CX23885_MORE_BUFFERS_FOLLOW,
131 CX23885_LAST_BUFFER,
132 };
133 enum cx23885_picture_mask {
134 CX23885_PICTURE_MASK_NONE,
135 CX23885_PICTURE_MASK_I_FRAMES,
136 CX23885_PICTURE_MASK_I_P_FRAMES = 0x3,
137 CX23885_PICTURE_MASK_ALL_FRAMES = 0x7,
138 };
139 enum cx23885_vbi_mode_bits {
140 CX23885_VBI_BITS_SLICED,
141 CX23885_VBI_BITS_RAW,
142 };
143 enum cx23885_vbi_insertion_bits {
144 CX23885_VBI_BITS_INSERT_IN_XTENSION_USR_DATA,
145 CX23885_VBI_BITS_INSERT_IN_PRIVATE_PACKETS = 0x1 << 1,
146 CX23885_VBI_BITS_SEPARATE_STREAM = 0x2 << 1,
147 CX23885_VBI_BITS_SEPARATE_STREAM_USR_DATA = 0x4 << 1,
148 CX23885_VBI_BITS_SEPARATE_STREAM_PRV_DATA = 0x5 << 1,
149 };
150 enum cx23885_dma_unit {
151 CX23885_DMA_BYTES,
152 CX23885_DMA_FRAMES,
153 };
154 enum cx23885_dma_transfer_status_bits {
155 CX23885_DMA_TRANSFER_BITS_DONE = 0x01,
156 CX23885_DMA_TRANSFER_BITS_ERROR = 0x04,
157 CX23885_DMA_TRANSFER_BITS_LL_ERROR = 0x10,
158 };
159 enum cx23885_pause {
160 CX23885_PAUSE_ENCODING,
161 CX23885_RESUME_ENCODING,
162 };
163 enum cx23885_copyright {
164 CX23885_COPYRIGHT_OFF,
165 CX23885_COPYRIGHT_ON,
166 };
167 enum cx23885_notification_type {
168 CX23885_NOTIFICATION_REFRESH,
169 };
170 enum cx23885_notification_status {
171 CX23885_NOTIFICATION_OFF,
172 CX23885_NOTIFICATION_ON,
173 };
174 enum cx23885_notification_mailbox {
175 CX23885_NOTIFICATION_NO_MAILBOX = -1,
176 };
177 enum cx23885_field1_lines {
178 CX23885_FIELD1_SAA7114 = 0x00EF, /* 239 */
179 CX23885_FIELD1_SAA7115 = 0x00F0, /* 240 */
180 CX23885_FIELD1_MICRONAS = 0x0105, /* 261 */
181 };
182 enum cx23885_field2_lines {
183 CX23885_FIELD2_SAA7114 = 0x00EF, /* 239 */
184 CX23885_FIELD2_SAA7115 = 0x00F0, /* 240 */
185 CX23885_FIELD2_MICRONAS = 0x0106, /* 262 */
186 };
187 enum cx23885_custom_data_type {
188 CX23885_CUSTOM_EXTENSION_USR_DATA,
189 CX23885_CUSTOM_PRIVATE_PACKET,
190 };
191 enum cx23885_mute {
192 CX23885_UNMUTE,
193 CX23885_MUTE,
194 };
195 enum cx23885_mute_video_mask {
196 CX23885_MUTE_VIDEO_V_MASK = 0x0000FF00,
197 CX23885_MUTE_VIDEO_U_MASK = 0x00FF0000,
198 CX23885_MUTE_VIDEO_Y_MASK = 0xFF000000,
199 };
200 enum cx23885_mute_video_shift {
201 CX23885_MUTE_VIDEO_V_SHIFT = 8,
202 CX23885_MUTE_VIDEO_U_SHIFT = 16,
203 CX23885_MUTE_VIDEO_Y_SHIFT = 24,
204 };
205
206 /* defines below are from ivtv-driver.h */
207 #define IVTV_CMD_HW_BLOCKS_RST 0xFFFFFFFF
208
209 /* Firmware API commands */
210 #define IVTV_API_STD_TIMEOUT 500
211
212 /* Registers */
213 /* IVTV_REG_OFFSET */
214 #define IVTV_REG_ENC_SDRAM_REFRESH (0x07F8)
215 #define IVTV_REG_ENC_SDRAM_PRECHARGE (0x07FC)
216 #define IVTV_REG_SPU (0x9050)
217 #define IVTV_REG_HW_BLOCKS (0x9054)
218 #define IVTV_REG_VPU (0x9058)
219 #define IVTV_REG_APU (0xA064)
220
221 /**** Bit definitions for MC417_RWD and MC417_OEN registers ***
222 bits 31-16
223 +-----------+
224 | Reserved |
225 +-----------+
226 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8
227 +-------+-------+-------+-------+-------+-------+-------+-------+
228 | MIWR# | MIRD# | MICS# |MIRDY# |MIADDR3|MIADDR2|MIADDR1|MIADDR0|
229 +-------+-------+-------+-------+-------+-------+-------+-------+
230 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
231 +-------+-------+-------+-------+-------+-------+-------+-------+
232 |MIDATA7|MIDATA6|MIDATA5|MIDATA4|MIDATA3|MIDATA2|MIDATA1|MIDATA0|
233 +-------+-------+-------+-------+-------+-------+-------+-------+
234 ***/
235 #define MC417_MIWR 0x8000
236 #define MC417_MIRD 0x4000
237 #define MC417_MICS 0x2000
238 #define MC417_MIRDY 0x1000
239 #define MC417_MIADDR 0x0F00
240 #define MC417_MIDATA 0x00FF
241
242 /* MIADDR* nibble definitions */
243 #define MCI_MEMORY_DATA_BYTE0 0x000
244 #define MCI_MEMORY_DATA_BYTE1 0x100
245 #define MCI_MEMORY_DATA_BYTE2 0x200
246 #define MCI_MEMORY_DATA_BYTE3 0x300
247 #define MCI_MEMORY_ADDRESS_BYTE2 0x400
248 #define MCI_MEMORY_ADDRESS_BYTE1 0x500
249 #define MCI_MEMORY_ADDRESS_BYTE0 0x600
250 #define MCI_REGISTER_DATA_BYTE0 0x800
251 #define MCI_REGISTER_DATA_BYTE1 0x900
252 #define MCI_REGISTER_DATA_BYTE2 0xA00
253 #define MCI_REGISTER_DATA_BYTE3 0xB00
254 #define MCI_REGISTER_ADDRESS_BYTE0 0xC00
255 #define MCI_REGISTER_ADDRESS_BYTE1 0xD00
256 #define MCI_REGISTER_MODE 0xE00
257
258 /* Read and write modes */
259 #define MCI_MODE_REGISTER_READ 0
260 #define MCI_MODE_REGISTER_WRITE 1
261 #define MCI_MODE_MEMORY_READ 0
262 #define MCI_MODE_MEMORY_WRITE 0x40
263
264 /*** Bit definitions for MC417_CTL register ****
265 bits 31-6 bits 5-4 bit 3 bits 2-1 Bit 0
266 +--------+-------------+--------+--------------+------------+
267 |Reserved|MC417_SPD_CTL|Reserved|MC417_GPIO_SEL|UART_GPIO_EN|
268 +--------+-------------+--------+--------------+------------+
269 ***/
270 #define MC417_SPD_CTL(x) (((x) << 4) & 0x00000030)
271 #define MC417_GPIO_SEL(x) (((x) << 1) & 0x00000006)
272 #define MC417_UART_GPIO_EN 0x00000001
273
274 /* Values for speed control */
275 #define MC417_SPD_CTL_SLOW 0x1
276 #define MC417_SPD_CTL_MEDIUM 0x0
277 #define MC417_SPD_CTL_FAST 0x3 /* b'1x, but we use b'11 */
278
279 /* Values for GPIO select */
280 #define MC417_GPIO_SEL_GPIO3 0x3
281 #define MC417_GPIO_SEL_GPIO2 0x2
282 #define MC417_GPIO_SEL_GPIO1 0x1
283 #define MC417_GPIO_SEL_GPIO0 0x0
284
285 void cx23885_mc417_init(struct cx23885_dev *dev)
286 {
287 u32 regval;
288
289 dprintk(2, "%s()\n", __func__);
290
291 /* Configure MC417_CTL register to defaults. */
292 regval = MC417_SPD_CTL(MC417_SPD_CTL_FAST) |
293 MC417_GPIO_SEL(MC417_GPIO_SEL_GPIO3) |
294 MC417_UART_GPIO_EN;
295 cx_write(MC417_CTL, regval);
296
297 /* Configure MC417_OEN to defaults. */
298 regval = MC417_MIRDY;
299 cx_write(MC417_OEN, regval);
300
301 /* Configure MC417_RWD to defaults. */
302 regval = MC417_MIWR | MC417_MIRD | MC417_MICS;
303 cx_write(MC417_RWD, regval);
304 }
305
306 static int mc417_wait_ready(struct cx23885_dev *dev)
307 {
308 u32 mi_ready;
309 unsigned long timeout = jiffies + msecs_to_jiffies(1);
310
311 for (;;) {
312 mi_ready = cx_read(MC417_RWD) & MC417_MIRDY;
313 if (mi_ready != 0)
314 return 0;
315 if (time_after(jiffies, timeout))
316 return -1;
317 udelay(1);
318 }
319 }
320
321 static int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value)
322 {
323 u32 regval;
324
325 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
326 * which is an input.
327 */
328 cx_write(MC417_OEN, MC417_MIRDY);
329
330 /* Write data byte 0 */
331 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0 |
332 (value & 0x000000FF);
333 cx_write(MC417_RWD, regval);
334
335 /* Transition CS/WR to effect write transaction across bus. */
336 regval |= MC417_MICS | MC417_MIWR;
337 cx_write(MC417_RWD, regval);
338
339 /* Write data byte 1 */
340 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1 |
341 ((value >> 8) & 0x000000FF);
342 cx_write(MC417_RWD, regval);
343 regval |= MC417_MICS | MC417_MIWR;
344 cx_write(MC417_RWD, regval);
345
346 /* Write data byte 2 */
347 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2 |
348 ((value >> 16) & 0x000000FF);
349 cx_write(MC417_RWD, regval);
350 regval |= MC417_MICS | MC417_MIWR;
351 cx_write(MC417_RWD, regval);
352
353 /* Write data byte 3 */
354 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3 |
355 ((value >> 24) & 0x000000FF);
356 cx_write(MC417_RWD, regval);
357 regval |= MC417_MICS | MC417_MIWR;
358 cx_write(MC417_RWD, regval);
359
360 /* Write address byte 0 */
361 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
362 (address & 0xFF);
363 cx_write(MC417_RWD, regval);
364 regval |= MC417_MICS | MC417_MIWR;
365 cx_write(MC417_RWD, regval);
366
367 /* Write address byte 1 */
368 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
369 ((address >> 8) & 0xFF);
370 cx_write(MC417_RWD, regval);
371 regval |= MC417_MICS | MC417_MIWR;
372 cx_write(MC417_RWD, regval);
373
374 /* Indicate that this is a write. */
375 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
376 MCI_MODE_REGISTER_WRITE;
377 cx_write(MC417_RWD, regval);
378 regval |= MC417_MICS | MC417_MIWR;
379 cx_write(MC417_RWD, regval);
380
381 /* Wait for the trans to complete (MC417_MIRDY asserted). */
382 return mc417_wait_ready(dev);
383 }
384
385 static int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value)
386 {
387 int retval;
388 u32 regval;
389 u32 tempval;
390 u32 dataval;
391
392 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
393 * which is an input.
394 */
395 cx_write(MC417_OEN, MC417_MIRDY);
396
397 /* Write address byte 0 */
398 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE0 |
399 ((address & 0x00FF));
400 cx_write(MC417_RWD, regval);
401 regval |= MC417_MICS | MC417_MIWR;
402 cx_write(MC417_RWD, regval);
403
404 /* Write address byte 1 */
405 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_ADDRESS_BYTE1 |
406 ((address >> 8) & 0xFF);
407 cx_write(MC417_RWD, regval);
408 regval |= MC417_MICS | MC417_MIWR;
409 cx_write(MC417_RWD, regval);
410
411 /* Indicate that this is a register read. */
412 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_MODE |
413 MCI_MODE_REGISTER_READ;
414 cx_write(MC417_RWD, regval);
415 regval |= MC417_MICS | MC417_MIWR;
416 cx_write(MC417_RWD, regval);
417
418 /* Wait for the trans to complete (MC417_MIRDY asserted). */
419 retval = mc417_wait_ready(dev);
420
421 /* switch the DAT0-7 GPIO[10:3] to input mode */
422 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
423
424 /* Read data byte 0 */
425 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
426 cx_write(MC417_RWD, regval);
427
428 /* Transition RD to effect read transaction across bus.
429 * Transtion 0x5000 -> 0x9000 correct (RD/RDY -> WR/RDY)?
430 * Should it be 0x9000 -> 0xF000 (also why is RDY being set, its
431 * input only...)
432 */
433 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE0;
434 cx_write(MC417_RWD, regval);
435
436 /* Collect byte */
437 tempval = cx_read(MC417_RWD);
438 dataval = tempval & 0x000000FF;
439
440 /* Bring CS and RD high. */
441 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
442 cx_write(MC417_RWD, regval);
443
444 /* Read data byte 1 */
445 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
446 cx_write(MC417_RWD, regval);
447 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE1;
448 cx_write(MC417_RWD, regval);
449 tempval = cx_read(MC417_RWD);
450 dataval |= ((tempval & 0x000000FF) << 8);
451 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
452 cx_write(MC417_RWD, regval);
453
454 /* Read data byte 2 */
455 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
456 cx_write(MC417_RWD, regval);
457 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE2;
458 cx_write(MC417_RWD, regval);
459 tempval = cx_read(MC417_RWD);
460 dataval |= ((tempval & 0x000000FF) << 16);
461 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
462 cx_write(MC417_RWD, regval);
463
464 /* Read data byte 3 */
465 regval = MC417_MIRD | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
466 cx_write(MC417_RWD, regval);
467 regval = MC417_MIWR | MC417_MIRDY | MCI_REGISTER_DATA_BYTE3;
468 cx_write(MC417_RWD, regval);
469 tempval = cx_read(MC417_RWD);
470 dataval |= ((tempval & 0x000000FF) << 24);
471 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
472 cx_write(MC417_RWD, regval);
473
474 *value = dataval;
475
476 return retval;
477 }
478
479 int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value)
480 {
481 u32 regval;
482
483 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
484 * which is an input.
485 */
486 cx_write(MC417_OEN, MC417_MIRDY);
487
488 /* Write data byte 0 */
489 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0 |
490 (value & 0x000000FF);
491 cx_write(MC417_RWD, regval);
492
493 /* Transition CS/WR to effect write transaction across bus. */
494 regval |= MC417_MICS | MC417_MIWR;
495 cx_write(MC417_RWD, regval);
496
497 /* Write data byte 1 */
498 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1 |
499 ((value >> 8) & 0x000000FF);
500 cx_write(MC417_RWD, regval);
501 regval |= MC417_MICS | MC417_MIWR;
502 cx_write(MC417_RWD, regval);
503
504 /* Write data byte 2 */
505 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2 |
506 ((value >> 16) & 0x000000FF);
507 cx_write(MC417_RWD, regval);
508 regval |= MC417_MICS | MC417_MIWR;
509 cx_write(MC417_RWD, regval);
510
511 /* Write data byte 3 */
512 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3 |
513 ((value >> 24) & 0x000000FF);
514 cx_write(MC417_RWD, regval);
515 regval |= MC417_MICS | MC417_MIWR;
516 cx_write(MC417_RWD, regval);
517
518 /* Write address byte 2 */
519 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
520 MCI_MODE_MEMORY_WRITE | ((address >> 16) & 0x3F);
521 cx_write(MC417_RWD, regval);
522 regval |= MC417_MICS | MC417_MIWR;
523 cx_write(MC417_RWD, regval);
524
525 /* Write address byte 1 */
526 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
527 ((address >> 8) & 0xFF);
528 cx_write(MC417_RWD, regval);
529 regval |= MC417_MICS | MC417_MIWR;
530 cx_write(MC417_RWD, regval);
531
532 /* Write address byte 0 */
533 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
534 (address & 0xFF);
535 cx_write(MC417_RWD, regval);
536 regval |= MC417_MICS | MC417_MIWR;
537 cx_write(MC417_RWD, regval);
538
539 /* Wait for the trans to complete (MC417_MIRDY asserted). */
540 return mc417_wait_ready(dev);
541 }
542
543 int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value)
544 {
545 int retval;
546 u32 regval;
547 u32 tempval;
548 u32 dataval;
549
550 /* Enable MC417 GPIO outputs except for MC417_MIRDY,
551 * which is an input.
552 */
553 cx_write(MC417_OEN, MC417_MIRDY);
554
555 /* Write address byte 2 */
556 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE2 |
557 MCI_MODE_MEMORY_READ | ((address >> 16) & 0x3F);
558 cx_write(MC417_RWD, regval);
559 regval |= MC417_MICS | MC417_MIWR;
560 cx_write(MC417_RWD, regval);
561
562 /* Write address byte 1 */
563 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE1 |
564 ((address >> 8) & 0xFF);
565 cx_write(MC417_RWD, regval);
566 regval |= MC417_MICS | MC417_MIWR;
567 cx_write(MC417_RWD, regval);
568
569 /* Write address byte 0 */
570 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_ADDRESS_BYTE0 |
571 (address & 0xFF);
572 cx_write(MC417_RWD, regval);
573 regval |= MC417_MICS | MC417_MIWR;
574 cx_write(MC417_RWD, regval);
575
576 /* Wait for the trans to complete (MC417_MIRDY asserted). */
577 retval = mc417_wait_ready(dev);
578
579 /* switch the DAT0-7 GPIO[10:3] to input mode */
580 cx_write(MC417_OEN, MC417_MIRDY | MC417_MIDATA);
581
582 /* Read data byte 3 */
583 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
584 cx_write(MC417_RWD, regval);
585
586 /* Transition RD to effect read transaction across bus. */
587 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE3;
588 cx_write(MC417_RWD, regval);
589
590 /* Collect byte */
591 tempval = cx_read(MC417_RWD);
592 dataval = ((tempval & 0x000000FF) << 24);
593
594 /* Bring CS and RD high. */
595 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
596 cx_write(MC417_RWD, regval);
597
598 /* Read data byte 2 */
599 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
600 cx_write(MC417_RWD, regval);
601 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE2;
602 cx_write(MC417_RWD, regval);
603 tempval = cx_read(MC417_RWD);
604 dataval |= ((tempval & 0x000000FF) << 16);
605 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
606 cx_write(MC417_RWD, regval);
607
608 /* Read data byte 1 */
609 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
610 cx_write(MC417_RWD, regval);
611 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE1;
612 cx_write(MC417_RWD, regval);
613 tempval = cx_read(MC417_RWD);
614 dataval |= ((tempval & 0x000000FF) << 8);
615 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
616 cx_write(MC417_RWD, regval);
617
618 /* Read data byte 0 */
619 regval = MC417_MIRD | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
620 cx_write(MC417_RWD, regval);
621 regval = MC417_MIWR | MC417_MIRDY | MCI_MEMORY_DATA_BYTE0;
622 cx_write(MC417_RWD, regval);
623 tempval = cx_read(MC417_RWD);
624 dataval |= (tempval & 0x000000FF);
625 regval = MC417_MIWR | MC417_MIRD | MC417_MICS | MC417_MIRDY;
626 cx_write(MC417_RWD, regval);
627
628 *value = dataval;
629
630 return retval;
631 }
632
633 /* ------------------------------------------------------------------ */
634
635 /* MPEG encoder API */
636 static char *cmd_to_str(int cmd)
637 {
638 switch (cmd) {
639 case CX2341X_ENC_PING_FW:
640 return "PING_FW";
641 case CX2341X_ENC_START_CAPTURE:
642 return "START_CAPTURE";
643 case CX2341X_ENC_STOP_CAPTURE:
644 return "STOP_CAPTURE";
645 case CX2341X_ENC_SET_AUDIO_ID:
646 return "SET_AUDIO_ID";
647 case CX2341X_ENC_SET_VIDEO_ID:
648 return "SET_VIDEO_ID";
649 case CX2341X_ENC_SET_PCR_ID:
650 return "SET_PCR_PID";
651 case CX2341X_ENC_SET_FRAME_RATE:
652 return "SET_FRAME_RATE";
653 case CX2341X_ENC_SET_FRAME_SIZE:
654 return "SET_FRAME_SIZE";
655 case CX2341X_ENC_SET_BIT_RATE:
656 return "SET_BIT_RATE";
657 case CX2341X_ENC_SET_GOP_PROPERTIES:
658 return "SET_GOP_PROPERTIES";
659 case CX2341X_ENC_SET_ASPECT_RATIO:
660 return "SET_ASPECT_RATIO";
661 case CX2341X_ENC_SET_DNR_FILTER_MODE:
662 return "SET_DNR_FILTER_PROPS";
663 case CX2341X_ENC_SET_DNR_FILTER_PROPS:
664 return "SET_DNR_FILTER_PROPS";
665 case CX2341X_ENC_SET_CORING_LEVELS:
666 return "SET_CORING_LEVELS";
667 case CX2341X_ENC_SET_SPATIAL_FILTER_TYPE:
668 return "SET_SPATIAL_FILTER_TYPE";
669 case CX2341X_ENC_SET_VBI_LINE:
670 return "SET_VBI_LINE";
671 case CX2341X_ENC_SET_STREAM_TYPE:
672 return "SET_STREAM_TYPE";
673 case CX2341X_ENC_SET_OUTPUT_PORT:
674 return "SET_OUTPUT_PORT";
675 case CX2341X_ENC_SET_AUDIO_PROPERTIES:
676 return "SET_AUDIO_PROPERTIES";
677 case CX2341X_ENC_HALT_FW:
678 return "HALT_FW";
679 case CX2341X_ENC_GET_VERSION:
680 return "GET_VERSION";
681 case CX2341X_ENC_SET_GOP_CLOSURE:
682 return "SET_GOP_CLOSURE";
683 case CX2341X_ENC_GET_SEQ_END:
684 return "GET_SEQ_END";
685 case CX2341X_ENC_SET_PGM_INDEX_INFO:
686 return "SET_PGM_INDEX_INFO";
687 case CX2341X_ENC_SET_VBI_CONFIG:
688 return "SET_VBI_CONFIG";
689 case CX2341X_ENC_SET_DMA_BLOCK_SIZE:
690 return "SET_DMA_BLOCK_SIZE";
691 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_10:
692 return "GET_PREV_DMA_INFO_MB_10";
693 case CX2341X_ENC_GET_PREV_DMA_INFO_MB_9:
694 return "GET_PREV_DMA_INFO_MB_9";
695 case CX2341X_ENC_SCHED_DMA_TO_HOST:
696 return "SCHED_DMA_TO_HOST";
697 case CX2341X_ENC_INITIALIZE_INPUT:
698 return "INITIALIZE_INPUT";
699 case CX2341X_ENC_SET_FRAME_DROP_RATE:
700 return "SET_FRAME_DROP_RATE";
701 case CX2341X_ENC_PAUSE_ENCODER:
702 return "PAUSE_ENCODER";
703 case CX2341X_ENC_REFRESH_INPUT:
704 return "REFRESH_INPUT";
705 case CX2341X_ENC_SET_COPYRIGHT:
706 return "SET_COPYRIGHT";
707 case CX2341X_ENC_SET_EVENT_NOTIFICATION:
708 return "SET_EVENT_NOTIFICATION";
709 case CX2341X_ENC_SET_NUM_VSYNC_LINES:
710 return "SET_NUM_VSYNC_LINES";
711 case CX2341X_ENC_SET_PLACEHOLDER:
712 return "SET_PLACEHOLDER";
713 case CX2341X_ENC_MUTE_VIDEO:
714 return "MUTE_VIDEO";
715 case CX2341X_ENC_MUTE_AUDIO:
716 return "MUTE_AUDIO";
717 case CX2341X_ENC_MISC:
718 return "MISC";
719 default:
720 return "UNKNOWN";
721 }
722 }
723
724 static int cx23885_mbox_func(void *priv,
725 u32 command,
726 int in,
727 int out,
728 u32 data[CX2341X_MBOX_MAX_DATA])
729 {
730 struct cx23885_dev *dev = priv;
731 unsigned long timeout;
732 u32 value, flag, retval = 0;
733 int i;
734
735 dprintk(3, "%s: command(0x%X) = %s\n", __func__, command,
736 cmd_to_str(command));
737
738 /* this may not be 100% safe if we can't read any memory location
739 without side effects */
740 mc417_memory_read(dev, dev->cx23417_mailbox - 4, &value);
741 if (value != 0x12345678) {
742 printk(KERN_ERR
743 "Firmware and/or mailbox pointer not initialized "
744 "or corrupted, signature = 0x%x, cmd = %s\n", value,
745 cmd_to_str(command));
746 return -1;
747 }
748
749 /* This read looks at 32 bits, but flag is only 8 bits.
750 * Seems we also bail if CMD or TIMEOUT bytes are set???
751 */
752 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
753 if (flag) {
754 printk(KERN_ERR "ERROR: Mailbox appears to be in use "
755 "(%x), cmd = %s\n", flag, cmd_to_str(command));
756 return -1;
757 }
758
759 flag |= 1; /* tell 'em we're working on it */
760 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
761
762 /* write command + args + fill remaining with zeros */
763 /* command code */
764 mc417_memory_write(dev, dev->cx23417_mailbox + 1, command);
765 mc417_memory_write(dev, dev->cx23417_mailbox + 3,
766 IVTV_API_STD_TIMEOUT); /* timeout */
767 for (i = 0; i < in; i++) {
768 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, data[i]);
769 dprintk(3, "API Input %d = %d\n", i, data[i]);
770 }
771 for (; i < CX2341X_MBOX_MAX_DATA; i++)
772 mc417_memory_write(dev, dev->cx23417_mailbox + 4 + i, 0);
773
774 flag |= 3; /* tell 'em we're done writing */
775 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
776
777 /* wait for firmware to handle the API command */
778 timeout = jiffies + msecs_to_jiffies(10);
779 for (;;) {
780 mc417_memory_read(dev, dev->cx23417_mailbox, &flag);
781 if (0 != (flag & 4))
782 break;
783 if (time_after(jiffies, timeout)) {
784 printk(KERN_ERR "ERROR: API Mailbox timeout\n");
785 return -1;
786 }
787 udelay(10);
788 }
789
790 /* read output values */
791 for (i = 0; i < out; i++) {
792 mc417_memory_read(dev, dev->cx23417_mailbox + 4 + i, data + i);
793 dprintk(3, "API Output %d = %d\n", i, data[i]);
794 }
795
796 mc417_memory_read(dev, dev->cx23417_mailbox + 2, &retval);
797 dprintk(3, "API result = %d\n", retval);
798
799 flag = 0;
800 mc417_memory_write(dev, dev->cx23417_mailbox, flag);
801
802 return retval;
803 }
804
805 /* We don't need to call the API often, so using just one
806 * mailbox will probably suffice
807 */
808 static int cx23885_api_cmd(struct cx23885_dev *dev,
809 u32 command,
810 u32 inputcnt,
811 u32 outputcnt,
812 ...)
813 {
814 u32 data[CX2341X_MBOX_MAX_DATA];
815 va_list vargs;
816 int i, err;
817
818 dprintk(3, "%s() cmds = 0x%08x\n", __func__, command);
819
820 va_start(vargs, outputcnt);
821 for (i = 0; i < inputcnt; i++)
822 data[i] = va_arg(vargs, int);
823
824 err = cx23885_mbox_func(dev, command, inputcnt, outputcnt, data);
825 for (i = 0; i < outputcnt; i++) {
826 int *vptr = va_arg(vargs, int *);
827 *vptr = data[i];
828 }
829 va_end(vargs);
830
831 return err;
832 }
833
834 static int cx23885_find_mailbox(struct cx23885_dev *dev)
835 {
836 u32 signature[4] = {
837 0x12345678, 0x34567812, 0x56781234, 0x78123456
838 };
839 int signaturecnt = 0;
840 u32 value;
841 int i;
842
843 dprintk(2, "%s()\n", __func__);
844
845 for (i = 0; i < CX23885_FIRM_IMAGE_SIZE; i++) {
846 mc417_memory_read(dev, i, &value);
847 if (value == signature[signaturecnt])
848 signaturecnt++;
849 else
850 signaturecnt = 0;
851 if (4 == signaturecnt) {
852 dprintk(1, "Mailbox signature found at 0x%x\n", i+1);
853 return i+1;
854 }
855 }
856 printk(KERN_ERR "Mailbox signature values not found!\n");
857 return -1;
858 }
859
860 static int cx23885_load_firmware(struct cx23885_dev *dev)
861 {
862 static const unsigned char magic[8] = {
863 0xa7, 0x0d, 0x00, 0x00, 0x66, 0xbb, 0x55, 0xaa
864 };
865 const struct firmware *firmware;
866 int i, retval = 0;
867 u32 value = 0;
868 u32 gpio_output = 0;
869 u32 checksum = 0;
870 u32 *dataptr;
871
872 dprintk(2, "%s()\n", __func__);
873
874 /* Save GPIO settings before reset of APU */
875 retval |= mc417_memory_read(dev, 0x9020, &gpio_output);
876 retval |= mc417_memory_read(dev, 0x900C, &value);
877
878 retval = mc417_register_write(dev,
879 IVTV_REG_VPU, 0xFFFFFFED);
880 retval |= mc417_register_write(dev,
881 IVTV_REG_HW_BLOCKS, IVTV_CMD_HW_BLOCKS_RST);
882 retval |= mc417_register_write(dev,
883 IVTV_REG_ENC_SDRAM_REFRESH, 0x80000800);
884 retval |= mc417_register_write(dev,
885 IVTV_REG_ENC_SDRAM_PRECHARGE, 0x1A);
886 retval |= mc417_register_write(dev,
887 IVTV_REG_APU, 0);
888
889 if (retval != 0) {
890 printk(KERN_ERR "%s: Error with mc417_register_write\n",
891 __func__);
892 return -1;
893 }
894
895 retval = request_firmware(&firmware, CX23885_FIRM_IMAGE_NAME,
896 &dev->pci->dev);
897
898 if (retval != 0) {
899 printk(KERN_ERR
900 "ERROR: Hotplug firmware request failed (%s).\n",
901 CX23885_FIRM_IMAGE_NAME);
902 printk(KERN_ERR "Please fix your hotplug setup, the board will "
903 "not work without firmware loaded!\n");
904 return -1;
905 }
906
907 if (firmware->size != CX23885_FIRM_IMAGE_SIZE) {
908 printk(KERN_ERR "ERROR: Firmware size mismatch "
909 "(have %zd, expected %d)\n",
910 firmware->size, CX23885_FIRM_IMAGE_SIZE);
911 release_firmware(firmware);
912 return -1;
913 }
914
915 if (0 != memcmp(firmware->data, magic, 8)) {
916 printk(KERN_ERR
917 "ERROR: Firmware magic mismatch, wrong file?\n");
918 release_firmware(firmware);
919 return -1;
920 }
921
922 /* transfer to the chip */
923 dprintk(2, "Loading firmware ...\n");
924 dataptr = (u32 *)firmware->data;
925 for (i = 0; i < (firmware->size >> 2); i++) {
926 value = *dataptr;
927 checksum += ~value;
928 if (mc417_memory_write(dev, i, value) != 0) {
929 printk(KERN_ERR "ERROR: Loading firmware failed!\n");
930 release_firmware(firmware);
931 return -1;
932 }
933 dataptr++;
934 }
935
936 /* read back to verify with the checksum */
937 dprintk(1, "Verifying firmware ...\n");
938 for (i--; i >= 0; i--) {
939 if (mc417_memory_read(dev, i, &value) != 0) {
940 printk(KERN_ERR "ERROR: Reading firmware failed!\n");
941 release_firmware(firmware);
942 return -1;
943 }
944 checksum -= ~value;
945 }
946 if (checksum) {
947 printk(KERN_ERR
948 "ERROR: Firmware load failed (checksum mismatch).\n");
949 release_firmware(firmware);
950 return -1;
951 }
952 release_firmware(firmware);
953 dprintk(1, "Firmware upload successful.\n");
954
955 retval |= mc417_register_write(dev, IVTV_REG_HW_BLOCKS,
956 IVTV_CMD_HW_BLOCKS_RST);
957
958 /* Restore GPIO settings, make sure EIO14 is enabled as an output. */
959 dprintk(2, "%s: GPIO output EIO 0-15 was = 0x%x\n",
960 __func__, gpio_output);
961 /* Power-up seems to have GPIOs AFU. This was causing digital side
962 * to fail at power-up. Seems GPIOs should be set to 0x10ff0411 at
963 * power-up.
964 * gpio_output |= (1<<14);
965 */
966 /* Note: GPIO14 is specific to the HVR1800 here */
967 gpio_output = 0x10ff0411 | (1<<14);
968 retval |= mc417_register_write(dev, 0x9020, gpio_output | (1<<14));
969 dprintk(2, "%s: GPIO output EIO 0-15 now = 0x%x\n",
970 __func__, gpio_output);
971
972 dprintk(1, "%s: GPIO value EIO 0-15 was = 0x%x\n",
973 __func__, value);
974 value |= (1<<14);
975 dprintk(1, "%s: GPIO value EIO 0-15 now = 0x%x\n",
976 __func__, value);
977 retval |= mc417_register_write(dev, 0x900C, value);
978
979 retval |= mc417_register_read(dev, IVTV_REG_VPU, &value);
980 retval |= mc417_register_write(dev, IVTV_REG_VPU, value & 0xFFFFFFE8);
981
982 if (retval < 0)
983 printk(KERN_ERR "%s: Error with mc417_register_write\n",
984 __func__);
985 return 0;
986 }
987
988 void cx23885_417_check_encoder(struct cx23885_dev *dev)
989 {
990 u32 status, seq;
991
992 status = seq = 0;
993 cx23885_api_cmd(dev, CX2341X_ENC_GET_SEQ_END, 0, 2, &status, &seq);
994 dprintk(1, "%s() status = %d, seq = %d\n", __func__, status, seq);
995 }
996
997 static void cx23885_codec_settings(struct cx23885_dev *dev)
998 {
999 dprintk(1, "%s()\n", __func__);
1000
1001 /* assign frame size */
1002 cx23885_api_cmd(dev, CX2341X_ENC_SET_FRAME_SIZE, 2, 0,
1003 dev->ts1.height, dev->ts1.width);
1004
1005 dev->mpeg_params.width = dev->ts1.width;
1006 dev->mpeg_params.height = dev->ts1.height;
1007 dev->mpeg_params.is_50hz =
1008 (dev->encodernorm.id & V4L2_STD_625_50) != 0;
1009
1010 cx2341x_update(dev, cx23885_mbox_func, NULL, &dev->mpeg_params);
1011
1012 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 3, 1);
1013 cx23885_api_cmd(dev, CX2341X_ENC_MISC, 2, 0, 4, 1);
1014 }
1015
1016 static int cx23885_initialize_codec(struct cx23885_dev *dev)
1017 {
1018 int version;
1019 int retval;
1020 u32 i, data[7];
1021
1022 dprintk(1, "%s()\n", __func__);
1023
1024 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0); /* ping */
1025 if (retval < 0) {
1026 dprintk(2, "%s() PING OK\n", __func__);
1027 retval = cx23885_load_firmware(dev);
1028 if (retval < 0) {
1029 printk(KERN_ERR "%s() f/w load failed\n", __func__);
1030 return retval;
1031 }
1032 retval = cx23885_find_mailbox(dev);
1033 if (retval < 0) {
1034 printk(KERN_ERR "%s() mailbox < 0, error\n",
1035 __func__);
1036 return -1;
1037 }
1038 dev->cx23417_mailbox = retval;
1039 retval = cx23885_api_cmd(dev, CX2341X_ENC_PING_FW, 0, 0);
1040 if (retval < 0) {
1041 printk(KERN_ERR
1042 "ERROR: cx23417 firmware ping failed!\n");
1043 return -1;
1044 }
1045 retval = cx23885_api_cmd(dev, CX2341X_ENC_GET_VERSION, 0, 1,
1046 &version);
1047 if (retval < 0) {
1048 printk(KERN_ERR "ERROR: cx23417 firmware get encoder :"
1049 "version failed!\n");
1050 return -1;
1051 }
1052 dprintk(1, "cx23417 firmware version is 0x%08x\n", version);
1053 msleep(200);
1054 }
1055
1056 cx23885_codec_settings(dev);
1057 msleep(60);
1058
1059 cx23885_api_cmd(dev, CX2341X_ENC_SET_NUM_VSYNC_LINES, 2, 0,
1060 CX23885_FIELD1_SAA7115, CX23885_FIELD2_SAA7115);
1061 cx23885_api_cmd(dev, CX2341X_ENC_SET_PLACEHOLDER, 12, 0,
1062 CX23885_CUSTOM_EXTENSION_USR_DATA, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1063 0, 0);
1064
1065 /* Setup to capture VBI */
1066 data[0] = 0x0001BD00;
1067 data[1] = 1; /* frames per interrupt */
1068 data[2] = 4; /* total bufs */
1069 data[3] = 0x91559155; /* start codes */
1070 data[4] = 0x206080C0; /* stop codes */
1071 data[5] = 6; /* lines */
1072 data[6] = 64; /* BPL */
1073
1074 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_CONFIG, 7, 0, data[0], data[1],
1075 data[2], data[3], data[4], data[5], data[6]);
1076
1077 for (i = 2; i <= 24; i++) {
1078 int valid;
1079
1080 valid = ((i >= 19) && (i <= 21));
1081 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0, i,
1082 valid, 0 , 0, 0);
1083 cx23885_api_cmd(dev, CX2341X_ENC_SET_VBI_LINE, 5, 0,
1084 i | 0x80000000, valid, 0, 0, 0);
1085 }
1086
1087 cx23885_api_cmd(dev, CX2341X_ENC_MUTE_AUDIO, 1, 0, CX23885_UNMUTE);
1088 msleep(60);
1089
1090 /* initialize the video input */
1091 cx23885_api_cmd(dev, CX2341X_ENC_INITIALIZE_INPUT, 0, 0);
1092 msleep(60);
1093
1094 /* Enable VIP style pixel invalidation so we work with scaled mode */
1095 mc417_memory_write(dev, 2120, 0x00000080);
1096
1097 /* start capturing to the host interface */
1098 cx23885_api_cmd(dev, CX2341X_ENC_START_CAPTURE, 2, 0,
1099 CX23885_MPEG_CAPTURE, CX23885_RAW_BITS_NONE);
1100 msleep(10);
1101
1102 return 0;
1103 }
1104
1105 /* ------------------------------------------------------------------ */
1106
1107 static int bb_buf_setup(struct videobuf_queue *q,
1108 unsigned int *count, unsigned int *size)
1109 {
1110 struct cx23885_fh *fh = q->priv_data;
1111
1112 fh->dev->ts1.ts_packet_size = mpeglinesize;
1113 fh->dev->ts1.ts_packet_count = mpeglines;
1114
1115 *size = fh->dev->ts1.ts_packet_size * fh->dev->ts1.ts_packet_count;
1116 *count = mpegbufs;
1117
1118 return 0;
1119 }
1120
1121 static int bb_buf_prepare(struct videobuf_queue *q,
1122 struct videobuf_buffer *vb, enum v4l2_field field)
1123 {
1124 struct cx23885_fh *fh = q->priv_data;
1125 return cx23885_buf_prepare(q, &fh->dev->ts1,
1126 (struct cx23885_buffer *)vb,
1127 field);
1128 }
1129
1130 static void bb_buf_queue(struct videobuf_queue *q,
1131 struct videobuf_buffer *vb)
1132 {
1133 struct cx23885_fh *fh = q->priv_data;
1134 cx23885_buf_queue(&fh->dev->ts1, (struct cx23885_buffer *)vb);
1135 }
1136
1137 static void bb_buf_release(struct videobuf_queue *q,
1138 struct videobuf_buffer *vb)
1139 {
1140 cx23885_free_buffer(q, (struct cx23885_buffer *)vb);
1141 }
1142
1143 static struct videobuf_queue_ops cx23885_qops = {
1144 .buf_setup = bb_buf_setup,
1145 .buf_prepare = bb_buf_prepare,
1146 .buf_queue = bb_buf_queue,
1147 .buf_release = bb_buf_release,
1148 };
1149
1150 /* ------------------------------------------------------------------ */
1151
1152 static const u32 *ctrl_classes[] = {
1153 cx2341x_mpeg_ctrls,
1154 NULL
1155 };
1156
1157 static int cx23885_queryctrl(struct cx23885_dev *dev,
1158 struct v4l2_queryctrl *qctrl)
1159 {
1160 qctrl->id = v4l2_ctrl_next(ctrl_classes, qctrl->id);
1161 if (qctrl->id == 0)
1162 return -EINVAL;
1163
1164 /* MPEG V4L2 controls */
1165 if (cx2341x_ctrl_query(&dev->mpeg_params, qctrl))
1166 qctrl->flags |= V4L2_CTRL_FLAG_DISABLED;
1167
1168 return 0;
1169 }
1170
1171 static int cx23885_querymenu(struct cx23885_dev *dev,
1172 struct v4l2_querymenu *qmenu)
1173 {
1174 struct v4l2_queryctrl qctrl;
1175
1176 qctrl.id = qmenu->id;
1177 cx23885_queryctrl(dev, &qctrl);
1178 return v4l2_ctrl_query_menu(qmenu, &qctrl,
1179 cx2341x_ctrl_get_menu(&dev->mpeg_params, qmenu->id));
1180 }
1181
1182 static int vidioc_s_std(struct file *file, void *priv, v4l2_std_id *id)
1183 {
1184 struct cx23885_fh *fh = file->private_data;
1185 struct cx23885_dev *dev = fh->dev;
1186 unsigned int i;
1187
1188 for (i = 0; i < ARRAY_SIZE(cx23885_tvnorms); i++)
1189 if (*id & cx23885_tvnorms[i].id)
1190 break;
1191 if (i == ARRAY_SIZE(cx23885_tvnorms))
1192 return -EINVAL;
1193 dev->encodernorm = cx23885_tvnorms[i];
1194 return 0;
1195 }
1196
1197 static int vidioc_enum_input(struct file *file, void *priv,
1198 struct v4l2_input *i)
1199 {
1200 struct cx23885_fh *fh = file->private_data;
1201 struct cx23885_dev *dev = fh->dev;
1202 struct cx23885_input *input;
1203 int n;
1204
1205 if (i->index >= 4)
1206 return -EINVAL;
1207
1208 input = &cx23885_boards[dev->board].input[i->index];
1209
1210 if (input->type == 0)
1211 return -EINVAL;
1212
1213 /* FIXME
1214 * strcpy(i->name, input->name); */
1215 strcpy(i->name, "unset");
1216
1217 if (input->type == CX23885_VMUX_TELEVISION ||
1218 input->type == CX23885_VMUX_CABLE)
1219 i->type = V4L2_INPUT_TYPE_TUNER;
1220 else
1221 i->type = V4L2_INPUT_TYPE_CAMERA;
1222
1223 for (n = 0; n < ARRAY_SIZE(cx23885_tvnorms); n++)
1224 i->std |= cx23885_tvnorms[n].id;
1225 return 0;
1226 }
1227
1228 static int vidioc_g_input(struct file *file, void *priv, unsigned int *i)
1229 {
1230 struct cx23885_fh *fh = file->private_data;
1231 struct cx23885_dev *dev = fh->dev;
1232
1233 *i = dev->input;
1234 return 0;
1235 }
1236
1237 static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
1238 {
1239 if (i >= 4)
1240 return -EINVAL;
1241
1242 return 0;
1243 }
1244
1245 static int vidioc_g_tuner(struct file *file, void *priv,
1246 struct v4l2_tuner *t)
1247 {
1248 struct cx23885_fh *fh = file->private_data;
1249 struct cx23885_dev *dev = fh->dev;
1250
1251 if (UNSET == dev->tuner_type)
1252 return -EINVAL;
1253 if (0 != t->index)
1254 return -EINVAL;
1255 strcpy(t->name, "Television");
1256 call_all(dev, tuner, g_tuner, t);
1257
1258 dprintk(1, "VIDIOC_G_TUNER: tuner type %d\n", t->type);
1259
1260 return 0;
1261 }
1262
1263 static int vidioc_s_tuner(struct file *file, void *priv,
1264 struct v4l2_tuner *t)
1265 {
1266 struct cx23885_fh *fh = file->private_data;
1267 struct cx23885_dev *dev = fh->dev;
1268
1269 if (UNSET == dev->tuner_type)
1270 return -EINVAL;
1271
1272 /* Update the A/V core */
1273 call_all(dev, tuner, s_tuner, t);
1274
1275 return 0;
1276 }
1277
1278 static int vidioc_g_frequency(struct file *file, void *priv,
1279 struct v4l2_frequency *f)
1280 {
1281 struct cx23885_fh *fh = file->private_data;
1282 struct cx23885_dev *dev = fh->dev;
1283
1284 if (UNSET == dev->tuner_type)
1285 return -EINVAL;
1286 f->type = V4L2_TUNER_ANALOG_TV;
1287 f->frequency = dev->freq;
1288
1289 call_all(dev, tuner, g_frequency, f);
1290
1291 return 0;
1292 }
1293
1294 static int vidioc_s_frequency(struct file *file, void *priv,
1295 struct v4l2_frequency *f)
1296 {
1297 struct cx23885_fh *fh = file->private_data;
1298 struct cx23885_dev *dev = fh->dev;
1299
1300 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1301 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1302 CX23885_RAW_BITS_NONE);
1303
1304 dprintk(1, "VIDIOC_S_FREQUENCY: dev type %d, f\n",
1305 dev->tuner_type);
1306 dprintk(1, "VIDIOC_S_FREQUENCY: f tuner %d, f type %d\n",
1307 f->tuner, f->type);
1308 if (UNSET == dev->tuner_type)
1309 return -EINVAL;
1310 if (f->tuner != 0)
1311 return -EINVAL;
1312 if (f->type != V4L2_TUNER_ANALOG_TV)
1313 return -EINVAL;
1314 dev->freq = f->frequency;
1315
1316 call_all(dev, tuner, s_frequency, f);
1317
1318 cx23885_initialize_codec(dev);
1319
1320 return 0;
1321 }
1322
1323 static int vidioc_s_ctrl(struct file *file, void *priv,
1324 struct v4l2_control *ctl)
1325 {
1326 struct cx23885_fh *fh = file->private_data;
1327 struct cx23885_dev *dev = fh->dev;
1328
1329 /* Update the A/V core */
1330 call_all(dev, core, s_ctrl, ctl);
1331 return 0;
1332 }
1333
1334 static int vidioc_querycap(struct file *file, void *priv,
1335 struct v4l2_capability *cap)
1336 {
1337 struct cx23885_fh *fh = file->private_data;
1338 struct cx23885_dev *dev = fh->dev;
1339 struct cx23885_tsport *tsport = &dev->ts1;
1340
1341 strcpy(cap->driver, dev->name);
1342 strlcpy(cap->card, cx23885_boards[tsport->dev->board].name,
1343 sizeof(cap->card));
1344 sprintf(cap->bus_info, "PCI:%s", pci_name(dev->pci));
1345 cap->version = CX23885_VERSION_CODE;
1346 cap->capabilities =
1347 V4L2_CAP_VIDEO_CAPTURE |
1348 V4L2_CAP_READWRITE |
1349 V4L2_CAP_STREAMING |
1350 0;
1351 if (UNSET != dev->tuner_type)
1352 cap->capabilities |= V4L2_CAP_TUNER;
1353
1354 return 0;
1355 }
1356
1357 static int vidioc_enum_fmt_vid_cap(struct file *file, void *priv,
1358 struct v4l2_fmtdesc *f)
1359 {
1360 if (f->index != 0)
1361 return -EINVAL;
1362
1363 strlcpy(f->description, "MPEG", sizeof(f->description));
1364 f->pixelformat = V4L2_PIX_FMT_MPEG;
1365
1366 return 0;
1367 }
1368
1369 static int vidioc_g_fmt_vid_cap(struct file *file, void *priv,
1370 struct v4l2_format *f)
1371 {
1372 struct cx23885_fh *fh = file->private_data;
1373 struct cx23885_dev *dev = fh->dev;
1374
1375 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1376 f->fmt.pix.bytesperline = 0;
1377 f->fmt.pix.sizeimage =
1378 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1379 f->fmt.pix.colorspace = 0;
1380 f->fmt.pix.width = dev->ts1.width;
1381 f->fmt.pix.height = dev->ts1.height;
1382 f->fmt.pix.field = fh->mpegq.field;
1383 dprintk(1, "VIDIOC_G_FMT: w: %d, h: %d, f: %d\n",
1384 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1385 return 0;
1386 }
1387
1388 static int vidioc_try_fmt_vid_cap(struct file *file, void *priv,
1389 struct v4l2_format *f)
1390 {
1391 struct cx23885_fh *fh = file->private_data;
1392 struct cx23885_dev *dev = fh->dev;
1393
1394 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1395 f->fmt.pix.bytesperline = 0;
1396 f->fmt.pix.sizeimage =
1397 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1398 f->fmt.pix.colorspace = 0;
1399 dprintk(1, "VIDIOC_TRY_FMT: w: %d, h: %d, f: %d\n",
1400 dev->ts1.width, dev->ts1.height, fh->mpegq.field);
1401 return 0;
1402 }
1403
1404 static int vidioc_s_fmt_vid_cap(struct file *file, void *priv,
1405 struct v4l2_format *f)
1406 {
1407 struct cx23885_fh *fh = file->private_data;
1408 struct cx23885_dev *dev = fh->dev;
1409
1410 f->fmt.pix.pixelformat = V4L2_PIX_FMT_MPEG;
1411 f->fmt.pix.bytesperline = 0;
1412 f->fmt.pix.sizeimage =
1413 dev->ts1.ts_packet_size * dev->ts1.ts_packet_count;
1414 f->fmt.pix.colorspace = 0;
1415 dprintk(1, "VIDIOC_S_FMT: w: %d, h: %d, f: %d\n",
1416 f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.field);
1417 return 0;
1418 }
1419
1420 static int vidioc_reqbufs(struct file *file, void *priv,
1421 struct v4l2_requestbuffers *p)
1422 {
1423 struct cx23885_fh *fh = file->private_data;
1424
1425 return videobuf_reqbufs(&fh->mpegq, p);
1426 }
1427
1428 static int vidioc_querybuf(struct file *file, void *priv,
1429 struct v4l2_buffer *p)
1430 {
1431 struct cx23885_fh *fh = file->private_data;
1432
1433 return videobuf_querybuf(&fh->mpegq, p);
1434 }
1435
1436 static int vidioc_qbuf(struct file *file, void *priv,
1437 struct v4l2_buffer *p)
1438 {
1439 struct cx23885_fh *fh = file->private_data;
1440
1441 return videobuf_qbuf(&fh->mpegq, p);
1442 }
1443
1444 static int vidioc_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
1445 {
1446 struct cx23885_fh *fh = priv;
1447
1448 return videobuf_dqbuf(&fh->mpegq, b, file->f_flags & O_NONBLOCK);
1449 }
1450
1451
1452 static int vidioc_streamon(struct file *file, void *priv,
1453 enum v4l2_buf_type i)
1454 {
1455 struct cx23885_fh *fh = file->private_data;
1456
1457 return videobuf_streamon(&fh->mpegq);
1458 }
1459
1460 static int vidioc_streamoff(struct file *file, void *priv, enum v4l2_buf_type i)
1461 {
1462 struct cx23885_fh *fh = file->private_data;
1463
1464 return videobuf_streamoff(&fh->mpegq);
1465 }
1466
1467 static int vidioc_g_ext_ctrls(struct file *file, void *priv,
1468 struct v4l2_ext_controls *f)
1469 {
1470 struct cx23885_fh *fh = priv;
1471 struct cx23885_dev *dev = fh->dev;
1472
1473 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1474 return -EINVAL;
1475 return cx2341x_ext_ctrls(&dev->mpeg_params, 0, f, VIDIOC_G_EXT_CTRLS);
1476 }
1477
1478 static int vidioc_s_ext_ctrls(struct file *file, void *priv,
1479 struct v4l2_ext_controls *f)
1480 {
1481 struct cx23885_fh *fh = priv;
1482 struct cx23885_dev *dev = fh->dev;
1483 struct cx2341x_mpeg_params p;
1484 int err;
1485
1486 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1487 return -EINVAL;
1488
1489 p = dev->mpeg_params;
1490 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_S_EXT_CTRLS);
1491
1492 if (err == 0) {
1493 err = cx2341x_update(dev, cx23885_mbox_func,
1494 &dev->mpeg_params, &p);
1495 dev->mpeg_params = p;
1496 }
1497 return err;
1498 }
1499
1500 static int vidioc_try_ext_ctrls(struct file *file, void *priv,
1501 struct v4l2_ext_controls *f)
1502 {
1503 struct cx23885_fh *fh = priv;
1504 struct cx23885_dev *dev = fh->dev;
1505 struct cx2341x_mpeg_params p;
1506 int err;
1507
1508 if (f->ctrl_class != V4L2_CTRL_CLASS_MPEG)
1509 return -EINVAL;
1510
1511 p = dev->mpeg_params;
1512 err = cx2341x_ext_ctrls(&p, 0, f, VIDIOC_TRY_EXT_CTRLS);
1513 return err;
1514 }
1515
1516 static int vidioc_log_status(struct file *file, void *priv)
1517 {
1518 struct cx23885_fh *fh = priv;
1519 struct cx23885_dev *dev = fh->dev;
1520 char name[32 + 2];
1521
1522 snprintf(name, sizeof(name), "%s/2", dev->name);
1523 printk(KERN_INFO
1524 "%s/2: ============ START LOG STATUS ============\n",
1525 dev->name);
1526 call_all(dev, core, log_status);
1527 cx2341x_log_status(&dev->mpeg_params, name);
1528 printk(KERN_INFO
1529 "%s/2: ============= END LOG STATUS =============\n",
1530 dev->name);
1531 return 0;
1532 }
1533
1534 static int vidioc_querymenu(struct file *file, void *priv,
1535 struct v4l2_querymenu *a)
1536 {
1537 struct cx23885_fh *fh = priv;
1538 struct cx23885_dev *dev = fh->dev;
1539
1540 return cx23885_querymenu(dev, a);
1541 }
1542
1543 static int vidioc_queryctrl(struct file *file, void *priv,
1544 struct v4l2_queryctrl *c)
1545 {
1546 struct cx23885_fh *fh = priv;
1547 struct cx23885_dev *dev = fh->dev;
1548
1549 return cx23885_queryctrl(dev, c);
1550 }
1551
1552 static int mpeg_open(struct file *file)
1553 {
1554 int minor = video_devdata(file)->minor;
1555 struct cx23885_dev *h, *dev = NULL;
1556 struct list_head *list;
1557 struct cx23885_fh *fh;
1558
1559 dprintk(2, "%s()\n", __func__);
1560
1561 lock_kernel();
1562 list_for_each(list, &cx23885_devlist) {
1563 h = list_entry(list, struct cx23885_dev, devlist);
1564 if (h->v4l_device &&
1565 h->v4l_device->minor == minor) {
1566 dev = h;
1567 break;
1568 }
1569 }
1570
1571 if (dev == NULL) {
1572 unlock_kernel();
1573 return -ENODEV;
1574 }
1575
1576 /* allocate + initialize per filehandle data */
1577 fh = kzalloc(sizeof(*fh), GFP_KERNEL);
1578 if (NULL == fh) {
1579 unlock_kernel();
1580 return -ENOMEM;
1581 }
1582
1583 file->private_data = fh;
1584 fh->dev = dev;
1585
1586 videobuf_queue_sg_init(&fh->mpegq, &cx23885_qops,
1587 &dev->pci->dev, &dev->ts1.slock,
1588 V4L2_BUF_TYPE_VIDEO_CAPTURE,
1589 V4L2_FIELD_INTERLACED,
1590 sizeof(struct cx23885_buffer),
1591 fh);
1592 unlock_kernel();
1593
1594 return 0;
1595 }
1596
1597 static int mpeg_release(struct file *file)
1598 {
1599 struct cx23885_fh *fh = file->private_data;
1600 struct cx23885_dev *dev = fh->dev;
1601
1602 dprintk(2, "%s()\n", __func__);
1603
1604 /* FIXME: Review this crap */
1605 /* Shut device down on last close */
1606 if (atomic_cmpxchg(&fh->v4l_reading, 1, 0) == 1) {
1607 if (atomic_dec_return(&dev->v4l_reader_count) == 0) {
1608 /* stop mpeg capture */
1609 cx23885_api_cmd(fh->dev, CX2341X_ENC_STOP_CAPTURE, 3, 0,
1610 CX23885_END_NOW, CX23885_MPEG_CAPTURE,
1611 CX23885_RAW_BITS_NONE);
1612
1613 msleep(500);
1614 cx23885_417_check_encoder(dev);
1615
1616 cx23885_cancel_buffers(&fh->dev->ts1);
1617 }
1618 }
1619
1620 if (fh->mpegq.streaming)
1621 videobuf_streamoff(&fh->mpegq);
1622 if (fh->mpegq.reading)
1623 videobuf_read_stop(&fh->mpegq);
1624
1625 videobuf_mmap_free(&fh->mpegq);
1626 file->private_data = NULL;
1627 kfree(fh);
1628
1629 return 0;
1630 }
1631
1632 static ssize_t mpeg_read(struct file *file, char __user *data,
1633 size_t count, loff_t *ppos)
1634 {
1635 struct cx23885_fh *fh = file->private_data;
1636 struct cx23885_dev *dev = fh->dev;
1637
1638 dprintk(2, "%s()\n", __func__);
1639
1640 /* Deal w/ A/V decoder * and mpeg encoder sync issues. */
1641 /* Start mpeg encoder on first read. */
1642 if (atomic_cmpxchg(&fh->v4l_reading, 0, 1) == 0) {
1643 if (atomic_inc_return(&dev->v4l_reader_count) == 1) {
1644 if (cx23885_initialize_codec(dev) < 0)
1645 return -EINVAL;
1646 }
1647 }
1648
1649 return videobuf_read_stream(&fh->mpegq, data, count, ppos, 0,
1650 file->f_flags & O_NONBLOCK);
1651 }
1652
1653 static unsigned int mpeg_poll(struct file *file,
1654 struct poll_table_struct *wait)
1655 {
1656 struct cx23885_fh *fh = file->private_data;
1657 struct cx23885_dev *dev = fh->dev;
1658
1659 dprintk(2, "%s\n", __func__);
1660
1661 return videobuf_poll_stream(file, &fh->mpegq, wait);
1662 }
1663
1664 static int mpeg_mmap(struct file *file, struct vm_area_struct *vma)
1665 {
1666 struct cx23885_fh *fh = file->private_data;
1667 struct cx23885_dev *dev = fh->dev;
1668
1669 dprintk(2, "%s()\n", __func__);
1670
1671 return videobuf_mmap_mapper(&fh->mpegq, vma);
1672 }
1673
1674 static struct v4l2_file_operations mpeg_fops = {
1675 .owner = THIS_MODULE,
1676 .open = mpeg_open,
1677 .release = mpeg_release,
1678 .read = mpeg_read,
1679 .poll = mpeg_poll,
1680 .mmap = mpeg_mmap,
1681 .ioctl = video_ioctl2,
1682 };
1683
1684 static const struct v4l2_ioctl_ops mpeg_ioctl_ops = {
1685 .vidioc_s_std = vidioc_s_std,
1686 .vidioc_enum_input = vidioc_enum_input,
1687 .vidioc_g_input = vidioc_g_input,
1688 .vidioc_s_input = vidioc_s_input,
1689 .vidioc_g_tuner = vidioc_g_tuner,
1690 .vidioc_s_tuner = vidioc_s_tuner,
1691 .vidioc_g_frequency = vidioc_g_frequency,
1692 .vidioc_s_frequency = vidioc_s_frequency,
1693 .vidioc_s_ctrl = vidioc_s_ctrl,
1694 .vidioc_querycap = vidioc_querycap,
1695 .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt_vid_cap,
1696 .vidioc_g_fmt_vid_cap = vidioc_g_fmt_vid_cap,
1697 .vidioc_try_fmt_vid_cap = vidioc_try_fmt_vid_cap,
1698 .vidioc_s_fmt_vid_cap = vidioc_s_fmt_vid_cap,
1699 .vidioc_reqbufs = vidioc_reqbufs,
1700 .vidioc_querybuf = vidioc_querybuf,
1701 .vidioc_qbuf = vidioc_qbuf,
1702 .vidioc_dqbuf = vidioc_dqbuf,
1703 .vidioc_streamon = vidioc_streamon,
1704 .vidioc_streamoff = vidioc_streamoff,
1705 .vidioc_g_ext_ctrls = vidioc_g_ext_ctrls,
1706 .vidioc_s_ext_ctrls = vidioc_s_ext_ctrls,
1707 .vidioc_try_ext_ctrls = vidioc_try_ext_ctrls,
1708 .vidioc_log_status = vidioc_log_status,
1709 .vidioc_querymenu = vidioc_querymenu,
1710 .vidioc_queryctrl = vidioc_queryctrl,
1711 };
1712
1713 static struct video_device cx23885_mpeg_template = {
1714 .name = "cx23885",
1715 .fops = &mpeg_fops,
1716 .ioctl_ops = &mpeg_ioctl_ops,
1717 .minor = -1,
1718 .tvnorms = CX23885_NORMS,
1719 .current_norm = V4L2_STD_NTSC_M,
1720 };
1721
1722 void cx23885_417_unregister(struct cx23885_dev *dev)
1723 {
1724 dprintk(1, "%s()\n", __func__);
1725
1726 if (dev->v4l_device) {
1727 if (-1 != dev->v4l_device->minor)
1728 video_unregister_device(dev->v4l_device);
1729 else
1730 video_device_release(dev->v4l_device);
1731 dev->v4l_device = NULL;
1732 }
1733 }
1734
1735 static struct video_device *cx23885_video_dev_alloc(
1736 struct cx23885_tsport *tsport,
1737 struct pci_dev *pci,
1738 struct video_device *template,
1739 char *type)
1740 {
1741 struct video_device *vfd;
1742 struct cx23885_dev *dev = tsport->dev;
1743
1744 dprintk(1, "%s()\n", __func__);
1745
1746 vfd = video_device_alloc();
1747 if (NULL == vfd)
1748 return NULL;
1749 *vfd = *template;
1750 snprintf(vfd->name, sizeof(vfd->name), "%s %s (%s)", dev->name,
1751 type, cx23885_boards[tsport->dev->board].name);
1752 vfd->parent = &pci->dev;
1753 vfd->release = video_device_release;
1754 return vfd;
1755 }
1756
1757 int cx23885_417_register(struct cx23885_dev *dev)
1758 {
1759 /* FIXME: Port1 hardcoded here */
1760 int err = -ENODEV;
1761 struct cx23885_tsport *tsport = &dev->ts1;
1762
1763 dprintk(1, "%s()\n", __func__);
1764
1765 if (cx23885_boards[dev->board].portb != CX23885_MPEG_ENCODER)
1766 return err;
1767
1768 /* Set default TV standard */
1769 dev->encodernorm = cx23885_tvnorms[0];
1770
1771 if (dev->encodernorm.id & V4L2_STD_525_60)
1772 tsport->height = 480;
1773 else
1774 tsport->height = 576;
1775
1776 tsport->width = 720;
1777 cx2341x_fill_defaults(&dev->mpeg_params);
1778
1779 dev->mpeg_params.port = CX2341X_PORT_SERIAL;
1780
1781 /* Allocate and initialize V4L video device */
1782 dev->v4l_device = cx23885_video_dev_alloc(tsport,
1783 dev->pci, &cx23885_mpeg_template, "mpeg");
1784 err = video_register_device(dev->v4l_device,
1785 VFL_TYPE_GRABBER, -1);
1786 if (err < 0) {
1787 printk(KERN_INFO "%s: can't register mpeg device\n", dev->name);
1788 return err;
1789 }
1790
1791 /* Initialize MC417 registers */
1792 cx23885_mc417_init(dev);
1793
1794 printk(KERN_INFO "%s: registered device video%d [mpeg]\n",
1795 dev->name, dev->v4l_device->num);
1796
1797 return 0;
1798 }
Linux with added FPC-III support