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md/raid: only permit hot-add of compatible integrity profiles
[linux/fpc-iii.git] / sound / soc / fsl / fsl_sai.c
blob08b460ba06efc28906fe1094e9e68b7c4e1e66cf
1 /*
2 * Freescale ALSA SoC Digital Audio Interface (SAI) driver.
3 *
4 * Copyright 2012-2015 Freescale Semiconductor, Inc.
5 *
6 * This program is free software, you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation, either version 2 of the License, or(at your
9 * option) any later version.
10 *
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dmaengine.h>
16 #include <linux/module.h>
17 #include <linux/of_address.h>
18 #include <linux/regmap.h>
19 #include <linux/slab.h>
20 #include <sound/core.h>
21 #include <sound/dmaengine_pcm.h>
22 #include <sound/pcm_params.h>
23
24 #include "fsl_sai.h"
25 #include "imx-pcm.h"
26
27 #define FSL_SAI_FLAGS (FSL_SAI_CSR_SEIE |\
28 FSL_SAI_CSR_FEIE)
29
30 static const unsigned int fsl_sai_rates[] = {
31 8000, 11025, 12000, 16000, 22050,
32 24000, 32000, 44100, 48000, 64000,
33 88200, 96000, 176400, 192000
34 };
35
36 static const struct snd_pcm_hw_constraint_list fsl_sai_rate_constraints = {
37 .count = ARRAY_SIZE(fsl_sai_rates),
38 .list = fsl_sai_rates,
39 };
40
41 static irqreturn_t fsl_sai_isr(int irq, void *devid)
42 {
43 struct fsl_sai *sai = (struct fsl_sai *)devid;
44 struct device *dev = &sai->pdev->dev;
45 u32 flags, xcsr, mask;
46 bool irq_none = true;
47
48 /*
49 * Both IRQ status bits and IRQ mask bits are in the xCSR but
50 * different shifts. And we here create a mask only for those
51 * IRQs that we activated.
52 */
53 mask = (FSL_SAI_FLAGS >> FSL_SAI_CSR_xIE_SHIFT) << FSL_SAI_CSR_xF_SHIFT;
54
55 /* Tx IRQ */
56 regmap_read(sai->regmap, FSL_SAI_TCSR, &xcsr);
57 flags = xcsr & mask;
58
59 if (flags)
60 irq_none = false;
61 else
62 goto irq_rx;
63
64 if (flags & FSL_SAI_CSR_WSF)
65 dev_dbg(dev, "isr: Start of Tx word detected\n");
66
67 if (flags & FSL_SAI_CSR_SEF)
68 dev_warn(dev, "isr: Tx Frame sync error detected\n");
69
70 if (flags & FSL_SAI_CSR_FEF) {
71 dev_warn(dev, "isr: Transmit underrun detected\n");
72 /* FIFO reset for safety */
73 xcsr |= FSL_SAI_CSR_FR;
74 }
75
76 if (flags & FSL_SAI_CSR_FWF)
77 dev_dbg(dev, "isr: Enabled transmit FIFO is empty\n");
78
79 if (flags & FSL_SAI_CSR_FRF)
80 dev_dbg(dev, "isr: Transmit FIFO watermark has been reached\n");
81
82 flags &= FSL_SAI_CSR_xF_W_MASK;
83 xcsr &= ~FSL_SAI_CSR_xF_MASK;
84
85 if (flags)
86 regmap_write(sai->regmap, FSL_SAI_TCSR, flags | xcsr);
87
88 irq_rx:
89 /* Rx IRQ */
90 regmap_read(sai->regmap, FSL_SAI_RCSR, &xcsr);
91 flags = xcsr & mask;
92
93 if (flags)
94 irq_none = false;
95 else
96 goto out;
97
98 if (flags & FSL_SAI_CSR_WSF)
99 dev_dbg(dev, "isr: Start of Rx word detected\n");
100
101 if (flags & FSL_SAI_CSR_SEF)
102 dev_warn(dev, "isr: Rx Frame sync error detected\n");
103
104 if (flags & FSL_SAI_CSR_FEF) {
105 dev_warn(dev, "isr: Receive overflow detected\n");
106 /* FIFO reset for safety */
107 xcsr |= FSL_SAI_CSR_FR;
108 }
109
110 if (flags & FSL_SAI_CSR_FWF)
111 dev_dbg(dev, "isr: Enabled receive FIFO is full\n");
112
113 if (flags & FSL_SAI_CSR_FRF)
114 dev_dbg(dev, "isr: Receive FIFO watermark has been reached\n");
115
116 flags &= FSL_SAI_CSR_xF_W_MASK;
117 xcsr &= ~FSL_SAI_CSR_xF_MASK;
118
119 if (flags)
120 regmap_write(sai->regmap, FSL_SAI_RCSR, flags | xcsr);
121
122 out:
123 if (irq_none)
124 return IRQ_NONE;
125 else
126 return IRQ_HANDLED;
127 }
128
129 static int fsl_sai_set_dai_sysclk_tr(struct snd_soc_dai *cpu_dai,
130 int clk_id, unsigned int freq, int fsl_dir)
131 {
132 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
133 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
134 u32 val_cr2 = 0;
135
136 switch (clk_id) {
137 case FSL_SAI_CLK_BUS:
138 val_cr2 |= FSL_SAI_CR2_MSEL_BUS;
139 break;
140 case FSL_SAI_CLK_MAST1:
141 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK1;
142 break;
143 case FSL_SAI_CLK_MAST2:
144 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK2;
145 break;
146 case FSL_SAI_CLK_MAST3:
147 val_cr2 |= FSL_SAI_CR2_MSEL_MCLK3;
148 break;
149 default:
150 return -EINVAL;
151 }
152
153 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
154 FSL_SAI_CR2_MSEL_MASK, val_cr2);
155
156 return 0;
157 }
158
159 static int fsl_sai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
160 int clk_id, unsigned int freq, int dir)
161 {
162 int ret;
163
164 if (dir == SND_SOC_CLOCK_IN)
165 return 0;
166
167 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
168 FSL_FMT_TRANSMITTER);
169 if (ret) {
170 dev_err(cpu_dai->dev, "Cannot set tx sysclk: %d\n", ret);
171 return ret;
172 }
173
174 ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,
175 FSL_FMT_RECEIVER);
176 if (ret)
177 dev_err(cpu_dai->dev, "Cannot set rx sysclk: %d\n", ret);
178
179 return ret;
180 }
181
182 static int fsl_sai_set_dai_fmt_tr(struct snd_soc_dai *cpu_dai,
183 unsigned int fmt, int fsl_dir)
184 {
185 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
186 bool tx = fsl_dir == FSL_FMT_TRANSMITTER;
187 u32 val_cr2 = 0, val_cr4 = 0;
188
189 if (!sai->is_lsb_first)
190 val_cr4 |= FSL_SAI_CR4_MF;
191
192 /* DAI mode */
193 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
194 case SND_SOC_DAIFMT_I2S:
195 /*
196 * Frame low, 1clk before data, one word length for frame sync,
197 * frame sync starts one serial clock cycle earlier,
198 * that is, together with the last bit of the previous
199 * data word.
200 */
201 val_cr2 |= FSL_SAI_CR2_BCP;
202 val_cr4 |= FSL_SAI_CR4_FSE | FSL_SAI_CR4_FSP;
203 break;
204 case SND_SOC_DAIFMT_LEFT_J:
205 /*
206 * Frame high, one word length for frame sync,
207 * frame sync asserts with the first bit of the frame.
208 */
209 val_cr2 |= FSL_SAI_CR2_BCP;
210 break;
211 case SND_SOC_DAIFMT_DSP_A:
212 /*
213 * Frame high, 1clk before data, one bit for frame sync,
214 * frame sync starts one serial clock cycle earlier,
215 * that is, together with the last bit of the previous
216 * data word.
217 */
218 val_cr2 |= FSL_SAI_CR2_BCP;
219 val_cr4 |= FSL_SAI_CR4_FSE;
220 sai->is_dsp_mode = true;
221 break;
222 case SND_SOC_DAIFMT_DSP_B:
223 /*
224 * Frame high, one bit for frame sync,
225 * frame sync asserts with the first bit of the frame.
226 */
227 val_cr2 |= FSL_SAI_CR2_BCP;
228 sai->is_dsp_mode = true;
229 break;
230 case SND_SOC_DAIFMT_RIGHT_J:
231 /* To be done */
232 default:
233 return -EINVAL;
234 }
235
236 /* DAI clock inversion */
237 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
238 case SND_SOC_DAIFMT_IB_IF:
239 /* Invert both clocks */
240 val_cr2 ^= FSL_SAI_CR2_BCP;
241 val_cr4 ^= FSL_SAI_CR4_FSP;
242 break;
243 case SND_SOC_DAIFMT_IB_NF:
244 /* Invert bit clock */
245 val_cr2 ^= FSL_SAI_CR2_BCP;
246 break;
247 case SND_SOC_DAIFMT_NB_IF:
248 /* Invert frame clock */
249 val_cr4 ^= FSL_SAI_CR4_FSP;
250 break;
251 case SND_SOC_DAIFMT_NB_NF:
252 /* Nothing to do for both normal cases */
253 break;
254 default:
255 return -EINVAL;
256 }
257
258 /* DAI clock master masks */
259 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
260 case SND_SOC_DAIFMT_CBS_CFS:
261 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
262 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
263 break;
264 case SND_SOC_DAIFMT_CBM_CFM:
265 sai->is_slave_mode = true;
266 break;
267 case SND_SOC_DAIFMT_CBS_CFM:
268 val_cr2 |= FSL_SAI_CR2_BCD_MSTR;
269 break;
270 case SND_SOC_DAIFMT_CBM_CFS:
271 val_cr4 |= FSL_SAI_CR4_FSD_MSTR;
272 sai->is_slave_mode = true;
273 break;
274 default:
275 return -EINVAL;
276 }
277
278 regmap_update_bits(sai->regmap, FSL_SAI_xCR2(tx),
279 FSL_SAI_CR2_BCP | FSL_SAI_CR2_BCD_MSTR, val_cr2);
280 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
281 FSL_SAI_CR4_MF | FSL_SAI_CR4_FSE |
282 FSL_SAI_CR4_FSP | FSL_SAI_CR4_FSD_MSTR, val_cr4);
283
284 return 0;
285 }
286
287 static int fsl_sai_set_dai_fmt(struct snd_soc_dai *cpu_dai, unsigned int fmt)
288 {
289 int ret;
290
291 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_TRANSMITTER);
292 if (ret) {
293 dev_err(cpu_dai->dev, "Cannot set tx format: %d\n", ret);
294 return ret;
295 }
296
297 ret = fsl_sai_set_dai_fmt_tr(cpu_dai, fmt, FSL_FMT_RECEIVER);
298 if (ret)
299 dev_err(cpu_dai->dev, "Cannot set rx format: %d\n", ret);
300
301 return ret;
302 }
303
304 static int fsl_sai_set_bclk(struct snd_soc_dai *dai, bool tx, u32 freq)
305 {
306 struct fsl_sai *sai = snd_soc_dai_get_drvdata(dai);
307 unsigned long clk_rate;
308 u32 savediv = 0, ratio, savesub = freq;
309 u32 id;
310 int ret = 0;
311
312 /* Don't apply to slave mode */
313 if (sai->is_slave_mode)
314 return 0;
315
316 for (id = 0; id < FSL_SAI_MCLK_MAX; id++) {
317 clk_rate = clk_get_rate(sai->mclk_clk[id]);
318 if (!clk_rate)
319 continue;
320
321 ratio = clk_rate / freq;
322
323 ret = clk_rate - ratio * freq;
324
325 /*
326 * Drop the source that can not be
327 * divided into the required rate.
328 */
329 if (ret != 0 && clk_rate / ret < 1000)
330 continue;
331
332 dev_dbg(dai->dev,
333 "ratio %d for freq %dHz based on clock %ldHz\n",
334 ratio, freq, clk_rate);
335
336 if (ratio % 2 == 0 && ratio >= 2 && ratio <= 512)
337 ratio /= 2;
338 else
339 continue;
340
341 if (ret < savesub) {
342 savediv = ratio;
343 sai->mclk_id[tx] = id;
344 savesub = ret;
345 }
346
347 if (ret == 0)
348 break;
349 }
350
351 if (savediv == 0) {
352 dev_err(dai->dev, "failed to derive required %cx rate: %d\n",
353 tx ? 'T' : 'R', freq);
354 return -EINVAL;
355 }
356
357 if ((tx && sai->synchronous[TX]) || (!tx && !sai->synchronous[RX])) {
358 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
359 FSL_SAI_CR2_MSEL_MASK,
360 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
361 regmap_update_bits(sai->regmap, FSL_SAI_RCR2,
362 FSL_SAI_CR2_DIV_MASK, savediv - 1);
363 } else {
364 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
365 FSL_SAI_CR2_MSEL_MASK,
366 FSL_SAI_CR2_MSEL(sai->mclk_id[tx]));
367 regmap_update_bits(sai->regmap, FSL_SAI_TCR2,
368 FSL_SAI_CR2_DIV_MASK, savediv - 1);
369 }
370
371 dev_dbg(dai->dev, "best fit: clock id=%d, div=%d, deviation =%d\n",
372 sai->mclk_id[tx], savediv, savesub);
373
374 return 0;
375 }
376
377 static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
378 struct snd_pcm_hw_params *params,
379 struct snd_soc_dai *cpu_dai)
380 {
381 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
382 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
383 unsigned int channels = params_channels(params);
384 u32 word_width = snd_pcm_format_width(params_format(params));
385 u32 val_cr4 = 0, val_cr5 = 0;
386 int ret;
387
388 if (!sai->is_slave_mode) {
389 ret = fsl_sai_set_bclk(cpu_dai, tx,
390 2 * word_width * params_rate(params));
391 if (ret)
392 return ret;
393
394 /* Do not enable the clock if it is already enabled */
395 if (!(sai->mclk_streams & BIT(substream->stream))) {
396 ret = clk_prepare_enable(sai->mclk_clk[sai->mclk_id[tx]]);
397 if (ret)
398 return ret;
399
400 sai->mclk_streams |= BIT(substream->stream);
401 }
402
403 }
404
405 if (!sai->is_dsp_mode)
406 val_cr4 |= FSL_SAI_CR4_SYWD(word_width);
407
408 val_cr5 |= FSL_SAI_CR5_WNW(word_width);
409 val_cr5 |= FSL_SAI_CR5_W0W(word_width);
410
411 if (sai->is_lsb_first)
412 val_cr5 |= FSL_SAI_CR5_FBT(0);
413 else
414 val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
415
416 val_cr4 |= FSL_SAI_CR4_FRSZ(channels);
417
418 regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
419 FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
420 val_cr4);
421 regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx),
422 FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
423 FSL_SAI_CR5_FBT_MASK, val_cr5);
424 regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
425
426 return 0;
427 }
428
429 static int fsl_sai_hw_free(struct snd_pcm_substream *substream,
430 struct snd_soc_dai *cpu_dai)
431 {
432 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
433 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
434
435 if (!sai->is_slave_mode &&
436 sai->mclk_streams & BIT(substream->stream)) {
437 clk_disable_unprepare(sai->mclk_clk[sai->mclk_id[tx]]);
438 sai->mclk_streams &= ~BIT(substream->stream);
439 }
440
441 return 0;
442 }
443
444
445 static int fsl_sai_trigger(struct snd_pcm_substream *substream, int cmd,
446 struct snd_soc_dai *cpu_dai)
447 {
448 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
449 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
450 u32 xcsr, count = 100;
451
452 /*
453 * Asynchronous mode: Clear SYNC for both Tx and Rx.
454 * Rx sync with Tx clocks: Clear SYNC for Tx, set it for Rx.
455 * Tx sync with Rx clocks: Clear SYNC for Rx, set it for Tx.
456 */
457 regmap_update_bits(sai->regmap, FSL_SAI_TCR2, FSL_SAI_CR2_SYNC,
458 sai->synchronous[TX] ? FSL_SAI_CR2_SYNC : 0);
459 regmap_update_bits(sai->regmap, FSL_SAI_RCR2, FSL_SAI_CR2_SYNC,
460 sai->synchronous[RX] ? FSL_SAI_CR2_SYNC : 0);
461
462 /*
463 * It is recommended that the transmitter is the last enabled
464 * and the first disabled.
465 */
466 switch (cmd) {
467 case SNDRV_PCM_TRIGGER_START:
468 case SNDRV_PCM_TRIGGER_RESUME:
469 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
470 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
471 FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
472
473 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
474 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
475 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
476 FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
477
478 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
479 FSL_SAI_CSR_xIE_MASK, FSL_SAI_FLAGS);
480 break;
481 case SNDRV_PCM_TRIGGER_STOP:
482 case SNDRV_PCM_TRIGGER_SUSPEND:
483 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
484 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
485 FSL_SAI_CSR_FRDE, 0);
486 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
487 FSL_SAI_CSR_xIE_MASK, 0);
488
489 /* Check if the opposite FRDE is also disabled */
490 regmap_read(sai->regmap, FSL_SAI_xCSR(!tx), &xcsr);
491 if (!(xcsr & FSL_SAI_CSR_FRDE)) {
492 /* Disable both directions and reset their FIFOs */
493 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
494 FSL_SAI_CSR_TERE, 0);
495 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
496 FSL_SAI_CSR_TERE, 0);
497
498 /* TERE will remain set till the end of current frame */
499 do {
500 udelay(10);
501 regmap_read(sai->regmap, FSL_SAI_xCSR(tx), &xcsr);
502 } while (--count && xcsr & FSL_SAI_CSR_TERE);
503
504 regmap_update_bits(sai->regmap, FSL_SAI_TCSR,
505 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
506 regmap_update_bits(sai->regmap, FSL_SAI_RCSR,
507 FSL_SAI_CSR_FR, FSL_SAI_CSR_FR);
508
509 /*
510 * For sai master mode, after several open/close sai,
511 * there will be no frame clock, and can't recover
512 * anymore. Add software reset to fix this issue.
513 * This is a hardware bug, and will be fix in the
514 * next sai version.
515 */
516 if (!sai->is_slave_mode) {
517 /* Software Reset for both Tx and Rx */
518 regmap_write(sai->regmap,
519 FSL_SAI_TCSR, FSL_SAI_CSR_SR);
520 regmap_write(sai->regmap,
521 FSL_SAI_RCSR, FSL_SAI_CSR_SR);
522 /* Clear SR bit to finish the reset */
523 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
524 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
525 }
526 }
527 break;
528 default:
529 return -EINVAL;
530 }
531
532 return 0;
533 }
534
535 static int fsl_sai_startup(struct snd_pcm_substream *substream,
536 struct snd_soc_dai *cpu_dai)
537 {
538 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
539 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
540 struct device *dev = &sai->pdev->dev;
541 int ret;
542
543 ret = clk_prepare_enable(sai->bus_clk);
544 if (ret) {
545 dev_err(dev, "failed to enable bus clock: %d\n", ret);
546 return ret;
547 }
548
549 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE,
550 FSL_SAI_CR3_TRCE);
551
552 ret = snd_pcm_hw_constraint_list(substream->runtime, 0,
553 SNDRV_PCM_HW_PARAM_RATE, &fsl_sai_rate_constraints);
554
555 return ret;
556 }
557
558 static void fsl_sai_shutdown(struct snd_pcm_substream *substream,
559 struct snd_soc_dai *cpu_dai)
560 {
561 struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
562 bool tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
563
564 regmap_update_bits(sai->regmap, FSL_SAI_xCR3(tx), FSL_SAI_CR3_TRCE, 0);
565
566 clk_disable_unprepare(sai->bus_clk);
567 }
568
569 static const struct snd_soc_dai_ops fsl_sai_pcm_dai_ops = {
570 .set_sysclk = fsl_sai_set_dai_sysclk,
571 .set_fmt = fsl_sai_set_dai_fmt,
572 .hw_params = fsl_sai_hw_params,
573 .hw_free = fsl_sai_hw_free,
574 .trigger = fsl_sai_trigger,
575 .startup = fsl_sai_startup,
576 .shutdown = fsl_sai_shutdown,
577 };
578
579 static int fsl_sai_dai_probe(struct snd_soc_dai *cpu_dai)
580 {
581 struct fsl_sai *sai = dev_get_drvdata(cpu_dai->dev);
582
583 /* Software Reset for both Tx and Rx */
584 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
585 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
586 /* Clear SR bit to finish the reset */
587 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
588 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
589
590 regmap_update_bits(sai->regmap, FSL_SAI_TCR1, FSL_SAI_CR1_RFW_MASK,
591 FSL_SAI_MAXBURST_TX * 2);
592 regmap_update_bits(sai->regmap, FSL_SAI_RCR1, FSL_SAI_CR1_RFW_MASK,
593 FSL_SAI_MAXBURST_RX - 1);
594
595 snd_soc_dai_init_dma_data(cpu_dai, &sai->dma_params_tx,
596 &sai->dma_params_rx);
597
598 snd_soc_dai_set_drvdata(cpu_dai, sai);
599
600 return 0;
601 }
602
603 static struct snd_soc_dai_driver fsl_sai_dai = {
604 .probe = fsl_sai_dai_probe,
605 .playback = {
606 .stream_name = "CPU-Playback",
607 .channels_min = 1,
608 .channels_max = 2,
609 .rate_min = 8000,
610 .rate_max = 192000,
611 .rates = SNDRV_PCM_RATE_KNOT,
612 .formats = FSL_SAI_FORMATS,
613 },
614 .capture = {
615 .stream_name = "CPU-Capture",
616 .channels_min = 1,
617 .channels_max = 2,
618 .rate_min = 8000,
619 .rate_max = 192000,
620 .rates = SNDRV_PCM_RATE_KNOT,
621 .formats = FSL_SAI_FORMATS,
622 },
623 .ops = &fsl_sai_pcm_dai_ops,
624 };
625
626 static const struct snd_soc_component_driver fsl_component = {
627 .name = "fsl-sai",
628 };
629
630 static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg)
631 {
632 switch (reg) {
633 case FSL_SAI_TCSR:
634 case FSL_SAI_TCR1:
635 case FSL_SAI_TCR2:
636 case FSL_SAI_TCR3:
637 case FSL_SAI_TCR4:
638 case FSL_SAI_TCR5:
639 case FSL_SAI_TFR:
640 case FSL_SAI_TMR:
641 case FSL_SAI_RCSR:
642 case FSL_SAI_RCR1:
643 case FSL_SAI_RCR2:
644 case FSL_SAI_RCR3:
645 case FSL_SAI_RCR4:
646 case FSL_SAI_RCR5:
647 case FSL_SAI_RDR:
648 case FSL_SAI_RFR:
649 case FSL_SAI_RMR:
650 return true;
651 default:
652 return false;
653 }
654 }
655
656 static bool fsl_sai_volatile_reg(struct device *dev, unsigned int reg)
657 {
658 switch (reg) {
659 case FSL_SAI_TCSR:
660 case FSL_SAI_RCSR:
661 case FSL_SAI_TFR:
662 case FSL_SAI_RFR:
663 case FSL_SAI_TDR:
664 case FSL_SAI_RDR:
665 return true;
666 default:
667 return false;
668 }
669
670 }
671
672 static bool fsl_sai_writeable_reg(struct device *dev, unsigned int reg)
673 {
674 switch (reg) {
675 case FSL_SAI_TCSR:
676 case FSL_SAI_TCR1:
677 case FSL_SAI_TCR2:
678 case FSL_SAI_TCR3:
679 case FSL_SAI_TCR4:
680 case FSL_SAI_TCR5:
681 case FSL_SAI_TDR:
682 case FSL_SAI_TMR:
683 case FSL_SAI_RCSR:
684 case FSL_SAI_RCR1:
685 case FSL_SAI_RCR2:
686 case FSL_SAI_RCR3:
687 case FSL_SAI_RCR4:
688 case FSL_SAI_RCR5:
689 case FSL_SAI_RMR:
690 return true;
691 default:
692 return false;
693 }
694 }
695
696 static const struct regmap_config fsl_sai_regmap_config = {
697 .reg_bits = 32,
698 .reg_stride = 4,
699 .val_bits = 32,
700
701 .max_register = FSL_SAI_RMR,
702 .readable_reg = fsl_sai_readable_reg,
703 .volatile_reg = fsl_sai_volatile_reg,
704 .writeable_reg = fsl_sai_writeable_reg,
705 .cache_type = REGCACHE_FLAT,
706 };
707
708 static int fsl_sai_probe(struct platform_device *pdev)
709 {
710 struct device_node *np = pdev->dev.of_node;
711 struct fsl_sai *sai;
712 struct resource *res;
713 void __iomem *base;
714 char tmp[8];
715 int irq, ret, i;
716
717 sai = devm_kzalloc(&pdev->dev, sizeof(*sai), GFP_KERNEL);
718 if (!sai)
719 return -ENOMEM;
720
721 sai->pdev = pdev;
722
723 if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx6sx-sai"))
724 sai->sai_on_imx = true;
725
726 sai->is_lsb_first = of_property_read_bool(np, "lsb-first");
727
728 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
729 base = devm_ioremap_resource(&pdev->dev, res);
730 if (IS_ERR(base))
731 return PTR_ERR(base);
732
733 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
734 "bus", base, &fsl_sai_regmap_config);
735
736 /* Compatible with old DTB cases */
737 if (IS_ERR(sai->regmap))
738 sai->regmap = devm_regmap_init_mmio_clk(&pdev->dev,
739 "sai", base, &fsl_sai_regmap_config);
740 if (IS_ERR(sai->regmap)) {
741 dev_err(&pdev->dev, "regmap init failed\n");
742 return PTR_ERR(sai->regmap);
743 }
744
745 /* No error out for old DTB cases but only mark the clock NULL */
746 sai->bus_clk = devm_clk_get(&pdev->dev, "bus");
747 if (IS_ERR(sai->bus_clk)) {
748 dev_err(&pdev->dev, "failed to get bus clock: %ld\n",
749 PTR_ERR(sai->bus_clk));
750 sai->bus_clk = NULL;
751 }
752
753 sai->mclk_clk[0] = sai->bus_clk;
754 for (i = 1; i < FSL_SAI_MCLK_MAX; i++) {
755 sprintf(tmp, "mclk%d", i);
756 sai->mclk_clk[i] = devm_clk_get(&pdev->dev, tmp);
757 if (IS_ERR(sai->mclk_clk[i])) {
758 dev_err(&pdev->dev, "failed to get mclk%d clock: %ld\n",
759 i + 1, PTR_ERR(sai->mclk_clk[i]));
760 sai->mclk_clk[i] = NULL;
761 }
762 }
763
764 irq = platform_get_irq(pdev, 0);
765 if (irq < 0) {
766 dev_err(&pdev->dev, "no irq for node %s\n", pdev->name);
767 return irq;
768 }
769
770 ret = devm_request_irq(&pdev->dev, irq, fsl_sai_isr, 0, np->name, sai);
771 if (ret) {
772 dev_err(&pdev->dev, "failed to claim irq %u\n", irq);
773 return ret;
774 }
775
776 /* Sync Tx with Rx as default by following old DT binding */
777 sai->synchronous[RX] = true;
778 sai->synchronous[TX] = false;
779 fsl_sai_dai.symmetric_rates = 1;
780 fsl_sai_dai.symmetric_channels = 1;
781 fsl_sai_dai.symmetric_samplebits = 1;
782
783 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL) &&
784 of_find_property(np, "fsl,sai-asynchronous", NULL)) {
785 /* error out if both synchronous and asynchronous are present */
786 dev_err(&pdev->dev, "invalid binding for synchronous mode\n");
787 return -EINVAL;
788 }
789
790 if (of_find_property(np, "fsl,sai-synchronous-rx", NULL)) {
791 /* Sync Rx with Tx */
792 sai->synchronous[RX] = false;
793 sai->synchronous[TX] = true;
794 } else if (of_find_property(np, "fsl,sai-asynchronous", NULL)) {
795 /* Discard all settings for asynchronous mode */
796 sai->synchronous[RX] = false;
797 sai->synchronous[TX] = false;
798 fsl_sai_dai.symmetric_rates = 0;
799 fsl_sai_dai.symmetric_channels = 0;
800 fsl_sai_dai.symmetric_samplebits = 0;
801 }
802
803 sai->dma_params_rx.addr = res->start + FSL_SAI_RDR;
804 sai->dma_params_tx.addr = res->start + FSL_SAI_TDR;
805 sai->dma_params_rx.maxburst = FSL_SAI_MAXBURST_RX;
806 sai->dma_params_tx.maxburst = FSL_SAI_MAXBURST_TX;
807
808 platform_set_drvdata(pdev, sai);
809
810 ret = devm_snd_soc_register_component(&pdev->dev, &fsl_component,
811 &fsl_sai_dai, 1);
812 if (ret)
813 return ret;
814
815 if (sai->sai_on_imx)
816 return imx_pcm_dma_init(pdev, IMX_SAI_DMABUF_SIZE);
817 else
818 return devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
819 }
820
821 static const struct of_device_id fsl_sai_ids[] = {
822 { .compatible = "fsl,vf610-sai", },
823 { .compatible = "fsl,imx6sx-sai", },
824 { /* sentinel */ }
825 };
826 MODULE_DEVICE_TABLE(of, fsl_sai_ids);
827
828 #ifdef CONFIG_PM_SLEEP
829 static int fsl_sai_suspend(struct device *dev)
830 {
831 struct fsl_sai *sai = dev_get_drvdata(dev);
832
833 regcache_cache_only(sai->regmap, true);
834 regcache_mark_dirty(sai->regmap);
835
836 return 0;
837 }
838
839 static int fsl_sai_resume(struct device *dev)
840 {
841 struct fsl_sai *sai = dev_get_drvdata(dev);
842
843 regcache_cache_only(sai->regmap, false);
844 regmap_write(sai->regmap, FSL_SAI_TCSR, FSL_SAI_CSR_SR);
845 regmap_write(sai->regmap, FSL_SAI_RCSR, FSL_SAI_CSR_SR);
846 msleep(1);
847 regmap_write(sai->regmap, FSL_SAI_TCSR, 0);
848 regmap_write(sai->regmap, FSL_SAI_RCSR, 0);
849 return regcache_sync(sai->regmap);
850 }
851 #endif /* CONFIG_PM_SLEEP */
852
853 static const struct dev_pm_ops fsl_sai_pm_ops = {
854 SET_SYSTEM_SLEEP_PM_OPS(fsl_sai_suspend, fsl_sai_resume)
855 };
856
857 static struct platform_driver fsl_sai_driver = {
858 .probe = fsl_sai_probe,
859 .driver = {
860 .name = "fsl-sai",
861 .pm = &fsl_sai_pm_ops,
862 .of_match_table = fsl_sai_ids,
863 },
864 };
865 module_platform_driver(fsl_sai_driver);
866
867 MODULE_DESCRIPTION("Freescale Soc SAI Interface");
868 MODULE_AUTHOR("Xiubo Li, <Li.Xiubo@freescale.com>");
869 MODULE_ALIAS("platform:fsl-sai");
870 MODULE_LICENSE("GPL");
Linux with added FPC-III support