sound/soc/mxs/mxs-saif.h

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19
  20 #ifndef _MXS_SAIF_H
  21 #define _MXS_SAIF_H
  22
  23 #define SAIF_CTRL       0x0
  24 #define SAIF_STAT       0x10
  25 #define SAIF_DATA       0x20
  26 #define SAIF_VERSION    0X30
  27
  28 /* SAIF_CTRL */
  29 #define BM_SAIF_CTRL_SFTRST             0x80000000
  30 #define BM_SAIF_CTRL_CLKGATE            0x40000000
  31 #define BP_SAIF_CTRL_BITCLK_MULT_RATE   27
  32 #define BM_SAIF_CTRL_BITCLK_MULT_RATE   0x38000000
  33 #define BF_SAIF_CTRL_BITCLK_MULT_RATE(v) \
  34                 (((v) << 27) & BM_SAIF_CTRL_BITCLK_MULT_RATE)
  35 #define BM_SAIF_CTRL_BITCLK_BASE_RATE   0x04000000
  36 #define BM_SAIF_CTRL_FIFO_ERROR_IRQ_EN  0x02000000
  37 #define BM_SAIF_CTRL_FIFO_SERVICE_IRQ_EN        0x01000000
  38 #define BP_SAIF_CTRL_RSRVD2             21
  39 #define BM_SAIF_CTRL_RSRVD2             0x00E00000
  40
  41 #define BP_SAIF_CTRL_DMAWAIT_COUNT      16
  42 #define BM_SAIF_CTRL_DMAWAIT_COUNT      0x001F0000
  43 #define BF_SAIF_CTRL_DMAWAIT_COUNT(v) \
  44                 (((v) << 16) & BM_SAIF_CTRL_DMAWAIT_COUNT)
  45 #define BP_SAIF_CTRL_CHANNEL_NUM_SELECT 14
  46 #define BM_SAIF_CTRL_CHANNEL_NUM_SELECT 0x0000C000
  47 #define BF_SAIF_CTRL_CHANNEL_NUM_SELECT(v) \
  48                 (((v) << 14) & BM_SAIF_CTRL_CHANNEL_NUM_SELECT)
  49 #define BM_SAIF_CTRL_LRCLK_PULSE        0x00002000
  50 #define BM_SAIF_CTRL_BIT_ORDER          0x00001000
  51 #define BM_SAIF_CTRL_DELAY              0x00000800
  52 #define BM_SAIF_CTRL_JUSTIFY            0x00000400
  53 #define BM_SAIF_CTRL_LRCLK_POLARITY     0x00000200
  54 #define BM_SAIF_CTRL_BITCLK_EDGE        0x00000100
  55 #define BP_SAIF_CTRL_WORD_LENGTH        4
  56 #define BM_SAIF_CTRL_WORD_LENGTH        0x000000F0
  57 #define BF_SAIF_CTRL_WORD_LENGTH(v) \
  58                 (((v) << 4) & BM_SAIF_CTRL_WORD_LENGTH)
  59 #define BM_SAIF_CTRL_BITCLK_48XFS_ENABLE        0x00000008
  60 #define BM_SAIF_CTRL_SLAVE_MODE         0x00000004
  61 #define BM_SAIF_CTRL_READ_MODE          0x00000002
  62 #define BM_SAIF_CTRL_RUN                0x00000001
  63
  64 /* SAIF_STAT */
  65 #define BM_SAIF_STAT_PRESENT            0x80000000
  66 #define BP_SAIF_STAT_RSRVD2             17
  67 #define BM_SAIF_STAT_RSRVD2             0x7FFE0000
  68 #define BF_SAIF_STAT_RSRVD2(v) \
  69                 (((v) << 17) & BM_SAIF_STAT_RSRVD2)
  70 #define BM_SAIF_STAT_DMA_PREQ           0x00010000
  71 #define BP_SAIF_STAT_RSRVD1             7
  72 #define BM_SAIF_STAT_RSRVD1             0x0000FF80
  73 #define BF_SAIF_STAT_RSRVD1(v) \
  74                 (((v) << 7) & BM_SAIF_STAT_RSRVD1)
  75
  76 #define BM_SAIF_STAT_FIFO_UNDERFLOW_IRQ 0x00000040
  77 #define BM_SAIF_STAT_FIFO_OVERFLOW_IRQ  0x00000020
  78 #define BM_SAIF_STAT_FIFO_SERVICE_IRQ   0x00000010
  79 #define BP_SAIF_STAT_RSRVD0             1
  80 #define BM_SAIF_STAT_RSRVD0             0x0000000E
  81 #define BF_SAIF_STAT_RSRVD0(v) \
  82                 (((v) << 1) & BM_SAIF_STAT_RSRVD0)
  83 #define BM_SAIF_STAT_BUSY               0x00000001
  84
  85 /* SAFI_DATA */
  86 #define BP_SAIF_DATA_PCM_RIGHT          16
  87 #define BM_SAIF_DATA_PCM_RIGHT          0xFFFF0000
  88 #define BF_SAIF_DATA_PCM_RIGHT(v) \
  89                 (((v) << 16) & BM_SAIF_DATA_PCM_RIGHT)
  90 #define BP_SAIF_DATA_PCM_LEFT           0
  91 #define BM_SAIF_DATA_PCM_LEFT           0x0000FFFF
  92 #define BF_SAIF_DATA_PCM_LEFT(v)        \
  93                 (((v) << 0) & BM_SAIF_DATA_PCM_LEFT)
  94
  95 /* SAIF_VERSION */
  96 #define BP_SAIF_VERSION_MAJOR           24
  97 #define BM_SAIF_VERSION_MAJOR           0xFF000000
  98 #define BF_SAIF_VERSION_MAJOR(v) \
  99                 (((v) << 24) & BM_SAIF_VERSION_MAJOR)
 100 #define BP_SAIF_VERSION_MINOR           16
 101 #define BM_SAIF_VERSION_MINOR           0x00FF0000
 102 #define BF_SAIF_VERSION_MINOR(v) \
 103                 (((v) << 16) & BM_SAIF_VERSION_MINOR)
 104 #define BP_SAIF_VERSION_STEP            0
 105 #define BM_SAIF_VERSION_STEP            0x0000FFFF
 106 #define BF_SAIF_VERSION_STEP(v) \
 107                 (((v) << 0) & BM_SAIF_VERSION_STEP)
 108
 109 #define MXS_SAIF_MCLK           0
 110
 111 #include "mxs-pcm.h"
 112
 113 struct mxs_saif {
 114         struct device *dev;
 115         struct clk *clk;
 116         unsigned int mclk;
 117         unsigned int mclk_in_use;
 118         void __iomem *base;
 119         unsigned int id;
 120         unsigned int master_id;
 121         unsigned int cur_rate;
 122         unsigned int ongoing;
 123
 124         u32 fifo_underrun;
 125         u32 fifo_overrun;
 126
 127         enum {
 128                 MXS_SAIF_STATE_STOPPED,
 129                 MXS_SAIF_STATE_RUNNING,
 130         } state;
 131 };
 132
 133 extern int mxs_saif_put_mclk(unsigned int saif_id);
 134 extern int mxs_saif_get_mclk(unsigned int saif_id, unsigned int mclk,
 135                                         unsigned int rate);
 136 #endif