virt/kvm/arm/vgic/vgic.h

   1 /*
   2  * Copyright (C) 2015, 2016 ARM Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16 #ifndef __KVM_ARM_VGIC_NEW_H__
  17 #define __KVM_ARM_VGIC_NEW_H__
  18
  19 #include <linux/irqchip/arm-gic-common.h>
  20
  21 #define PRODUCT_ID_KVM          0x4b    /* ASCII code K */
  22 #define IMPLEMENTER_ARM         0x43b
  23
  24 #define VGIC_ADDR_UNDEF         (-1)
  25 #define IS_VGIC_ADDR_UNDEF(_x)  ((_x) == VGIC_ADDR_UNDEF)
  26
  27 #define INTERRUPT_ID_BITS_SPIS  10
  28 #define INTERRUPT_ID_BITS_ITS   16
  29 #define VGIC_PRI_BITS           5
  30
  31 #define vgic_irq_is_sgi(intid) ((intid) < VGIC_NR_SGIS)
  32
  33 #define VGIC_AFFINITY_0_SHIFT 0
  34 #define VGIC_AFFINITY_0_MASK (0xffUL << VGIC_AFFINITY_0_SHIFT)
  35 #define VGIC_AFFINITY_1_SHIFT 8
  36 #define VGIC_AFFINITY_1_MASK (0xffUL << VGIC_AFFINITY_1_SHIFT)
  37 #define VGIC_AFFINITY_2_SHIFT 16
  38 #define VGIC_AFFINITY_2_MASK (0xffUL << VGIC_AFFINITY_2_SHIFT)
  39 #define VGIC_AFFINITY_3_SHIFT 24
  40 #define VGIC_AFFINITY_3_MASK (0xffUL << VGIC_AFFINITY_3_SHIFT)
  41
  42 #define VGIC_AFFINITY_LEVEL(reg, level) \
  43         ((((reg) & VGIC_AFFINITY_## level ##_MASK) \
  44         >> VGIC_AFFINITY_## level ##_SHIFT) << MPIDR_LEVEL_SHIFT(level))
  45
  46 /*
  47  * The Userspace encodes the affinity differently from the MPIDR,
  48  * Below macro converts vgic userspace format to MPIDR reg format.
  49  */
  50 #define VGIC_TO_MPIDR(val) (VGIC_AFFINITY_LEVEL(val, 0) | \
  51                             VGIC_AFFINITY_LEVEL(val, 1) | \
  52                             VGIC_AFFINITY_LEVEL(val, 2) | \
  53                             VGIC_AFFINITY_LEVEL(val, 3))
  54
  55 /*
  56  * As per Documentation/virtual/kvm/devices/arm-vgic-v3.txt,
  57  * below macros are defined for CPUREG encoding.
  58  */
  59 #define KVM_REG_ARM_VGIC_SYSREG_OP0_MASK   0x000000000000c000
  60 #define KVM_REG_ARM_VGIC_SYSREG_OP0_SHIFT  14
  61 #define KVM_REG_ARM_VGIC_SYSREG_OP1_MASK   0x0000000000003800
  62 #define KVM_REG_ARM_VGIC_SYSREG_OP1_SHIFT  11
  63 #define KVM_REG_ARM_VGIC_SYSREG_CRN_MASK   0x0000000000000780
  64 #define KVM_REG_ARM_VGIC_SYSREG_CRN_SHIFT  7
  65 #define KVM_REG_ARM_VGIC_SYSREG_CRM_MASK   0x0000000000000078
  66 #define KVM_REG_ARM_VGIC_SYSREG_CRM_SHIFT  3
  67 #define KVM_REG_ARM_VGIC_SYSREG_OP2_MASK   0x0000000000000007
  68 #define KVM_REG_ARM_VGIC_SYSREG_OP2_SHIFT  0
  69
  70 #define KVM_DEV_ARM_VGIC_SYSREG_MASK (KVM_REG_ARM_VGIC_SYSREG_OP0_MASK | \
  71                                       KVM_REG_ARM_VGIC_SYSREG_OP1_MASK | \
  72                                       KVM_REG_ARM_VGIC_SYSREG_CRN_MASK | \
  73                                       KVM_REG_ARM_VGIC_SYSREG_CRM_MASK | \
  74                                       KVM_REG_ARM_VGIC_SYSREG_OP2_MASK)
  75
  76 /*
  77  * As per Documentation/virtual/kvm/devices/arm-vgic-its.txt,
  78  * below macros are defined for ITS table entry encoding.
  79  */
  80 #define KVM_ITS_CTE_VALID_SHIFT         63
  81 #define KVM_ITS_CTE_VALID_MASK          BIT_ULL(63)
  82 #define KVM_ITS_CTE_RDBASE_SHIFT        16
  83 #define KVM_ITS_CTE_ICID_MASK           GENMASK_ULL(15, 0)
  84 #define KVM_ITS_ITE_NEXT_SHIFT          48
  85 #define KVM_ITS_ITE_PINTID_SHIFT        16
  86 #define KVM_ITS_ITE_PINTID_MASK         GENMASK_ULL(47, 16)
  87 #define KVM_ITS_ITE_ICID_MASK           GENMASK_ULL(15, 0)
  88 #define KVM_ITS_DTE_VALID_SHIFT         63
  89 #define KVM_ITS_DTE_VALID_MASK          BIT_ULL(63)
  90 #define KVM_ITS_DTE_NEXT_SHIFT          49
  91 #define KVM_ITS_DTE_NEXT_MASK           GENMASK_ULL(62, 49)
  92 #define KVM_ITS_DTE_ITTADDR_SHIFT       5
  93 #define KVM_ITS_DTE_ITTADDR_MASK        GENMASK_ULL(48, 5)
  94 #define KVM_ITS_DTE_SIZE_MASK           GENMASK_ULL(4, 0)
  95 #define KVM_ITS_L1E_VALID_MASK          BIT_ULL(63)
  96 /* we only support 64 kB translation table page size */
  97 #define KVM_ITS_L1E_ADDR_MASK           GENMASK_ULL(51, 16)
  98
  99 #define KVM_VGIC_V3_RDIST_INDEX_MASK    GENMASK_ULL(11, 0)
 100 #define KVM_VGIC_V3_RDIST_FLAGS_MASK    GENMASK_ULL(15, 12)
 101 #define KVM_VGIC_V3_RDIST_FLAGS_SHIFT   12
 102 #define KVM_VGIC_V3_RDIST_BASE_MASK     GENMASK_ULL(51, 16)
 103 #define KVM_VGIC_V3_RDIST_COUNT_MASK    GENMASK_ULL(63, 52)
 104 #define KVM_VGIC_V3_RDIST_COUNT_SHIFT   52
 105
 106 /* Requires the irq_lock to be held by the caller. */
 107 static inline bool irq_is_pending(struct vgic_irq *irq)
 108 {
 109         if (irq->config == VGIC_CONFIG_EDGE)
 110                 return irq->pending_latch;
 111         else
 112                 return irq->pending_latch || irq->line_level;
 113 }
 114
 115 static inline bool vgic_irq_is_mapped_level(struct vgic_irq *irq)
 116 {
 117         return irq->config == VGIC_CONFIG_LEVEL && irq->hw;
 118 }
 119
 120 static inline int vgic_irq_get_lr_count(struct vgic_irq *irq)
 121 {
 122         /* Account for the active state as an interrupt */
 123         if (vgic_irq_is_sgi(irq->intid) && irq->source)
 124                 return hweight8(irq->source) + irq->active;
 125
 126         return irq_is_pending(irq) || irq->active;
 127 }
 128
 129 static inline bool vgic_irq_is_multi_sgi(struct vgic_irq *irq)
 130 {
 131         return vgic_irq_get_lr_count(irq) > 1;
 132 }
 133
 134 /*
 135  * This struct provides an intermediate representation of the fields contained
 136  * in the GICH_VMCR and ICH_VMCR registers, such that code exporting the GIC
 137  * state to userspace can generate either GICv2 or GICv3 CPU interface
 138  * registers regardless of the hardware backed GIC used.
 139  */
 140 struct vgic_vmcr {
 141         u32     grpen0;
 142         u32     grpen1;
 143
 144         u32     ackctl;
 145         u32     fiqen;
 146         u32     cbpr;
 147         u32     eoim;
 148
 149         u32     abpr;
 150         u32     bpr;
 151         u32     pmr;  /* Priority mask field in the GICC_PMR and
 152                        * ICC_PMR_EL1 priority field format */
 153 };
 154
 155 struct vgic_reg_attr {
 156         struct kvm_vcpu *vcpu;
 157         gpa_t addr;
 158 };
 159
 160 int vgic_v3_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 161                        struct vgic_reg_attr *reg_attr);
 162 int vgic_v2_parse_attr(struct kvm_device *dev, struct kvm_device_attr *attr,
 163                        struct vgic_reg_attr *reg_attr);
 164 const struct vgic_register_region *
 165 vgic_get_mmio_region(struct kvm_vcpu *vcpu, struct vgic_io_device *iodev,
 166                      gpa_t addr, int len);
 167 struct vgic_irq *vgic_get_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
 168                               u32 intid);
 169 void vgic_put_irq(struct kvm *kvm, struct vgic_irq *irq);
 170 bool vgic_get_phys_line_level(struct vgic_irq *irq);
 171 void vgic_irq_set_phys_pending(struct vgic_irq *irq, bool pending);
 172 void vgic_irq_set_phys_active(struct vgic_irq *irq, bool active);
 173 bool vgic_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq,
 174                            unsigned long flags);
 175 void vgic_kick_vcpus(struct kvm *kvm);
 176
 177 int vgic_check_ioaddr(struct kvm *kvm, phys_addr_t *ioaddr,
 178                       phys_addr_t addr, phys_addr_t alignment);
 179
 180 void vgic_v2_fold_lr_state(struct kvm_vcpu *vcpu);
 181 void vgic_v2_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 182 void vgic_v2_clear_lr(struct kvm_vcpu *vcpu, int lr);
 183 void vgic_v2_set_underflow(struct kvm_vcpu *vcpu);
 184 void vgic_v2_set_npie(struct kvm_vcpu *vcpu);
 185 int vgic_v2_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 186 int vgic_v2_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 187                          int offset, u32 *val);
 188 int vgic_v2_cpuif_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 189                           int offset, u32 *val);
 190 void vgic_v2_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 191 void vgic_v2_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 192 void vgic_v2_enable(struct kvm_vcpu *vcpu);
 193 int vgic_v2_probe(const struct gic_kvm_info *info);
 194 int vgic_v2_map_resources(struct kvm *kvm);
 195 int vgic_register_dist_iodev(struct kvm *kvm, gpa_t dist_base_address,
 196                              enum vgic_type);
 197
 198 void vgic_v2_init_lrs(void);
 199 void vgic_v2_load(struct kvm_vcpu *vcpu);
 200 void vgic_v2_put(struct kvm_vcpu *vcpu);
 201
 202 void vgic_v2_save_state(struct kvm_vcpu *vcpu);
 203 void vgic_v2_restore_state(struct kvm_vcpu *vcpu);
 204
 205 static inline void vgic_get_irq_kref(struct vgic_irq *irq)
 206 {
 207         if (irq->intid < VGIC_MIN_LPI)
 208                 return;
 209
 210         kref_get(&irq->refcount);
 211 }
 212
 213 void vgic_v3_fold_lr_state(struct kvm_vcpu *vcpu);
 214 void vgic_v3_populate_lr(struct kvm_vcpu *vcpu, struct vgic_irq *irq, int lr);
 215 void vgic_v3_clear_lr(struct kvm_vcpu *vcpu, int lr);
 216 void vgic_v3_set_underflow(struct kvm_vcpu *vcpu);
 217 void vgic_v3_set_npie(struct kvm_vcpu *vcpu);
 218 void vgic_v3_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 219 void vgic_v3_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 220 void vgic_v3_enable(struct kvm_vcpu *vcpu);
 221 int vgic_v3_probe(const struct gic_kvm_info *info);
 222 int vgic_v3_map_resources(struct kvm *kvm);
 223 int vgic_v3_lpi_sync_pending_status(struct kvm *kvm, struct vgic_irq *irq);
 224 int vgic_v3_save_pending_tables(struct kvm *kvm);
 225 int vgic_v3_set_redist_base(struct kvm *kvm, u32 index, u64 addr, u32 count);
 226 int vgic_register_redist_iodev(struct kvm_vcpu *vcpu);
 227 bool vgic_v3_check_base(struct kvm *kvm);
 228
 229 void vgic_v3_load(struct kvm_vcpu *vcpu);
 230 void vgic_v3_put(struct kvm_vcpu *vcpu);
 231
 232 bool vgic_has_its(struct kvm *kvm);
 233 int kvm_vgic_register_its_device(void);
 234 void vgic_enable_lpis(struct kvm_vcpu *vcpu);
 235 int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi);
 236 int vgic_v3_has_attr_regs(struct kvm_device *dev, struct kvm_device_attr *attr);
 237 int vgic_v3_dist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 238                          int offset, u32 *val);
 239 int vgic_v3_redist_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 240                          int offset, u32 *val);
 241 int vgic_v3_cpu_sysregs_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 242                          u64 id, u64 *val);
 243 int vgic_v3_has_cpu_sysregs_attr(struct kvm_vcpu *vcpu, bool is_write, u64 id,
 244                                 u64 *reg);
 245 int vgic_v3_line_level_info_uaccess(struct kvm_vcpu *vcpu, bool is_write,
 246                                     u32 intid, u64 *val);
 247 int kvm_register_vgic_device(unsigned long type);
 248 void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 249 void vgic_get_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
 250 int vgic_lazy_init(struct kvm *kvm);
 251 int vgic_init(struct kvm *kvm);
 252
 253 void vgic_debug_init(struct kvm *kvm);
 254 void vgic_debug_destroy(struct kvm *kvm);
 255
 256 bool lock_all_vcpus(struct kvm *kvm);
 257 void unlock_all_vcpus(struct kvm *kvm);
 258
 259 static inline int vgic_v3_max_apr_idx(struct kvm_vcpu *vcpu)
 260 {
 261         struct vgic_cpu *cpu_if = &vcpu->arch.vgic_cpu;
 262
 263         /*
 264          * num_pri_bits are initialized with HW supported values.
 265          * We can rely safely on num_pri_bits even if VM has not
 266          * restored ICC_CTLR_EL1 before restoring APnR registers.
 267          */
 268         switch (cpu_if->num_pri_bits) {
 269         case 7: return 3;
 270         case 6: return 1;
 271         default: return 0;
 272         }
 273 }
 274
 275 static inline bool
 276 vgic_v3_redist_region_full(struct vgic_redist_region *region)
 277 {
 278         if (!region->count)
 279                 return false;
 280
 281         return (region->free_index >= region->count);
 282 }
 283
 284 struct vgic_redist_region *vgic_v3_rdist_free_slot(struct list_head *rdregs);
 285
 286 static inline size_t
 287 vgic_v3_rd_region_size(struct kvm *kvm, struct vgic_redist_region *rdreg)
 288 {
 289         if (!rdreg->count)
 290                 return atomic_read(&kvm->online_vcpus) * KVM_VGIC_V3_REDIST_SIZE;
 291         else
 292                 return rdreg->count * KVM_VGIC_V3_REDIST_SIZE;
 293 }
 294
 295 struct vgic_redist_region *vgic_v3_rdist_region_from_index(struct kvm *kvm,
 296                                                            u32 index);
 297
 298 bool vgic_v3_rdist_overlap(struct kvm *kvm, gpa_t base, size_t size);
 299
 300 static inline bool vgic_dist_overlap(struct kvm *kvm, gpa_t base, size_t size)
 301 {
 302         struct vgic_dist *d = &kvm->arch.vgic;
 303
 304         return (base + size > d->vgic_dist_base) &&
 305                 (base < d->vgic_dist_base + KVM_VGIC_V3_DIST_SIZE);
 306 }
 307
 308 int vgic_its_resolve_lpi(struct kvm *kvm, struct vgic_its *its,
 309                          u32 devid, u32 eventid, struct vgic_irq **irq);
 310 struct vgic_its *vgic_msi_to_its(struct kvm *kvm, struct kvm_msi *msi);
 311
 312 bool vgic_supports_direct_msis(struct kvm *kvm);
 313 int vgic_v4_init(struct kvm *kvm);
 314 void vgic_v4_teardown(struct kvm *kvm);
 315 int vgic_v4_sync_hwstate(struct kvm_vcpu *vcpu);
 316 int vgic_v4_flush_hwstate(struct kvm_vcpu *vcpu);
 317
 318 #endif