?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
i2c-viapro: Add support for the VT8237A and VT8251
[linux/fpc-iii.git] / drivers / net / r8169.c
blob78c532df4037312a0cf342b75d10201646911e04
1 /*
2 =========================================================================
3 r8169.c: A RealTek RTL-8169 Gigabit Ethernet driver for Linux kernel 2.4.x.
4 --------------------------------------------------------------------
5
6 History:
7 Feb 4 2002 - created initially by ShuChen <shuchen@realtek.com.tw>.
8 May 20 2002 - Add link status force-mode and TBI mode support.
9 2004 - Massive updates. See kernel SCM system for details.
10 =========================================================================
11 1. [DEPRECATED: use ethtool instead] The media can be forced in 5 modes.
12 Command: 'insmod r8169 media = SET_MEDIA'
13 Ex: 'insmod r8169 media = 0x04' will force PHY to operate in 100Mpbs Half-duplex.
14
15 SET_MEDIA can be:
16 _10_Half = 0x01
17 _10_Full = 0x02
18 _100_Half = 0x04
19 _100_Full = 0x08
20 _1000_Full = 0x10
21
22 2. Support TBI mode.
23 =========================================================================
24 VERSION 1.1 <2002/10/4>
25
26 The bit4:0 of MII register 4 is called "selector field", and have to be
27 00001b to indicate support of IEEE std 802.3 during NWay process of
28 exchanging Link Code Word (FLP).
29
30 VERSION 1.2 <2002/11/30>
31
32 - Large style cleanup
33 - Use ether_crc in stock kernel (linux/crc32.h)
34 - Copy mc_filter setup code from 8139cp
35 (includes an optimization, and avoids set_bit use)
36
37 VERSION 1.6LK <2004/04/14>
38
39 - Merge of Realtek's version 1.6
40 - Conversion to DMA API
41 - Suspend/resume
42 - Endianness
43 - Misc Rx/Tx bugs
44
45 VERSION 2.2LK <2005/01/25>
46
47 - RX csum, TX csum/SG, TSO
48 - VLAN
49 - baby (< 7200) Jumbo frames support
50 - Merge of Realtek's version 2.2 (new phy)
51 */
52
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/pci.h>
56 #include <linux/netdevice.h>
57 #include <linux/etherdevice.h>
58 #include <linux/delay.h>
59 #include <linux/ethtool.h>
60 #include <linux/mii.h>
61 #include <linux/if_vlan.h>
62 #include <linux/crc32.h>
63 #include <linux/in.h>
64 #include <linux/ip.h>
65 #include <linux/tcp.h>
66 #include <linux/init.h>
67 #include <linux/dma-mapping.h>
68
69 #include <asm/io.h>
70 #include <asm/irq.h>
71
72 #ifdef CONFIG_R8169_NAPI
73 #define NAPI_SUFFIX "-NAPI"
74 #else
75 #define NAPI_SUFFIX ""
76 #endif
77
78 #define RTL8169_VERSION "2.2LK" NAPI_SUFFIX
79 #define MODULENAME "r8169"
80 #define PFX MODULENAME ": "
81
82 #ifdef RTL8169_DEBUG
83 #define assert(expr) \
84 if(!(expr)) { \
85 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
86 #expr,__FILE__,__FUNCTION__,__LINE__); \
87 }
88 #define dprintk(fmt, args...) do { printk(PFX fmt, ## args); } while (0)
89 #else
90 #define assert(expr) do {} while (0)
91 #define dprintk(fmt, args...) do {} while (0)
92 #endif /* RTL8169_DEBUG */
93
94 #define R8169_MSG_DEFAULT \
95 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
96
97 #define TX_BUFFS_AVAIL(tp) \
98 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
99
100 #ifdef CONFIG_R8169_NAPI
101 #define rtl8169_rx_skb netif_receive_skb
102 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_receive_skb
103 #define rtl8169_rx_quota(count, quota) min(count, quota)
104 #else
105 #define rtl8169_rx_skb netif_rx
106 #define rtl8169_rx_hwaccel_skb vlan_hwaccel_rx
107 #define rtl8169_rx_quota(count, quota) count
108 #endif
109
110 /* media options */
111 #define MAX_UNITS 8
112 static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
113 static int num_media = 0;
114
115 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
116 static int max_interrupt_work = 20;
117
118 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
119 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
120 static int multicast_filter_limit = 32;
121
122 /* MAC address length */
123 #define MAC_ADDR_LEN 6
124
125 #define RX_FIFO_THRESH 7 /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
126 #define RX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
127 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
128 #define EarlyTxThld 0x3F /* 0x3F means NO early transmit */
129 #define RxPacketMaxSize 0x3FE8 /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
130 #define SafeMtu 0x1c20 /* ... actually life sucks beyond ~7k */
131 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
132
133 #define R8169_REGS_SIZE 256
134 #define R8169_NAPI_WEIGHT 64
135 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
136 #define NUM_RX_DESC 256 /* Number of Rx descriptor registers */
137 #define RX_BUF_SIZE 1536 /* Rx Buffer size */
138 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
139 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
140
141 #define RTL8169_TX_TIMEOUT (6*HZ)
142 #define RTL8169_PHY_TIMEOUT (10*HZ)
143
144 /* write/read MMIO register */
145 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
146 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
147 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
148 #define RTL_R8(reg) readb (ioaddr + (reg))
149 #define RTL_R16(reg) readw (ioaddr + (reg))
150 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
151
152 enum mac_version {
153 RTL_GIGA_MAC_VER_B = 0x00,
154 /* RTL_GIGA_MAC_VER_C = 0x03, */
155 RTL_GIGA_MAC_VER_D = 0x01,
156 RTL_GIGA_MAC_VER_E = 0x02,
157 RTL_GIGA_MAC_VER_X = 0x04 /* Greater than RTL_GIGA_MAC_VER_E */
158 };
159
160 enum phy_version {
161 RTL_GIGA_PHY_VER_C = 0x03, /* PHY Reg 0x03 bit0-3 == 0x0000 */
162 RTL_GIGA_PHY_VER_D = 0x04, /* PHY Reg 0x03 bit0-3 == 0x0000 */
163 RTL_GIGA_PHY_VER_E = 0x05, /* PHY Reg 0x03 bit0-3 == 0x0000 */
164 RTL_GIGA_PHY_VER_F = 0x06, /* PHY Reg 0x03 bit0-3 == 0x0001 */
165 RTL_GIGA_PHY_VER_G = 0x07, /* PHY Reg 0x03 bit0-3 == 0x0002 */
166 RTL_GIGA_PHY_VER_H = 0x08, /* PHY Reg 0x03 bit0-3 == 0x0003 */
167 };
168
169
170 #define _R(NAME,MAC,MASK) \
171 { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
172
173 static const struct {
174 const char *name;
175 u8 mac_version;
176 u32 RxConfigMask; /* Clears the bits supported by this chip */
177 } rtl_chip_info[] = {
178 _R("RTL8169", RTL_GIGA_MAC_VER_B, 0xff7e1880),
179 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_D, 0xff7e1880),
180 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_E, 0xff7e1880),
181 _R("RTL8169s/8110s", RTL_GIGA_MAC_VER_X, 0xff7e1880),
182 };
183 #undef _R
184
185 static struct pci_device_id rtl8169_pci_tbl[] = {
186 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), },
187 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), },
188 { PCI_DEVICE(0x16ec, 0x0116), },
189 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024, },
190 {0,},
191 };
192
193 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
194
195 static int rx_copybreak = 200;
196 static int use_dac;
197 static int ignore_parity_err;
198 static struct {
199 u32 msg_enable;
200 } debug = { -1 };
201
202 enum RTL8169_registers {
203 MAC0 = 0, /* Ethernet hardware address. */
204 MAR0 = 8, /* Multicast filter. */
205 CounterAddrLow = 0x10,
206 CounterAddrHigh = 0x14,
207 TxDescStartAddrLow = 0x20,
208 TxDescStartAddrHigh = 0x24,
209 TxHDescStartAddrLow = 0x28,
210 TxHDescStartAddrHigh = 0x2c,
211 FLASH = 0x30,
212 ERSR = 0x36,
213 ChipCmd = 0x37,
214 TxPoll = 0x38,
215 IntrMask = 0x3C,
216 IntrStatus = 0x3E,
217 TxConfig = 0x40,
218 RxConfig = 0x44,
219 RxMissed = 0x4C,
220 Cfg9346 = 0x50,
221 Config0 = 0x51,
222 Config1 = 0x52,
223 Config2 = 0x53,
224 Config3 = 0x54,
225 Config4 = 0x55,
226 Config5 = 0x56,
227 MultiIntr = 0x5C,
228 PHYAR = 0x60,
229 TBICSR = 0x64,
230 TBI_ANAR = 0x68,
231 TBI_LPAR = 0x6A,
232 PHYstatus = 0x6C,
233 RxMaxSize = 0xDA,
234 CPlusCmd = 0xE0,
235 IntrMitigate = 0xE2,
236 RxDescAddrLow = 0xE4,
237 RxDescAddrHigh = 0xE8,
238 EarlyTxThres = 0xEC,
239 FuncEvent = 0xF0,
240 FuncEventMask = 0xF4,
241 FuncPresetState = 0xF8,
242 FuncForceEvent = 0xFC,
243 };
244
245 enum RTL8169_register_content {
246 /* InterruptStatusBits */
247 SYSErr = 0x8000,
248 PCSTimeout = 0x4000,
249 SWInt = 0x0100,
250 TxDescUnavail = 0x80,
251 RxFIFOOver = 0x40,
252 LinkChg = 0x20,
253 RxOverflow = 0x10,
254 TxErr = 0x08,
255 TxOK = 0x04,
256 RxErr = 0x02,
257 RxOK = 0x01,
258
259 /* RxStatusDesc */
260 RxFOVF = (1 << 23),
261 RxRWT = (1 << 22),
262 RxRES = (1 << 21),
263 RxRUNT = (1 << 20),
264 RxCRC = (1 << 19),
265
266 /* ChipCmdBits */
267 CmdReset = 0x10,
268 CmdRxEnb = 0x08,
269 CmdTxEnb = 0x04,
270 RxBufEmpty = 0x01,
271
272 /* Cfg9346Bits */
273 Cfg9346_Lock = 0x00,
274 Cfg9346_Unlock = 0xC0,
275
276 /* rx_mode_bits */
277 AcceptErr = 0x20,
278 AcceptRunt = 0x10,
279 AcceptBroadcast = 0x08,
280 AcceptMulticast = 0x04,
281 AcceptMyPhys = 0x02,
282 AcceptAllPhys = 0x01,
283
284 /* RxConfigBits */
285 RxCfgFIFOShift = 13,
286 RxCfgDMAShift = 8,
287
288 /* TxConfigBits */
289 TxInterFrameGapShift = 24,
290 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
291
292 /* Config1 register p.24 */
293 PMEnable = (1 << 0), /* Power Management Enable */
294
295 /* Config3 register p.25 */
296 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
297 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
298
299 /* Config5 register p.27 */
300 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
301 MWF = (1 << 5), /* Accept Multicast wakeup frame */
302 UWF = (1 << 4), /* Accept Unicast wakeup frame */
303 LanWake = (1 << 1), /* LanWake enable/disable */
304 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
305
306 /* TBICSR p.28 */
307 TBIReset = 0x80000000,
308 TBILoopback = 0x40000000,
309 TBINwEnable = 0x20000000,
310 TBINwRestart = 0x10000000,
311 TBILinkOk = 0x02000000,
312 TBINwComplete = 0x01000000,
313
314 /* CPlusCmd p.31 */
315 RxVlan = (1 << 6),
316 RxChkSum = (1 << 5),
317 PCIDAC = (1 << 4),
318 PCIMulRW = (1 << 3),
319
320 /* rtl8169_PHYstatus */
321 TBI_Enable = 0x80,
322 TxFlowCtrl = 0x40,
323 RxFlowCtrl = 0x20,
324 _1000bpsF = 0x10,
325 _100bps = 0x08,
326 _10bps = 0x04,
327 LinkStatus = 0x02,
328 FullDup = 0x01,
329
330 /* GIGABIT_PHY_registers */
331 PHY_CTRL_REG = 0,
332 PHY_STAT_REG = 1,
333 PHY_AUTO_NEGO_REG = 4,
334 PHY_1000_CTRL_REG = 9,
335
336 /* GIGABIT_PHY_REG_BIT */
337 PHY_Restart_Auto_Nego = 0x0200,
338 PHY_Enable_Auto_Nego = 0x1000,
339
340 /* PHY_STAT_REG = 1 */
341 PHY_Auto_Neco_Comp = 0x0020,
342
343 /* PHY_AUTO_NEGO_REG = 4 */
344 PHY_Cap_10_Half = 0x0020,
345 PHY_Cap_10_Full = 0x0040,
346 PHY_Cap_100_Half = 0x0080,
347 PHY_Cap_100_Full = 0x0100,
348
349 /* PHY_1000_CTRL_REG = 9 */
350 PHY_Cap_1000_Full = 0x0200,
351
352 PHY_Cap_Null = 0x0,
353
354 /* _MediaType */
355 _10_Half = 0x01,
356 _10_Full = 0x02,
357 _100_Half = 0x04,
358 _100_Full = 0x08,
359 _1000_Full = 0x10,
360
361 /* _TBICSRBit */
362 TBILinkOK = 0x02000000,
363
364 /* DumpCounterCommand */
365 CounterDump = 0x8,
366 };
367
368 enum _DescStatusBit {
369 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
370 RingEnd = (1 << 30), /* End of descriptor ring */
371 FirstFrag = (1 << 29), /* First segment of a packet */
372 LastFrag = (1 << 28), /* Final segment of a packet */
373
374 /* Tx private */
375 LargeSend = (1 << 27), /* TCP Large Send Offload (TSO) */
376 MSSShift = 16, /* MSS value position */
377 MSSMask = 0xfff, /* MSS value + LargeSend bit: 12 bits */
378 IPCS = (1 << 18), /* Calculate IP checksum */
379 UDPCS = (1 << 17), /* Calculate UDP/IP checksum */
380 TCPCS = (1 << 16), /* Calculate TCP/IP checksum */
381 TxVlanTag = (1 << 17), /* Add VLAN tag */
382
383 /* Rx private */
384 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
385 PID0 = (1 << 17), /* Protocol ID bit 2/2 */
386
387 #define RxProtoUDP (PID1)
388 #define RxProtoTCP (PID0)
389 #define RxProtoIP (PID1 | PID0)
390 #define RxProtoMask RxProtoIP
391
392 IPFail = (1 << 16), /* IP checksum failed */
393 UDPFail = (1 << 15), /* UDP/IP checksum failed */
394 TCPFail = (1 << 14), /* TCP/IP checksum failed */
395 RxVlanTag = (1 << 16), /* VLAN tag available */
396 };
397
398 #define RsvdMask 0x3fffc000
399
400 struct TxDesc {
401 u32 opts1;
402 u32 opts2;
403 u64 addr;
404 };
405
406 struct RxDesc {
407 u32 opts1;
408 u32 opts2;
409 u64 addr;
410 };
411
412 struct ring_info {
413 struct sk_buff *skb;
414 u32 len;
415 u8 __pad[sizeof(void *) - sizeof(u32)];
416 };
417
418 struct rtl8169_private {
419 void __iomem *mmio_addr; /* memory map physical address */
420 struct pci_dev *pci_dev; /* Index of PCI device */
421 struct net_device_stats stats; /* statistics of net device */
422 spinlock_t lock; /* spin lock flag */
423 u32 msg_enable;
424 int chipset;
425 int mac_version;
426 int phy_version;
427 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
428 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
429 u32 dirty_rx;
430 u32 dirty_tx;
431 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
432 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
433 dma_addr_t TxPhyAddr;
434 dma_addr_t RxPhyAddr;
435 struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
436 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
437 unsigned rx_buf_sz;
438 struct timer_list timer;
439 u16 cp_cmd;
440 u16 intr_mask;
441 int phy_auto_nego_reg;
442 int phy_1000_ctrl_reg;
443 #ifdef CONFIG_R8169_VLAN
444 struct vlan_group *vlgrp;
445 #endif
446 int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
447 void (*get_settings)(struct net_device *, struct ethtool_cmd *);
448 void (*phy_reset_enable)(void __iomem *);
449 unsigned int (*phy_reset_pending)(void __iomem *);
450 unsigned int (*link_ok)(void __iomem *);
451 struct work_struct task;
452 unsigned wol_enabled : 1;
453 };
454
455 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
456 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
457 module_param_array(media, int, &num_media, 0);
458 MODULE_PARM_DESC(media, "force phy operation. Deprecated by ethtool (8).");
459 module_param(rx_copybreak, int, 0);
460 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
461 module_param(use_dac, int, 0);
462 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
463 module_param_named(debug, debug.msg_enable, int, 0);
464 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
465 module_param_named(ignore_parity_err, ignore_parity_err, bool, 0);
466 MODULE_PARM_DESC(ignore_parity_err, "Ignore PCI parity error as target. Default: false");
467 MODULE_LICENSE("GPL");
468 MODULE_VERSION(RTL8169_VERSION);
469
470 static int rtl8169_open(struct net_device *dev);
471 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
472 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance,
473 struct pt_regs *regs);
474 static int rtl8169_init_ring(struct net_device *dev);
475 static void rtl8169_hw_start(struct net_device *dev);
476 static int rtl8169_close(struct net_device *dev);
477 static void rtl8169_set_rx_mode(struct net_device *dev);
478 static void rtl8169_tx_timeout(struct net_device *dev);
479 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
480 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
481 void __iomem *);
482 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
483 static void rtl8169_down(struct net_device *dev);
484
485 #ifdef CONFIG_R8169_NAPI
486 static int rtl8169_poll(struct net_device *dev, int *budget);
487 #endif
488
489 static const u16 rtl8169_intr_mask =
490 SYSErr | LinkChg | RxOverflow | RxFIFOOver | TxErr | TxOK | RxErr | RxOK;
491 static const u16 rtl8169_napi_event =
492 RxOK | RxOverflow | RxFIFOOver | TxOK | TxErr;
493 static const unsigned int rtl8169_rx_config =
494 (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
495
496 #define PHY_Cap_10_Half_Or_Less PHY_Cap_10_Half
497 #define PHY_Cap_10_Full_Or_Less PHY_Cap_10_Full | PHY_Cap_10_Half_Or_Less
498 #define PHY_Cap_100_Half_Or_Less PHY_Cap_100_Half | PHY_Cap_10_Full_Or_Less
499 #define PHY_Cap_100_Full_Or_Less PHY_Cap_100_Full | PHY_Cap_100_Half_Or_Less
500
501 static void mdio_write(void __iomem *ioaddr, int RegAddr, int value)
502 {
503 int i;
504
505 RTL_W32(PHYAR, 0x80000000 | (RegAddr & 0xFF) << 16 | value);
506
507 for (i = 20; i > 0; i--) {
508 /* Check if the RTL8169 has completed writing to the specified MII register */
509 if (!(RTL_R32(PHYAR) & 0x80000000))
510 break;
511 udelay(25);
512 }
513 }
514
515 static int mdio_read(void __iomem *ioaddr, int RegAddr)
516 {
517 int i, value = -1;
518
519 RTL_W32(PHYAR, 0x0 | (RegAddr & 0xFF) << 16);
520
521 for (i = 20; i > 0; i--) {
522 /* Check if the RTL8169 has completed retrieving data from the specified MII register */
523 if (RTL_R32(PHYAR) & 0x80000000) {
524 value = (int) (RTL_R32(PHYAR) & 0xFFFF);
525 break;
526 }
527 udelay(25);
528 }
529 return value;
530 }
531
532 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
533 {
534 RTL_W16(IntrMask, 0x0000);
535
536 RTL_W16(IntrStatus, 0xffff);
537 }
538
539 static void rtl8169_asic_down(void __iomem *ioaddr)
540 {
541 RTL_W8(ChipCmd, 0x00);
542 rtl8169_irq_mask_and_ack(ioaddr);
543 RTL_R16(CPlusCmd);
544 }
545
546 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
547 {
548 return RTL_R32(TBICSR) & TBIReset;
549 }
550
551 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
552 {
553 return mdio_read(ioaddr, 0) & 0x8000;
554 }
555
556 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
557 {
558 return RTL_R32(TBICSR) & TBILinkOk;
559 }
560
561 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
562 {
563 return RTL_R8(PHYstatus) & LinkStatus;
564 }
565
566 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
567 {
568 RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
569 }
570
571 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
572 {
573 unsigned int val;
574
575 val = (mdio_read(ioaddr, PHY_CTRL_REG) | 0x8000) & 0xffff;
576 mdio_write(ioaddr, PHY_CTRL_REG, val);
577 }
578
579 static void rtl8169_check_link_status(struct net_device *dev,
580 struct rtl8169_private *tp, void __iomem *ioaddr)
581 {
582 unsigned long flags;
583
584 spin_lock_irqsave(&tp->lock, flags);
585 if (tp->link_ok(ioaddr)) {
586 netif_carrier_on(dev);
587 if (netif_msg_ifup(tp))
588 printk(KERN_INFO PFX "%s: link up\n", dev->name);
589 } else {
590 if (netif_msg_ifdown(tp))
591 printk(KERN_INFO PFX "%s: link down\n", dev->name);
592 netif_carrier_off(dev);
593 }
594 spin_unlock_irqrestore(&tp->lock, flags);
595 }
596
597 static void rtl8169_link_option(int idx, u8 *autoneg, u16 *speed, u8 *duplex)
598 {
599 struct {
600 u16 speed;
601 u8 duplex;
602 u8 autoneg;
603 u8 media;
604 } link_settings[] = {
605 { SPEED_10, DUPLEX_HALF, AUTONEG_DISABLE, _10_Half },
606 { SPEED_10, DUPLEX_FULL, AUTONEG_DISABLE, _10_Full },
607 { SPEED_100, DUPLEX_HALF, AUTONEG_DISABLE, _100_Half },
608 { SPEED_100, DUPLEX_FULL, AUTONEG_DISABLE, _100_Full },
609 { SPEED_1000, DUPLEX_FULL, AUTONEG_DISABLE, _1000_Full },
610 /* Make TBI happy */
611 { SPEED_1000, DUPLEX_FULL, AUTONEG_ENABLE, 0xff }
612 }, *p;
613 unsigned char option;
614
615 option = ((idx < MAX_UNITS) && (idx >= 0)) ? media[idx] : 0xff;
616
617 if ((option != 0xff) && !idx && netif_msg_drv(&debug))
618 printk(KERN_WARNING PFX "media option is deprecated.\n");
619
620 for (p = link_settings; p->media != 0xff; p++) {
621 if (p->media == option)
622 break;
623 }
624 *autoneg = p->autoneg;
625 *speed = p->speed;
626 *duplex = p->duplex;
627 }
628
629 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
630 {
631 struct rtl8169_private *tp = netdev_priv(dev);
632 void __iomem *ioaddr = tp->mmio_addr;
633 u8 options;
634
635 wol->wolopts = 0;
636
637 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
638 wol->supported = WAKE_ANY;
639
640 spin_lock_irq(&tp->lock);
641
642 options = RTL_R8(Config1);
643 if (!(options & PMEnable))
644 goto out_unlock;
645
646 options = RTL_R8(Config3);
647 if (options & LinkUp)
648 wol->wolopts |= WAKE_PHY;
649 if (options & MagicPacket)
650 wol->wolopts |= WAKE_MAGIC;
651
652 options = RTL_R8(Config5);
653 if (options & UWF)
654 wol->wolopts |= WAKE_UCAST;
655 if (options & BWF)
656 wol->wolopts |= WAKE_BCAST;
657 if (options & MWF)
658 wol->wolopts |= WAKE_MCAST;
659
660 out_unlock:
661 spin_unlock_irq(&tp->lock);
662 }
663
664 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
665 {
666 struct rtl8169_private *tp = netdev_priv(dev);
667 void __iomem *ioaddr = tp->mmio_addr;
668 int i;
669 static struct {
670 u32 opt;
671 u16 reg;
672 u8 mask;
673 } cfg[] = {
674 { WAKE_ANY, Config1, PMEnable },
675 { WAKE_PHY, Config3, LinkUp },
676 { WAKE_MAGIC, Config3, MagicPacket },
677 { WAKE_UCAST, Config5, UWF },
678 { WAKE_BCAST, Config5, BWF },
679 { WAKE_MCAST, Config5, MWF },
680 { WAKE_ANY, Config5, LanWake }
681 };
682
683 spin_lock_irq(&tp->lock);
684
685 RTL_W8(Cfg9346, Cfg9346_Unlock);
686
687 for (i = 0; i < ARRAY_SIZE(cfg); i++) {
688 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
689 if (wol->wolopts & cfg[i].opt)
690 options |= cfg[i].mask;
691 RTL_W8(cfg[i].reg, options);
692 }
693
694 RTL_W8(Cfg9346, Cfg9346_Lock);
695
696 tp->wol_enabled = (wol->wolopts) ? 1 : 0;
697
698 spin_unlock_irq(&tp->lock);
699
700 return 0;
701 }
702
703 static void rtl8169_get_drvinfo(struct net_device *dev,
704 struct ethtool_drvinfo *info)
705 {
706 struct rtl8169_private *tp = netdev_priv(dev);
707
708 strcpy(info->driver, MODULENAME);
709 strcpy(info->version, RTL8169_VERSION);
710 strcpy(info->bus_info, pci_name(tp->pci_dev));
711 }
712
713 static int rtl8169_get_regs_len(struct net_device *dev)
714 {
715 return R8169_REGS_SIZE;
716 }
717
718 static int rtl8169_set_speed_tbi(struct net_device *dev,
719 u8 autoneg, u16 speed, u8 duplex)
720 {
721 struct rtl8169_private *tp = netdev_priv(dev);
722 void __iomem *ioaddr = tp->mmio_addr;
723 int ret = 0;
724 u32 reg;
725
726 reg = RTL_R32(TBICSR);
727 if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
728 (duplex == DUPLEX_FULL)) {
729 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
730 } else if (autoneg == AUTONEG_ENABLE)
731 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
732 else {
733 if (netif_msg_link(tp)) {
734 printk(KERN_WARNING "%s: "
735 "incorrect speed setting refused in TBI mode\n",
736 dev->name);
737 }
738 ret = -EOPNOTSUPP;
739 }
740
741 return ret;
742 }
743
744 static int rtl8169_set_speed_xmii(struct net_device *dev,
745 u8 autoneg, u16 speed, u8 duplex)
746 {
747 struct rtl8169_private *tp = netdev_priv(dev);
748 void __iomem *ioaddr = tp->mmio_addr;
749 int auto_nego, giga_ctrl;
750
751 auto_nego = mdio_read(ioaddr, PHY_AUTO_NEGO_REG);
752 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_10_Full |
753 PHY_Cap_100_Half | PHY_Cap_100_Full);
754 giga_ctrl = mdio_read(ioaddr, PHY_1000_CTRL_REG);
755 giga_ctrl &= ~(PHY_Cap_1000_Full | PHY_Cap_Null);
756
757 if (autoneg == AUTONEG_ENABLE) {
758 auto_nego |= (PHY_Cap_10_Half | PHY_Cap_10_Full |
759 PHY_Cap_100_Half | PHY_Cap_100_Full);
760 giga_ctrl |= PHY_Cap_1000_Full;
761 } else {
762 if (speed == SPEED_10)
763 auto_nego |= PHY_Cap_10_Half | PHY_Cap_10_Full;
764 else if (speed == SPEED_100)
765 auto_nego |= PHY_Cap_100_Half | PHY_Cap_100_Full;
766 else if (speed == SPEED_1000)
767 giga_ctrl |= PHY_Cap_1000_Full;
768
769 if (duplex == DUPLEX_HALF)
770 auto_nego &= ~(PHY_Cap_10_Full | PHY_Cap_100_Full);
771
772 if (duplex == DUPLEX_FULL)
773 auto_nego &= ~(PHY_Cap_10_Half | PHY_Cap_100_Half);
774 }
775
776 tp->phy_auto_nego_reg = auto_nego;
777 tp->phy_1000_ctrl_reg = giga_ctrl;
778
779 mdio_write(ioaddr, PHY_AUTO_NEGO_REG, auto_nego);
780 mdio_write(ioaddr, PHY_1000_CTRL_REG, giga_ctrl);
781 mdio_write(ioaddr, PHY_CTRL_REG, PHY_Enable_Auto_Nego |
782 PHY_Restart_Auto_Nego);
783 return 0;
784 }
785
786 static int rtl8169_set_speed(struct net_device *dev,
787 u8 autoneg, u16 speed, u8 duplex)
788 {
789 struct rtl8169_private *tp = netdev_priv(dev);
790 int ret;
791
792 ret = tp->set_speed(dev, autoneg, speed, duplex);
793
794 if (netif_running(dev) && (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
795 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
796
797 return ret;
798 }
799
800 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
801 {
802 struct rtl8169_private *tp = netdev_priv(dev);
803 unsigned long flags;
804 int ret;
805
806 spin_lock_irqsave(&tp->lock, flags);
807 ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
808 spin_unlock_irqrestore(&tp->lock, flags);
809
810 return ret;
811 }
812
813 static u32 rtl8169_get_rx_csum(struct net_device *dev)
814 {
815 struct rtl8169_private *tp = netdev_priv(dev);
816
817 return tp->cp_cmd & RxChkSum;
818 }
819
820 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
821 {
822 struct rtl8169_private *tp = netdev_priv(dev);
823 void __iomem *ioaddr = tp->mmio_addr;
824 unsigned long flags;
825
826 spin_lock_irqsave(&tp->lock, flags);
827
828 if (data)
829 tp->cp_cmd |= RxChkSum;
830 else
831 tp->cp_cmd &= ~RxChkSum;
832
833 RTL_W16(CPlusCmd, tp->cp_cmd);
834 RTL_R16(CPlusCmd);
835
836 spin_unlock_irqrestore(&tp->lock, flags);
837
838 return 0;
839 }
840
841 #ifdef CONFIG_R8169_VLAN
842
843 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
844 struct sk_buff *skb)
845 {
846 return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
847 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
848 }
849
850 static void rtl8169_vlan_rx_register(struct net_device *dev,
851 struct vlan_group *grp)
852 {
853 struct rtl8169_private *tp = netdev_priv(dev);
854 void __iomem *ioaddr = tp->mmio_addr;
855 unsigned long flags;
856
857 spin_lock_irqsave(&tp->lock, flags);
858 tp->vlgrp = grp;
859 if (tp->vlgrp)
860 tp->cp_cmd |= RxVlan;
861 else
862 tp->cp_cmd &= ~RxVlan;
863 RTL_W16(CPlusCmd, tp->cp_cmd);
864 RTL_R16(CPlusCmd);
865 spin_unlock_irqrestore(&tp->lock, flags);
866 }
867
868 static void rtl8169_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
869 {
870 struct rtl8169_private *tp = netdev_priv(dev);
871 unsigned long flags;
872
873 spin_lock_irqsave(&tp->lock, flags);
874 if (tp->vlgrp)
875 tp->vlgrp->vlan_devices[vid] = NULL;
876 spin_unlock_irqrestore(&tp->lock, flags);
877 }
878
879 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
880 struct sk_buff *skb)
881 {
882 u32 opts2 = le32_to_cpu(desc->opts2);
883 int ret;
884
885 if (tp->vlgrp && (opts2 & RxVlanTag)) {
886 rtl8169_rx_hwaccel_skb(skb, tp->vlgrp,
887 swab16(opts2 & 0xffff));
888 ret = 0;
889 } else
890 ret = -1;
891 desc->opts2 = 0;
892 return ret;
893 }
894
895 #else /* !CONFIG_R8169_VLAN */
896
897 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
898 struct sk_buff *skb)
899 {
900 return 0;
901 }
902
903 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
904 struct sk_buff *skb)
905 {
906 return -1;
907 }
908
909 #endif
910
911 static void rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
912 {
913 struct rtl8169_private *tp = netdev_priv(dev);
914 void __iomem *ioaddr = tp->mmio_addr;
915 u32 status;
916
917 cmd->supported =
918 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
919 cmd->port = PORT_FIBRE;
920 cmd->transceiver = XCVR_INTERNAL;
921
922 status = RTL_R32(TBICSR);
923 cmd->advertising = (status & TBINwEnable) ? ADVERTISED_Autoneg : 0;
924 cmd->autoneg = !!(status & TBINwEnable);
925
926 cmd->speed = SPEED_1000;
927 cmd->duplex = DUPLEX_FULL; /* Always set */
928 }
929
930 static void rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
931 {
932 struct rtl8169_private *tp = netdev_priv(dev);
933 void __iomem *ioaddr = tp->mmio_addr;
934 u8 status;
935
936 cmd->supported = SUPPORTED_10baseT_Half |
937 SUPPORTED_10baseT_Full |
938 SUPPORTED_100baseT_Half |
939 SUPPORTED_100baseT_Full |
940 SUPPORTED_1000baseT_Full |
941 SUPPORTED_Autoneg |
942 SUPPORTED_TP;
943
944 cmd->autoneg = 1;
945 cmd->advertising = ADVERTISED_TP | ADVERTISED_Autoneg;
946
947 if (tp->phy_auto_nego_reg & PHY_Cap_10_Half)
948 cmd->advertising |= ADVERTISED_10baseT_Half;
949 if (tp->phy_auto_nego_reg & PHY_Cap_10_Full)
950 cmd->advertising |= ADVERTISED_10baseT_Full;
951 if (tp->phy_auto_nego_reg & PHY_Cap_100_Half)
952 cmd->advertising |= ADVERTISED_100baseT_Half;
953 if (tp->phy_auto_nego_reg & PHY_Cap_100_Full)
954 cmd->advertising |= ADVERTISED_100baseT_Full;
955 if (tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full)
956 cmd->advertising |= ADVERTISED_1000baseT_Full;
957
958 status = RTL_R8(PHYstatus);
959
960 if (status & _1000bpsF)
961 cmd->speed = SPEED_1000;
962 else if (status & _100bps)
963 cmd->speed = SPEED_100;
964 else if (status & _10bps)
965 cmd->speed = SPEED_10;
966
967 cmd->duplex = ((status & _1000bpsF) || (status & FullDup)) ?
968 DUPLEX_FULL : DUPLEX_HALF;
969 }
970
971 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
972 {
973 struct rtl8169_private *tp = netdev_priv(dev);
974 unsigned long flags;
975
976 spin_lock_irqsave(&tp->lock, flags);
977
978 tp->get_settings(dev, cmd);
979
980 spin_unlock_irqrestore(&tp->lock, flags);
981 return 0;
982 }
983
984 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
985 void *p)
986 {
987 struct rtl8169_private *tp = netdev_priv(dev);
988 unsigned long flags;
989
990 if (regs->len > R8169_REGS_SIZE)
991 regs->len = R8169_REGS_SIZE;
992
993 spin_lock_irqsave(&tp->lock, flags);
994 memcpy_fromio(p, tp->mmio_addr, regs->len);
995 spin_unlock_irqrestore(&tp->lock, flags);
996 }
997
998 static u32 rtl8169_get_msglevel(struct net_device *dev)
999 {
1000 struct rtl8169_private *tp = netdev_priv(dev);
1001
1002 return tp->msg_enable;
1003 }
1004
1005 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1006 {
1007 struct rtl8169_private *tp = netdev_priv(dev);
1008
1009 tp->msg_enable = value;
1010 }
1011
1012 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1013 "tx_packets",
1014 "rx_packets",
1015 "tx_errors",
1016 "rx_errors",
1017 "rx_missed",
1018 "align_errors",
1019 "tx_single_collisions",
1020 "tx_multi_collisions",
1021 "unicast",
1022 "broadcast",
1023 "multicast",
1024 "tx_aborted",
1025 "tx_underrun",
1026 };
1027
1028 struct rtl8169_counters {
1029 u64 tx_packets;
1030 u64 rx_packets;
1031 u64 tx_errors;
1032 u32 rx_errors;
1033 u16 rx_missed;
1034 u16 align_errors;
1035 u32 tx_one_collision;
1036 u32 tx_multi_collision;
1037 u64 rx_unicast;
1038 u64 rx_broadcast;
1039 u32 rx_multicast;
1040 u16 tx_aborted;
1041 u16 tx_underun;
1042 };
1043
1044 static int rtl8169_get_stats_count(struct net_device *dev)
1045 {
1046 return ARRAY_SIZE(rtl8169_gstrings);
1047 }
1048
1049 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1050 struct ethtool_stats *stats, u64 *data)
1051 {
1052 struct rtl8169_private *tp = netdev_priv(dev);
1053 void __iomem *ioaddr = tp->mmio_addr;
1054 struct rtl8169_counters *counters;
1055 dma_addr_t paddr;
1056 u32 cmd;
1057
1058 ASSERT_RTNL();
1059
1060 counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1061 if (!counters)
1062 return;
1063
1064 RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1065 cmd = (u64)paddr & DMA_32BIT_MASK;
1066 RTL_W32(CounterAddrLow, cmd);
1067 RTL_W32(CounterAddrLow, cmd | CounterDump);
1068
1069 while (RTL_R32(CounterAddrLow) & CounterDump) {
1070 if (msleep_interruptible(1))
1071 break;
1072 }
1073
1074 RTL_W32(CounterAddrLow, 0);
1075 RTL_W32(CounterAddrHigh, 0);
1076
1077 data[0] = le64_to_cpu(counters->tx_packets);
1078 data[1] = le64_to_cpu(counters->rx_packets);
1079 data[2] = le64_to_cpu(counters->tx_errors);
1080 data[3] = le32_to_cpu(counters->rx_errors);
1081 data[4] = le16_to_cpu(counters->rx_missed);
1082 data[5] = le16_to_cpu(counters->align_errors);
1083 data[6] = le32_to_cpu(counters->tx_one_collision);
1084 data[7] = le32_to_cpu(counters->tx_multi_collision);
1085 data[8] = le64_to_cpu(counters->rx_unicast);
1086 data[9] = le64_to_cpu(counters->rx_broadcast);
1087 data[10] = le32_to_cpu(counters->rx_multicast);
1088 data[11] = le16_to_cpu(counters->tx_aborted);
1089 data[12] = le16_to_cpu(counters->tx_underun);
1090
1091 pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1092 }
1093
1094 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1095 {
1096 switch(stringset) {
1097 case ETH_SS_STATS:
1098 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1099 break;
1100 }
1101 }
1102
1103
1104 static struct ethtool_ops rtl8169_ethtool_ops = {
1105 .get_drvinfo = rtl8169_get_drvinfo,
1106 .get_regs_len = rtl8169_get_regs_len,
1107 .get_link = ethtool_op_get_link,
1108 .get_settings = rtl8169_get_settings,
1109 .set_settings = rtl8169_set_settings,
1110 .get_msglevel = rtl8169_get_msglevel,
1111 .set_msglevel = rtl8169_set_msglevel,
1112 .get_rx_csum = rtl8169_get_rx_csum,
1113 .set_rx_csum = rtl8169_set_rx_csum,
1114 .get_tx_csum = ethtool_op_get_tx_csum,
1115 .set_tx_csum = ethtool_op_set_tx_csum,
1116 .get_sg = ethtool_op_get_sg,
1117 .set_sg = ethtool_op_set_sg,
1118 .get_tso = ethtool_op_get_tso,
1119 .set_tso = ethtool_op_set_tso,
1120 .get_regs = rtl8169_get_regs,
1121 .get_wol = rtl8169_get_wol,
1122 .set_wol = rtl8169_set_wol,
1123 .get_strings = rtl8169_get_strings,
1124 .get_stats_count = rtl8169_get_stats_count,
1125 .get_ethtool_stats = rtl8169_get_ethtool_stats,
1126 .get_perm_addr = ethtool_op_get_perm_addr,
1127 };
1128
1129 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg, int bitnum,
1130 int bitval)
1131 {
1132 int val;
1133
1134 val = mdio_read(ioaddr, reg);
1135 val = (bitval == 1) ?
1136 val | (bitval << bitnum) : val & ~(0x0001 << bitnum);
1137 mdio_write(ioaddr, reg, val & 0xffff);
1138 }
1139
1140 static void rtl8169_get_mac_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1141 {
1142 const struct {
1143 u32 mask;
1144 int mac_version;
1145 } mac_info[] = {
1146 { 0x1 << 28, RTL_GIGA_MAC_VER_X },
1147 { 0x1 << 26, RTL_GIGA_MAC_VER_E },
1148 { 0x1 << 23, RTL_GIGA_MAC_VER_D },
1149 { 0x00000000, RTL_GIGA_MAC_VER_B } /* Catch-all */
1150 }, *p = mac_info;
1151 u32 reg;
1152
1153 reg = RTL_R32(TxConfig) & 0x7c800000;
1154 while ((reg & p->mask) != p->mask)
1155 p++;
1156 tp->mac_version = p->mac_version;
1157 }
1158
1159 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1160 {
1161 struct {
1162 int version;
1163 char *msg;
1164 } mac_print[] = {
1165 { RTL_GIGA_MAC_VER_E, "RTL_GIGA_MAC_VER_E" },
1166 { RTL_GIGA_MAC_VER_D, "RTL_GIGA_MAC_VER_D" },
1167 { RTL_GIGA_MAC_VER_B, "RTL_GIGA_MAC_VER_B" },
1168 { 0, NULL }
1169 }, *p;
1170
1171 for (p = mac_print; p->msg; p++) {
1172 if (tp->mac_version == p->version) {
1173 dprintk("mac_version == %s (%04d)\n", p->msg,
1174 p->version);
1175 return;
1176 }
1177 }
1178 dprintk("mac_version == Unknown\n");
1179 }
1180
1181 static void rtl8169_get_phy_version(struct rtl8169_private *tp, void __iomem *ioaddr)
1182 {
1183 const struct {
1184 u16 mask;
1185 u16 set;
1186 int phy_version;
1187 } phy_info[] = {
1188 { 0x000f, 0x0002, RTL_GIGA_PHY_VER_G },
1189 { 0x000f, 0x0001, RTL_GIGA_PHY_VER_F },
1190 { 0x000f, 0x0000, RTL_GIGA_PHY_VER_E },
1191 { 0x0000, 0x0000, RTL_GIGA_PHY_VER_D } /* Catch-all */
1192 }, *p = phy_info;
1193 u16 reg;
1194
1195 reg = mdio_read(ioaddr, 3) & 0xffff;
1196 while ((reg & p->mask) != p->set)
1197 p++;
1198 tp->phy_version = p->phy_version;
1199 }
1200
1201 static void rtl8169_print_phy_version(struct rtl8169_private *tp)
1202 {
1203 struct {
1204 int version;
1205 char *msg;
1206 u32 reg;
1207 } phy_print[] = {
1208 { RTL_GIGA_PHY_VER_G, "RTL_GIGA_PHY_VER_G", 0x0002 },
1209 { RTL_GIGA_PHY_VER_F, "RTL_GIGA_PHY_VER_F", 0x0001 },
1210 { RTL_GIGA_PHY_VER_E, "RTL_GIGA_PHY_VER_E", 0x0000 },
1211 { RTL_GIGA_PHY_VER_D, "RTL_GIGA_PHY_VER_D", 0x0000 },
1212 { 0, NULL, 0x0000 }
1213 }, *p;
1214
1215 for (p = phy_print; p->msg; p++) {
1216 if (tp->phy_version == p->version) {
1217 dprintk("phy_version == %s (%04x)\n", p->msg, p->reg);
1218 return;
1219 }
1220 }
1221 dprintk("phy_version == Unknown\n");
1222 }
1223
1224 static void rtl8169_hw_phy_config(struct net_device *dev)
1225 {
1226 struct rtl8169_private *tp = netdev_priv(dev);
1227 void __iomem *ioaddr = tp->mmio_addr;
1228 struct {
1229 u16 regs[5]; /* Beware of bit-sign propagation */
1230 } phy_magic[5] = { {
1231 { 0x0000, //w 4 15 12 0
1232 0x00a1, //w 3 15 0 00a1
1233 0x0008, //w 2 15 0 0008
1234 0x1020, //w 1 15 0 1020
1235 0x1000 } },{ //w 0 15 0 1000
1236 { 0x7000, //w 4 15 12 7
1237 0xff41, //w 3 15 0 ff41
1238 0xde60, //w 2 15 0 de60
1239 0x0140, //w 1 15 0 0140
1240 0x0077 } },{ //w 0 15 0 0077
1241 { 0xa000, //w 4 15 12 a
1242 0xdf01, //w 3 15 0 df01
1243 0xdf20, //w 2 15 0 df20
1244 0xff95, //w 1 15 0 ff95
1245 0xfa00 } },{ //w 0 15 0 fa00
1246 { 0xb000, //w 4 15 12 b
1247 0xff41, //w 3 15 0 ff41
1248 0xde20, //w 2 15 0 de20
1249 0x0140, //w 1 15 0 0140
1250 0x00bb } },{ //w 0 15 0 00bb
1251 { 0xf000, //w 4 15 12 f
1252 0xdf01, //w 3 15 0 df01
1253 0xdf20, //w 2 15 0 df20
1254 0xff95, //w 1 15 0 ff95
1255 0xbf00 } //w 0 15 0 bf00
1256 }
1257 }, *p = phy_magic;
1258 int i;
1259
1260 rtl8169_print_mac_version(tp);
1261 rtl8169_print_phy_version(tp);
1262
1263 if (tp->mac_version <= RTL_GIGA_MAC_VER_B)
1264 return;
1265 if (tp->phy_version >= RTL_GIGA_PHY_VER_H)
1266 return;
1267
1268 dprintk("MAC version != 0 && PHY version == 0 or 1\n");
1269 dprintk("Do final_reg2.cfg\n");
1270
1271 /* Shazam ! */
1272
1273 if (tp->mac_version == RTL_GIGA_MAC_VER_X) {
1274 mdio_write(ioaddr, 31, 0x0001);
1275 mdio_write(ioaddr, 9, 0x273a);
1276 mdio_write(ioaddr, 14, 0x7bfb);
1277 mdio_write(ioaddr, 27, 0x841e);
1278
1279 mdio_write(ioaddr, 31, 0x0002);
1280 mdio_write(ioaddr, 1, 0x90d0);
1281 mdio_write(ioaddr, 31, 0x0000);
1282 return;
1283 }
1284
1285 /* phy config for RTL8169s mac_version C chip */
1286 mdio_write(ioaddr, 31, 0x0001); //w 31 2 0 1
1287 mdio_write(ioaddr, 21, 0x1000); //w 21 15 0 1000
1288 mdio_write(ioaddr, 24, 0x65c7); //w 24 15 0 65c7
1289 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1290
1291 for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1292 int val, pos = 4;
1293
1294 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1295 mdio_write(ioaddr, pos, val);
1296 while (--pos >= 0)
1297 mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1298 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1299 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1300 }
1301 mdio_write(ioaddr, 31, 0x0000); //w 31 2 0 0
1302 }
1303
1304 static void rtl8169_phy_timer(unsigned long __opaque)
1305 {
1306 struct net_device *dev = (struct net_device *)__opaque;
1307 struct rtl8169_private *tp = netdev_priv(dev);
1308 struct timer_list *timer = &tp->timer;
1309 void __iomem *ioaddr = tp->mmio_addr;
1310 unsigned long timeout = RTL8169_PHY_TIMEOUT;
1311
1312 assert(tp->mac_version > RTL_GIGA_MAC_VER_B);
1313 assert(tp->phy_version < RTL_GIGA_PHY_VER_H);
1314
1315 if (!(tp->phy_1000_ctrl_reg & PHY_Cap_1000_Full))
1316 return;
1317
1318 spin_lock_irq(&tp->lock);
1319
1320 if (tp->phy_reset_pending(ioaddr)) {
1321 /*
1322 * A busy loop could burn quite a few cycles on nowadays CPU.
1323 * Let's delay the execution of the timer for a few ticks.
1324 */
1325 timeout = HZ/10;
1326 goto out_mod_timer;
1327 }
1328
1329 if (tp->link_ok(ioaddr))
1330 goto out_unlock;
1331
1332 if (netif_msg_link(tp))
1333 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1334
1335 tp->phy_reset_enable(ioaddr);
1336
1337 out_mod_timer:
1338 mod_timer(timer, jiffies + timeout);
1339 out_unlock:
1340 spin_unlock_irq(&tp->lock);
1341 }
1342
1343 static inline void rtl8169_delete_timer(struct net_device *dev)
1344 {
1345 struct rtl8169_private *tp = netdev_priv(dev);
1346 struct timer_list *timer = &tp->timer;
1347
1348 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1349 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1350 return;
1351
1352 del_timer_sync(timer);
1353 }
1354
1355 static inline void rtl8169_request_timer(struct net_device *dev)
1356 {
1357 struct rtl8169_private *tp = netdev_priv(dev);
1358 struct timer_list *timer = &tp->timer;
1359
1360 if ((tp->mac_version <= RTL_GIGA_MAC_VER_B) ||
1361 (tp->phy_version >= RTL_GIGA_PHY_VER_H))
1362 return;
1363
1364 init_timer(timer);
1365 timer->expires = jiffies + RTL8169_PHY_TIMEOUT;
1366 timer->data = (unsigned long)(dev);
1367 timer->function = rtl8169_phy_timer;
1368 add_timer(timer);
1369 }
1370
1371 #ifdef CONFIG_NET_POLL_CONTROLLER
1372 /*
1373 * Polling 'interrupt' - used by things like netconsole to send skbs
1374 * without having to re-enable interrupts. It's not called while
1375 * the interrupt routine is executing.
1376 */
1377 static void rtl8169_netpoll(struct net_device *dev)
1378 {
1379 struct rtl8169_private *tp = netdev_priv(dev);
1380 struct pci_dev *pdev = tp->pci_dev;
1381
1382 disable_irq(pdev->irq);
1383 rtl8169_interrupt(pdev->irq, dev, NULL);
1384 enable_irq(pdev->irq);
1385 }
1386 #endif
1387
1388 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1389 void __iomem *ioaddr)
1390 {
1391 iounmap(ioaddr);
1392 pci_release_regions(pdev);
1393 pci_disable_device(pdev);
1394 free_netdev(dev);
1395 }
1396
1397 static int __devinit
1398 rtl8169_init_board(struct pci_dev *pdev, struct net_device **dev_out,
1399 void __iomem **ioaddr_out)
1400 {
1401 void __iomem *ioaddr;
1402 struct net_device *dev;
1403 struct rtl8169_private *tp;
1404 int rc = -ENOMEM, i, acpi_idle_state = 0, pm_cap;
1405
1406 assert(ioaddr_out != NULL);
1407
1408 /* dev zeroed in alloc_etherdev */
1409 dev = alloc_etherdev(sizeof (*tp));
1410 if (dev == NULL) {
1411 if (netif_msg_drv(&debug))
1412 printk(KERN_ERR PFX "unable to alloc new ethernet\n");
1413 goto err_out;
1414 }
1415
1416 SET_MODULE_OWNER(dev);
1417 SET_NETDEV_DEV(dev, &pdev->dev);
1418 tp = netdev_priv(dev);
1419 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
1420
1421 /* enable device (incl. PCI PM wakeup and hotplug setup) */
1422 rc = pci_enable_device(pdev);
1423 if (rc < 0) {
1424 if (netif_msg_probe(tp)) {
1425 printk(KERN_ERR PFX "%s: enable failure\n",
1426 pci_name(pdev));
1427 }
1428 goto err_out_free_dev;
1429 }
1430
1431 rc = pci_set_mwi(pdev);
1432 if (rc < 0)
1433 goto err_out_disable;
1434
1435 /* save power state before pci_enable_device overwrites it */
1436 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
1437 if (pm_cap) {
1438 u16 pwr_command;
1439
1440 pci_read_config_word(pdev, pm_cap + PCI_PM_CTRL, &pwr_command);
1441 acpi_idle_state = pwr_command & PCI_PM_CTRL_STATE_MASK;
1442 } else {
1443 if (netif_msg_probe(tp)) {
1444 printk(KERN_ERR PFX
1445 "PowerManagement capability not found.\n");
1446 }
1447 }
1448
1449 /* make sure PCI base addr 1 is MMIO */
1450 if (!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
1451 if (netif_msg_probe(tp)) {
1452 printk(KERN_ERR PFX
1453 "region #1 not an MMIO resource, aborting\n");
1454 }
1455 rc = -ENODEV;
1456 goto err_out_mwi;
1457 }
1458 /* check for weird/broken PCI region reporting */
1459 if (pci_resource_len(pdev, 1) < R8169_REGS_SIZE) {
1460 if (netif_msg_probe(tp)) {
1461 printk(KERN_ERR PFX
1462 "Invalid PCI region size(s), aborting\n");
1463 }
1464 rc = -ENODEV;
1465 goto err_out_mwi;
1466 }
1467
1468 rc = pci_request_regions(pdev, MODULENAME);
1469 if (rc < 0) {
1470 if (netif_msg_probe(tp)) {
1471 printk(KERN_ERR PFX "%s: could not request regions.\n",
1472 pci_name(pdev));
1473 }
1474 goto err_out_mwi;
1475 }
1476
1477 tp->cp_cmd = PCIMulRW | RxChkSum;
1478
1479 if ((sizeof(dma_addr_t) > 4) &&
1480 !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
1481 tp->cp_cmd |= PCIDAC;
1482 dev->features |= NETIF_F_HIGHDMA;
1483 } else {
1484 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1485 if (rc < 0) {
1486 if (netif_msg_probe(tp)) {
1487 printk(KERN_ERR PFX
1488 "DMA configuration failed.\n");
1489 }
1490 goto err_out_free_res;
1491 }
1492 }
1493
1494 pci_set_master(pdev);
1495
1496 /* ioremap MMIO region */
1497 ioaddr = ioremap(pci_resource_start(pdev, 1), R8169_REGS_SIZE);
1498 if (ioaddr == NULL) {
1499 if (netif_msg_probe(tp))
1500 printk(KERN_ERR PFX "cannot remap MMIO, aborting\n");
1501 rc = -EIO;
1502 goto err_out_free_res;
1503 }
1504
1505 /* Unneeded ? Don't mess with Mrs. Murphy. */
1506 rtl8169_irq_mask_and_ack(ioaddr);
1507
1508 /* Soft reset the chip. */
1509 RTL_W8(ChipCmd, CmdReset);
1510
1511 /* Check that the chip has finished the reset. */
1512 for (i = 1000; i > 0; i--) {
1513 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1514 break;
1515 udelay(10);
1516 }
1517
1518 /* Identify chip attached to board */
1519 rtl8169_get_mac_version(tp, ioaddr);
1520 rtl8169_get_phy_version(tp, ioaddr);
1521
1522 rtl8169_print_mac_version(tp);
1523 rtl8169_print_phy_version(tp);
1524
1525 for (i = ARRAY_SIZE(rtl_chip_info) - 1; i >= 0; i--) {
1526 if (tp->mac_version == rtl_chip_info[i].mac_version)
1527 break;
1528 }
1529 if (i < 0) {
1530 /* Unknown chip: assume array element #0, original RTL-8169 */
1531 if (netif_msg_probe(tp)) {
1532 printk(KERN_DEBUG PFX "PCI device %s: "
1533 "unknown chip version, assuming %s\n",
1534 pci_name(pdev), rtl_chip_info[0].name);
1535 }
1536 i++;
1537 }
1538 tp->chipset = i;
1539
1540 RTL_W8(Cfg9346, Cfg9346_Unlock);
1541 RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
1542 RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
1543 RTL_W8(Cfg9346, Cfg9346_Lock);
1544
1545 *ioaddr_out = ioaddr;
1546 *dev_out = dev;
1547 out:
1548 return rc;
1549
1550 err_out_free_res:
1551 pci_release_regions(pdev);
1552
1553 err_out_mwi:
1554 pci_clear_mwi(pdev);
1555
1556 err_out_disable:
1557 pci_disable_device(pdev);
1558
1559 err_out_free_dev:
1560 free_netdev(dev);
1561 err_out:
1562 *ioaddr_out = NULL;
1563 *dev_out = NULL;
1564 goto out;
1565 }
1566
1567 static int __devinit
1568 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1569 {
1570 struct net_device *dev = NULL;
1571 struct rtl8169_private *tp;
1572 void __iomem *ioaddr = NULL;
1573 static int board_idx = -1;
1574 u8 autoneg, duplex;
1575 u16 speed;
1576 int i, rc;
1577
1578 assert(pdev != NULL);
1579 assert(ent != NULL);
1580
1581 board_idx++;
1582
1583 if (netif_msg_drv(&debug)) {
1584 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1585 MODULENAME, RTL8169_VERSION);
1586 }
1587
1588 rc = rtl8169_init_board(pdev, &dev, &ioaddr);
1589 if (rc)
1590 return rc;
1591
1592 tp = netdev_priv(dev);
1593 assert(ioaddr != NULL);
1594
1595 if (RTL_R8(PHYstatus) & TBI_Enable) {
1596 tp->set_speed = rtl8169_set_speed_tbi;
1597 tp->get_settings = rtl8169_gset_tbi;
1598 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
1599 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
1600 tp->link_ok = rtl8169_tbi_link_ok;
1601
1602 tp->phy_1000_ctrl_reg = PHY_Cap_1000_Full; /* Implied by TBI */
1603 } else {
1604 tp->set_speed = rtl8169_set_speed_xmii;
1605 tp->get_settings = rtl8169_gset_xmii;
1606 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
1607 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
1608 tp->link_ok = rtl8169_xmii_link_ok;
1609 }
1610
1611 /* Get MAC address. FIXME: read EEPROM */
1612 for (i = 0; i < MAC_ADDR_LEN; i++)
1613 dev->dev_addr[i] = RTL_R8(MAC0 + i);
1614 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1615
1616 dev->open = rtl8169_open;
1617 dev->hard_start_xmit = rtl8169_start_xmit;
1618 dev->get_stats = rtl8169_get_stats;
1619 SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
1620 dev->stop = rtl8169_close;
1621 dev->tx_timeout = rtl8169_tx_timeout;
1622 dev->set_multicast_list = rtl8169_set_rx_mode;
1623 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
1624 dev->irq = pdev->irq;
1625 dev->base_addr = (unsigned long) ioaddr;
1626 dev->change_mtu = rtl8169_change_mtu;
1627
1628 #ifdef CONFIG_R8169_NAPI
1629 dev->poll = rtl8169_poll;
1630 dev->weight = R8169_NAPI_WEIGHT;
1631 #endif
1632
1633 #ifdef CONFIG_R8169_VLAN
1634 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
1635 dev->vlan_rx_register = rtl8169_vlan_rx_register;
1636 dev->vlan_rx_kill_vid = rtl8169_vlan_rx_kill_vid;
1637 #endif
1638
1639 #ifdef CONFIG_NET_POLL_CONTROLLER
1640 dev->poll_controller = rtl8169_netpoll;
1641 #endif
1642
1643 tp->intr_mask = 0xffff;
1644 tp->pci_dev = pdev;
1645 tp->mmio_addr = ioaddr;
1646
1647 spin_lock_init(&tp->lock);
1648
1649 rc = register_netdev(dev);
1650 if (rc) {
1651 rtl8169_release_board(pdev, dev, ioaddr);
1652 return rc;
1653 }
1654
1655 if (netif_msg_probe(tp)) {
1656 printk(KERN_DEBUG "%s: Identified chip type is '%s'.\n",
1657 dev->name, rtl_chip_info[tp->chipset].name);
1658 }
1659
1660 pci_set_drvdata(pdev, dev);
1661
1662 if (netif_msg_probe(tp)) {
1663 printk(KERN_INFO "%s: %s at 0x%lx, "
1664 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1665 "IRQ %d\n",
1666 dev->name,
1667 rtl_chip_info[ent->driver_data].name,
1668 dev->base_addr,
1669 dev->dev_addr[0], dev->dev_addr[1],
1670 dev->dev_addr[2], dev->dev_addr[3],
1671 dev->dev_addr[4], dev->dev_addr[5], dev->irq);
1672 }
1673
1674 rtl8169_hw_phy_config(dev);
1675
1676 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1677 RTL_W8(0x82, 0x01);
1678
1679 if (tp->mac_version < RTL_GIGA_MAC_VER_E) {
1680 dprintk("Set PCI Latency=0x40\n");
1681 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x40);
1682 }
1683
1684 if (tp->mac_version == RTL_GIGA_MAC_VER_D) {
1685 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1686 RTL_W8(0x82, 0x01);
1687 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1688 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1689 }
1690
1691 rtl8169_link_option(board_idx, &autoneg, &speed, &duplex);
1692
1693 rtl8169_set_speed(dev, autoneg, speed, duplex);
1694
1695 if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1696 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1697
1698 return 0;
1699 }
1700
1701 static void __devexit
1702 rtl8169_remove_one(struct pci_dev *pdev)
1703 {
1704 struct net_device *dev = pci_get_drvdata(pdev);
1705 struct rtl8169_private *tp = netdev_priv(dev);
1706
1707 assert(dev != NULL);
1708 assert(tp != NULL);
1709
1710 unregister_netdev(dev);
1711 rtl8169_release_board(pdev, dev, tp->mmio_addr);
1712 pci_set_drvdata(pdev, NULL);
1713 }
1714
1715 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
1716 struct net_device *dev)
1717 {
1718 unsigned int mtu = dev->mtu;
1719
1720 tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
1721 }
1722
1723 static int rtl8169_open(struct net_device *dev)
1724 {
1725 struct rtl8169_private *tp = netdev_priv(dev);
1726 struct pci_dev *pdev = tp->pci_dev;
1727 int retval;
1728
1729 rtl8169_set_rxbufsize(tp, dev);
1730
1731 retval =
1732 request_irq(dev->irq, rtl8169_interrupt, SA_SHIRQ, dev->name, dev);
1733 if (retval < 0)
1734 goto out;
1735
1736 retval = -ENOMEM;
1737
1738 /*
1739 * Rx and Tx desscriptors needs 256 bytes alignment.
1740 * pci_alloc_consistent provides more.
1741 */
1742 tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
1743 &tp->TxPhyAddr);
1744 if (!tp->TxDescArray)
1745 goto err_free_irq;
1746
1747 tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
1748 &tp->RxPhyAddr);
1749 if (!tp->RxDescArray)
1750 goto err_free_tx;
1751
1752 retval = rtl8169_init_ring(dev);
1753 if (retval < 0)
1754 goto err_free_rx;
1755
1756 INIT_WORK(&tp->task, NULL, dev);
1757
1758 rtl8169_hw_start(dev);
1759
1760 rtl8169_request_timer(dev);
1761
1762 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
1763 out:
1764 return retval;
1765
1766 err_free_rx:
1767 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
1768 tp->RxPhyAddr);
1769 err_free_tx:
1770 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
1771 tp->TxPhyAddr);
1772 err_free_irq:
1773 free_irq(dev->irq, dev);
1774 goto out;
1775 }
1776
1777 static void rtl8169_hw_reset(void __iomem *ioaddr)
1778 {
1779 /* Disable interrupts */
1780 rtl8169_irq_mask_and_ack(ioaddr);
1781
1782 /* Reset the chipset */
1783 RTL_W8(ChipCmd, CmdReset);
1784
1785 /* PCI commit */
1786 RTL_R8(ChipCmd);
1787 }
1788
1789 static void
1790 rtl8169_hw_start(struct net_device *dev)
1791 {
1792 struct rtl8169_private *tp = netdev_priv(dev);
1793 void __iomem *ioaddr = tp->mmio_addr;
1794 u32 i;
1795
1796 /* Soft reset the chip. */
1797 RTL_W8(ChipCmd, CmdReset);
1798
1799 /* Check that the chip has finished the reset. */
1800 for (i = 1000; i > 0; i--) {
1801 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
1802 break;
1803 udelay(10);
1804 }
1805
1806 RTL_W8(Cfg9346, Cfg9346_Unlock);
1807 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
1808 RTL_W8(EarlyTxThres, EarlyTxThld);
1809
1810 /* Low hurts. Let's disable the filtering. */
1811 RTL_W16(RxMaxSize, 16383);
1812
1813 /* Set Rx Config register */
1814 i = rtl8169_rx_config |
1815 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
1816 RTL_W32(RxConfig, i);
1817
1818 /* Set DMA burst size and Interframe Gap Time */
1819 RTL_W32(TxConfig,
1820 (TX_DMA_BURST << TxDMAShift) | (InterFrameGap <<
1821 TxInterFrameGapShift));
1822 tp->cp_cmd |= RTL_R16(CPlusCmd);
1823 RTL_W16(CPlusCmd, tp->cp_cmd);
1824
1825 if ((tp->mac_version == RTL_GIGA_MAC_VER_D) ||
1826 (tp->mac_version == RTL_GIGA_MAC_VER_E)) {
1827 dprintk(KERN_INFO PFX "Set MAC Reg C+CR Offset 0xE0. "
1828 "Bit-3 and bit-14 MUST be 1\n");
1829 tp->cp_cmd |= (1 << 14) | PCIMulRW;
1830 RTL_W16(CPlusCmd, tp->cp_cmd);
1831 }
1832
1833 /*
1834 * Undocumented corner. Supposedly:
1835 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
1836 */
1837 RTL_W16(IntrMitigate, 0x0000);
1838
1839 RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr & DMA_32BIT_MASK));
1840 RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr >> 32));
1841 RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr & DMA_32BIT_MASK));
1842 RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr >> 32));
1843 RTL_W8(Cfg9346, Cfg9346_Lock);
1844 udelay(10);
1845
1846 RTL_W32(RxMissed, 0);
1847
1848 rtl8169_set_rx_mode(dev);
1849
1850 /* no early-rx interrupts */
1851 RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
1852
1853 /* Enable all known interrupts by setting the interrupt mask. */
1854 RTL_W16(IntrMask, rtl8169_intr_mask);
1855
1856 netif_start_queue(dev);
1857 }
1858
1859 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
1860 {
1861 struct rtl8169_private *tp = netdev_priv(dev);
1862 int ret = 0;
1863
1864 if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
1865 return -EINVAL;
1866
1867 dev->mtu = new_mtu;
1868
1869 if (!netif_running(dev))
1870 goto out;
1871
1872 rtl8169_down(dev);
1873
1874 rtl8169_set_rxbufsize(tp, dev);
1875
1876 ret = rtl8169_init_ring(dev);
1877 if (ret < 0)
1878 goto out;
1879
1880 netif_poll_enable(dev);
1881
1882 rtl8169_hw_start(dev);
1883
1884 rtl8169_request_timer(dev);
1885
1886 out:
1887 return ret;
1888 }
1889
1890 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
1891 {
1892 desc->addr = 0x0badbadbadbadbadull;
1893 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
1894 }
1895
1896 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
1897 struct sk_buff **sk_buff, struct RxDesc *desc)
1898 {
1899 struct pci_dev *pdev = tp->pci_dev;
1900
1901 pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
1902 PCI_DMA_FROMDEVICE);
1903 dev_kfree_skb(*sk_buff);
1904 *sk_buff = NULL;
1905 rtl8169_make_unusable_by_asic(desc);
1906 }
1907
1908 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
1909 {
1910 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
1911
1912 desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
1913 }
1914
1915 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
1916 u32 rx_buf_sz)
1917 {
1918 desc->addr = cpu_to_le64(mapping);
1919 wmb();
1920 rtl8169_mark_to_asic(desc, rx_buf_sz);
1921 }
1922
1923 static int rtl8169_alloc_rx_skb(struct pci_dev *pdev, struct sk_buff **sk_buff,
1924 struct RxDesc *desc, int rx_buf_sz)
1925 {
1926 struct sk_buff *skb;
1927 dma_addr_t mapping;
1928 int ret = 0;
1929
1930 skb = dev_alloc_skb(rx_buf_sz + NET_IP_ALIGN);
1931 if (!skb)
1932 goto err_out;
1933
1934 skb_reserve(skb, NET_IP_ALIGN);
1935 *sk_buff = skb;
1936
1937 mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
1938 PCI_DMA_FROMDEVICE);
1939
1940 rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
1941
1942 out:
1943 return ret;
1944
1945 err_out:
1946 ret = -ENOMEM;
1947 rtl8169_make_unusable_by_asic(desc);
1948 goto out;
1949 }
1950
1951 static void rtl8169_rx_clear(struct rtl8169_private *tp)
1952 {
1953 int i;
1954
1955 for (i = 0; i < NUM_RX_DESC; i++) {
1956 if (tp->Rx_skbuff[i]) {
1957 rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
1958 tp->RxDescArray + i);
1959 }
1960 }
1961 }
1962
1963 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
1964 u32 start, u32 end)
1965 {
1966 u32 cur;
1967
1968 for (cur = start; end - cur > 0; cur++) {
1969 int ret, i = cur % NUM_RX_DESC;
1970
1971 if (tp->Rx_skbuff[i])
1972 continue;
1973
1974 ret = rtl8169_alloc_rx_skb(tp->pci_dev, tp->Rx_skbuff + i,
1975 tp->RxDescArray + i, tp->rx_buf_sz);
1976 if (ret < 0)
1977 break;
1978 }
1979 return cur - start;
1980 }
1981
1982 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
1983 {
1984 desc->opts1 |= cpu_to_le32(RingEnd);
1985 }
1986
1987 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
1988 {
1989 tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
1990 }
1991
1992 static int rtl8169_init_ring(struct net_device *dev)
1993 {
1994 struct rtl8169_private *tp = netdev_priv(dev);
1995
1996 rtl8169_init_ring_indexes(tp);
1997
1998 memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
1999 memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
2000
2001 if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
2002 goto err_out;
2003
2004 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
2005
2006 return 0;
2007
2008 err_out:
2009 rtl8169_rx_clear(tp);
2010 return -ENOMEM;
2011 }
2012
2013 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
2014 struct TxDesc *desc)
2015 {
2016 unsigned int len = tx_skb->len;
2017
2018 pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
2019 desc->opts1 = 0x00;
2020 desc->opts2 = 0x00;
2021 desc->addr = 0x00;
2022 tx_skb->len = 0;
2023 }
2024
2025 static void rtl8169_tx_clear(struct rtl8169_private *tp)
2026 {
2027 unsigned int i;
2028
2029 for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
2030 unsigned int entry = i % NUM_TX_DESC;
2031 struct ring_info *tx_skb = tp->tx_skb + entry;
2032 unsigned int len = tx_skb->len;
2033
2034 if (len) {
2035 struct sk_buff *skb = tx_skb->skb;
2036
2037 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
2038 tp->TxDescArray + entry);
2039 if (skb) {
2040 dev_kfree_skb(skb);
2041 tx_skb->skb = NULL;
2042 }
2043 tp->stats.tx_dropped++;
2044 }
2045 }
2046 tp->cur_tx = tp->dirty_tx = 0;
2047 }
2048
2049 static void rtl8169_schedule_work(struct net_device *dev, void (*task)(void *))
2050 {
2051 struct rtl8169_private *tp = netdev_priv(dev);
2052
2053 PREPARE_WORK(&tp->task, task, dev);
2054 schedule_delayed_work(&tp->task, 4);
2055 }
2056
2057 static void rtl8169_wait_for_quiescence(struct net_device *dev)
2058 {
2059 struct rtl8169_private *tp = netdev_priv(dev);
2060 void __iomem *ioaddr = tp->mmio_addr;
2061
2062 synchronize_irq(dev->irq);
2063
2064 /* Wait for any pending NAPI task to complete */
2065 netif_poll_disable(dev);
2066
2067 rtl8169_irq_mask_and_ack(ioaddr);
2068
2069 netif_poll_enable(dev);
2070 }
2071
2072 static void rtl8169_reinit_task(void *_data)
2073 {
2074 struct net_device *dev = _data;
2075 int ret;
2076
2077 if (netif_running(dev)) {
2078 rtl8169_wait_for_quiescence(dev);
2079 rtl8169_close(dev);
2080 }
2081
2082 ret = rtl8169_open(dev);
2083 if (unlikely(ret < 0)) {
2084 if (net_ratelimit()) {
2085 struct rtl8169_private *tp = netdev_priv(dev);
2086
2087 if (netif_msg_drv(tp)) {
2088 printk(PFX KERN_ERR
2089 "%s: reinit failure (status = %d)."
2090 " Rescheduling.\n", dev->name, ret);
2091 }
2092 }
2093 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2094 }
2095 }
2096
2097 static void rtl8169_reset_task(void *_data)
2098 {
2099 struct net_device *dev = _data;
2100 struct rtl8169_private *tp = netdev_priv(dev);
2101
2102 if (!netif_running(dev))
2103 return;
2104
2105 rtl8169_wait_for_quiescence(dev);
2106
2107 rtl8169_rx_interrupt(dev, tp, tp->mmio_addr);
2108 rtl8169_tx_clear(tp);
2109
2110 if (tp->dirty_rx == tp->cur_rx) {
2111 rtl8169_init_ring_indexes(tp);
2112 rtl8169_hw_start(dev);
2113 netif_wake_queue(dev);
2114 } else {
2115 if (net_ratelimit()) {
2116 struct rtl8169_private *tp = netdev_priv(dev);
2117
2118 if (netif_msg_intr(tp)) {
2119 printk(PFX KERN_EMERG
2120 "%s: Rx buffers shortage\n", dev->name);
2121 }
2122 }
2123 rtl8169_schedule_work(dev, rtl8169_reset_task);
2124 }
2125 }
2126
2127 static void rtl8169_tx_timeout(struct net_device *dev)
2128 {
2129 struct rtl8169_private *tp = netdev_priv(dev);
2130
2131 rtl8169_hw_reset(tp->mmio_addr);
2132
2133 /* Let's wait a bit while any (async) irq lands on */
2134 rtl8169_schedule_work(dev, rtl8169_reset_task);
2135 }
2136
2137 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
2138 u32 opts1)
2139 {
2140 struct skb_shared_info *info = skb_shinfo(skb);
2141 unsigned int cur_frag, entry;
2142 struct TxDesc *txd;
2143
2144 entry = tp->cur_tx;
2145 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
2146 skb_frag_t *frag = info->frags + cur_frag;
2147 dma_addr_t mapping;
2148 u32 status, len;
2149 void *addr;
2150
2151 entry = (entry + 1) % NUM_TX_DESC;
2152
2153 txd = tp->TxDescArray + entry;
2154 len = frag->size;
2155 addr = ((void *) page_address(frag->page)) + frag->page_offset;
2156 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
2157
2158 /* anti gcc 2.95.3 bugware (sic) */
2159 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2160
2161 txd->opts1 = cpu_to_le32(status);
2162 txd->addr = cpu_to_le64(mapping);
2163
2164 tp->tx_skb[entry].len = len;
2165 }
2166
2167 if (cur_frag) {
2168 tp->tx_skb[entry].skb = skb;
2169 txd->opts1 |= cpu_to_le32(LastFrag);
2170 }
2171
2172 return cur_frag;
2173 }
2174
2175 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
2176 {
2177 if (dev->features & NETIF_F_TSO) {
2178 u32 mss = skb_shinfo(skb)->tso_size;
2179
2180 if (mss)
2181 return LargeSend | ((mss & MSSMask) << MSSShift);
2182 }
2183 if (skb->ip_summed == CHECKSUM_HW) {
2184 const struct iphdr *ip = skb->nh.iph;
2185
2186 if (ip->protocol == IPPROTO_TCP)
2187 return IPCS | TCPCS;
2188 else if (ip->protocol == IPPROTO_UDP)
2189 return IPCS | UDPCS;
2190 WARN_ON(1); /* we need a WARN() */
2191 }
2192 return 0;
2193 }
2194
2195 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
2196 {
2197 struct rtl8169_private *tp = netdev_priv(dev);
2198 unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
2199 struct TxDesc *txd = tp->TxDescArray + entry;
2200 void __iomem *ioaddr = tp->mmio_addr;
2201 dma_addr_t mapping;
2202 u32 status, len;
2203 u32 opts1;
2204 int ret = 0;
2205
2206 if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
2207 if (netif_msg_drv(tp)) {
2208 printk(KERN_ERR
2209 "%s: BUG! Tx Ring full when queue awake!\n",
2210 dev->name);
2211 }
2212 goto err_stop;
2213 }
2214
2215 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
2216 goto err_stop;
2217
2218 opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
2219
2220 frags = rtl8169_xmit_frags(tp, skb, opts1);
2221 if (frags) {
2222 len = skb_headlen(skb);
2223 opts1 |= FirstFrag;
2224 } else {
2225 len = skb->len;
2226
2227 if (unlikely(len < ETH_ZLEN)) {
2228 skb = skb_padto(skb, ETH_ZLEN);
2229 if (!skb)
2230 goto err_update_stats;
2231 len = ETH_ZLEN;
2232 }
2233
2234 opts1 |= FirstFrag | LastFrag;
2235 tp->tx_skb[entry].skb = skb;
2236 }
2237
2238 mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
2239
2240 tp->tx_skb[entry].len = len;
2241 txd->addr = cpu_to_le64(mapping);
2242 txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
2243
2244 wmb();
2245
2246 /* anti gcc 2.95.3 bugware (sic) */
2247 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
2248 txd->opts1 = cpu_to_le32(status);
2249
2250 dev->trans_start = jiffies;
2251
2252 tp->cur_tx += frags + 1;
2253
2254 smp_wmb();
2255
2256 RTL_W8(TxPoll, 0x40); /* set polling bit */
2257
2258 if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
2259 netif_stop_queue(dev);
2260 smp_rmb();
2261 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
2262 netif_wake_queue(dev);
2263 }
2264
2265 out:
2266 return ret;
2267
2268 err_stop:
2269 netif_stop_queue(dev);
2270 ret = 1;
2271 err_update_stats:
2272 tp->stats.tx_dropped++;
2273 goto out;
2274 }
2275
2276 static void rtl8169_pcierr_interrupt(struct net_device *dev)
2277 {
2278 struct rtl8169_private *tp = netdev_priv(dev);
2279 struct pci_dev *pdev = tp->pci_dev;
2280 void __iomem *ioaddr = tp->mmio_addr;
2281 u16 pci_status, pci_cmd;
2282
2283 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
2284 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
2285
2286 if (netif_msg_intr(tp)) {
2287 printk(KERN_ERR
2288 "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
2289 dev->name, pci_cmd, pci_status);
2290 }
2291
2292 /*
2293 * The recovery sequence below admits a very elaborated explanation:
2294 * - it seems to work;
2295 * - I did not see what else could be done;
2296 * - it makes iop3xx happy.
2297 *
2298 * Feel free to adjust to your needs.
2299 */
2300 if (ignore_parity_err)
2301 pci_cmd &= ~PCI_COMMAND_PARITY;
2302 else
2303 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
2304
2305 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
2306
2307 pci_write_config_word(pdev, PCI_STATUS,
2308 pci_status & (PCI_STATUS_DETECTED_PARITY |
2309 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
2310 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
2311
2312 /* The infamous DAC f*ckup only happens at boot time */
2313 if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
2314 if (netif_msg_intr(tp))
2315 printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
2316 tp->cp_cmd &= ~PCIDAC;
2317 RTL_W16(CPlusCmd, tp->cp_cmd);
2318 dev->features &= ~NETIF_F_HIGHDMA;
2319 }
2320
2321 rtl8169_hw_reset(ioaddr);
2322
2323 rtl8169_schedule_work(dev, rtl8169_reinit_task);
2324 }
2325
2326 static void
2327 rtl8169_tx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2328 void __iomem *ioaddr)
2329 {
2330 unsigned int dirty_tx, tx_left;
2331
2332 assert(dev != NULL);
2333 assert(tp != NULL);
2334 assert(ioaddr != NULL);
2335
2336 dirty_tx = tp->dirty_tx;
2337 smp_rmb();
2338 tx_left = tp->cur_tx - dirty_tx;
2339
2340 while (tx_left > 0) {
2341 unsigned int entry = dirty_tx % NUM_TX_DESC;
2342 struct ring_info *tx_skb = tp->tx_skb + entry;
2343 u32 len = tx_skb->len;
2344 u32 status;
2345
2346 rmb();
2347 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
2348 if (status & DescOwn)
2349 break;
2350
2351 tp->stats.tx_bytes += len;
2352 tp->stats.tx_packets++;
2353
2354 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
2355
2356 if (status & LastFrag) {
2357 dev_kfree_skb_irq(tx_skb->skb);
2358 tx_skb->skb = NULL;
2359 }
2360 dirty_tx++;
2361 tx_left--;
2362 }
2363
2364 if (tp->dirty_tx != dirty_tx) {
2365 tp->dirty_tx = dirty_tx;
2366 smp_wmb();
2367 if (netif_queue_stopped(dev) &&
2368 (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
2369 netif_wake_queue(dev);
2370 }
2371 }
2372 }
2373
2374 static inline int rtl8169_fragmented_frame(u32 status)
2375 {
2376 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
2377 }
2378
2379 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
2380 {
2381 u32 opts1 = le32_to_cpu(desc->opts1);
2382 u32 status = opts1 & RxProtoMask;
2383
2384 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
2385 ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
2386 ((status == RxProtoIP) && !(opts1 & IPFail)))
2387 skb->ip_summed = CHECKSUM_UNNECESSARY;
2388 else
2389 skb->ip_summed = CHECKSUM_NONE;
2390 }
2391
2392 static inline int rtl8169_try_rx_copy(struct sk_buff **sk_buff, int pkt_size,
2393 struct RxDesc *desc, int rx_buf_sz)
2394 {
2395 int ret = -1;
2396
2397 if (pkt_size < rx_copybreak) {
2398 struct sk_buff *skb;
2399
2400 skb = dev_alloc_skb(pkt_size + NET_IP_ALIGN);
2401 if (skb) {
2402 skb_reserve(skb, NET_IP_ALIGN);
2403 eth_copy_and_sum(skb, sk_buff[0]->data, pkt_size, 0);
2404 *sk_buff = skb;
2405 rtl8169_mark_to_asic(desc, rx_buf_sz);
2406 ret = 0;
2407 }
2408 }
2409 return ret;
2410 }
2411
2412 static int
2413 rtl8169_rx_interrupt(struct net_device *dev, struct rtl8169_private *tp,
2414 void __iomem *ioaddr)
2415 {
2416 unsigned int cur_rx, rx_left;
2417 unsigned int delta, count;
2418
2419 assert(dev != NULL);
2420 assert(tp != NULL);
2421 assert(ioaddr != NULL);
2422
2423 cur_rx = tp->cur_rx;
2424 rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
2425 rx_left = rtl8169_rx_quota(rx_left, (u32) dev->quota);
2426
2427 for (; rx_left > 0; rx_left--, cur_rx++) {
2428 unsigned int entry = cur_rx % NUM_RX_DESC;
2429 struct RxDesc *desc = tp->RxDescArray + entry;
2430 u32 status;
2431
2432 rmb();
2433 status = le32_to_cpu(desc->opts1);
2434
2435 if (status & DescOwn)
2436 break;
2437 if (unlikely(status & RxRES)) {
2438 if (netif_msg_rx_err(tp)) {
2439 printk(KERN_INFO
2440 "%s: Rx ERROR. status = %08x\n",
2441 dev->name, status);
2442 }
2443 tp->stats.rx_errors++;
2444 if (status & (RxRWT | RxRUNT))
2445 tp->stats.rx_length_errors++;
2446 if (status & RxCRC)
2447 tp->stats.rx_crc_errors++;
2448 if (status & RxFOVF) {
2449 rtl8169_schedule_work(dev, rtl8169_reset_task);
2450 tp->stats.rx_fifo_errors++;
2451 }
2452 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2453 } else {
2454 struct sk_buff *skb = tp->Rx_skbuff[entry];
2455 int pkt_size = (status & 0x00001FFF) - 4;
2456 void (*pci_action)(struct pci_dev *, dma_addr_t,
2457 size_t, int) = pci_dma_sync_single_for_device;
2458
2459 /*
2460 * The driver does not support incoming fragmented
2461 * frames. They are seen as a symptom of over-mtu
2462 * sized frames.
2463 */
2464 if (unlikely(rtl8169_fragmented_frame(status))) {
2465 tp->stats.rx_dropped++;
2466 tp->stats.rx_length_errors++;
2467 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
2468 continue;
2469 }
2470
2471 rtl8169_rx_csum(skb, desc);
2472
2473 pci_dma_sync_single_for_cpu(tp->pci_dev,
2474 le64_to_cpu(desc->addr), tp->rx_buf_sz,
2475 PCI_DMA_FROMDEVICE);
2476
2477 if (rtl8169_try_rx_copy(&skb, pkt_size, desc,
2478 tp->rx_buf_sz)) {
2479 pci_action = pci_unmap_single;
2480 tp->Rx_skbuff[entry] = NULL;
2481 }
2482
2483 pci_action(tp->pci_dev, le64_to_cpu(desc->addr),
2484 tp->rx_buf_sz, PCI_DMA_FROMDEVICE);
2485
2486 skb->dev = dev;
2487 skb_put(skb, pkt_size);
2488 skb->protocol = eth_type_trans(skb, dev);
2489
2490 if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
2491 rtl8169_rx_skb(skb);
2492
2493 dev->last_rx = jiffies;
2494 tp->stats.rx_bytes += pkt_size;
2495 tp->stats.rx_packets++;
2496 }
2497 }
2498
2499 count = cur_rx - tp->cur_rx;
2500 tp->cur_rx = cur_rx;
2501
2502 delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
2503 if (!delta && count && netif_msg_intr(tp))
2504 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
2505 tp->dirty_rx += delta;
2506
2507 /*
2508 * FIXME: until there is periodic timer to try and refill the ring,
2509 * a temporary shortage may definitely kill the Rx process.
2510 * - disable the asic to try and avoid an overflow and kick it again
2511 * after refill ?
2512 * - how do others driver handle this condition (Uh oh...).
2513 */
2514 if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
2515 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
2516
2517 return count;
2518 }
2519
2520 /* The interrupt handler does all of the Rx thread work and cleans up after the Tx thread. */
2521 static irqreturn_t
2522 rtl8169_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
2523 {
2524 struct net_device *dev = (struct net_device *) dev_instance;
2525 struct rtl8169_private *tp = netdev_priv(dev);
2526 int boguscnt = max_interrupt_work;
2527 void __iomem *ioaddr = tp->mmio_addr;
2528 int status;
2529 int handled = 0;
2530
2531 do {
2532 status = RTL_R16(IntrStatus);
2533
2534 /* hotplug/major error/no more work/shared irq */
2535 if ((status == 0xFFFF) || !status)
2536 break;
2537
2538 handled = 1;
2539
2540 if (unlikely(!netif_running(dev))) {
2541 rtl8169_asic_down(ioaddr);
2542 goto out;
2543 }
2544
2545 status &= tp->intr_mask;
2546 RTL_W16(IntrStatus,
2547 (status & RxFIFOOver) ? (status | RxOverflow) : status);
2548
2549 if (!(status & rtl8169_intr_mask))
2550 break;
2551
2552 if (unlikely(status & SYSErr)) {
2553 rtl8169_pcierr_interrupt(dev);
2554 break;
2555 }
2556
2557 if (status & LinkChg)
2558 rtl8169_check_link_status(dev, tp, ioaddr);
2559
2560 #ifdef CONFIG_R8169_NAPI
2561 RTL_W16(IntrMask, rtl8169_intr_mask & ~rtl8169_napi_event);
2562 tp->intr_mask = ~rtl8169_napi_event;
2563
2564 if (likely(netif_rx_schedule_prep(dev)))
2565 __netif_rx_schedule(dev);
2566 else if (netif_msg_intr(tp)) {
2567 printk(KERN_INFO "%s: interrupt %04x taken in poll\n",
2568 dev->name, status);
2569 }
2570 break;
2571 #else
2572 /* Rx interrupt */
2573 if (status & (RxOK | RxOverflow | RxFIFOOver)) {
2574 rtl8169_rx_interrupt(dev, tp, ioaddr);
2575 }
2576 /* Tx interrupt */
2577 if (status & (TxOK | TxErr))
2578 rtl8169_tx_interrupt(dev, tp, ioaddr);
2579 #endif
2580
2581 boguscnt--;
2582 } while (boguscnt > 0);
2583
2584 if (boguscnt <= 0) {
2585 if (netif_msg_intr(tp) && net_ratelimit() ) {
2586 printk(KERN_WARNING
2587 "%s: Too much work at interrupt!\n", dev->name);
2588 }
2589 /* Clear all interrupt sources. */
2590 RTL_W16(IntrStatus, 0xffff);
2591 }
2592 out:
2593 return IRQ_RETVAL(handled);
2594 }
2595
2596 #ifdef CONFIG_R8169_NAPI
2597 static int rtl8169_poll(struct net_device *dev, int *budget)
2598 {
2599 unsigned int work_done, work_to_do = min(*budget, dev->quota);
2600 struct rtl8169_private *tp = netdev_priv(dev);
2601 void __iomem *ioaddr = tp->mmio_addr;
2602
2603 work_done = rtl8169_rx_interrupt(dev, tp, ioaddr);
2604 rtl8169_tx_interrupt(dev, tp, ioaddr);
2605
2606 *budget -= work_done;
2607 dev->quota -= work_done;
2608
2609 if (work_done < work_to_do) {
2610 netif_rx_complete(dev);
2611 tp->intr_mask = 0xffff;
2612 /*
2613 * 20040426: the barrier is not strictly required but the
2614 * behavior of the irq handler could be less predictable
2615 * without it. Btw, the lack of flush for the posted pci
2616 * write is safe - FR
2617 */
2618 smp_wmb();
2619 RTL_W16(IntrMask, rtl8169_intr_mask);
2620 }
2621
2622 return (work_done >= work_to_do);
2623 }
2624 #endif
2625
2626 static void rtl8169_down(struct net_device *dev)
2627 {
2628 struct rtl8169_private *tp = netdev_priv(dev);
2629 void __iomem *ioaddr = tp->mmio_addr;
2630 unsigned int poll_locked = 0;
2631 unsigned int intrmask;
2632
2633 rtl8169_delete_timer(dev);
2634
2635 netif_stop_queue(dev);
2636
2637 flush_scheduled_work();
2638
2639 core_down:
2640 spin_lock_irq(&tp->lock);
2641
2642 rtl8169_asic_down(ioaddr);
2643
2644 /* Update the error counts. */
2645 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2646 RTL_W32(RxMissed, 0);
2647
2648 spin_unlock_irq(&tp->lock);
2649
2650 synchronize_irq(dev->irq);
2651
2652 if (!poll_locked) {
2653 netif_poll_disable(dev);
2654 poll_locked++;
2655 }
2656
2657 /* Give a racing hard_start_xmit a few cycles to complete. */
2658 synchronize_sched(); /* FIXME: should this be synchronize_irq()? */
2659
2660 /*
2661 * And now for the 50k$ question: are IRQ disabled or not ?
2662 *
2663 * Two paths lead here:
2664 * 1) dev->close
2665 * -> netif_running() is available to sync the current code and the
2666 * IRQ handler. See rtl8169_interrupt for details.
2667 * 2) dev->change_mtu
2668 * -> rtl8169_poll can not be issued again and re-enable the
2669 * interruptions. Let's simply issue the IRQ down sequence again.
2670 *
2671 * No loop if hotpluged or major error (0xffff).
2672 */
2673 intrmask = RTL_R16(IntrMask);
2674 if (intrmask && (intrmask != 0xffff))
2675 goto core_down;
2676
2677 rtl8169_tx_clear(tp);
2678
2679 rtl8169_rx_clear(tp);
2680 }
2681
2682 static int rtl8169_close(struct net_device *dev)
2683 {
2684 struct rtl8169_private *tp = netdev_priv(dev);
2685 struct pci_dev *pdev = tp->pci_dev;
2686
2687 rtl8169_down(dev);
2688
2689 free_irq(dev->irq, dev);
2690
2691 netif_poll_enable(dev);
2692
2693 pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2694 tp->RxPhyAddr);
2695 pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2696 tp->TxPhyAddr);
2697 tp->TxDescArray = NULL;
2698 tp->RxDescArray = NULL;
2699
2700 return 0;
2701 }
2702
2703 static void
2704 rtl8169_set_rx_mode(struct net_device *dev)
2705 {
2706 struct rtl8169_private *tp = netdev_priv(dev);
2707 void __iomem *ioaddr = tp->mmio_addr;
2708 unsigned long flags;
2709 u32 mc_filter[2]; /* Multicast hash filter */
2710 int i, rx_mode;
2711 u32 tmp = 0;
2712
2713 if (dev->flags & IFF_PROMISC) {
2714 /* Unconditionally log net taps. */
2715 if (netif_msg_link(tp)) {
2716 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2717 dev->name);
2718 }
2719 rx_mode =
2720 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2721 AcceptAllPhys;
2722 mc_filter[1] = mc_filter[0] = 0xffffffff;
2723 } else if ((dev->mc_count > multicast_filter_limit)
2724 || (dev->flags & IFF_ALLMULTI)) {
2725 /* Too many to filter perfectly -- accept all multicasts. */
2726 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2727 mc_filter[1] = mc_filter[0] = 0xffffffff;
2728 } else {
2729 struct dev_mc_list *mclist;
2730 rx_mode = AcceptBroadcast | AcceptMyPhys;
2731 mc_filter[1] = mc_filter[0] = 0;
2732 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2733 i++, mclist = mclist->next) {
2734 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2735 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2736 rx_mode |= AcceptMulticast;
2737 }
2738 }
2739
2740 spin_lock_irqsave(&tp->lock, flags);
2741
2742 tmp = rtl8169_rx_config | rx_mode |
2743 (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2744
2745 RTL_W32(RxConfig, tmp);
2746 RTL_W32(MAR0 + 0, mc_filter[0]);
2747 RTL_W32(MAR0 + 4, mc_filter[1]);
2748
2749 spin_unlock_irqrestore(&tp->lock, flags);
2750 }
2751
2752 /**
2753 * rtl8169_get_stats - Get rtl8169 read/write statistics
2754 * @dev: The Ethernet Device to get statistics for
2755 *
2756 * Get TX/RX statistics for rtl8169
2757 */
2758 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
2759 {
2760 struct rtl8169_private *tp = netdev_priv(dev);
2761 void __iomem *ioaddr = tp->mmio_addr;
2762 unsigned long flags;
2763
2764 if (netif_running(dev)) {
2765 spin_lock_irqsave(&tp->lock, flags);
2766 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2767 RTL_W32(RxMissed, 0);
2768 spin_unlock_irqrestore(&tp->lock, flags);
2769 }
2770
2771 return &tp->stats;
2772 }
2773
2774 #ifdef CONFIG_PM
2775
2776 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
2777 {
2778 struct net_device *dev = pci_get_drvdata(pdev);
2779 struct rtl8169_private *tp = netdev_priv(dev);
2780 void __iomem *ioaddr = tp->mmio_addr;
2781
2782 if (!netif_running(dev))
2783 goto out;
2784
2785 netif_device_detach(dev);
2786 netif_stop_queue(dev);
2787
2788 spin_lock_irq(&tp->lock);
2789
2790 rtl8169_asic_down(ioaddr);
2791
2792 tp->stats.rx_missed_errors += RTL_R32(RxMissed);
2793 RTL_W32(RxMissed, 0);
2794
2795 spin_unlock_irq(&tp->lock);
2796
2797 pci_save_state(pdev);
2798 pci_enable_wake(pdev, pci_choose_state(pdev, state), tp->wol_enabled);
2799 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2800 out:
2801 return 0;
2802 }
2803
2804 static int rtl8169_resume(struct pci_dev *pdev)
2805 {
2806 struct net_device *dev = pci_get_drvdata(pdev);
2807
2808 if (!netif_running(dev))
2809 goto out;
2810
2811 netif_device_attach(dev);
2812
2813 pci_set_power_state(pdev, PCI_D0);
2814 pci_restore_state(pdev);
2815 pci_enable_wake(pdev, PCI_D0, 0);
2816
2817 rtl8169_schedule_work(dev, rtl8169_reset_task);
2818 out:
2819 return 0;
2820 }
2821
2822 #endif /* CONFIG_PM */
2823
2824 static struct pci_driver rtl8169_pci_driver = {
2825 .name = MODULENAME,
2826 .id_table = rtl8169_pci_tbl,
2827 .probe = rtl8169_init_one,
2828 .remove = __devexit_p(rtl8169_remove_one),
2829 #ifdef CONFIG_PM
2830 .suspend = rtl8169_suspend,
2831 .resume = rtl8169_resume,
2832 #endif
2833 };
2834
2835 static int __init
2836 rtl8169_init_module(void)
2837 {
2838 return pci_module_init(&rtl8169_pci_driver);
2839 }
2840
2841 static void __exit
2842 rtl8169_cleanup_module(void)
2843 {
2844 pci_unregister_driver(&rtl8169_pci_driver);
2845 }
2846
2847 module_init(rtl8169_init_module);
2848 module_exit(rtl8169_cleanup_module);
Linux with added FPC-III support