drivers/i2c/busses/i2c-bfin-twi.c

   1 /*
   2  * Blackfin On-Chip Two Wire Interface Driver
   3  *
   4  * Copyright 2005-2007 Analog Devices Inc.
   5  *
   6  * Enter bugs at http://blackfin.uclinux.org/
   7  *
   8  * Licensed under the GPL-2 or later.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/i2c.h>
  15 #include <linux/slab.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/timer.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/completion.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24 #include <linux/i2c/bfin_twi.h>
  25
  26 #include <asm/irq.h>
  27 #include <asm/portmux.h>
  28 #include <asm/bfin_twi.h>
  29
  30 /* SMBus mode*/
  31 #define TWI_I2C_MODE_STANDARD           1
  32 #define TWI_I2C_MODE_STANDARDSUB        2
  33 #define TWI_I2C_MODE_COMBINED           3
  34 #define TWI_I2C_MODE_REPEAT             4
  35
  36 static void bfin_twi_handle_interrupt(struct bfin_twi_iface *iface,
  37                                         unsigned short twi_int_status)
  38 {
  39         unsigned short mast_stat = read_MASTER_STAT(iface);
  40
  41         if (twi_int_status & XMTSERV) {
  42                 if (iface->writeNum <= 0) {
  43                         /* start receive immediately after complete sending in
  44                          * combine mode.
  45                          */
  46                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED)
  47                                 write_MASTER_CTL(iface,
  48                                         read_MASTER_CTL(iface) | MDIR);
  49                         else if (iface->manual_stop)
  50                                 write_MASTER_CTL(iface,
  51                                         read_MASTER_CTL(iface) | STOP);
  52                         else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
  53                                 iface->cur_msg + 1 < iface->msg_num) {
  54                                 if (iface->pmsg[iface->cur_msg + 1].flags &
  55                                         I2C_M_RD)
  56                                         write_MASTER_CTL(iface,
  57                                                 read_MASTER_CTL(iface) |
  58                                                 MDIR);
  59                                 else
  60                                         write_MASTER_CTL(iface,
  61                                                 read_MASTER_CTL(iface) &
  62                                                 ~MDIR);
  63                         }
  64                 }
  65                 /* Transmit next data */
  66                 while (iface->writeNum > 0 &&
  67                         (read_FIFO_STAT(iface) & XMTSTAT) != XMT_FULL) {
  68                         write_XMT_DATA8(iface, *(iface->transPtr++));
  69                         iface->writeNum--;
  70                 }
  71         }
  72         if (twi_int_status & RCVSERV) {
  73                 while (iface->readNum > 0 &&
  74                         (read_FIFO_STAT(iface) & RCVSTAT)) {
  75                         /* Receive next data */
  76                         *(iface->transPtr) = read_RCV_DATA8(iface);
  77                         if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
  78                                 /* Change combine mode into sub mode after
  79                                  * read first data.
  80                                  */
  81                                 iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
  82                                 /* Get read number from first byte in block
  83                                  * combine mode.
  84                                  */
  85                                 if (iface->readNum == 1 && iface->manual_stop)
  86                                         iface->readNum = *iface->transPtr + 1;
  87                         }
  88                         iface->transPtr++;
  89                         iface->readNum--;
  90                 }
  91
  92                 if (iface->readNum == 0) {
  93                         if (iface->manual_stop) {
  94                                 /* Temporary workaround to avoid possible bus stall -
  95                                  * Flush FIFO before issuing the STOP condition
  96                                  */
  97                                 read_RCV_DATA16(iface);
  98                                 write_MASTER_CTL(iface,
  99                                         read_MASTER_CTL(iface) | STOP);
 100                         } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 101                                         iface->cur_msg + 1 < iface->msg_num) {
 102                                 if (iface->pmsg[iface->cur_msg + 1].flags & I2C_M_RD)
 103                                         write_MASTER_CTL(iface,
 104                                                 read_MASTER_CTL(iface) | MDIR);
 105                                 else
 106                                         write_MASTER_CTL(iface,
 107                                                 read_MASTER_CTL(iface) & ~MDIR);
 108                         }
 109                 }
 110         }
 111         if (twi_int_status & MERR) {
 112                 write_INT_MASK(iface, 0);
 113                 write_MASTER_STAT(iface, 0x3e);
 114                 write_MASTER_CTL(iface, 0);
 115                 iface->result = -EIO;
 116
 117                 if (mast_stat & LOSTARB)
 118                         dev_dbg(&iface->adap.dev, "Lost Arbitration\n");
 119                 if (mast_stat & ANAK)
 120                         dev_dbg(&iface->adap.dev, "Address Not Acknowledged\n");
 121                 if (mast_stat & DNAK)
 122                         dev_dbg(&iface->adap.dev, "Data Not Acknowledged\n");
 123                 if (mast_stat & BUFRDERR)
 124                         dev_dbg(&iface->adap.dev, "Buffer Read Error\n");
 125                 if (mast_stat & BUFWRERR)
 126                         dev_dbg(&iface->adap.dev, "Buffer Write Error\n");
 127
 128                 /* Faulty slave devices, may drive SDA low after a transfer
 129                  * finishes. To release the bus this code generates up to 9
 130                  * extra clocks until SDA is released.
 131                  */
 132
 133                 if (read_MASTER_STAT(iface) & SDASEN) {
 134                         int cnt = 9;
 135                         do {
 136                                 write_MASTER_CTL(iface, SCLOVR);
 137                                 udelay(6);
 138                                 write_MASTER_CTL(iface, 0);
 139                                 udelay(6);
 140                         } while ((read_MASTER_STAT(iface) & SDASEN) && cnt--);
 141
 142                         write_MASTER_CTL(iface, SDAOVR | SCLOVR);
 143                         udelay(6);
 144                         write_MASTER_CTL(iface, SDAOVR);
 145                         udelay(6);
 146                         write_MASTER_CTL(iface, 0);
 147                 }
 148
 149                 /* If it is a quick transfer, only address without data,
 150                  * not an err, return 1.
 151                  */
 152                 if (iface->cur_mode == TWI_I2C_MODE_STANDARD &&
 153                         iface->transPtr == NULL &&
 154                         (twi_int_status & MCOMP) && (mast_stat & DNAK))
 155                         iface->result = 1;
 156
 157                 complete(&iface->complete);
 158                 return;
 159         }
 160         if (twi_int_status & MCOMP) {
 161                 if (twi_int_status & (XMTSERV | RCVSERV) &&
 162                         (read_MASTER_CTL(iface) & MEN) == 0 &&
 163                         (iface->cur_mode == TWI_I2C_MODE_REPEAT ||
 164                         iface->cur_mode == TWI_I2C_MODE_COMBINED)) {
 165                         iface->result = -1;
 166                         write_INT_MASK(iface, 0);
 167                         write_MASTER_CTL(iface, 0);
 168                 } else if (iface->cur_mode == TWI_I2C_MODE_COMBINED) {
 169                         if (iface->readNum == 0) {
 170                                 /* set the read number to 1 and ask for manual
 171                                  * stop in block combine mode
 172                                  */
 173                                 iface->readNum = 1;
 174                                 iface->manual_stop = 1;
 175                                 write_MASTER_CTL(iface,
 176                                         read_MASTER_CTL(iface) | (0xff << 6));
 177                         } else {
 178                                 /* set the readd number in other
 179                                  * combine mode.
 180                                  */
 181                                 write_MASTER_CTL(iface,
 182                                         (read_MASTER_CTL(iface) &
 183                                         (~(0xff << 6))) |
 184                                         (iface->readNum << 6));
 185                         }
 186                         /* remove restart bit and enable master receive */
 187                         write_MASTER_CTL(iface,
 188                                 read_MASTER_CTL(iface) & ~RSTART);
 189                 } else if (iface->cur_mode == TWI_I2C_MODE_REPEAT &&
 190                                 iface->cur_msg + 1 < iface->msg_num) {
 191                         iface->cur_msg++;
 192                         iface->transPtr = iface->pmsg[iface->cur_msg].buf;
 193                         iface->writeNum = iface->readNum =
 194                                 iface->pmsg[iface->cur_msg].len;
 195                         /* Set Transmit device address */
 196                         write_MASTER_ADDR(iface,
 197                                 iface->pmsg[iface->cur_msg].addr);
 198                         if (iface->pmsg[iface->cur_msg].flags & I2C_M_RD)
 199                                 iface->read_write = I2C_SMBUS_READ;
 200                         else {
 201                                 iface->read_write = I2C_SMBUS_WRITE;
 202                                 /* Transmit first data */
 203                                 if (iface->writeNum > 0) {
 204                                         write_XMT_DATA8(iface,
 205                                                 *(iface->transPtr++));
 206                                         iface->writeNum--;
 207                                 }
 208                         }
 209
 210                         if (iface->pmsg[iface->cur_msg].len <= 255) {
 211                                 write_MASTER_CTL(iface,
 212                                         (read_MASTER_CTL(iface) &
 213                                         (~(0xff << 6))) |
 214                                         (iface->pmsg[iface->cur_msg].len << 6));
 215                                 iface->manual_stop = 0;
 216                         } else {
 217                                 write_MASTER_CTL(iface,
 218                                         (read_MASTER_CTL(iface) |
 219                                         (0xff << 6)));
 220                                 iface->manual_stop = 1;
 221                         }
 222                         /* remove restart bit before last message */
 223                         if (iface->cur_msg + 1 == iface->msg_num)
 224                                 write_MASTER_CTL(iface,
 225                                         read_MASTER_CTL(iface) & ~RSTART);
 226                 } else {
 227                         iface->result = 1;
 228                         write_INT_MASK(iface, 0);
 229                         write_MASTER_CTL(iface, 0);
 230                 }
 231                 complete(&iface->complete);
 232         }
 233 }
 234
 235 /* Interrupt handler */
 236 static irqreturn_t bfin_twi_interrupt_entry(int irq, void *dev_id)
 237 {
 238         struct bfin_twi_iface *iface = dev_id;
 239         unsigned long flags;
 240         unsigned short twi_int_status;
 241
 242         spin_lock_irqsave(&iface->lock, flags);
 243         while (1) {
 244                 twi_int_status = read_INT_STAT(iface);
 245                 if (!twi_int_status)
 246                         break;
 247                 /* Clear interrupt status */
 248                 write_INT_STAT(iface, twi_int_status);
 249                 bfin_twi_handle_interrupt(iface, twi_int_status);
 250         }
 251         spin_unlock_irqrestore(&iface->lock, flags);
 252         return IRQ_HANDLED;
 253 }
 254
 255 /*
 256  * One i2c master transfer
 257  */
 258 static int bfin_twi_do_master_xfer(struct i2c_adapter *adap,
 259                                 struct i2c_msg *msgs, int num)
 260 {
 261         struct bfin_twi_iface *iface = adap->algo_data;
 262         struct i2c_msg *pmsg;
 263         int rc = 0;
 264
 265         if (!(read_CONTROL(iface) & TWI_ENA))
 266                 return -ENXIO;
 267
 268         if (read_MASTER_STAT(iface) & BUSBUSY)
 269                 return -EAGAIN;
 270
 271         iface->pmsg = msgs;
 272         iface->msg_num = num;
 273         iface->cur_msg = 0;
 274
 275         pmsg = &msgs[0];
 276         if (pmsg->flags & I2C_M_TEN) {
 277                 dev_err(&adap->dev, "10 bits addr not supported!\n");
 278                 return -EINVAL;
 279         }
 280
 281         if (iface->msg_num > 1)
 282                 iface->cur_mode = TWI_I2C_MODE_REPEAT;
 283         iface->manual_stop = 0;
 284         iface->transPtr = pmsg->buf;
 285         iface->writeNum = iface->readNum = pmsg->len;
 286         iface->result = 0;
 287         init_completion(&(iface->complete));
 288         /* Set Transmit device address */
 289         write_MASTER_ADDR(iface, pmsg->addr);
 290
 291         /* FIFO Initiation. Data in FIFO should be
 292          *  discarded before start a new operation.
 293          */
 294         write_FIFO_CTL(iface, 0x3);
 295         write_FIFO_CTL(iface, 0);
 296
 297         if (pmsg->flags & I2C_M_RD)
 298                 iface->read_write = I2C_SMBUS_READ;
 299         else {
 300                 iface->read_write = I2C_SMBUS_WRITE;
 301                 /* Transmit first data */
 302                 if (iface->writeNum > 0) {
 303                         write_XMT_DATA8(iface, *(iface->transPtr++));
 304                         iface->writeNum--;
 305                 }
 306         }
 307
 308         /* clear int stat */
 309         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 310
 311         /* Interrupt mask . Enable XMT, RCV interrupt */
 312         write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 313
 314         if (pmsg->len <= 255)
 315                 write_MASTER_CTL(iface, pmsg->len << 6);
 316         else {
 317                 write_MASTER_CTL(iface, 0xff << 6);
 318                 iface->manual_stop = 1;
 319         }
 320
 321         /* Master enable */
 322         write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 323                 (iface->msg_num > 1 ? RSTART : 0) |
 324                 ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 325                 ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 326
 327         while (!iface->result) {
 328                 if (!wait_for_completion_timeout(&iface->complete,
 329                         adap->timeout)) {
 330                         iface->result = -1;
 331                         dev_err(&adap->dev, "master transfer timeout\n");
 332                 }
 333         }
 334
 335         if (iface->result == 1)
 336                 rc = iface->cur_msg + 1;
 337         else
 338                 rc = iface->result;
 339
 340         return rc;
 341 }
 342
 343 /*
 344  * Generic i2c master transfer entrypoint
 345  */
 346 static int bfin_twi_master_xfer(struct i2c_adapter *adap,
 347                                 struct i2c_msg *msgs, int num)
 348 {
 349         return bfin_twi_do_master_xfer(adap, msgs, num);
 350 }
 351
 352 /*
 353  * One I2C SMBus transfer
 354  */
 355 int bfin_twi_do_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 356                         unsigned short flags, char read_write,
 357                         u8 command, int size, union i2c_smbus_data *data)
 358 {
 359         struct bfin_twi_iface *iface = adap->algo_data;
 360         int rc = 0;
 361
 362         if (!(read_CONTROL(iface) & TWI_ENA))
 363                 return -ENXIO;
 364
 365         if (read_MASTER_STAT(iface) & BUSBUSY)
 366                 return -EAGAIN;
 367
 368         iface->writeNum = 0;
 369         iface->readNum = 0;
 370
 371         /* Prepare datas & select mode */
 372         switch (size) {
 373         case I2C_SMBUS_QUICK:
 374                 iface->transPtr = NULL;
 375                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 376                 break;
 377         case I2C_SMBUS_BYTE:
 378                 if (data == NULL)
 379                         iface->transPtr = NULL;
 380                 else {
 381                         if (read_write == I2C_SMBUS_READ)
 382                                 iface->readNum = 1;
 383                         else
 384                                 iface->writeNum = 1;
 385                         iface->transPtr = &data->byte;
 386                 }
 387                 iface->cur_mode = TWI_I2C_MODE_STANDARD;
 388                 break;
 389         case I2C_SMBUS_BYTE_DATA:
 390                 if (read_write == I2C_SMBUS_READ) {
 391                         iface->readNum = 1;
 392                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 393                 } else {
 394                         iface->writeNum = 1;
 395                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 396                 }
 397                 iface->transPtr = &data->byte;
 398                 break;
 399         case I2C_SMBUS_WORD_DATA:
 400                 if (read_write == I2C_SMBUS_READ) {
 401                         iface->readNum = 2;
 402                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 403                 } else {
 404                         iface->writeNum = 2;
 405                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 406                 }
 407                 iface->transPtr = (u8 *)&data->word;
 408                 break;
 409         case I2C_SMBUS_PROC_CALL:
 410                 iface->writeNum = 2;
 411                 iface->readNum = 2;
 412                 iface->cur_mode = TWI_I2C_MODE_COMBINED;
 413                 iface->transPtr = (u8 *)&data->word;
 414                 break;
 415         case I2C_SMBUS_BLOCK_DATA:
 416                 if (read_write == I2C_SMBUS_READ) {
 417                         iface->readNum = 0;
 418                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 419                 } else {
 420                         iface->writeNum = data->block[0] + 1;
 421                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 422                 }
 423                 iface->transPtr = data->block;
 424                 break;
 425         case I2C_SMBUS_I2C_BLOCK_DATA:
 426                 if (read_write == I2C_SMBUS_READ) {
 427                         iface->readNum = data->block[0];
 428                         iface->cur_mode = TWI_I2C_MODE_COMBINED;
 429                 } else {
 430                         iface->writeNum = data->block[0];
 431                         iface->cur_mode = TWI_I2C_MODE_STANDARDSUB;
 432                 }
 433                 iface->transPtr = (u8 *)&data->block[1];
 434                 break;
 435         default:
 436                 return -1;
 437         }
 438
 439         iface->result = 0;
 440         iface->manual_stop = 0;
 441         iface->read_write = read_write;
 442         iface->command = command;
 443         init_completion(&(iface->complete));
 444
 445         /* FIFO Initiation. Data in FIFO should be discarded before
 446          * start a new operation.
 447          */
 448         write_FIFO_CTL(iface, 0x3);
 449         write_FIFO_CTL(iface, 0);
 450
 451         /* clear int stat */
 452         write_INT_STAT(iface, MERR | MCOMP | XMTSERV | RCVSERV);
 453
 454         /* Set Transmit device address */
 455         write_MASTER_ADDR(iface, addr);
 456
 457         switch (iface->cur_mode) {
 458         case TWI_I2C_MODE_STANDARDSUB:
 459                 write_XMT_DATA8(iface, iface->command);
 460                 write_INT_MASK(iface, MCOMP | MERR |
 461                         ((iface->read_write == I2C_SMBUS_READ) ?
 462                         RCVSERV : XMTSERV));
 463
 464                 if (iface->writeNum + 1 <= 255)
 465                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 466                 else {
 467                         write_MASTER_CTL(iface, 0xff << 6);
 468                         iface->manual_stop = 1;
 469                 }
 470                 /* Master enable */
 471                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 472                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 473                 break;
 474         case TWI_I2C_MODE_COMBINED:
 475                 write_XMT_DATA8(iface, iface->command);
 476                 write_INT_MASK(iface, MCOMP | MERR | RCVSERV | XMTSERV);
 477
 478                 if (iface->writeNum > 0)
 479                         write_MASTER_CTL(iface, (iface->writeNum + 1) << 6);
 480                 else
 481                         write_MASTER_CTL(iface, 0x1 << 6);
 482                 /* Master enable */
 483                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN | RSTART |
 484                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ>100) ? FAST : 0));
 485                 break;
 486         default:
 487                 write_MASTER_CTL(iface, 0);
 488                 if (size != I2C_SMBUS_QUICK) {
 489                         /* Don't access xmit data register when this is a
 490                          * read operation.
 491                          */
 492                         if (iface->read_write != I2C_SMBUS_READ) {
 493                                 if (iface->writeNum > 0) {
 494                                         write_XMT_DATA8(iface,
 495                                                 *(iface->transPtr++));
 496                                         if (iface->writeNum <= 255)
 497                                                 write_MASTER_CTL(iface,
 498                                                         iface->writeNum << 6);
 499                                         else {
 500                                                 write_MASTER_CTL(iface,
 501                                                         0xff << 6);
 502                                                 iface->manual_stop = 1;
 503                                         }
 504                                         iface->writeNum--;
 505                                 } else {
 506                                         write_XMT_DATA8(iface, iface->command);
 507                                         write_MASTER_CTL(iface, 1 << 6);
 508                                 }
 509                         } else {
 510                                 if (iface->readNum > 0 && iface->readNum <= 255)
 511                                         write_MASTER_CTL(iface,
 512                                                 iface->readNum << 6);
 513                                 else if (iface->readNum > 255) {
 514                                         write_MASTER_CTL(iface, 0xff << 6);
 515                                         iface->manual_stop = 1;
 516                                 } else
 517                                         break;
 518                         }
 519                 }
 520                 write_INT_MASK(iface, MCOMP | MERR |
 521                         ((iface->read_write == I2C_SMBUS_READ) ?
 522                         RCVSERV : XMTSERV));
 523
 524                 /* Master enable */
 525                 write_MASTER_CTL(iface, read_MASTER_CTL(iface) | MEN |
 526                         ((iface->read_write == I2C_SMBUS_READ) ? MDIR : 0) |
 527                         ((CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ > 100) ? FAST : 0));
 528                 break;
 529         }
 530
 531         while (!iface->result) {
 532                 if (!wait_for_completion_timeout(&iface->complete,
 533                         adap->timeout)) {
 534                         iface->result = -1;
 535                         dev_err(&adap->dev, "smbus transfer timeout\n");
 536                 }
 537         }
 538
 539         rc = (iface->result >= 0) ? 0 : -1;
 540
 541         return rc;
 542 }
 543
 544 /*
 545  * Generic I2C SMBus transfer entrypoint
 546  */
 547 int bfin_twi_smbus_xfer(struct i2c_adapter *adap, u16 addr,
 548                         unsigned short flags, char read_write,
 549                         u8 command, int size, union i2c_smbus_data *data)
 550 {
 551         return bfin_twi_do_smbus_xfer(adap, addr, flags,
 552                         read_write, command, size, data);
 553 }
 554
 555 /*
 556  * Return what the adapter supports
 557  */
 558 static u32 bfin_twi_functionality(struct i2c_adapter *adap)
 559 {
 560         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 561                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 562                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_PROC_CALL |
 563                I2C_FUNC_I2C | I2C_FUNC_SMBUS_I2C_BLOCK;
 564 }
 565
 566 static struct i2c_algorithm bfin_twi_algorithm = {
 567         .master_xfer   = bfin_twi_master_xfer,
 568         .smbus_xfer    = bfin_twi_smbus_xfer,
 569         .functionality = bfin_twi_functionality,
 570 };
 571
 572 #ifdef CONFIG_PM_SLEEP
 573 static int i2c_bfin_twi_suspend(struct device *dev)
 574 {
 575         struct bfin_twi_iface *iface = dev_get_drvdata(dev);
 576
 577         iface->saved_clkdiv = read_CLKDIV(iface);
 578         iface->saved_control = read_CONTROL(iface);
 579
 580         free_irq(iface->irq, iface);
 581
 582         /* Disable TWI */
 583         write_CONTROL(iface, iface->saved_control & ~TWI_ENA);
 584
 585         return 0;
 586 }
 587
 588 static int i2c_bfin_twi_resume(struct device *dev)
 589 {
 590         struct bfin_twi_iface *iface = dev_get_drvdata(dev);
 591
 592         int rc = request_irq(iface->irq, bfin_twi_interrupt_entry,
 593                 0, to_platform_device(dev)->name, iface);
 594         if (rc) {
 595                 dev_err(dev, "Can't get IRQ %d !\n", iface->irq);
 596                 return -ENODEV;
 597         }
 598
 599         /* Resume TWI interface clock as specified */
 600         write_CLKDIV(iface, iface->saved_clkdiv);
 601
 602         /* Resume TWI */
 603         write_CONTROL(iface, iface->saved_control);
 604
 605         return 0;
 606 }
 607
 608 static SIMPLE_DEV_PM_OPS(i2c_bfin_twi_pm,
 609                          i2c_bfin_twi_suspend, i2c_bfin_twi_resume);
 610 #define I2C_BFIN_TWI_PM_OPS     (&i2c_bfin_twi_pm)
 611 #else
 612 #define I2C_BFIN_TWI_PM_OPS     NULL
 613 #endif
 614
 615 static int i2c_bfin_twi_probe(struct platform_device *pdev)
 616 {
 617         struct bfin_twi_iface *iface;
 618         struct i2c_adapter *p_adap;
 619         struct resource *res;
 620         int rc;
 621         unsigned int clkhilow;
 622
 623         iface = devm_kzalloc(&pdev->dev, sizeof(struct bfin_twi_iface),
 624                         GFP_KERNEL);
 625         if (!iface) {
 626                 dev_err(&pdev->dev, "Cannot allocate memory\n");
 627                 return -ENOMEM;
 628         }
 629
 630         spin_lock_init(&(iface->lock));
 631
 632         /* Find and map our resources */
 633         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 634         iface->regs_base = devm_ioremap_resource(&pdev->dev, res);
 635         if (IS_ERR(iface->regs_base)) {
 636                 dev_err(&pdev->dev, "Cannot map IO\n");
 637                 return PTR_ERR(iface->regs_base);
 638         }
 639
 640         iface->irq = platform_get_irq(pdev, 0);
 641         if (iface->irq < 0) {
 642                 dev_err(&pdev->dev, "No IRQ specified\n");
 643                 return -ENOENT;
 644         }
 645
 646         p_adap = &iface->adap;
 647         p_adap->nr = pdev->id;
 648         strlcpy(p_adap->name, pdev->name, sizeof(p_adap->name));
 649         p_adap->algo = &bfin_twi_algorithm;
 650         p_adap->algo_data = iface;
 651         p_adap->class = I2C_CLASS_DEPRECATED;
 652         p_adap->dev.parent = &pdev->dev;
 653         p_adap->timeout = 5 * HZ;
 654         p_adap->retries = 3;
 655
 656         rc = peripheral_request_list(
 657                         dev_get_platdata(&pdev->dev),
 658                         "i2c-bfin-twi");
 659         if (rc) {
 660                 dev_err(&pdev->dev, "Can't setup pin mux!\n");
 661                 return -EBUSY;
 662         }
 663
 664         rc = devm_request_irq(&pdev->dev, iface->irq, bfin_twi_interrupt_entry,
 665                 0, pdev->name, iface);
 666         if (rc) {
 667                 dev_err(&pdev->dev, "Can't get IRQ %d !\n", iface->irq);
 668                 rc = -ENODEV;
 669                 goto out_error;
 670         }
 671
 672         /* Set TWI internal clock as 10MHz */
 673         write_CONTROL(iface, ((get_sclk() / 1000 / 1000 + 5) / 10) & 0x7F);
 674
 675         /*
 676          * We will not end up with a CLKDIV=0 because no one will specify
 677          * 20kHz SCL or less in Kconfig now. (5 * 1000 / 20 = 250)
 678          */
 679         clkhilow = ((10 * 1000 / CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ) + 1) / 2;
 680
 681         /* Set Twi interface clock as specified */
 682         write_CLKDIV(iface, (clkhilow << 8) | clkhilow);
 683
 684         /* Enable TWI */
 685         write_CONTROL(iface, read_CONTROL(iface) | TWI_ENA);
 686
 687         rc = i2c_add_numbered_adapter(p_adap);
 688         if (rc < 0) {
 689                 dev_err(&pdev->dev, "Can't add i2c adapter!\n");
 690                 goto out_error;
 691         }
 692
 693         platform_set_drvdata(pdev, iface);
 694
 695         dev_info(&pdev->dev, "Blackfin BF5xx on-chip I2C TWI Controller, "
 696                 "regs_base@%p\n", iface->regs_base);
 697
 698         return 0;
 699
 700 out_error:
 701         peripheral_free_list(dev_get_platdata(&pdev->dev));
 702         return rc;
 703 }
 704
 705 static int i2c_bfin_twi_remove(struct platform_device *pdev)
 706 {
 707         struct bfin_twi_iface *iface = platform_get_drvdata(pdev);
 708
 709         i2c_del_adapter(&(iface->adap));
 710         peripheral_free_list(dev_get_platdata(&pdev->dev));
 711
 712         return 0;
 713 }
 714
 715 static struct platform_driver i2c_bfin_twi_driver = {
 716         .probe          = i2c_bfin_twi_probe,
 717         .remove         = i2c_bfin_twi_remove,
 718         .driver         = {
 719                 .name   = "i2c-bfin-twi",
 720                 .pm     = I2C_BFIN_TWI_PM_OPS,
 721         },
 722 };
 723
 724 static int __init i2c_bfin_twi_init(void)
 725 {
 726         return platform_driver_register(&i2c_bfin_twi_driver);
 727 }
 728
 729 static void __exit i2c_bfin_twi_exit(void)
 730 {
 731         platform_driver_unregister(&i2c_bfin_twi_driver);
 732 }
 733
 734 subsys_initcall(i2c_bfin_twi_init);
 735 module_exit(i2c_bfin_twi_exit);
 736
 737 MODULE_AUTHOR("Bryan Wu, Sonic Zhang");
 738 MODULE_DESCRIPTION("Blackfin BF5xx on-chip I2C TWI Controller Driver");
 739 MODULE_LICENSE("GPL");
 740 MODULE_ALIAS("platform:i2c-bfin-twi");